Heterojunction sensing-storage-computing device and manufacturing method therefor

Abstract

A heterojunction sensing-storage-computing device and a manufacturing method therefor. The heterojunction sensing-storage-computing device comprises: a substrate; a back gate electrode, formed on the substrate; a first gate dielectric layer / second gate dielectric layer / third gate dielectric layer stack, formed on the back gate electrode; one-dimensional nanowires, which are semiconductor materials having a response in a near-infrared band and are formed on the third gate dielectric layer; two-dimensional layered semiconductor materials, which are semiconductor materials having a response in a visible light band, are formed on the third gate dielectric layer, and overlap with the one-dimensional nanowires to form one-dimensional and two-dimensional heterojunctions as channel layers; and source electrodes and drain electrodes, formed on two sides of the corresponding channel layers. Information sensing, storage and computing functions are integrated in a same device unit, thereby improving a photoelectric sensing range and sensitivity of the device, and realizing the storage-computing integrated application with the information sensing capability in the visible-near-infrared band.

Description

Heterojunction inductive storage and computing device and preparation method thereof Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a heterojunction inductive storage and computing device and a preparation method thereof. Background Art

[0002] Traditional integrated circuit chips face the limitation of separate memory and computing units. Information needs to frequently exchange between the two, which increases the complexity of information transmission and system energy consumption, and is not conducive to further improving information processing efficiency. In particular, the need for additional signal conversion units such as analog-to-digital converters between sensors and computing units further reduces system efficiency. In order to achieve efficient information perception, computing, and storage, and avoid the complex process of converting, processing, and transmitting information to computing units after acquisition at the sensor end, and then processing and converting information to storage units after processing, it is of key significance to develop new neuromorphic devices that integrate sensing, storage, and computing with simultaneous perception, computing, and storage functions.

[0003] As a new type of semiconductor material, two-dimensional materials not only possess sub-nanometer ultra-thin thickness, high mobility, and tunable band structures, but also possess excellent photoelectric response properties, making them suitable for information collection applications such as photoelectric detection. By leveraging the intrinsic photoresponsiveness of two-dimensional materials, the perception function within sensing, storage, and computing can be realized, thereby constructing integrated sensing, storage, and computing devices.

[0004] Compared to traditional thin-film and two-dimensional materials, one-dimensional materials offer further miniaturization and exhibit excellent semiconductor properties in one dimension, facilitating their replacement for traditional semiconductor materials and enabling high-density integration in integrated circuits. Furthermore, by leveraging the excellent photoelectric response of one-dimensional and two-dimensional semiconductor materials across different wavelengths, heterogeneous integration of one-dimensional and two-dimensional materials can enhance the optical response band and sensitivity of devices.

[0005] Summary of the Invention

[0006] In order to solve the above problems, the present invention discloses a heterojunction sensing and computing device, comprising: a substrate; a back gate electrode formed on the substrate; a first gate dielectric layer / second gate dielectric layer / third gate dielectric layer stack formed on the back gate electrode; a one-dimensional nanowire, which is a semiconductor material with a near-infrared band response, formed on the third gate dielectric layer; a two-dimensional layered semiconductor material, which is a semiconductor material with a visible light band response, formed on the third gate dielectric layer and overlapped with the one-dimensional nanowire to form a one-dimensional and two-dimensional heterojunction as a channel layer; a source electrode and a drain electrode formed on both sides of the channel layer.

[0007] In the heterojunction inductive storage device of the present invention, preferably, the first gate dielectric layer and the third gate dielectric layer are boron nitride, aluminum oxide, tantalum oxide, titanium oxide or silicon oxide; and the second gate dielectric layer is hafnium oxide, zirconium oxide, zinc oxide or gallium oxide.

[0008] In the heterojunction sensing and computing device of the present invention, preferably, the one-dimensional nanowire is CdSe, CdS, Te, Se or Sb2Se3.

[0009] In the heterojunction sensing and computing device of the present invention, preferably, the two-dimensional layered semiconductor material is ReS2, WS2, PtS2 or MoS2.

[0010] In the heterojunction inductive storage device of the present invention, preferably, the thickness of the first gate dielectric layer is 20 nm to 30 nm, the thickness of the second gate dielectric layer is 8 nm to 12 nm, and the thickness of the third gate dielectric layer is 3 nm to 5 nm.

[0011] The present invention also discloses a method for preparing a heterojunction sensing and computing device, comprising the following steps: forming a back gate electrode on a substrate; forming a first gate dielectric layer / second gate dielectric layer / third gate dielectric layer stack on the back gate electrode; forming a one-dimensional nanowire semiconductor material with a near-infrared band response on the third gate dielectric layer, and annealing it in a nitrogen environment; forming a two-dimensional layered semiconductor material with a visible light band response on the third gate dielectric layer, and annealing it in a nitrogen environment, wherein the two-dimensional layered semiconductor material is overlapped with the one-dimensional nanowire to form a one-dimensional and two-dimensional heterojunction as a channel layer; and forming a source electrode and a drain electrode on both sides of the channel layer.

[0012] In the method for preparing the heterojunction sensing and computing device of the present invention, preferably, the one-dimensional nanowire is CdSe, CdS, Te, Se or Sb2Se3.

[0013] In the method for preparing the heterojunction sensing and computing device of the present invention, preferably, the two-dimensional layered semiconductor material is ReS2, WS2, PtS2 or MoS2.

[0014] In the method for preparing the heterojunction inductive storage and computing device of the present invention, preferably, the one-dimensional nanowire semiconductor material is annealed in a nitrogen environment at 400-600° C., and the annealing time is controlled to be 30 minutes to 3 hours.

[0015] In the method for preparing the heterojunction inductive storage and computing device of the present invention, preferably, the two-dimensional layered semiconductor material is annealed in a nitrogen environment at 600-800° C., and the annealing time is controlled within 20 minutes to 1 hour. Beneficial effects:

[0016] Traditional integrated circuit chips face the limitation of separate memory and computing units. Information needs to frequently exchange between the two, which increases the complexity of information transmission and system energy consumption, and is not conducive to further improving information processing efficiency. In particular, the need for additional signal conversion units such as analog-to-digital converters between sensors and computing units further reduces system efficiency. In order to achieve efficient information perception, computing, and storage, and avoid the complex process of converting, processing, and transmitting information to computing units after acquisition at the sensor end, and then processing and converting information to storage units after processing, it is of key significance to develop new neuromorphic devices that integrate sensing, storage, and computing with simultaneous perception, computing, and storage functions.

[0017] As a new type of semiconductor material, two-dimensional materials not only possess sub-nanometer ultra-thin thickness, high mobility, and tunable band structures, but also possess excellent photoelectric response properties, making them suitable for information collection applications such as photoelectric detection. By leveraging the intrinsic photoresponsiveness of two-dimensional materials, the perception function within sensing, storage, and computing can be realized, thereby constructing integrated sensing, storage, and computing devices.

[0018] Compared to traditional thin-film and two-dimensional materials, one-dimensional materials offer further miniaturization and exhibit excellent semiconductor properties in one dimension, facilitating their replacement for traditional semiconductor materials and enabling high-density integration in integrated circuits. Furthermore, by leveraging the excellent photoelectric response of one-dimensional and two-dimensional semiconductor materials across different wavelengths, heterogeneous integration of one-dimensional and two-dimensional materials can enhance the optical response band and sensitivity of devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] FIG1 is a flow chart of a method for preparing a heterojunction inductive storage and computing device.

[0020] 2 to 7 are schematic structural diagrams of various stages of the heterojunction inductive storage and computing device preparation method. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solutions and advantages of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. The described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0022] In the description of the present invention, it should be noted that the terms "upper," "lower," "vertical," and "horizontal," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of the present invention. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limitations on the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0023] In addition, many specific details of the present invention are described below, such as device structure, materials, dimensions, processing techniques, and technologies, to facilitate a clearer understanding of the present invention. However, as will be appreciated by those skilled in the art, the present invention may be practiced without following these specific details. Unless otherwise noted below, various components of the device may be constructed from materials known to those skilled in the art, or materials with similar functions developed in the future may be used.

[0024] Figure 1 is a flow chart of a method for preparing a heterojunction inductive storage and computing device. As shown in Figure 1, the method for preparing a heterojunction inductive storage and computing device includes the following steps:

[0025] In step S1, a Pd electrode is grown on the surface of a 300nm thick silicon oxide wafer 100 by physical vapor deposition, electron beam evaporation, thermal evaporation, or the like as a back gate electrode 101, with a thickness controlled to be 10-30nm. The resulting structure is shown in FIG2 . The electrode material may be Pd, Pt, Ir, Ru, Ni, Au, Ag, or the like.

[0026] In step S2, a boron nitride film is deposited on the back gate electrode 101 by chemical vapor deposition, atomic layer deposition, mechanical lift-off, or the like as the first gate dielectric layer 102 to achieve a charge blocking effect. The thickness is controlled to be 20 nm to 30 nm. The resulting structure is shown in FIG3 . The material of the first gate dielectric layer can be selected from insulating thin film materials such as boron nitride, aluminum oxide, tantalum oxide, titanium oxide, and silicon oxide.

[0027] In step S3, hafnium oxide is deposited on the first gate dielectric layer 102 by chemical vapor deposition, atomic layer deposition, physical vapor deposition, or other methods as the second gate dielectric layer 103 to achieve a charge trapping effect. The resulting structure is shown in FIG4 . The thickness of the second gate dielectric layer is controlled to be 8 nm to 12 nm, and the material can be selected from insulating thin film materials such as hafnium oxide, zirconium oxide, zinc oxide, and gallium oxide.

[0028] In step S4, a boron nitride film is deposited on the second gate dielectric layer 103 by chemical vapor deposition, atomic layer deposition, mechanical lift-off, or other methods as the third gate dielectric layer 104 to achieve a charge tunneling effect. The resulting structure is shown in FIG5 . The thickness of the third gate dielectric layer is controlled to be 3 nm to 5 nm, and the material can be selected from insulating thin film materials such as boron nitride, aluminum oxide, tantalum oxide, titanium oxide, and silicon oxide.

[0029] In step S5, a one-dimensional CdSe nanowire semiconductor material 105 with near-infrared response is grown on the third gate dielectric layer 104 using atomic layer deposition, chemical vapor deposition, or other methods. The nanowire is then annealed in a nitrogen environment at 400-600°C for 30 minutes to 3 hours. The one-dimensional nanowire semiconductor material can be selected from materials with excellent photoelectric response in the near-infrared band, such as CdSe, CdS, Te, Se, or Sb2Se3.

[0030] In step S6, a ReS2 two-dimensional layered semiconductor material 106 with visible light response is grown on the third gate dielectric layer 104 using atomic layer deposition, chemical vapor deposition, or other methods, partially covering and overlapping the CdSe one-dimensional semiconductor material 105. The material is then annealed in a nitrogen environment at 600-800°C for 20 minutes to 1 hour. The two-dimensional layered semiconductor material 106 forms a one-dimensional heterojunction with the one-dimensional nanowire semiconductor material 105, serving as the channel layer. The resulting structure is shown in Figure 6. The two-dimensional layered semiconductor material can be selected from materials with excellent photoelectric response in the visible light band, such as ReS2, WS2, PtS2, and MoS2.

[0031] In step S7, Ti / Au electrodes are grown on both sides of the channel layer as the source electrode 107 and the drain electrode 108 by physical vapor deposition, electron beam evaporation, thermal evaporation, etc., with thicknesses controlled to be 10-30 nm and 50-100 nm, respectively, to complete the fabrication of the heterojunction inductive storage device. The resulting structure is shown in FIG7 . The electrode materials can be Ti / Au, Ti / Pd, Ti / Pt, Cr / Au, Cr / Pd, Cr / Pt, etc.

[0032] As shown in Figure 7, the heterojunction sensing and storage device includes: a substrate 100; a back gate electrode 101, formed on the substrate 100; a first gate dielectric layer 102 / a second gate dielectric layer 103 / a third gate dielectric layer 104 stack, formed on the back gate electrode 101, to achieve the effect of charge capture and storage; a one-dimensional nanowire 105, which is a semiconductor material with a near-infrared band response, formed on the third gate dielectric layer 104; a two-dimensional layered semiconductor material 108, which is a semiconductor material with a visible light band response, formed on the third gate dielectric layer 104, overlapped with the one-dimensional nanowire 105 to form a one-dimensional and two-dimensional heterojunction as a channel layer; a source electrode 107 and a drain electrode 108, formed on both sides of the channel layer.

[0033] By utilizing the unique photoelectric response characteristics of one-dimensional and two-dimensional semiconductors, a heterojunction of one-dimensional and two-dimensional semiconductors is constructed, and a heterojunction-type integrated sensing, storage, and computing device is prepared. The information perception, storage, and computing functions are integrated in the same device unit, which improves the photoelectric perception range and sensitivity of the device, and realizes the integrated storage and computing application of information perception capabilities in the visible-near-infrared band.

[0034] The above description is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with this technical field within the technical scope disclosed in the present invention should be covered by the scope of protection of the present invention.

Claims

1. A heterojunction inductive storage and computing device, characterized in that: include: substrate; A back gate electrode formed on the substrate; A first gate dielectric layer / a second gate dielectric layer / a third gate dielectric layer stack is formed on the back gate electrode; A one-dimensional nanowire, which is a semiconductor material with near-infrared band response, formed on the third gate dielectric layer; A two-dimensional layered semiconductor material, which is a semiconductor material with visible light band response, is formed on the third gate dielectric layer and overlapped with the one-dimensional nanowire to form a one-dimensional and two-dimensional heterojunction as a channel layer; A source electrode and a drain electrode are formed on both sides of the channel layer.

2. The heterojunction inductive storage and computing device according to claim 1, characterized in that: The first gate dielectric layer and the third gate dielectric layer are made of boron nitride, aluminum oxide, tantalum oxide, titanium oxide or silicon oxide; the second gate dielectric layer is made of hafnium oxide, zirconium oxide, zinc oxide or gallium oxide.

3. The heterojunction inductive storage and computing device according to claim 1, characterized in that: The one-dimensional nanowire is CdSe, CdS, Te, Se or Sb2Se3.

4. The heterojunction inductive storage and computing device according to claim 1, characterized in that: The two-dimensional layered semiconductor material is ReS2, WS2, PtS2 or MoS2.

5. The heterojunction inductive storage and computing device according to claim 1, characterized in that: The thickness of the first gate dielectric layer is 20 nm to 30 nm, the thickness of the second gate dielectric layer is 8 nm to 12 nm, and the thickness of the third gate dielectric layer is 3 nm to 5 nm.

6. A method for preparing a heterojunction inductive storage device, characterized in that: The following steps are involved: forming a back gate electrode on the substrate; forming a first gate dielectric layer / a second gate dielectric layer / a third gate dielectric layer stack on the back gate electrode; Forming a one-dimensional nanowire semiconductor material having a near-infrared band response on the third gate dielectric layer, and performing annealing treatment in a nitrogen environment; Forming a two-dimensional layered semiconductor material with visible light band response on the third gate dielectric layer, and performing annealing treatment in a nitrogen environment, wherein the two-dimensional layered semiconductor material is overlapped with the one-dimensional nanowire to form a one-dimensional and two-dimensional heterojunction as a channel layer; A source electrode and a drain electrode are formed on both sides of the channel layer.

7. The method for preparing a heterojunction inductive storage and computing device according to claim 6, characterized in that: The one-dimensional nanowire is CdSe, CdS, Te, Se or Sb2Se3.

8. The method for preparing a heterojunction inductive storage and computing device according to claim 6, characterized in that: The two-dimensional layered semiconductor material is ReS2, WS2, PtS2 or MoS2.

9. The method for preparing a heterojunction inductive storage and computing device according to claim 6, characterized in that: The one-dimensional nanowire semiconductor material is annealed in a nitrogen environment at 400-600° C., and the annealing time is controlled within 30 minutes to 3 hours.

10. The method for preparing a heterojunction inductive storage and computing device according to claim 6, characterized in that: The two-dimensional layered semiconductor material is annealed in a nitrogen environment at 600-800°C, and the annealing time is controlled at 20 minutes to 1 hour.

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