Power device having low on-resistance and manufacturing method therefor

Abstract

The present invention relates to a power device having low on-resistance and a manufacturing method therefor. The power device having low on-resistance comprises various second conductive-type electrical field shielding regions (9), various metal components (11), and various conductive source region components of a preset thickness, as well as a bottom metal layer (8), a first conductive-type substrate (1), a first conductive-type epitaxial layer (2), and a second conductive-type body region layer (5) which are sequentially stacked from bottom to top. The power device is constructed according to design implementation. By arranging a second conductivity-type electrical field shielding region (9) below a gate trench (10), the electrical field can be effectively shielded, so that the reverse electrical field intensity borne by a gate dielectric layer (3) of the device is greatly reduced, increasing the breakdown voltage of the device and enhancing the reliability of the device. Meanwhile, the second conductive-type electrical field shielding regions (9) are designed to be in contact with the second conductive-type body region layer (5) connected to a corresponding gate trench node, so that the problems of reduced switching speed, increased on-resistance, and the like caused by the shielding region are solved from cellular structure design.

Description

A power device with low on-resistance and a manufacturing method thereof Technical Field

[0001] The present invention relates to a power device with low on-resistance and a manufacturing method thereof, belonging to the technical field of power semiconductor device structure design and manufacturing. Background Art

[0002] Devices made from third-generation semiconductor materials, such as silicon carbide, exhibit excellent high-frequency, high-voltage, high-temperature, and radiation-resistant capabilities, enabling higher power density and efficiency. Silicon carbide (SiC) power MOSFETs, a representative SiC switching device, boast low switching losses and high operating frequencies, and are now widely used in power electronics. Currently, there are two technological approaches to SiC power MOSFETs: planar gate and trench gate. The trench gate structure offers improved conduction capability due to its higher channel mobility and smaller cell size. However, the trench gate structure exhibits electric field peaks at the corners of the trench bottom, which can easily cause semiconductor avalanche breakdown and gate dielectric degradation. The electric field peaks are even greater at the corners of three-dimensional trenches, further reducing the device's breakdown voltage and reliability. To address this issue, electric field shielding regions have been introduced into trench gate power devices. However, in traditional trench-gate power devices, the electric field shielding regions are isolated from each other and lack a fixed potential. This requires additional solutions to address the potential of the shielding regions. Otherwise, problems such as reduced switching speed, degraded on-resistance, and reduced device avalanche surge reliability can occur. To address the shielding region grounding issue, traditional trench-gate MOSFETs sacrifice active area, reducing their conduction efficiency.

[0003] Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a power device with low on-resistance, innovate the device structure, break the original problem limitations, and improve the conduction efficiency and reliability of the device.

[0005] In order to solve the above technical problems, the present invention adopts the following technical solution: the present invention designs a power device with low on-resistance, comprising respective second conductive type electric field shielding regions (9), respective metal parts (11), respective conductive source region parts of preset thickness, and a bottom metal layer (8), a first conductive type substrate (1), a first conductive type epitaxial layer (2), and a second conductive type body region layer (5) stacked in sequence from bottom to top;

[0006] The structural dimensions of each conductive source region are identical to each other, the surface of the conductive source region is a regular polygon, the positions of the opposite sides of adjacent conductive source regions correspond to each other, and a preset spacing is maintained, each conductive source region is distributed on the upper surface of the second conductive type body region layer (5), a gate trench (10) is embedded in the non-conductive source region covering area on the upper surface of the second conductive type body region layer (5), and the bottom depth of the gate trench (10) is lower than the depth of the lower surface of the second conductive type body region layer (5), the inner bottom surface and inner sidewall of the gate trench (10) are covered with a gate dielectric layer (3), and a gate (4) is filled in the area surrounded by the gate dielectric layer (3);

[0007] The number of metal parts (11) is equal to the number of conductive source area parts, each metal part (11) corresponds to each conductive source area part one by one, and each metal part (11) is respectively arranged on the upper surface of the corresponding conductive source area part; the intersection position between the gate grooves (10) in different directions constitutes a gate groove node, the number of the second conductive type electric field shielding area (9) is equal to the number of the gate groove nodes, each second conductive type electric field shielding area (9) is arranged in the first conductive type epitaxial layer (2), and each second conductive type electric field shielding area (9) is respectively arranged at the outer bottom of the corresponding gate groove node, and each second conductive type electric field shielding area (9) is respectively extended to contact the second conductive type body region layer (5) area connected to its corresponding gate groove node.

[0008] As a preferred technical solution of the present invention: the conductive source region comprises a second conductive type source region (6) and a first conductive type source region (7) having the same regular polygonal surface shape, and the regular polygon is the regular polygonal shape of the surface of the conductive source region, the thickness of the second conductive type source region (6) and the thickness of the first conductive type source region (7) are both equal to the thickness of the conductive source region, the outer diameter of the first conductive type source region (7) is greater than the outer diameter of the second conductive type source region (6), the second conductive type source region (6) is embedded in the first conductive type source region (7), and the surface of the second conductive type source region (6) is adjacent to the first conductive type source region. The surfaces of the second conductive type source region (7) are parallel to each other, and the surfaces of the two surfaces of the second conductive type source region (6) are coplanar with the surfaces of the corresponding side surfaces of the first conductive type source region (7), the center position of the second conductive type source region (6) overlaps with the center position of the first conductive type source region (7), and the side edges of the second conductive type source region (6) are parallel to the side edges of the first conductive type source region (7) in a one-to-one correspondence; in a direction perpendicular to the surface of the conductive source region, the projection of the second conductive type source region (6) is located within the projection of its corresponding metal member (11), and the projection of the metal member (11) is located within the projection of its corresponding conductive source region.

[0009] As a preferred technical solution of the present invention, each second conductive type electric field shielding region (9) covers the area at the outer bottom of its corresponding gate trench node, and the proportion of the area at the outer bottom of the corresponding gate trench node is within a preset fluctuation range of about one quarter.

[0010] As a preferred technical solution of the present invention: each second conductive type electric field shielding region (9) covers the entire area outside the bottom of its corresponding gate trench node, and each second conductive type electric field shielding region (9) extends around its corresponding gate trench node and contacts the second conductive type body region layer (5) area connected thereto.

[0011] As a preferred technical solution of the present invention: in a direction perpendicular to the outer bottom surface of the gate trench node, the projections of each second conductive type electric field shielding region (9) are symmetrical.

[0012] As a preferred technical solution of the present invention: in a direction perpendicular to the outer bottom surface of the gate trench node, each second conductive type electric field shielding region (9) is projected in a quadrilateral, a circle, a triangle, or a hexagon.

[0013] As a preferred technical solution of the present invention: the first conductive type substrate (1) and the second conductive type electric field shielding region (9) have a first ion doping concentration, the first conductive type epitaxial layer (2) and the second conductive type body layer (5) have a second ion doping concentration, and the second conductive type source region (6) and the first conductive type source region (7) have a third ion doping concentration, wherein the first ion doping concentration is greater than or equal to the second ion doping concentration, and the third ion doping concentration is greater than the second ion doping concentration.

[0014] As a preferred technical solution of the present invention: the regular polygonal surface of the conductive source area component is a regular triangle, a regular quadrilateral, or a regular hexagon.

[0015] Corresponding to the above, the technical problem that the present invention also needs to solve is to provide a method for manufacturing a power device with low on-resistance. According to the structural design, the structure construction process is designed in sequence to efficiently realize the manufacturing of the designed device and improve the manufacturing work efficiency.

[0016] In order to solve the above technical problems, the present invention adopts the following technical solution: The present invention designs a method for manufacturing a power device with low on-resistance, comprising the following steps:

[0017] Step A. constructing a first conductive type epitaxial layer (2) based on the growth of the upper surface of the first conductive type substrate (1), and then constructing various second conductive type body region layers (5) on the upper surface of the first conductive type epitaxial layer (2);

[0018] Step B. applying an ion implantation process to form a second conductive type source region (6) and a first conductive type source region (7) on the upper surface of each second conductive type body region layer (5), respectively, and the second conductive type source region (6) and the first conductive type source region (7) on the upper surface of each second conductive type body region layer (5) constitute a conductive source region component;

[0019] Step C. constructing a gate trench (10) between adjacent second conductive type body region layers (5) by using an etching process, and forming a gate dielectric layer (3) on the inner bottom surface and inner sidewall of the gate trench (10) by using a chemical vapor deposition process; and depositing a gate material in the gate trench (10) by using a chemical vapor deposition process to form a gate (4);

[0020] Step D. For each gate trench node formed by the intersection of gate trenches (10) in different directions, a second conductive type electric field shielding region (9) is formed at the outer bottom of the gate trench node by means of inclined ion implantation, and the second conductive type electric field shielding region (9) extends to contact the second conductive type body region layer (5) connected to the corresponding gate trench node;

[0021] Step E. For each conductive source region component, a sputtering process is used to form a metal component (11) on the upper surface of the conductive source region component, and the metal component (11) is connected to the second conductive type source region (6) and the first conductive type source region (7);

[0022] Step F: forming a bottom metal layer (8) on the lower surface of the first conductive type substrate (1).

[0023] The low on-resistance power device and manufacturing method described in the present invention, using the above technical solution, has the following technical effects compared with the prior art:

[0024] (1) In a power device with low on-resistance designed by the present invention, the gate trench (10) has better conduction capability due to its higher channel mobility and smaller cell size, and introduces a second conductive type electric field shielding area (9) design, which aims at the electric field peak at the bottom corner of the gate trench (10), thereby avoiding semiconductor avalanche breakdown at the corner and degradation of the device gate dielectric layer to the greatest extent, reducing the electric field peak at the corner of the gate trench (10), increasing the breakdown voltage drop of the device, and ensuring the reliability of the device; in addition, the design proposes a second conductive type The invention provides a novel cellular structure of a second conductive type electric field shielding region (9), wherein the second conductive type electric field shielding region (9) is arranged below the gate trench node and arranged along each gate trench node, and a depletion layer is formed between the second conductive type electric field shielding region (9) and the first conductive type epitaxial layer (2), which can effectively reduce the electric field intensity in the gate dielectric layer (3), prevent the gate dielectric layer (3) from breaking down, and improve the device breakdown voltage; at the same time, the structure of the invention solves the problem of potential floating of the second conductive type electric field shielding region (9) from the perspective of the cellular structure, thereby improving the avalanche surge reliability of the device;

[0025] (2) The device designed by the present invention solves the problem of floating electric field shielding region potential in traditional MOSFET devices from the perspective of cellular structure, without sacrificing the active area. At the same time, it avoids the problems of reduced switching speed and degradation of on-resistance caused by the floating electric field shielding region, thereby improving the switching frequency of the device and reducing switching loss. In addition, the second conductive type electric field shielding region (9) in the device designed by the present invention is arranged along with each gate groove node, and the second conductive type electric field shielding region (9) is set below the gate groove node to protect the electric field of the gate dielectric layer (3). At the same time, the gate groove (10) between adjacent second conductive type electric field shielding regions (9) will not be pinched off by the depletion layer between the second conductive type electric field shielding region (9) and the first conductive type epitaxial layer (2), thereby retaining the area of ​​the gate groove (10) to the greatest extent, ensuring the current density of the device conduction, improving the device conduction efficiency, and reducing the device specific on-resistance.

[0026] (3) The cell structure designed in the present invention has an innovative cell structure, which realizes the simultaneous improvement of the reverse withstand voltage and reliability of the device, as well as the forward conduction efficiency, and overcomes the shortcomings of the existing structure: 1) The problem of floating potential of the shielding area when the electric field shielding area is set at the bottom of the groove requires the electric field shielding area to be grounded from the layout, thereby reducing the device's specific on-resistance; 2) The asymmetric half-wrapped groove structure is adopted, and the electric field shielding area does not need to be additionally grounded, but half of the area of ​​the channel area is sacrificed; 3) The bipolar groove structure is adopted, and the source level of the device is made into a groove structure, and the bottom of the gate groove is protected by the second conductive type shielding area at the bottom of the source groove on both sides, but this scheme introduces the JFET region resistance, while increasing the cell area and reducing the device conduction efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] FIG1 is a top view of a device having a regular quadrilateral conductive source region, which is an embodiment of a power device with low on-resistance designed according to the present invention;

[0028] FIG2 is a schematic diagram of the three-dimensional structure of the trench gate power device cell 100 in FIG1 according to a first design embodiment of the present invention;

[0029] FIG3 is a cross-sectional view of the trench gate power device cell 100 in FIG1 along the direction 1001 in FIG2 according to a first embodiment of the present invention;

[0030] FIG4 is a cross-sectional view of the trench gate power device cell 100 in FIG1 along the direction 1002 in FIG2 according to a first design embodiment of the present invention;

[0031] FIG5 is a cross-sectional view of the trench gate power device cell 100 in FIG1 along the direction 1003 in FIG2 according to a first embodiment of the present invention;

[0032] FIG6 is a top view of a device having a regular quadrilateral conductive source region according to a second embodiment of a power device with low on-resistance designed according to the present invention;

[0033] FIG7 is a schematic diagram of the three-dimensional structure of the trench gate power device cell 200 in FIG6 according to a second design embodiment of the present invention;

[0034] FIG8 is a cross-sectional view of the trench gate power device cell 200 in FIG6 corresponding to the direction 1004 in FIG7 according to a second design embodiment of the present invention;

[0035] FIG9 is a cross-sectional view of the trench gate power device cell 200 in FIG6 corresponding to the direction 1005 in FIG7 according to a second design embodiment of the present invention;

[0036] FIG10 is a cross-sectional view of the trench gate power device cell 200 in FIG6 corresponding to the direction 1006 in FIG7 according to a second design embodiment of the present invention;

[0037] FIG11 is a top view of a device having a regular quadrilateral conductive source region according to a third embodiment of a power device with low on-resistance designed according to the present invention;

[0038] FIG12 is a top view of a device having a regular quadrilateral conductive source region according to a fourth embodiment of a power device with low on-resistance designed according to the present invention;

[0039] FIG13 is a top view of a device having an equilateral triangle conductive source region according to a fifth embodiment of a power device with low on-resistance designed according to the present invention;

[0040] FIG14 is a top view of a device having a regular hexagonal conductive source region according to a sixth embodiment of a power device with low on-resistance designed according to the present invention. DETAILED DESCRIPTION

[0041] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0042] The present invention is directed to a power device with low on-resistance. In actual application, as shown in Figures 1 to 14, the specific design includes various second conductive type electric field shielding regions (9), various metal parts (11), various conductive source region parts of preset thickness, and a bottom metal layer (8), a first conductive type substrate (1), a first conductive type epitaxial layer (2), and a second conductive type body region layer (5) stacked in sequence from bottom to top. The bottom metal layer (8) forms an ohmic contact with the lower surface of the first conductive type substrate (1).

[0043] The structural dimensions of each conductive source region are identical to each other, the surface of the conductive source region is a regular polygon, the positions of the opposite sides of adjacent conductive source regions correspond to each other, and a preset spacing is maintained, each conductive source region is distributed on the upper surface of the second conductive type body region layer (5), a gate trench (10) is embedded in the non-conductive source region covering area on the upper surface of the second conductive type body region layer (5), and the bottom depth of the gate trench (10) is lower than the depth of the lower surface of the second conductive type body region layer (5), the inner bottom surface and inner sidewall of the gate trench (10) are covered with a gate dielectric layer (3), and the area surrounded by the gate dielectric layer (3) is filled with A gate (4) is provided; in the region where the side wall of the gate dielectric layer (3) in the gate trench (10) corresponds to the position of the second conductive type electric field shielding region (9), the side wall of the gate dielectric layer (3) will not form a channel, and no channel current will be generated; whereas in the region where the side wall of the gate dielectric layer (3) in the gate trench (10) does not have the second conductive type electric field shielding region (9), the side wall of the gate dielectric layer (3) will form a channel, and a channel current will be generated. The structure of the present invention effectively retains more channel area, separates the electric field protection region and the conductive region, and achieves the good effect of both ensuring the on-current and effectively reducing the electric field of the gate dielectric layer (3).

[0044] The number of metal parts (11) is equal to the number of conductive source parts, each metal part (11) corresponds to each conductive source part one by one, and each metal part (11) is respectively arranged on the upper surface of the corresponding conductive source part; the intersection of gate grooves (10) in different directions constitutes a gate groove node; the number of second conductive type electric field shielding regions (9) is equal to the number of gate groove nodes; each second conductive type electric field shielding region (9) is arranged in the first conductive type epitaxial layer (2), and each second conductive type electric field shielding region (9) is respectively arranged at the outer bottom of the corresponding gate groove node, and each second conductive type electric field shielding region (9) is respectively extended to the second conductive type body region layer (5) connected to its corresponding gate groove node to contact. While reducing the electric field of the gate dielectric layer (3), protecting the gate dielectric layer (3) at the bottom of the gate groove (10), and improving the voltage resistance of the device, as many gate grooves (10) as possible are retained as conductive channels, thereby improving the forward conduction efficiency of the device and reducing switching loss.

[0045] Regarding the conductive source region, as shown in Figures 1 to 14, the conductive source region is specifically designed to include a second conductive type source region (6) and a first conductive type source region (7) having the same regular polygonal surface shape, and the regular polygon is the regular polygonal shape of the surface of the conductive source region, the thickness of the second conductive type source region (6) and the thickness of the first conductive type source region (7) are both equal to the thickness of the conductive source region, the outer diameter of the first conductive type source region (7) is greater than the outer diameter of the second conductive type source region (6), the second conductive type source region (6) is embedded in the first conductive type source region (7), the surface of the second conductive type source region (6) and the surface of the first conductive type source region (7) are parallel to each other, and the second conductive type source region (6) is substantially parallel to the first conductive type source region (7). The two surfaces of the second conductive type source region (6) are coplanar with the corresponding side surfaces of the first conductive type source region (7), the center position of the second conductive type source region (6) overlaps with the center position of the first conductive type source region (7), and the side edges of the second conductive type source region (6) are parallel to the side edges of the first conductive type source region (7) in a one-to-one correspondence; in a direction perpendicular to the surface of the conductive source region, the projection of the second conductive type source region (6) is located within the projection of its corresponding metal member (11), and the projection of the metal member (11) is located within the projection of its corresponding conductive source region, and the metal member (11) forms an ohmic contact with the upper surfaces of the first conductive type source region (7) and the second conductive type source region (6).

[0046] Regarding the above-mentioned design of a power device with low on-resistance, in practical applications, the following five embodiments are designed, wherein the first embodiment is shown in Figures 1 to 5, wherein the regular polygonal surface of the conductive source region is a regular quadrilateral, and each second conductive type electric field shielding region (9) is specifically designed to cover the area of ​​the outer bottom of its corresponding gate trench node, and the proportion of the area of ​​the outer bottom of the corresponding gate trench node is within a preset fluctuation range of one-fourth. In practical applications of the structure of the first embodiment, the gate trenches (10) are connected in a grid shape to form a square cell, with high channel utilization, strong current conduction capability, and the realization of the same gate potential. Therefore, the gate can be directly led out through a metal wire, without the need for additional metal bus on the layout, the cell uniformity is good, and the chip area is effectively saved.

[0047] In the second embodiment, as shown in Figures 6 to 10, the regular polygonal surface of the conductive source region is a regular quadrilateral, and each second conductive type electric field shielding region (9) is specifically designed to cover the entire area of ​​the outer bottom of its corresponding gate trench node, and each second conductive type electric field shielding region (9) extends around its corresponding gate trench node to contact the second conductive type body region layer (5) area connected thereto, and in actual application, in a direction perpendicular to the outer bottom surface of the gate trench node, each second conductive type electric field shielding region (9) is projected in a symmetrical shape. This second embodiment reduces the electric field of the gate dielectric layer (3) in the reverse blocking state of the device to a greater extent, thereby improving the reliability of the device.

[0048] As shown in FIG11 , the regular polygonal surface of the conductive source region is a regular quadrilateral, and based on the second embodiment, each second conductive type electric field shielding region (9) is designed to have a circular projection in a direction perpendicular to the outer bottom surface of the gate trench node.

[0049] As shown in FIG12 , the regular polygonal surface of the conductive source region is a regular quadrilateral, and based on the second embodiment, each second conductive type electric field shielding region (9) is designed to be projected in a hexagonal shape in a direction perpendicular to the outer bottom surface of the gate trench node.

[0050] As shown in FIG13 , the regular polygonal surface of the conductive source region component is a regular triangle, and based on the position of each regular triangle conductive source region component, each second conductive type electric field shielding region (9) is constructed, such as shown in FIG13 , in a direction perpendicular to the outer bottom surface of the gate trench node, each second conductive type electric field shielding region (9) is designed to be projected in a quadrilateral.

[0051] As shown in FIG14 , the regular polygonal surface of the conductive source region is a regular hexagon, and based on the position of each regular hexagonal conductive source region, each second conductive type electric field shielding region (9) is constructed, such as shown in FIG13 . In the direction perpendicular to the outer bottom surface of the gate trench node, each second conductive type electric field shielding region (9) is designed to be projected in a quadrilateral.

[0052] Regarding the above-mentioned specific implementation and application of the embodiment 1 to embodiment 6, that is, in actual application, the regular polygonal surface of the conductive source area is a regular triangle, a regular quadrilateral, or a regular hexagon, and regarding the second conductive type electric field shielding area (9), in the direction perpendicular to the outer bottom surface of the gate groove node, the projection of each second conductive type electric field shielding area (9) can be a quadrilateral, a circle, a triangle, or a hexagon according to the actual scene position relationship. The advantages of each embodiment over the traditional cell design in actual implementation are that by optimizing the three-dimensional structure of the device, the gate groove (10) is arranged in a grid shape, and as many conductive channels as possible are retained, the channel utilization rate is improved, the conduction efficiency of the device is improved, and the on-resistance of the device is reduced. In addition, the second conductive type electric field shielding region (9) is placed at the bottom of the gate trench node, and the second conductive type electric field shielding region (9) extends to the second conductive type body region layer (5) connected to the corresponding gate trench node to contact the region. The second conductive type body region layer (5) contacts the metal part (11) through the second conductive type source region (6), i.e., the P+ active region. This can effectively solve the grounding problem of the shielding region, and no longer requires grounding the floating electric field shielding region through additional bonding methods, thereby increasing the switching frequency of the device and reducing switching losses. At the same time, it can effectively shield the electric field at the bottom of the trench, reduce the electric field strength of the gate dielectric layer (3), and improve the breakdown voltage and reliability of the device.

[0053] In the specific practical application of the power device with low on-resistance, regarding the ion doping concentration of each structure, the first conductive type substrate (1) and the second conductive type electric field shielding region (9) are specifically designed to have a first ion doping concentration, the first conductive type epitaxial layer (2) and the second conductive type body layer (5) have a second ion doping concentration, and the second conductive type source region (6) and the first conductive type source region (7) have a third ion doping concentration, wherein the first ion doping concentration is greater than or equal to the second ion doping concentration, and the third ion doping concentration is greater than the second ion doping concentration; in the actual specific design implementation, for example, the first ion doping concentration is designed to be 1×10 19 cm -3 , the second ion doping concentration is 6.5×10 15 cm -3 , the third ion doping concentration is designed to be 1×10 19 cm -3 .

[0054] Corresponding to the above, the present invention designs a method for manufacturing a power device with low on-resistance, and specifically designs and implements the following steps A to F.

[0055] Step A: constructing a first conductive type epitaxial layer (2) based on the growth of the upper surface of the first conductive type substrate (1), and then constructing various second conductive type body region layers (5) on the upper surface of the first conductive type epitaxial layer (2). In practical applications, the first conductive type substrate (1) is, for example, a silicon carbide substrate.

[0056] Step B. Applying an ion implantation process, a second conductive type source region (6) and a first conductive type source region (7) are formed on the upper surface of each second conductive type body region layer (5), and the second conductive type source region (6) and the first conductive type source region (7) on the upper surface of each second conductive type body region layer (5) constitute a conductive source region component.

[0057] Step C. Between adjacent second conductive type body region layers (5), an etching process is applied to construct a gate trench (10), and a chemical vapor deposition process is used to form a gate dielectric layer (3) on the inner bottom surface and inner sidewall of the gate trench (10); and a gate material is deposited in the gate trench (10) using a chemical vapor deposition process to form a gate (4).

[0058] Step D. For each gate trench node formed by the intersection of gate trenches (10) in different directions, a second conductive type electric field shielding region (9) is formed at the outer bottom of the gate trench node by means of inclined ion implantation, and the second conductive type electric field shielding region (9) extends to contact the second conductive type body region layer (5) connected to its corresponding gate trench node.

[0059] Step E: For each conductive source region, a sputtering process is used to form a metal member (11) on the upper surface of the conductive source region, and the metal member (11) is connected to the second conductive type source region (6) and the first conductive type source region (7).

[0060] Step F: forming a bottom metal layer (8) on the lower surface of the first conductive type substrate (1).

[0061] In the design and implementation of the above technical solution, the gate trench (10) has better conduction capability due to its higher channel mobility and smaller cell size, and the second conductive type electric field shielding area (9) is introduced to design the electric field peak at the bottom corner of the gate trench (10), thereby avoiding semiconductor avalanche breakdown and device gate dielectric layer degradation at the corner to the greatest extent, reducing the electric field peak at the corner of the gate trench (10), increasing the breakdown voltage drop of the device, and ensuring the reliability of the device; in addition, in traditional trench gate power devices, the electric field shielding areas are isolated from each other and have no fixed potential. The electric field shielding area with floating potential will store charge, reducing Device switching speed and avalanche surge reliability are improved. In this regard, the present invention proposes a novel cellular structure for a second conductive type electric field shielding region (9), wherein the second conductive type electric field shielding region (9) is arranged below the gate trench node and arranged along each gate trench node. A depletion layer is formed between the second conductive type electric field shielding region (9) and the first conductive type epitaxial layer (2), which can effectively reduce the electric field intensity in the gate dielectric layer (3), prevent the gate dielectric layer (3) from breaking down, and improve the device breakdown voltage. At the same time, the structure of the present invention solves the potential floating problem of the second conductive type electric field shielding region (9) from the cellular structure, thereby improving the avalanche surge reliability of the device.

[0062] In order to reduce the peak electric field at the bottom of the device trench, the traditional trench MOSFET structure sets an electric field shielding area at the bottom of the trench, but there is a problem of floating potential in the electric field shielding area, which requires grounding the electric field shielding area from the layout, which not only increases the device processing cost, but also sacrifices the area of ​​the device active area and reduces the device specific on-resistance. The device designed by the present invention solves the problem of floating potential in the electric field shielding area of ​​traditional MOSFET devices from the perspective of cellular structure, without sacrificing the active area, and at the same time avoids the problems of reduced switching speed and degradation of on-resistance caused by the floating electric field shielding area, thereby improving the switching frequency of the device. , reducing switching losses; and in the device designed by the present invention, each second conductive type electric field shielding region (9) is arranged along each gate trench node, and the second conductive type electric field shielding region (9) is arranged below the gate trench node to protect the electric field of the gate dielectric layer (3); at the same time, the gate trench (10) between adjacent second conductive type electric field shielding regions (9) will not be pinched off by the depletion layer between the second conductive type electric field shielding region (9) and the first conductive type epitaxial layer (2), thereby retaining the area of ​​the gate trench (10) to the greatest extent, ensuring the current density of the device conduction, improving the device conduction efficiency, and reducing the device specific on-resistance.

[0063] In addition, the cellular structure designed in the present invention has an innovative cellular structure, which realizes the simultaneous improvement of the reverse withstand voltage and reliability of the device, as well as the forward conduction efficiency, and overcomes the shortcomings of the existing structure: 1) The problem of floating potential of the shielding area when the electric field shielding area is set at the bottom of the groove requires the electric field shielding area to be grounded from the layout, thereby reducing the device's specific on-resistance; 2) An asymmetric half-wrapped trench structure is adopted, which does not require additional grounding of the electric field shielding area, but sacrifices half of the area of ​​the channel area; 3) A bipolar trench structure is adopted, and the source level of the device is made into a trench structure, and the bottom of the gate trench is protected by the second conductive type shielding area at the bottom of the source level trench on both sides, but this scheme introduces the JFET region resistance, while increasing the cell area and reducing the device conduction efficiency.

[0064] The embodiments of the present invention are described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Various changes can be made within the scope of knowledge possessed by ordinary technicians in this field without departing from the spirit of the present invention.

Claims

1. A power device with low on-resistance, characterized in that: The invention comprises a plurality of second conductive type electric field shielding regions (9), a plurality of metal parts (11), a plurality of conductive source region parts of a preset thickness, and a bottom metal layer (8), a first conductive type substrate (1), a first conductive type epitaxial layer (2), and a second conductive type body region layer (5) stacked in sequence from bottom to top; wherein the structural dimensions of the plurality of conductive source region parts are the same, the surfaces of the conductive source region parts are regular polygons, the positions of the sides of adjacent conductive source region parts relative to each other correspond to each other, and a preset spacing is maintained, the plurality of conductive source region parts are distributed on the upper surface of the second conductive type body region layer (5), a gate groove (10) is embedded in the non-conductive source region part-covered area on the upper surface of the second conductive type body region layer (5), and the bottom depth of the gate groove (10) is lower than the depth of the lower surface of the second conductive type body region layer (5), the inner bottom surface and the inner side wall of the gate groove (10) are covered with a gate dielectric layer (3), and a gate (4) is filled in the area surrounded by the gate dielectric layer (3); The number of metal parts (11) is equal to the number of conductive source area parts, each metal part (11) corresponds to each conductive source area part one by one, and each metal part (11) is arranged on the upper surface of the corresponding conductive source area part; the intersection between the gate grooves (10) in different directions constitutes a gate groove node, the number of the second conductive type electric field shielding area (9) is equal to the number of the gate groove nodes, each second conductive type electric field shielding area (9) is arranged in the first conductive type epitaxial layer (2), and each second conductive type electric field shielding area (9) is arranged at the outer bottom of the corresponding gate groove node, and each second conductive type electric field shielding area (9) extends to contact the second conductive type body region layer (5) area connected to its corresponding gate groove node.

2. A power device with low on-resistance according to claim 1, characterized in that: The conductive source region component comprises a second conductive type source region (6) and a first conductive type source region (7) having the same regular polygonal surface shape, and the regular polygon is the regular polygonal shape of the surface of the conductive source region component, the thickness of the second conductive type source region (6) and the thickness of the first conductive type source region (7) are both equal to the thickness of the conductive source region component, the outer diameter of the first conductive type source region (7) is greater than the outer diameter of the second conductive type source region (6), the second conductive type source region (6) is embedded in the first conductive type source region (7), and the surface of the second conductive type source region (6) is located on the same plane as the surface of the first conductive type source region (7). The surfaces are parallel to each other, and the surfaces where the two surfaces of the second conductive type source region (6) are located are coplanar with the surfaces where the corresponding side surfaces of the first conductive type source region (7) are located, the center position of the second conductive type source region (6) overlaps with the center position of the first conductive type source region (7), and the side edges of the second conductive type source region (6) are parallel to the side edges of the first conductive type source region (7) in a one-to-one correspondence; in a direction perpendicular to the surface of the conductive source region, the projection of the second conductive type source region (6) is located within the projection of its corresponding metal member (11), and the projection of the metal member (11) is located within the projection of its corresponding conductive source region.

3. A power device with low on-resistance according to claim 1 or 2, characterized in that: Each second conductive type electric field shielding region (9) covers an area at the outer bottom of its corresponding gate trench node, and the proportion of the area at the outer bottom of the corresponding gate trench node is within a preset fluctuation range of about one quarter.

4. A power device with low on-resistance according to claim 1 or 2, characterized in that: Each second conductive type electric field shielding region (9) covers the entire area of ​​the outer bottom of its corresponding gate trench node, and each second conductive type electric field shielding region (9) extends around its corresponding gate trench node to contact the area of ​​the second conductive type body region layer (5) connected thereto.

5. A power device with low on-resistance according to claim 4, characterized in that: In a direction perpendicular to the outer bottom surface of the gate trench node, each second conductive type electric field shielding region (9) is projected into a symmetrical shape.

6. A power device with low on-resistance according to claim 5, characterized in that: In a direction perpendicular to the outer bottom surface of the gate trench node, each second conductive type electric field shielding region (9) is projected in a quadrilateral, a circle, a triangle or a hexagon.

7. A power device with low on-resistance according to claim 2, characterized in that: The first conductive type substrate (1) and the second conductive type electric field shielding region (9) have a first ion doping concentration, the first conductive type epitaxial layer (2) and the second conductive type body layer (5) have a second ion doping concentration, and the second conductive type source region (6) and the first conductive type source region (7) have a third ion doping concentration, wherein the first ion doping concentration is greater than or equal to the second ion doping concentration, and the third ion doping concentration is greater than the second ion doping concentration.

8. A power device with low on-resistance according to any one of claims 1 to 7, characterized in that: The regular polygonal surface of the conductive source region is a regular triangle, a regular quadrilateral, or a regular hexagon.

9. A method for manufacturing a power device with low on-resistance according to any one of claims 1 to 8, characterized in that: The steps include: Step A. constructing a first conductivity type epitaxial layer (2) based on the growth on the upper surface of the first conductivity type substrate (1), and then constructing various second conductivity type body region layers (5) on the upper surface of the first conductivity type epitaxial layer (2); Step B. using an ion implantation process to form a second conductivity type source region (6) and a first conductivity type source region (7) on the upper surface of each second conductivity type body region layer (5), respectively, and the second conductivity type source region (6) and the first conductivity type source region (7) on the upper surface of each second conductivity type body region layer (5) constitute a conductive source region component; Step C. constructing a gate trench (10) between adjacent second conductivity type body region layers (5) by using an etching process, and forming a gate dielectric layer (3) on the inner bottom surface and inner sidewall of the gate trench (10) by using a chemical vapor deposition process; and depositing a gate material in the gate trench (10) by using a chemical vapor deposition process to form a gate (4); Step D. for each gate trench node formed by the intersection of the gate trenches (10) in different directions, a second conductive type electric field shielding region (9) is formed at the outer bottom of the gate trench node by means of inclined ion implantation, and the second conductive type electric field shielding region (9) extends to contact the second conductive type body region layer (5) region connected to the corresponding gate trench node; Step E: For each conductive source region component, use a sputtering process to form a metal component (11) on the upper surface of the conductive source region component. The metal member (11) is connected to the second conductive type source region (6) and the first conductive type source region (7); Step F: forming a bottom metal layer (8) on the lower surface of the first conductive type substrate (1).

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