Trench gate design and manufacturing for a power mosfet

Abstract

A power semiconductor device and method of forming the same, the power semiconductor device comprising a substrate; a drift region formed above the substrate; a first trench region formed in the drift region, the first trench region extending longitudinally from a surface of the drift region towards the substrate; and a second trench region formed in the drift region, the second trench region extending longitudinally from the surface of the drift region towards the substrate. The first and second trench regions each comprise an isolation layer formed along a sidewall and a base of the first and second trench regions; and the first and second trench regions are positioned laterally adjacent to each other such that they are separated by only the isolation layers.

Description

[0001] Trench Gate Design and Manufacturing for a Power MOSFET

[0002] Field of Disclosure

[0003] The present application relates to trench gate designs in power devices with a MOS structure, and in particular but not limited to high power density Si trench power devices with an MOS structure.

[0004] Background

[0005] High power Silicon Carbide (SiC) MOSFETs are generally considered to be one of the most promising power semiconductor technologies of the next decade. In particular, by utilising trench gate technology, static and dynamic performances of SiC MOSFETS can be improved compared with planar gate structures.

[0006] Figure 1 shows an example state of the art trench gate MOSFET 100. The device comprises a substrate 4, a drift region or epitaxial layer 3, a P-well or body region 2 and a contact metallization source 1. The structure of the trench gate MOSFET 100 can increase the power density and reduce the dynamic on state resistance (Rdson) of the device. However, the structure of the device can result in a high electric field being concentrated at the bottom and corner(s) of the trench gate oxide 5, which can lead to breakdown failures. For example, with state of the art gate oxide SiO2 technology, such as that shown in Figure 1 , the maximum allowed electric field in the SiO2 material is typically below 4MV / cm. However, Because the permittivity of SiC is about 2.5 times of Silica (SiO2), the electric field in SiO2 is about 2.5 times of that in SiC.

[0007] Therefore, it is desirable to lower the gate oxide electric field in SiC MOSFETs because of the high potential of bottom oxide and electric field concentration effects at the trench oxide corners.

[0008] An existing attempt to solve these issues is shown in Figure 1. A P type implantation 6 is provided under the bottom of the trench gate oxide 5 to help push the high electric field away from the trench gate oxide 5. This helps to reduce the electric field strength at the trench oxide layer to thereby reduce the risks of breakdown. Despite developments such as this, the reliability of SiC MOSFET trench gate designs remains an issue, and manufacturers remain limited in their available options for reliable trench gate SiC MOSFET designs for high volume production. The Applicant has therefore recognised a need for a new design of trench gates for power MOSFET cells to provide effective trench gate oxide protection in a manner that remains cost effective for device processing.

[0009] US10608105B2 describes a substrate for a metal oxide semiconductor field effect transistor. The substrate is characterized in that an implantation depth (P) of the p+ implantation is at least as great as a depth of the trench. The deep p+ implantation can separate adjacent trenches in such a way that a field can no longer attack a gate oxide because it is directed around the gate oxide.

[0010] DE102011052473B4 describes a semiconductor device with a silicon carbide semiconductor body. A trench extends into the silicon carbide semiconductor body. A body zone of a first conductivity type adjoins to a sidewall of the trench, the body zone being electrically coupled to a contact via a body contact zone including a higher maximum concentration of dopants than the body zone.

[0011] WO2018161412A1 describes a SiC dual-trench MOSFET device having an integrated Schottky diode. Two trenches are provided in a cell structure of an active region of the SiC dual-trench MOSFET device, said trenches being a gate trench which is provided in the center of the cell structure and a source trench which is arranged at the periphery of the gate trench.

[0012] JP6667893B2 describes a semiconductor device and a semiconductor device manufacturing method which can prevent aging degradation due to a bipolar operation and reduce leakage current of a parasitic pn diode.

[0013] US2022 / 0069088 A1 describes a SiC semiconductor device including a SiC semiconductor layer of a first conductivity type having a main surface, a source trench formed in the main surface and having a side wall and a bottom wall.

[0014] Summary

[0015] Aspects and preferred features are outlined in the accompanying claims.

[0016] According to a first aspect of the present disclosure, there is provided a power semiconductor device comprising: a substrate; a drift region formed above the substrate; a first trench region formed in the drift region, the first trench region extending longitudinally from a surface of the drift region towards the substrate; a second trench region formed in the drift region, the second trench region extending longitudinally from the surface of the drift region towards the substrate; wherein the first and second trench regions each comprise an isolation layer formed along a sidewall and a base of the first and second trench regions; and wherein the first and second trench regions are positioned laterally adjacent to each other such that they are separated by only the isolation layers.

[0017] By providing adjacent trench regions for the source and gate electrodes, a cell pitch and mesa of the semiconductor device can be reduced. This may facilitate improved cell and therefore current density of the device. The provision of a thin isolation layer to separate the trenches assist in reducing leakage and maintaining the reliability of the resulting device.

[0018] The isolation layer may comprise an oxide material such as silica, or any other suitable material such as silicon nitride. The isolation layer may be thin, e.g. having a thickness of about 0.1 m or less, such as 0.06pm. In implementations, separate isolation layers may be provided in each of the first and second trench regions, such that the first and second trench regions are separated by two thin isolation layers.

[0019] In implementations, the first trench region has a greater longitudinal dimension than the second trench region. For example, the first trench region may have a depth in the longitudinal dimension of between about 1 pm and about 3pm, while the second trench region may have a depth in the longitudinal dimension of between about 0.5pm and about 2pm.

[0020] The drift region may be a region of a first conductivity type, and wherein the semiconductor device further comprises a doped region of a second conductivity type at least partially surrounding the first trench region. For example, the drift region may have an n-type doing, while the doped region has a p-type doping or vice versa. The doped region may be formed to partially surround the first trench region such that it is positioned between the first trench region and the drift region.

[0021] An aim of the present disclosure is to provide a trench gate power semiconductor with reduced a gate leakage to thereby enhance a reliability of a trench gate in a semiconductor power device. One method for this is to provide high energy implantation of p-type impurities. However, high energy implantations are difficult and costly to manufacture. Thus, the present disclosure provides a source trenches beside the gate trench, and implants p-type impurities into the sidewalls and bottom of the source trench. In this manner, the semiconductor device may provide the same reliability enhancements as deep high energy implantations, but which is able to be manufactured in a cost effective manner.

[0022] Thus, the deep source trench may be formed first and followed by surrounded by p+ implantation, such that the implantation of the p+ doped region into the sidewalls and bottom of the source trench is shallow and hence does not require high energy implantation techniques.

[0023] In implementations therefore, a source electrode may be formed in the first trench region and a gate electrode may be formed in the second trench region. The first and second trench regions may therefore be referred to as source and gate trenches, respectively.

[0024] One or both of the isolation layers formed along the sidewall and the base of the first and second trench regions may comprise a doped channel region adjacent to the sidewall of the respective first and second trench regions.

[0025] In implementations, the first trench region and the second trench region may form a first cell, and wherein the semiconductor device further comprises one or more second cells spaced laterally apart from the first cell, each second cell comprising: a third trench region formed in the drift region, the third trench region extending longitudinally from a surface of the drift region towards the substrate; a fourth trench region formed in the drift region, the fourth trench region extending longitudinally from the surface of the drift region towards the substrate; wherein the third and fourth trench regions each comprise a second isolation layer formed along a sidewall and a base of the third and fourth trench regions; and wherein the third and fourth trench regions are positioned laterally adjacent to each other such that they are separated by only the second isolation layers.

[0026] The proximity of the source and gate trenches may facilitate the placement of additional cells within the same surface area of the device, to thereby increase the cell and current density. For example, a cell pitch of the first cell and the one or more second cells may be 2pm or less.

[0027] In implementations, the semiconductor device is a SiC MOSFET device. More generally, the present disclosure may be applicable to any high voltage high power density Si trench power devices with MOS structure, such as super junction MOSFET, IGBT etc. or other SiC power devices with MOS structure, such as super junction MOSFET, SiC IGBT. Additionally, the trench gate structures described herein may be provided in other wide bandgap power devices with MOS structure, such as AI2O3, AIGaN, AIN MOS devices.

[0028] According to a second aspect of the present disclosure, there is provided a method of forming a power semiconductor device, the method comprising: forming an epitaxial layer above a substrate; forming one or more first trenches in the epitaxial layer, the one or more first trenches extending longitudinally from a surface of the epitaxial layer towards the substrate; forming a first isolation layer on a side wall and base of the one or more first trenches; forming one or more second trenches in the epitaxial layer, the one or more first trenches extending from a surface of the epitaxial layer towards the substrate, wherein each of the one or more second trenches is formed adjacent to a respective first trench of the one or more first trenches; and forming a second isolation layer on a side wall and base of the one or more second trenches; wherein the one or more second trenches are each separated from their respective first trenches by only the first and second isolation layers.

[0029] Each of the one or more first trenches may be formed with a greater longitudinal dimension than the one or more second trench regions. For example, the one or more first trenches may each have a depth in the longitudinal dimension of between about 1 m and about 3pm, and the one or more second trenches may each have a depth in the longitudinal dimension of between about 0.5pm and about 2pm.

[0030] In implementations, the epitaxial layer may be formed with a first conductivity type, and the method comprises forming a doped region of a second conductivity type on a side wall and base of the one or more first trenches. The doped region may partially surround each of the one or more first trenches such that it is positioned between each of the one or more first trenches and the epitaxial layer.

[0031] Forming the doped region comprises implanting a doped material into the side wall and base of the one or more first trenches. As previously described, implanting the doped material into the side walls and base of a trench provide similar advantages to high energy deep implantation of a doped region, without requiring the costs and challenges of said high energy deep implantations. The first and second isolation layers may be formed with a thickness of about 0.1 pm or less, for example a thickness of about 0.06pm.

[0032] The method may further comprise forming a source electrode in each of the one or more first trenches and forming a gate electrode in each of the one or more second trenches.

[0033] In implementations, the method comprises forming a plurality of first trenches and a plurality of second trenches, to thereby provide a multi-cell structure.

[0034] Brief Description of the Figures

[0035] Some preferred embodiments of the invention will now be described, by way of example only and with reference to the accompanying drawings, in which:

[0036] Figure 1 illustrates an example power trench gate device.

[0037] Figure 2 illustrates an example power trench gate device according to the present disclosure.

[0038] Figure 3 illustrates an example alternative trench gate design.

[0039] Figure 4 illustrates a further example alternative trench gate design.

[0040] Figures 5a-r illustrate example manufacturing process steps for a power trench gate device according to the present disclosure.

[0041] Figure 6 illustrates a further example power trench gate device according to the present disclosure.

[0042] Detailed Description of the Preferred Embodiments

[0043] Figure 2 illustrates an example trench gate power MOSFET 200 according to the present disclosure comprising a substrate 201 and a drift region 202. In device 200, each SiC MOSFET cell structure comprises a gate trench 203 and an adjacent source trench 204 comprising gate and source electrodes respectively. The walls and base of each source and gate trench may comprise a thin (e.g. 0.1 m or less) isolation layer 206, such as an oxide layer. The isolation layer 206 separates the source and gate trench from one another, to thereby isolate the gate and source trench electrodes. This in turn facilitates a closer placement of the source and gate trenches to reduce a cell pitch and mesa, thereby increasing a current density and reducing an on state resistance of device 200. For example, the device 200 may have a cell pitch of 2pm or less. The isolation layer 206 therefore serves to both protect the trench gate electrode and to increase the cell density of device 200.

[0044] Other materials, such as silicon nitride, can be used to instead of or in addition to the oxide layer to isolate the source and gate trenches.

[0045] While device 200 is depicted with three cells each comprising respective gate and source trenches, it will be understood that more or fewer cells may be provided according to the needs of the device. More generally, the device 200 may be provided with one or more such cells.

[0046] In order to further assist in the protection of the trench gate electrode (i.e. by mitigating the electric field at bottom and corners of the trench then improving long term reliability and reducing leakage), each source trench 204 is deeper than the adjacent trench gate 203. For example, a source trench 204 may have a depth of between 1 pm and 3pm, while a trench gate 203 may have a depth of 0.5pm to 2pm. Generally speaking, deeper source and gate trenches provide superior operational performance, but at a cost of more difficult or more expensive manufacturing processes.

[0047] Each source trench 204 is at least partially surrounded by doped (P+) regions 205. P+ regions 205 may be provided by e.g. P+ implantations into the sidewalls and bottom of the trench. The P+N- junction formed between the P+ region 205 and the drift region 202 assist in further protecting the trench gate electrode, as the electric field distribution is pushed down deeper into the drift region 203 and therefore further away from the trench gate electrode.

[0048] By etching a deep source trench and prior to p+ implantation, the p+ implementation to form region 205 may be shallow enough to not require high energy implantation techniques, while still providing effective protection of trench the gate electrode.

[0049] The device 200 therefore may combine the benefits of high energy implantation and a deep source trench while maintaining a cost effective manufacturing process to provide a trench gate MOSFET with improved of reliability.

[0050] While device 200 is depicted with an n-type drift region 202 and p-type doped regions 205, it will be understood that the conductivity type of these regions may be swapped to provide a p- type drift region with n-type doped implantation regions. It will be understood that various implementations of a device according to the present disclosure may be provided. For example, the gate and source trench shapes and dimensions (e.g. width, depth, etc.) may vary according to the specific needs and desired functionality of the specific device.

[0051] Figure 3 depicts one such example variation of a trench gate MOSFET design. The device of Figure 3 comprises a V-groove trench 301 that may be provided as a trench gate for a MOSFET device according to the present disclosure. In this example implementation, the buried p-region 302 may be grounded to thereby reduce the reverse transfer capacitance, and thus improve the switching time and dynamic performance of the device. It will be understood that additional source trenches may be provided adjacent to the V-shaped trench gates of such a device in a similar manner to the single gate device shown in Figure 2, i.e. such that the source trench or trenches are deeper than the respective adjacent V-shaped trench gate and separated from the trench gate only by a thin isolation layer.

[0052] A further variation is depicted in Figure 4. Figure 4 shows a split gate device comprising an N+ Substrate 401 , N- epitaxy layer 402, a P well 403, Gate trench(es) 404 comprises Gate oxide 405, Poly silicon 406, N+ source 407, Source metal 408 and a Floating P region 409. The split gate trenches 404 may be provided adjacent to a source trench in a device according to the present disclosure. As depicted in Figure 4, the bottom of the gate trenches has a thick oxide implant p region 409 that facilitates an increase in the gate oxide 405 reliability and reduces the gate capacitance, effects which are particularly advantageous for SiC trench gate MOSFET devices. It will be understood that additional source trenches may be provided adjacent to and between the trenches of such a split gate device in a similar manner to the single gate device shown in Figure 2, i.e. such that the source trench or trenches are deeper than the respective adjacent trench gates and separated from them only by a thin isolation layer.

[0053] Figures 5a-r depict an example process for manufacturing a MOSFET device according to the present disclosure, such as device 200 of Figure 2. In particular, the following example process flow shows four main example process modules, including:

[0054] 1. Source trench etching, reshaping and poly filling

[0055] 2. n+, p well and p+ implantation and activation annealing

[0056] 3. Gate trench etching and reshaping

[0057] 4. Gate oxidation and further general processes Figure 5a depicts a first step of the example process flow. A buffer layer 502 is provided above a substrate 501 and below an epitaxial layer 503. It will be understood that the dimensions provided for these layers are merely illustrative examples, and that the dimensions of the layers may be varied according to the needs of the device. The epitaxial layer is etched to produce one or more source trenches 504. The trenches 504 may be formed by e.g. dry etching and may have a depth of between e.g. 1 m and 3pm. Optionally the process may comprise a step of trench annealing, to further enhance the shape and smoothness of the trenches 504. For example, the trenches may be annealed at 1400°C for 30s.

[0058] In Figure 5b, several materials may be deposited in on the surface of the device. This may include e.g. Liquid Phase Chemical Vapour Deposition (LPCVD) of a first Tetraethyl orthosilicate (TEOS) layer on the front side and back side of the device. The first TEOS layer may be e.g. ~30nm thick. An undoped polysilicon material may then be deposited on the device to fill the trenches 504. Optionally, the polysilicon material may be etched (e.g. dry etched) and / or oxidised to provide a polysilicon oxidation layer with a thickness of e.g. 400nm. Finally, a second LPCVD process may deposit a second e.g. 30nm thick layer of TEOS on the front side and back side of the device.

[0059] In Figures 5c and d, a n+ region 507 may be provided. For example, the n+ region 507 may be implanted via Nitrogen Ion implantation 506 using a perpendicular ion-beam at 0°. A p-well region 508 may also be provided, as shown in Figures 5e and f, for example via Aluminium ion implantation using a using a perpendicular ion-beam at 0°. Various Al doses and energies may be provided depending on the needs of the device.

[0060] In Figure 5g, the device may be etched (e.g. via wet etching oxidisation) to remove the thermal oxide, polysilicon and TEOS layer(s) deposited in the process steps shown in Figure 5b.

[0061] In Figure 5h and i, a p+ region 510 may be formed on the side walls and base of the trench(es) 504. The p+ region may be provided via e.g. Aluminium ion implantation 509. Optionally, additional p+ regions 511 may be formed via the same or subsequent ion implantation steps, such as p-contact, p-shielding and / or floating field ring regions.

[0062] In Figure 5j, activation annealing may be performed. The activation annealing may comprise, for example, heating the device at 1700°C for 30min in an Argon atmosphere. The activation annealing may form a capping layer 512 out of carbonized photoresist due to the high temperature. As a result, optionally the capping layer and / or a sacrificial oxidation may be removed, as shown in Figure 5k.

[0063] In Figure 51, a trench oxide layer 513 may be deposited. The trench oxide layer 513 may comprise e.g. a TEOS layer with a thickness of ~55nm, and may be provided with no annealing step. Additionally, LPCVD processes may be used to deposit doped polysilicon. The doped polysilicon may then be etched (e.g. via wet etching), as shown in Figure 5m, such that the doped polysilicon is provided in only the trench(es) 504.

[0064] In Figure 5n, one or more gate trenches 514 are etched adjacent to source trenches 504. The trenches 514 may be formed by e.g. dry etching and may have a depth of between e.g. 0.5pm and 2pm. As with the source trenches 504, the process may optionally comprise a step of trench annealing, to further enhance the shape and smoothness of the trenches 514 as depicted in Figure 5o. For example, the trenches may be annealed at 1400°C for 30s.

[0065] In Figures 5p, a further trench oxide layer 515 may be deposited. The trench oxide layer 515 may comprise e.g. a TEOS layer with a thickness of ~55nm, and may be provided with no annealing step. Additionally, LPCVD processes may be used to deposit doped polysilicon. The doped polysilicon may then be etched (e.g. via wet etching), as shown in Figure 5q such that the doped polysilicon is provided in only the trench(es) 514.

[0066] Thus, via the process steps depicted in Figures 5I and p, both the source trench(es) 504 and their adjacent gate trench(es) 515 may be provided with an isolating oxide layer on their sidewalls and base, and filled with a doped polysilicon material. It will be understood that alternative materials may also be used in variations of the process. For example, the isolating layer may be provided by silicon nitride.

[0067] In Figure 5r, a field oxide layer may be provided. For example, LPCVD processes may be used to deposit a TEOS layer on the front and back sides. Additionally, and SiO2 layer present on the back side of the device may be removed. Finally, contacts may be provided for the device. Any suitable contacts may be used. In implementations, this may include or comprise source ohmic metal deposition sputtering to provide a thin NiAl layer or contact, metallization source and gate sputtering to provide Ti / AI / Ni layers or contacts, back grinding, ohmic contact and laser annealing, and / or back metallization with Al / Ti / N i / Ag.

[0068] It will be understood that the example process flow according to Figures 5a-r depicts only one options for the manufacturing of a device according to the present disclosure. For example, while implementations of the present disclosure, such as Figure 2, depict a channel formed in the p-well adjacent to one side of a trench gate, a channel may instead be provided adjacent to or near both sides of a trench gate. In one implementation, the gate trench and source trench may have a small separation, such that a channel may be provided at both sides of the trench gate. In other words, while a crystal face is used for the channel in the depicted process of Figures 5a-r, the other side of the gate trench can also be used for the channels.

[0069] Thus, in some implementations, the gate trench and source trench are separated by implanted doped regions, such as both silicon oxide and SiC, to thereby facilitate the use of both sidewalls of the gate trench as channels. An example implementation of such a device is shown in Figure 6. In device of Figure 6, p-well and n-doped regions 606 are provided to separate each trench gate 602 and source trench 604, rather than being provided only to separate each cell region as in the device 200 of Figure 2. In other words, each source and gate trench in Figure 6 is separated from one another by both an isolation layer and a doped region.

[0070] A device produced according to the steps depicted in Figures 5a-r may therefore provide a P+N- junction in a deep drift region to thereby protect a trench gate electrode. In particular, the use of deep source trench etching may provide a deep baseline for the following p+ implantation, which may allow the manufacturing process to avoid or reduce the use of high energy implantation techniques. The implantation of the p+ regions into the deep source trench means that the P+N- junction is pushed down deep into the drift region, and thereby assists in keeping the electric field away from the trench gate electrode during the off state of the device.

[0071] Advantageously therefore, the deep source trench etching may provide a source trench that is deeper than the gate trench, to thereby enhance the protection provided to the gate electrode.

[0072] Moreover, the gate trench and source trench may be separated solely by a thin isolation layer, such as an oxide layer. It will however be understood that a gap may also be provided between the trenches, such that there is additional material (such as SiC) between the source and gate trench. The presence of the additional isolating material between the trenches may further enhance the isolation of the trenches.

[0073] More generally however, by separating the gate trench and source trenches by only a thin isolation layer, the gate trench may be provided adjacent to the source trench to reduce cell pitch and increase current density. Thus, after the source trench etching and implantations steps, the gate trench may be etched close to the source trench. A thin layer of silicon oxide is used to separate the gate trench and source trench, also act as the gate oxide. The cell pitch is therefore effectively reduced to thereby increase the cell and current density of the device.

[0074] The skilled person will understand that in the preceding description and appended claims, positional terms such as ‘above’, ‘below’, ‘adjacent, ‘under’, etc. are made with reference to conceptual illustrations of an apparatus, such as those showing standard cross-sectional perspectives and those shown in the appended drawings. These terms are used for ease of reference but are not intended to be of limiting nature. These terms are therefore to be understood as referring to a device when in an orientation as shown in the accompanying drawings.

[0075] Although the disclosure has been described in terms of preferred embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives in view of the disclosure, which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may be incorporated in the disclosure, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein.

Claims

CLAIMS:

1. A power semiconductor device comprising: a substrate; a drift region formed above the substrate; a first trench region formed in the drift region, the first trench region extending longitudinally from a surface of the drift region towards the substrate; a second trench region formed in the drift region, the second trench region extending longitudinally from the surface of the drift region towards the substrate; wherein the first and second trench regions each comprise an isolation layer formed along a sidewall and a base of the first and second trench regions; and wherein the first and second trench regions are positioned laterally adjacent to each other such that they are separated by only the isolation layers.

2. The power semiconductor device of claim 1 , wherein first trench region has a greater longitudinal dimension than the second trench region.

3. The power semiconductor device of claim 2, wherein: the first trench region has a depth in the longitudinal dimension of between about 1 m and about 3pm; and the second trench region has a depth in the longitudinal dimension of between about 0.5pm and about 2pm.

4. The power semiconductor device of any preceding claim, wherein the drift region is a region of a first conductivity type, and wherein the semiconductor device further comprises a doped region of a second conductivity type at least partially surrounding the first trench region.

5. The power semiconductor device of claim 4, wherein the doped region partially surrounds the first trench region such that it is positioned between the first trench region and the drift region.

6. The power semiconductor device of any preceding claim, wherein the isolation layer comprises an oxide material.

7. The power semiconductor device of any preceding claim, wherein the isolation layer has a thickness of about 0.1 pm or less.

8. The power semiconductor device of claim 7, wherein the isolation layer has a thickness of 0.06pm.

9. The power semiconductor device of any preceding claim, further comprising a source electrode formed in the first trench region; and a gate electrode formed in the second trench region.

10. The power semiconductor device of any preceding claim, wherein the first trench region and the second trench region form a first cell, and wherein the semiconductor device further comprises one or more second cells spaced laterally apart from the first cell, each second cell comprising: a third trench region formed in the drift region, the third trench region extending longitudinally from a surface of the drift region towards the substrate; a fourth trench region formed in the drift region, the fourth trench region extending longitudinally from the surface of the drift region towards the substrate; wherein the third and fourth trench regions each comprise a second isolation layer formed along a sidewall and a base of the third and fourth trench regions; and wherein the third and fourth trench regions are positioned laterally adjacent to each other such that they are separated by only the second isolation layers.

11. The power semiconductor device of claim 10, wherein a cell pitch of the first cell and the one or more second cells is about 2pm or less.

12. The power semiconductor device of any preceding claim, wherein the semiconductor device is a SiC MOSFET device.

13. The power semiconductor device of any preceding claim, wherein one or both of the isolation layers formed along the sidewall and the base of the first and second trench regions comprise a doped channel region adjacent to the sidewall of the respective first and second trench regions.

14. A method of forming a power semiconductor device, the method comprising: forming an epitaxial layer above a substrate; forming one or more first trenches in the epitaxial layer, the one or more first trenches extending longitudinally from a surface of the epitaxial layer towards the substrate; forming a first isolation layer on a side wall and base of the one or more first trenches;forming one or more second trenches in the epitaxial layer, the one or more first trenches extending from a surface of the epitaxial layer towards the substrate, wherein each of the one or more second trenches is formed adjacent to a respective first trench of the one or more first trenches; and forming a second isolation layer on a side wall and base of the one or more second trenches; wherein the one or more second trenches are each separated from their respective first trenches by only the first and second isolation layers.

15. The method of claim 14, wherein each of the one or more first trenches are formed with a greater longitudinal dimension than the one or more second trench regions.

16. The method of claim 15, wherein: the one or more first trenches each have a depth in the longitudinal dimension of between about 1 m and about 3pm; and the one or more second trenches each have a depth in the longitudinal dimension of between about 0.5pm and about 2pm.

17. The method of any one claims 14-16, wherein the epitaxial layer has a first conductivity type, and wherein the method comprises: forming a doped region of a second conductivity type on a side wall and base of the one or more first trenches.

18. The method of claim 16 or 17, wherein forming the doped region comprises implanting a doped material into the side wall and base of the one or more first trenches19. The method of any one of claims 14 to 18, wherein the first and second isolation layers are formed with a thickness of about 0.1pm or less.

20. The method of claim 19, wherein the first and second isolation layers are formed with a thickness of about 0.06pm.

21. The method of any one of claims 14 to 20, further comprising forming a source electrode in each of the one or more first trenches; and forming a gate electrode in each of the one or more second trenches.

22. The method of any one of claim 14 to 21 , further comprising forming a plurality of first trenches and a plurality of second trenches.

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