Semiconductor device and method for manufacturing semiconductor device

Abstract

This invention minimizes destruction of a gate insulation film in a semiconductor device having the gate insulation film different in thickness. This semiconductor device is provided with: a plurality of trenches that reach the inside of a drift layer from the upper surface of a source region via a base region; and a pull-up electrode that is provided across the plurality of trenches and electrically connects gate electrodes in the trenches. The thickness of the gate insulation film at a cell part is defined as a first thickness, and the thickness of the gate insulation film at a pull-up part is defined as a second thickness. The second thickness is greater than the first thickness. The height of the upper surfaces of the gate electrodes is lower than the height of the upper surface of the drift layer at a boundary part.

Description

Semiconductor device and method for manufacturing the same

[0001] The technology disclosed in this specification relates to semiconductor technology.

[0002] In semiconductor devices used as power semiconductor devices, such as trench-type metal-oxide-semiconductor field-effect transistors (MOSFETs), the gate insulating film may be destroyed. In particular, when a voltage is applied to the gate electrode, a higher electric field is concentrated at the corners of the upper part of the trench than at the channel part of the MOSFET, causing the gate insulating film in those parts to be destroyed.

[0003] For example, Patent Document 1 discloses a configuration in which a gate insulating film is formed thicker at the corners of the upper part of the trench to address the above-mentioned problem.

[0004] Japanese Patent Application Laid-Open No. 2015-230932

[0005] However, even when the configuration shown in Patent Document 1 is adopted, a new problem has been discovered in that the gate insulating film may be destroyed at the boundary between a thin portion and a thick portion of the gate insulating film.

[0006] The technology disclosed in the present specification has been made in consideration of the problems described above, and is a technology for suppressing breakdown of a gate insulating film in a semiconductor device having gate insulating films with different thicknesses.

[0007] a gate electrode surrounded by the gate insulating film and provided in the trench; a source electrode electrically connected to the source region adjacent to the trench; and pull-up electrodes provided across the plurality of trenches and electrically connecting the gate electrodes in the respective trenches; wherein a thickness of the gate insulating film in a cell portion where the source electrode is provided is a first thickness, and a thickness of the gate insulating film in a pull-up portion where the pull-up electrode is provided is a second thickness, the second thickness being greater than the first thickness, and a height of an upper surface of the gate electrode at a boundary portion between the cell portion and the pull-up portion is lower than a height of an upper surface of the drift layer.

[0008] According to at least the first aspect of the technology disclosed in the present specification, the distance between the edge of the upper surface of the trench and the upper surface of the gate electrode is increased, which can reduce the electric field applied to the gate insulating film, thereby suppressing breakdown of the gate insulating film.

[0009] Furthermore, objects, features, aspects, and advantages associated with the technology disclosed herein will become more apparent from the detailed description and accompanying drawings set forth below.

[0010] 6 is a plan view showing an example of the configuration of a semiconductor device according to an embodiment. FIG. 7 is a plan view showing more specifically a configuration corresponding to a region in FIG. 1. FIG. 8 is a plan view showing an example in which a pull-up electrode is provided in a region where a termination trench is formed. FIG. 9 is a cross-sectional view corresponding to the B-B' cross section in FIG. 2. FIG. 10 is a cross-sectional view corresponding to the A-A' cross section in FIG. 2. FIG. 11 is a plan view showing an example of the configuration of a semiconductor device according to an embodiment. FIG. 12 is a cross-sectional view corresponding to the A-A' cross section in FIG. 13. FIG. 13 is a cross-sectional view corresponding to the B-B' cross section in FIG. 14. FIG. 14 is a perspective view showing schematically an example of a gate trench portion of the above structure. FIG. 15 is a diagram showing an example of a manufacturing method of a semiconductor device according to an embodiment. FIG. 16 is a diagram showing an example of a manufacturing method of a semiconductor device according to an embodiment. FIG. 17 is a diagram showing an example of a manufacturing method of a semiconductor device according to an embodiment. FIG. 18 is a diagram showing an example of a manufacturing method of a semiconductor device according to an embodiment. FIG. 19 is a diagram showing an example of a manufacturing method of a semiconductor device according to an embodiment. FIG. 19 is a diagram showing an example of a manufacturing method of a semiconductor device according to an embodiment. 7A and 7B are cross-sectional views showing another example of the configuration corresponding to the cross sections AA' and BB' in FIG. 6.

[0011] Hereinafter, embodiments will be described with reference to the accompanying drawings. In the following embodiments, detailed features are shown for the purpose of explaining the technology, but these are merely examples and are not necessarily essential features for enabling the embodiments to be implemented.

[0012] The drawings are schematic, and for the sake of convenience, components may be omitted or simplified as appropriate. The relative sizes and positions of components shown in different drawings are not necessarily accurately depicted and may be changed as appropriate. Hatching may also be used in drawings such as plan views that are not cross-sectional views to facilitate understanding of the embodiments.

[0013] In the following description, the same components are denoted by the same reference numerals, and their names and functions are also the same. Therefore, detailed descriptions of them may be omitted to avoid duplication.

[0014] Furthermore, in the description given in this specification, when a certain component is described as "comprising," "including," or "having," unless otherwise specified, this is not an exclusive expression that excludes the presence of other components.

[0015] Furthermore, in the description of this specification, even if ordinal numbers such as "first" or "second" are used, these terms are used for convenience to make it easier to understand the contents of the embodiments, and the contents of the embodiments are not limited to the order that may result from these ordinal numbers.

[0016] Furthermore, in the description provided in this specification, terms that indicate specific positions or directions, such as "top," "bottom," "left," "right," "side," "bottom," "front," or "back," may be used, but these terms are used for convenience to facilitate understanding of the contents of the embodiments and have no relation to the positions or directions when the embodiments are actually implemented.

[0017] Furthermore, in the description of the present specification, when "the upper surface of ..." or "the lower surface of ..." is used, it is intended to include not only the upper surface or lower surface of the target component itself, but also a state in which another component is formed on the upper surface or lower surface of the target component. For example, when it is described as "B provided on the upper surface of A," it does not preclude the interposition of another component "C" between A and B.

[0018] First Embodiment A semiconductor device and a method for manufacturing the semiconductor device according to this embodiment will be described below.

[0019] <Configuration of Semiconductor Device> Fig. 1 is a plan view showing an example of the configuration of a semiconductor device according to the present embodiment, in which some components are omitted for convenience.

[0020] As shown in FIG. 1, the semiconductor device 100 includes a cell portion, which is an active region where a plurality of active cells 10 are provided, and a termination region that surrounds the cell portion in a plan view.

[0021] A plurality of gate trenches 6 are formed in the cell area. A termination trench 16 and gate wiring 18 are formed in the termination area.

[0022] Fig. 2 is a plan view showing in more detail the configuration corresponding to the region 101 in Fig. 1. Note that in Fig. 2, some components are omitted for convenience.

[0023] As shown in FIG. 2, in the cell section 20, a source electrode 11 is formed via an ohmic electrode 32.

[0024] In the termination region 30, gate electrodes 17 are formed in gate trenches 6 extending from the cell section 20, and some of the gate electrodes 17 are electrically connected to a pull-up electrode 17A formed across the multiple gate electrodes 17. The pull-up electrode 17A is further connected to the gate electrode 8.

[0025] Furthermore, in the termination region 30, a termination trench 16 is formed to surround the plurality of gate trenches 6 arranged, and an interlayer insulating film 13 and a gate wiring 18 are formed in the termination trench 16. The gate electrode 8 is connected to the gate wiring 18 via an ohmic electrode 25. Note that the gate wiring 18 does not necessarily have to be electrically connected to the gate electrode 17.

[0026] In the termination region 30, a gate trench 26 that is not covered with the source electrode 11 is also formed, and a gate electrode 17 is also formed in the gate trench 26.

[0027] Here, the pull-up electrode 17A may be provided so as to electrically connect the plurality of gate electrodes 17 in the region where the termination trench 16 is formed, rather than in the region of the termination region 30 where the gate trench 6 is formed. However, by providing the pull-up electrode 17A in the region where the gate trench 6 is formed, the chip area as a whole can be reduced, thereby suppressing heat generation and reducing costs.

[0028] 3 is a plan view showing an example in which the pull-up electrode 117A is provided in a region in which the termination trench 16 is formed. As shown in the example in Fig. 3, the pull-up electrode 117A is provided in a position in the termination region 30 so as not to overlap with the gate trench 6. Even when the pull-up electrode 117A is disposed in such a position, the pull-up electrode 117A is connected to each of the gate electrodes 17 so as to electrically connect the gate electrodes 17 together.

[0029] Fig. 4 is a cross-sectional view corresponding to the cross section BB' in Fig. 2. As shown in the example of Fig. 4, semiconductor device 100, which is a MOSFET, includes an n-type silicon carbide semiconductor substrate 1 and an n-type semiconductor layer 2 epitaxially grown on silicon carbide semiconductor substrate 1.

[0030] The cell portion 20, which is the active region of the semiconductor layer 2, is formed with a drift layer 3 made of an n-type silicon carbide semiconductor, a p-type base region 4 provided in the surface layer of the drift layer 3, a plurality of n-type source regions 5 selectively provided in the surface layer within the base region 4, a gate trench 6 extending from the upper surface of the source region 5 through the base region 4 into the drift layer 3, and a p-type diffusion protection layer 9 provided below the bottom surface of the gate trench 6.

[0031] A gate oxide film 7 is formed in the gate trench 6, and a gate electrode 17 is formed surrounded by the gate oxide film 7. An ohmic electrode 32 is provided across the source region 5 and the base region 4, and an interlayer insulating film 13 is formed with the region where the ohmic electrode 32 is formed serving as a source contact 31. A source electrode 11 is formed covering the ohmic electrode 32 and the interlayer insulating film 13 (i.e., the source electrode 11 is electrically connected to the source region 5 via the ohmic electrode 32).

[0032] Meanwhile, in the termination region 30 of the semiconductor layer 2, a termination trench 16 is formed, the bottom of which is located deeper than the base region 4 and in the n-type drift layer 3, and a p-type termination protection layer 19 is provided below the bottom of the termination trench 16. An interlayer insulating film 13 and a gate wiring 18 are formed in the termination trench 16, both surrounded by a gate oxide film 7. An ohmic electrode 25 is provided on the upper surface of the gate wiring 18, and an interlayer insulating film 13 is formed with the region where the ohmic electrode 25 is formed serving as a gate contact 34. Furthermore, a gate electrode 8 is formed covering the ohmic electrode 25 and the interlayer insulating film 13.

[0033] When semiconductor device 100 is configured as an IGBT, silicon carbide semiconductor substrate 1 may have a p-type conductivity.

[0034] Here, the n-type impurity concentration of the drift layer 3 is, for example, 1×10 １４ cm －３ or more, and 1 x 10 １７ cm －３ The thickness of the drift layer 3 may be, for example, not less than 5 μm and not more than 200 μm.

[0035] The p-type impurity concentration of the base region 4 is, for example, 1×10 １７ cm －３ or more, and 1 x 10 ２０ cm －３ The n-type impurity concentration of the source region 5 may be, for example, equal to or higher than the p-type impurity concentration of the base region 4 and equal to or lower than 1×10 ２１ cm －３ The p-type impurity concentration of the diffusion protection layer 9 and the termination protection layer 19 may be, for example, 1×10 １７ cm －３ or more, and 1 x 10 １９ cm －３ The p-type impurity concentration of the diffusion protection layer 9 is preferably the same as or equal to or higher than the p-type impurity concentration of the termination protection layer 19.

[0036] Fig. 5 is a cross-sectional view corresponding to the cross section AA' in Fig. 2. As shown in the example of Fig. 5, the semiconductor device 100 includes an n-type silicon carbide semiconductor substrate 1 and an n-type semiconductor layer 2.

[0037] In a cell portion 20 which is an active region of the semiconductor layer 2, a drift layer 3, a p-type base region 4, an n-type source region 5, a gate trench 6, and a p-type diffusion protection layer 9 are formed.

[0038] Furthermore, a gate oxide film 7 or a gate oxide film 7A is formed in the gate trench 6. The thickness of the gate oxide film 7A is thicker than that of the gate oxide film 7. The gate oxide film 7A is also formed on the upper surface (mesa portion) of the base region 4 and the upper surface (mesa portion) of the source region 5. That is, the gate oxide film 7 in the A-A' cross section in FIG. 2 is thicker in the B-B' cross section in FIG. 2, and the area in which it is formed is also expanded.

[0039] The gate electrode 17 formed in the gate trench 6 and surrounded by the gate oxide film 7A is connected to a pull-up electrode 17A. The pull-up electrode 17A is provided across multiple gate trenches 6 and electrically connects the gate electrodes 17 in the respective gate trenches 6.

[0040] An ohmic electrode 32 is provided on the upper surface of the pull-up electrode 17A, and an interlayer insulating film 13 is formed with the region where the ohmic electrode 32 is formed serving as a source contact 31. Furthermore, a gate electrode 8 is formed to cover the ohmic electrode 32 and the interlayer insulating film 13. The location where the gate electrode 8 and the pull-up electrode 17A contact each other via the ohmic electrode 32 is located above the mesa portion of the semiconductor layer 2. The gate electrode 8 may be extended to a bonding pad for wire bonding connection during chip assembly.

[0041] The configuration of termination region 30 is similar to that described in Fig. 4. Interlayer insulating film 13 is formed in termination trench 16, while polysilicon, which is gate electrode 17, is formed in gate trench 6 and gate trench 26, and layers of different materials are formed in the trenches.

[0042] 6 is a plan view showing an example of the configuration of a semiconductor device according to this embodiment, in which some components are omitted for convenience.

[0043] 6, in the cell region 20, a plurality of gate electrodes 17 are formed and are covered with the source electrode 11 via an interlayer insulating film, etc. In the termination region 30, the gate electrode 8 is connected to the gate wiring 18.

[0044] 7 is a cross-sectional view corresponding to the A-A' cross section in FIG. 6. As shown in the example of FIG. 7, the thickness of the gate oxide film 7 in the A-A' cross section is thin. Furthermore, the height of the upper surface of the gate electrode 17 formed in the gate trench 6 is lower than the upper surfaces (mesa portions) of the base region 4 and the source region 5. In other words, the height of the upper surface of the gate electrode 17 formed in the gate trench 6 is lower than the upper surface (mesa portion) of the drift layer 3. Here, the difference in height between the upper surface of the gate electrode 17 and the mesa portion is defined as X1.

[0045] FIG. 8 is a cross-sectional view corresponding to the B-B' cross section in FIG. 6. As shown in FIG. 8, the thickness of the gate oxide film 7B in the B-B' cross section is thicker than the thickness of the gate oxide film 7 in the A-A' cross section. Furthermore, the height of the upper surface of the gate electrode 17 formed in the gate trench 6 is lower than the upper surfaces (mesa portions) of the base region 4 and the source region 5. That is, the height of the upper surface of the gate electrode 17 formed in the gate trench 6 is lower than the upper surface (mesa portion) of the drift layer 3. Here, if the difference in height between the upper surface of the gate electrode 17 and the mesa portion is X2, X2 is smaller than X1. That is, the height of the upper surface of the gate electrode 17 in the B-B' cross section is higher than the height of the upper surface of the gate electrode 17 in the A-A' cross section. Increasing the difference in height between the mesa portion and the gate electrode 17, X1 or X2, improves the reliability of the gate oxide film. Both X1 and X2 can be changed as appropriate, but are preferably, for example, 10 nm or more and 200 nm or less.

[0046] 9 is a cross-sectional view corresponding to the CC' cross section in FIG. 6. As shown in the example of FIG. 9, the gate oxide film 7A is formed so as to extend over the mesa portion. The thickness of the gate oxide film 7A in the CC' cross section is thicker than the thickness of the gate oxide film 7B in the BB' cross section. The gate electrode 17 formed in the gate trench 6 is connected to a pull-up electrode 17A.

[0047] Here, the cross sections shown in Figures 8 and 9 are included in the termination region 30 surrounding the cell portion 20 shown in Figure 7, but the portion where the pull-up electrode 17A in Figure 9 is formed is the pull-up portion, and the portion sandwiched between the cell portion 20 and the pull-up portion (i.e., the portion including the cross section shown in Figure 8) is the boundary portion.

[0048] With this configuration, in the cell portion 20 and the boundary portion, the distance between the end (corner) of the upper surface of the gate trench 6 and the upper surface of the gate electrode 17 is increased at the end (corner) of the upper surface of the gate trench 6 where the electric field is likely to concentrate. This makes it possible to alleviate the electric field applied to the gate oxide film 7 (or gate oxide film 7B). Note that it is desirable that the entire upper surface of the gate electrode 17 provided in the boundary portion is lower than the mesa portion.

[0049] Furthermore, in the pulled-up portion, the gate oxide film 7A is formed to have a large thickness, so that the electric field applied to the gate oxide film 7 (or gate oxide film 7B) can be alleviated.

[0050] Furthermore, although the thickness of the gate oxide film 7 in the cell portion 20 is thinner than the thickness of the gate oxide film 7B in the boundary portion, by making the height of the upper surface of the gate electrode 17 in the cell portion 20 lower than the height of the upper surface of the gate electrode 17 in the boundary portion, the distance between the end (corner) of the upper surface of the gate trench 6 and the upper surface of the gate electrode 17 is increased, and the electric field applied to the gate oxide film 7 can be alleviated.

[0051] 10 is a perspective view schematically illustrating an example of a gate trench portion of the above structure, in which some components are omitted for convenience.

[0052] 10 , the gate trench 6 is formed to extend from the cell portion 20 toward the termination region 30. In the cell portion 20, a thin gate oxide film 7 is formed in the gate trench 6, and the height of the upper surface of the gate electrode 17 is also lower than that of the mesa portion.

[0053] On the other hand, in the pull-up portion, the pull-up electrode 17A is connected to the gate electrode 17, and a thick gate oxide film 7A is formed in the gate trench 6 and on the mesa portion.

[0054] The thickness of the gate oxide film changes at the boundary (for convenience, this is referred to as gate oxide film 7B), and accordingly the height of the upper surface of gate electrode 17 also changes. However, the change in the thickness of the gate oxide film is not limited to occurring at a specific point at the boundary as shown in Figure 10, and may be such that the thickness of the gate oxide film gradually increases from cell portion 20 toward the pull-up portion, for example.

[0055] In the above configuration, the height of the upper surface of the gate electrode 17 at the boundary is lower than that of the mesa portion.

[0056] <Method of Manufacturing Semiconductor Device> Next, a method of manufacturing the semiconductor device 100 according to this embodiment will be described. Figures 11 to 21 are diagrams showing an example of a method of manufacturing the semiconductor device 100 according to this embodiment.

[0057] 11, 12, 13, and 14 show the steps up to forming the diffusion protection layer 9 at the bottom of the gate trench 6 and the termination protection layer 19 at the bottom of the termination trench 16. Figures 15, 16, and 17 show the steps from forming the diffusion protection layer 9 and the termination protection layer 19 to forming the gate electrode 8. Figures 18 and 19 show the steps from forming the gate electrode 8 to completing the semiconductor device 100.

[0058] 11, an n-type silicon carbide semiconductor substrate 1 having a polytype of 4H is prepared, and an n-type semiconductor layer 2 is epitaxially grown thereon by chemical vapor deposition (CVD). At this time, the n-type impurity concentration of the n-type semiconductor layer 2 is, for example, 1×10 １４ cm －３ or more, and 1 x 10 １７ cm －３ The thickness of the semiconductor layer 2 is, for example, 5 μm or more and 200 μm or less.

[0059] Next, aluminum (Al) ions, which are p-type impurities, are implanted into the surface of the epitaxially grown semiconductor layer 2 to form the base region 4. The depth of the Al ion implantation is set within a range not exceeding the thickness of the semiconductor layer 2, and is set to, for example, 0.3 μm or more and 3 μm or less. The impurity concentration of the Al ions implanted is set higher than the n-type impurity concentration of the epitaxially grown semiconductor layer 2, and the p-type impurity concentration of the base region 4 is set to, for example, 1×10 １７ cm －３ or more, and 1 x 10 ２０ cm －３As a result, the region of the semiconductor layer 2 other than the base region 4, which is deeper than the Al ion implantation depth, becomes the n-type drift layer 3. The base region 4 may be formed by epitaxially growing a p-type semiconductor, and in that case, the p-type impurity concentration and thickness of the base region 4 may be the same as when the base region 4 is formed by ion implantation.

[0060] Next, nitrogen (N), which is an n-type impurity, is selectively ion-implanted into the surface layer of the base region 4 to form the source region 5. The source region 5 is formed in a pattern corresponding to the layout of the gate electrode 8 to be formed in a later process. The depth of the N ion implantation is shallower than the thickness of the base region 4. The impurity concentration of the ion-implanted N is, for example, equal to or greater than the p-type impurity concentration of the base region 4 and is 1×10 ２１ cm －３ The following applies.

[0061] The order of the step of ion implanting Al to form the base region 4 and the step of ion implanting N to form the source region 5 may be reversed. Alternatively, after N ions are implanted into the entire upper part of the base region 4 to form an n-type semiconductor layer, the portion to be left as the source region 5 may be masked, and Al ions may be implanted again into the unmasked portion other than the source region 5 to return to the p-type base region 4. In this case, the impurity concentration of the Al ions implanted again may be made higher than the impurity concentration of Al in the portion of the base region 4 adjacent to the drift layer 3, thereby reducing the contact resistance with the source electrode.

[0062] 12 , a silicon oxide film 41 and an etching mask 42 are formed on the surface of the semiconductor layer 2. The silicon oxide film 41 is formed by deposition to a thickness of 1 μm or more and 2 μm or less, for example, and the etching mask 42 is formed on the upper surface of the silicon oxide film 41. A pattern having openings corresponding to regions where the gate trench 6 and the termination trench 16 are to be formed is formed in the etching mask 42 by photolithography.

[0063] Next, reactive ion etching (RIE) is performed using the etching mask 42 as a mask to pattern the silicon oxide film 41. That is, the pattern of the etching mask 42 is transferred to the silicon oxide film 41, and the silicon oxide film 41 is used as an etching mask for the semiconductor layer 2.

[0064] <Trench Etching> Next, as shown in FIG. 13 , using the patterned silicon oxide film 41 as a mask, a gate trench 6 penetrating the source region 5 and the base region 4, and a termination trench 16 penetrating the base region 4 are formed in the semiconductor layer 2 by RIE processing.

[0065] The depth of gate trench 6 and the depth of termination trench 16 are equal to or greater than the depth of base region 4 formed in semiconductor layer 2 by ion implantation, and may be, for example, 1.0 μm or more and 6.0 μm or less.

[0066] Using the silicon oxide film 41 as a mask, the gate trench 6 and the termination trench 16 are formed.

[0067] <Impurity injection into trench bottom> After forming the gate trench 6 and the termination trench 16, as shown in FIG. 14 , an implantation mask 43 having openings in the same pattern as the silicon oxide film 41 is formed, and Al ions are implanted to form a p-type diffusion protection layer 9 in the drift layer 3 at the bottom of the gate trench 6, and a p-type termination protection layer 19 in the drift layer 3 at the bottom of the termination trench 16.

[0068] The impurity concentration of Al ions to be implanted is, for example, 1×10 １７ cm －３ or more, and 1 x 10 １９ cm －３ The depth of ion implantation is preferably, for example, not less than 0.1 μm and not more than 2.0 μm.

[0069] The impurity concentration of Al to be ion-implanted may be determined from the electric field applied to the gate oxide film 7 when a voltage equal to the breakdown voltage of the semiconductor device 100 is applied between the drain electrode 12 and the source electrode 11 of the semiconductor device 100.

[0070] Note that by adjusting the thickness of silicon oxide film 41 or the etching conditions so that silicon oxide film 41 remains even after forming gate trench 6 and termination trench 16 using silicon oxide film 41 as a mask, the remaining silicon oxide film 41 can be used instead of implantation mask 43 when forming diffusion protection layer 9 and termination protection layer 19. This makes it possible to simplify the manufacturing process and reduce manufacturing costs.

[0071] Furthermore, when forming the diffusion protection layer 9, Al ions are implanted obliquely into the opening of the gate trench 6, thereby forming a p-type semiconductor layer in the drift layer 3 in contact with the side surface of the gate trench 6, and the p-type diffusion protection layer 9 and the p-type base region 4 can be connected by the p-type semiconductor layer. That is, the diffusion protection layer 9 and the source electrode 11 can be electrically connected.

[0072] After the diffusion protection layer 9 and the termination protection layer 19 are formed, the implantation mask 43 used for the ion implantation is removed, and an annealing process is performed using a heat treatment device to activate the implanted impurity ions.

[0073] The annealing treatment is performed in an inert gas atmosphere such as argon (Ar) or in a vacuum, for example, at a temperature of 1300° C. or higher and 1900° C. or lower for 30 seconds or longer and 1 hour or shorter.

[0074] 15, implantation mask 43 is removed, and the upper surface of semiconductor layer 2 is oxidized. The thickness of the oxide film is preferably, for example, about 5 nm or more and 100 nm or less. Thereafter, the oxide film is removed by hydrofluoric acid-based wet etching.

[0075] <Formation of Gate Oxide Film> Next, as shown in Fig. 16, a gate oxide film is deposited by CVD. The thickness of the oxide film is, for example, about 5 nm or more and 100 nm or less, and the deposition temperature is, for example, about 700°C or more and 950°C or less.

[0076] 17, a silicon oxide film 41A is formed as a resist mask so as to cover an area where a thick gate oxide film is desired to be formed. Thereafter, the oxide film in the area not covered by the resist mask is removed by hydrofluoric acid-based wet etching.

[0077] <Polysilicon Deposition> Then, a gate oxide film is deposited again by CVD. The thickness of the oxide film is, for example, about 20 nm or more and 200 nm or less, and the deposition temperature is, for example, about 700° C. or more and 950° C. or less. This process results in the formation of thick and thin gate oxide film regions within the semiconductor device.

[0078] 18 and 19, polysilicon 170 containing a high concentration of phosphorus is deposited. Here, Fig. 18 corresponds to the BB' cross section in Fig. 2, and Fig. 19 corresponds to the AA' cross section in Fig. 2.

[0079] The thickness of the gate oxide film 7A shown in FIG. 19 is thicker than the thickness of the gate oxide film 7 shown in FIG.

[0080] 20 and 21, the deposited polysilicon is etched back. Here, Fig. 20 corresponds to the BB' cross section in Fig. 2, and Fig. 21 corresponds to the AA' cross section in Fig. 2.

[0081] During the etch-back, a resist mask (silicon oxide film 41B) is used to protect a portion of the region, and resist is formed on the portion in the termination region 30 where polysilicon is used as gate wiring, and on the gate contact portion that connects the gate potential in the cell region 20 where the cells are arrayed.

[0082] The gate oxide film 7A is formed thicker in the area where the pull-up electrode 17A is formed from the corner of the upper part of the trench to the mesa portion.

[0083] As shown in FIGS. 7 and 8, the shape of the gate electrode 17 (polysilicon) after etching back is such that the height of the upper surface of the gate electrode 17 (polysilicon) in the gate trench 6 in the cell portion 20 and the boundary portion is lower than the height of the mesa portion. If necessary, etching of the polysilicon may be repeated after forming a resist mask in a further region. In this case, conditions that result in more isotropic etching than the previous etching may be applied. By using etching conditions that result in stronger isotropy, the polysilicon at the upper corners of the trench is etched with high efficiency.

[0084] When the height of the upper surface of the gate electrode 17 in the gate trench 6 is equal, the oxide film electric field of the gate oxide film 7 in the cell portion 20 is higher than that of the gate oxide film 7B in the boundary portion. By lowering the height of the upper surface of the gate electrode 17 surrounded by the gate oxide film 7 in the cell portion 20 in order to alleviate electric field concentration, the distance between the corner at the top end of the trench and the upper surface of the gate electrode 17 can be increased, and the reliability of the gate oxide film 7 in the cell portion 20 can be improved.

[0085] At the boundary, the thickness of the gate oxide film 7B is thinner than the thickness of the gate oxide film 7A in the pulled-up portion, and the height of the upper surface of the gate electrode 17 in the gate trench 6 is higher than the height of the upper surface of the gate electrode 17 in the cell portion 20. Therefore, in order to effectively alleviate the electric field at the boundary, it is important to adjust the height of the upper surface of the gate electrode 17 in accordance with the thickness of the gate oxide film 7B.

[0086] After trench etching, oxidation treatment is performed at, for example, 700° C. to 1050° C. The oxidation time is set so that the thickness of the polysilicon oxide film is, for example, 10 nm to 200 nm.

[0087] The oxidation rate of SiC is lower than that of polysilicon. During oxidation, the oxidizing agent diffuses within the gate oxide film and reacts with the oxidizing agent when it reaches the polysilicon surface, forming an oxide film. For this reason, the polysilicon at the corners of the upper trench is oxidized the most. This results in the gate oxide film gradually becoming thinner in the depth direction.

[0088] Furthermore, as a result of the above, the edge portions of the upper surface of the gate electrode 17 where oxidation has progressed rapidly become concave, and the central portion of the upper surface of the gate electrode 17 relatively protrudes.

[0089] Therefore, the gate oxide film formed relatively thick in the upper part of the trench and the edge of the upper surface of the gate electrode 17 having a concave shape increase the effective distance between the edge of the mesa portion and the upper surface of the gate electrode 17. In other words, it is possible to alleviate the electric field concentration when a gate voltage is applied, and to suppress breakdown of the gate oxide film.

[0090] <Formation of Gate Electrode> Next, the gate electrode 8 is formed. As shown in Figures 4 and 5, an interlayer insulating film 13 is formed on the upper surface of the semiconductor layer 2 by low-pressure CVD to cover the gate electrode 8 and gate wiring 18. Then, by patterning the interlayer insulating film 13, a source contact 31 is formed in the cell section 20, reaching the source region 5 and the base region 4. Furthermore, a gate contact 34 is formed in the termination region 30, reaching the gate wiring 18.

[0091] Thereafter, an ohmic electrode 32 is formed in the source contact 31. An ohmic electrode 25 is also formed in the gate contact 34. The ohmic electrode 32 may be a silicide film formed by forming a metal film mainly composed of nickel (Ni) on the upper surface of the semiconductor layer 2 and then reacting the Ni with the semiconductor through heat treatment at a temperature of 600°C or higher and 1100°C or lower, for example. The ohmic electrode 25 may be a silicide film formed by forming a metal film mainly composed of nickel (Ni) on the upper surface of the gate electrode 17 and then reacting the Ni with the semiconductor through heat treatment at a temperature of 600°C or higher and 1100°C or lower, for example. Thereafter, an Al alloy or the like is deposited on the upper surface of the interlayer insulating film 13, in the source contact 31, and on the gate contact 34 to form metal electrodes.

[0092] The metal electrode is then patterned to separate it into source electrode 11 and gate electrode 8. An Al alloy or the like is then deposited on the surface of silicon carbide semiconductor substrate 1 opposite to the surface on which semiconductor layer 2 is formed to form drain electrode 12. Through the above steps, semiconductor device 100 is formed.

[0093] Second Embodiment A semiconductor device and a method for manufacturing the semiconductor device according to this embodiment will be described. In the following description, components similar to those described in the above embodiments will be denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0094] <Regarding the configuration of the semiconductor device> Fig. 22 is a cross-sectional view showing another example of the configuration corresponding to the A-A' cross section and the B-B' cross section in Fig. 6. As shown in the example in Fig. 22, the depth of the gate trench 6B formed in the B-B' cross section is deeper by X3 than the depth of the gate trench 6 formed in the A-A' cross section.

[0095] 22, the height of the upper surface of gate electrode 17 formed on the A-A' cross section is higher than the height of the upper surface of gate electrode 17 formed on the B-B' cross section, but conversely, the height of the upper surface of gate electrode 17 formed on the A-A' cross section may be lower than the height of the upper surface of gate electrode 17 formed on the B-B' cross section. The height of the upper surface of gate electrode 17 formed on the B-B' cross section tends to be lower as the depth of gate trench 6B formed on the B-B' cross section increases, and tends to be higher as the thickness of gate oxide film 7B formed on the B-B' cross section increases.

[0096] Furthermore, the width of the gate trench 6B formed in the B-B' cross section may be wider than the width of the gate trench 6 formed in the A-A' cross section. The wider the width of the gate trench 6B formed in the B-B' cross section, the lower the height of the upper surface of the gate electrode 17 formed in the B-B' cross section tends to be.

[0097] <Method of Manufacturing Semiconductor Device> Next, a method of manufacturing semiconductor device 200 according to this embodiment will be described. Figures 23 and 24 are diagrams showing an example of a method of manufacturing semiconductor device 200 according to this embodiment. Below, differences from the method of manufacturing semiconductor device 100 according to the first embodiment will be described. The steps up to "implanting impurities into the trench bottom" in the first embodiment are the same as those in the first embodiment.

[0098] 23, a silicon oxide film 41C is deposited as a resist mask and then patterned to open a region where the gate trench 6 is to be made deeper. Then, trench etching is performed on the opening. After this process, the gate trench 6 and the gate trench 6B having different depths are formed.

[0099] The subsequent steps are processed in the same manner as in the first embodiment, as shown in FIG.

[0100] As in the first embodiment, the difference in height of the upper surface of the gate electrode 17 (polysilicon) in the gate trench 6 may be changed by etching back the polysilicon through multiple etching processes.

[0101] Third Embodiment A semiconductor device and a method for manufacturing the semiconductor device according to this embodiment will be described. In the following description, components similar to those described in the above embodiments will be denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0102] <Regarding the configuration of the semiconductor device> Fig. 25 is a cross-sectional view showing another example of the configuration corresponding to the A-A' cross section and the B-B' cross section in Fig. 6. As shown in the example in Fig. 25, the end of the upper surface of gate electrode 17C formed in the A-A' cross section has a concave shape, and the end of the upper surface of gate electrode 17B formed in the B-B' cross section has a concave shape.

[0103] The bird's beak shape of the top surface of the gate electrode increases the effective distance between the edge of the mesa and the top surface of the gate electrode, which reduces the electric field concentration when a gate voltage is applied and prevents breakdown of the gate oxide film.

[0104] If the difference in height (bird's beak length) between the center and end of the upper surface of gate electrode 17C formed on the A-A' cross section is X4 and the difference in height between the center and end of the upper surface of gate electrode 17B formed on the B-B' cross section is X5, X4 is smaller than X5. In other words, the depth of the recess in gate electrode 17C formed on the A-A' cross section is shallower than the depth of the recess in the upper surface of gate electrode 17B formed on the B-B' cross section.

[0105] <Method of Manufacturing Semiconductor Device> Next, a method of manufacturing a semiconductor device according to this embodiment will be described. As shown in the first embodiment, by performing oxidation treatment after etching the polysilicon, the gate oxide film gradually becomes thinner in the depth direction at the corners of the upper part of the trench.

[0106] During oxidation, oxidants diffuse through the gate oxide and react with the adjacent polysilicon to form an oxide film. In this case, thicker gate oxides have more oxidant diffusion than thinner gate oxides.

[0107] Therefore, a thicker oxide film is formed at the boundary portion than at the cell portion 20. That is, the amount of gate oxide film increased at the corners of the upper part of the trench at the boundary portion is greater than that at the cell portion 20. Also, because the oxidation process progresses faster at the boundary portion, the bird's beak length becomes longer than that at the cell portion 20, improving the reliability of the gate oxide film.

[0108] <Regarding the Effects Produced by the Multiple Embodiments Described Above> Next, examples of the effects produced by the multiple embodiments described above will be described. Note that in the following description, the effects will be described based on the specific configurations exemplified in the multiple embodiments described above, but these may be replaced with other specific configurations exemplified in the present specification to the extent that similar effects are produced. In other words, for convenience, only one of the associated specific configurations may be described as a representative below, but the representatively described specific configuration may be replaced with another associated specific configuration.

[0109] Furthermore, the replacement may be made across multiple embodiments, i.e., configurations illustrated in different embodiments may be combined to produce the same effect.

[0110] According to the embodiment described above, the semiconductor device includes an n-type (first conductivity type) drift layer 3, a p-type (second conductivity type) base region 4, an n-type source region 5, multiple trenches, a gate insulating film, a gate electrode 17 (or gate electrode 17B or gate electrode 17C), a source electrode 11, and a pull-up electrode 17A. Here, the multiple trenches correspond to, for example, gate trenches 6, 6B, etc. The gate insulating film corresponds to, for example, gate oxide film 7, 7A, 7B, etc. The base region 4 is provided in a surface layer of the drift layer 3. Multiple source regions 5 are provided in a surface layer of the base region 4. Multiple gate trenches 6 extend from the upper surfaces of the source regions 5 through the base region 4 and into the drift layer 3. The gate oxide film 7 is provided along at least the interior of each gate trench 6. The gate electrode 17 is provided in the gate trench 6, surrounded by the gate oxide film 7. The source electrode 11 is electrically connected to the source region 5 adjacent to the gate trench 6. The pull-up electrode 17A is provided across the multiple gate trenches 6. The pull-up electrode 17A electrically connects the gate electrodes 17 in each gate trench 6. Here, the thickness of the gate oxide film 7 in the cell section 20 where the source electrode 11 is provided is defined as a first thickness. The thickness of the gate oxide film 7B (or gate oxide film 7A) in the pull-up section where the pull-up electrode 17A is provided is defined as a second thickness. Alternatively, the thickness of the gate oxide film 7B (or gate oxide film 7) in the cell section 20 where the source electrode 11 is provided is defined as the first thickness. The thickness of the gate oxide film 7A in the pull-up section where the pull-up electrode 17A is provided is defined as a second thickness. The second thickness is thicker than the first thickness. At the boundary between the cell section 20 and the pull-up section, the height of the upper surface of the gate electrode 17 (or gate electrode 17B) is lower than the height of the upper surface of the drift layer 3.

[0111] With this configuration, the distance between the edge (corner) of the upper surface of the gate trench 6 and the upper surface of the gate electrode 17 is increased, and the electric field applied to the gate oxide film 7 can be alleviated, thereby suppressing breakdown of the gate oxide film 7.

[0112] Furthermore, even if other configurations shown as examples in this specification are appropriately added to the above configuration, that is, even if other configurations in this specification that were not mentioned as the above configuration are appropriately added, the same effect can be achieved.

[0113] Furthermore, according to the embodiment described above, the pull-up portion does not overlap, in plan view, with the gate trench 6. Such a configuration increases the degree of freedom in the location where the pull-up portion is formed.

[0114] Furthermore, according to the embodiment described above, at least a portion of the pull-up portion overlaps, in plan view, with the gate trench 6. With such a configuration, by providing the pull-up electrode 17A in the region where the gate trench 6 is formed, the chip area as a whole can be reduced, thereby suppressing heat generation and reducing costs.

[0115] Furthermore, according to the embodiment described above, the height of the upper surface of the gate electrode 17 in the cell portion 20 is lower than the height of the upper surface of the gate electrode 17 in the boundary portion. With this configuration, the distance between the end (corner) of the upper surface of the gate trench 6 and the upper surface of the gate electrode 17 is increased, and the electric field applied to the gate oxide film 7 can be alleviated. Therefore, even if the thickness of the gate oxide film 7 in the cell portion 20 is thinner than the thickness of the gate oxide film 7B in the boundary portion, breakdown of the gate oxide film 7 can be effectively suppressed.

[0116] Furthermore, according to the embodiment described above, the height of the upper surface of the gate electrode 17 in the cell portion 20 is higher than the height of the upper surface of the gate electrode 17 at the boundary portion. With such a configuration, the height of the upper surface of the gate electrode 17 tends to be lower as the depth of the gate trench 6B increases, tends to be higher as the thickness of the gate oxide film 7B increases, and tends to be lower as the width of the gate trench 6B increases. Therefore, it is possible to determine whether the height of the upper surface of the gate electrode 17 in the cell portion 20 is made higher than the height of the upper surface of the gate electrode 17 at the boundary portion depending on the depth and width of the gate trench 6B or the thickness of the gate oxide film 7B.

[0117] Furthermore, according to the embodiment described above, the depth of the gate trench 6B at the boundary portion is deeper than the depth of the gate trench 6 in the cell portion 20. With this configuration, the height of the upper surface of the gate electrode 17 tends to decrease as the depth of the gate trench 6B increases, and therefore, the depth of the gate trench 6B can be adjusted in order to control the height of the upper surface of the gate electrode 17 at the boundary portion.

[0118] Furthermore, according to the embodiment described above, the width of the gate trench 6B at the boundary portion is wider than the width of the gate trench 6 in the cell portion 20. With such a configuration, the height of the upper surface of the gate electrode 17 tends to decrease as the width of the gate trench 6B increases, and therefore, the width of the gate trench 6B can be adjusted in order to control the height of the upper surface of the gate electrode 17 at the boundary portion.

[0119] Furthermore, according to the embodiment described above, a first recess is formed at the edge of the upper surface of gate electrode 17B at the boundary, with the difference in height between the center and the edge being X5. With this configuration, the upper surface of gate electrode 17B has a bird's beak shape, which increases the effective distance between the edge of the mesa portion and the upper surface of gate electrode 17B. This makes it possible to alleviate electric field concentration when gate voltage is applied, and to suppress breakdown of gate oxide film 7B.

[0120] Furthermore, according to the embodiment described above, a second recess is formed at the edge of the top surface of gate electrode 17C in cell region 20, with the difference in height between the center and the edge being X4. The depth of the second recess is shallower than the depth of the first recess. With this configuration, the thicker the gate oxide film, the faster the oxidation process due to the diffusion of the oxidizing agent. Therefore, when gate oxide film 7B is thick at the boundary, it is easier to form a deep first recess. Furthermore, the bird's beak length at the boundary is longer than in cell region 20, improving the reliability of gate oxide film 7B.

[0121] According to the embodiment described above, in the method for manufacturing a semiconductor device, a p-type base region 4 is provided in the surface layer of an n-type drift layer 3. A plurality of n-type source regions 5 are provided in the surface layer of the base region 4. A plurality of gate trenches 6 are provided, extending from the upper surfaces of the source regions 5 through the base region 4 and into the drift layer 3. A gate oxide film 7 is provided along at least the interior of each of the gate trenches 6. A gate electrode 17 is provided in the gate trench 6 and surrounded by the gate oxide film 7. A source electrode 11 is provided, electrically connected to the source region 5 adjacent to the gate trench 6. A pull-up electrode 17A is provided, spanning the plurality of gate trenches 6 and electrically connecting the gate electrodes 17 in each of the gate trenches 6. Here, the thickness of the gate oxide film 7 in the cell section 20 where the source electrode 11 is provided is defined as a first thickness. The thickness of the gate oxide film 7B (or gate oxide film 7A) in the pull-up section where the pull-up electrode 17A is provided is defined as a second thickness. Alternatively, the thickness of the gate oxide film 7B (or the gate oxide film 7) in the cell region 20 where the source electrode 11 is provided is defined as the first thickness. The thickness of the gate oxide film 7A in the pull-up region where the pull-up electrode 17A is provided is defined as the second thickness. The second thickness is thicker than the first thickness. At the boundary between the cell region 20 and the pull-up region, the height of the top surface of the gate electrode 17 (or the gate electrode 17B) is lower than the height of the top surface of the drift layer 3.

[0122] With this configuration, the distance between the edge (corner) of the upper surface of the gate trench 6 and the upper surface of the gate electrode 17 is increased, and the electric field applied to the gate oxide film 7 can be alleviated, thereby suppressing breakdown of the gate oxide film 7.

[0123] Unless otherwise specified, the order in which the processes are performed can be changed.

[0124] Furthermore, even if other configurations shown as examples in this specification are appropriately added to the above configuration, that is, even if other configurations in this specification that were not mentioned as the above configuration are appropriately added, the same effect can be achieved.

[0125] <Regarding Modifications of the Multiple Embodiments Described Above> In the multiple embodiments described above, the materials, materials, dimensions, shapes, relative positional relationships, implementation conditions, and the like of each component may be described, but these are merely examples in all aspects and are not limiting. For example, in the multiple embodiments described above, an n-type silicon carbide semiconductor substrate 1 is used as the semiconductor substrate, but the material used for the semiconductor substrate is not limited to silicon carbide and may be silicon, gallium nitride, or the like.

[0126] Therefore, countless modifications and equivalents not shown as examples are contemplated within the scope of the technology disclosed in the present specification, including, for example, modifying, adding, or omitting at least one component, and further, extracting at least one component from at least one embodiment and combining it with a component from another embodiment.

[0127] Furthermore, in at least one embodiment described above, when a material name or the like is stated without being specifically specified, unless a contradiction arises, it is assumed that the material in question includes other additives, such as alloys.

[0128] Furthermore, unless a contradiction arises, when it is stated in the above-described embodiments that "one" component is provided, "one or more" of that component may be provided.

[0129] Furthermore, each component in the embodiments described above is a conceptual unit, and the scope of the technology disclosed in this specification includes cases where one component is made up of multiple structures, cases where one component corresponds to a part of a structure, and even cases where multiple components are provided in one structure.

[0130] Furthermore, each of the components in the embodiments described above includes structures having other structures or shapes as long as they perform the same function.

[0131] Furthermore, the descriptions in this specification are incorporated by reference for all purposes related to the present technology, and none of them are admitted to be prior art.

[0132] 1 Silicon carbide semiconductor substrate, 2 Semiconductor layer, 3 Drift layer, 4 Base region, 5 Source region, 6 Gate trench, 6B Gate trench, 7 Gate oxide film, 7A Gate oxide film, 7B Gate oxide film, 8 Gate electrode, 9 Diffusion protection layer, 10 Active cell, 11 Source electrode, 12 Drain electrode, 13 Interlayer insulating film, 16 Termination trench, 17 Gate electrode, 17A Pull-up electrode, 17B Gate electrode, 17C Gate electrode, 18 Gate wiring, 19 Termination protection layer, 20 Cell portion, 25 Ohmic electrode, 26 Gate trench, 30 Termination region, 31 Source contact, 32 Ohmic electrode, 34 Gate contact, 41 Silicon oxide film, 41A Silicon oxide film, 41B Silicon oxide film, 41C Silicon oxide film, 42 Etching mask, 43 Implantation mask, 100 Semiconductor device, 101 Region, 117A Pull-up electrode, 170 polysilicon, 200 semiconductor device.

Claims

1. A semiconductor device comprising a drift layer of a first conductivity type, a base region of a second conductivity type provided on the surface layer of the drift layer, a plurality of source regions of the first conductivity type provided on the surface layer of the base region, a plurality of trenches reaching from the upper surface of the source region through the base region into the drift layer, a gate insulating film provided along at least the inside of each of the trenches, a gate electrode provided in the trench surrounded by the gate insulating film, a source electrode electrically connected to the source region adjacent to the trench, and a pull-up electrode provided across the plurality of trenches for electrically connecting the gate electrodes in each of the trenches, wherein the thickness of the gate insulating film in the cell portion where the source electrode is provided is a first thickness, the thickness of the gate insulating film in the pull-up portion where the pull-up electrode is provided is a second thickness, the second thickness is greater than the first thickness, and the height of the upper surface of the gate electrode is lower than the height of the upper surface of the drift layer at the boundary between the cell portion and the pull-up portion.

2. The semiconductor device according to claim 1, wherein the pull-up portion does not overlap the trench in plan view.

3. The semiconductor device according to claim 1, wherein at least a part of the pull-up portion overlaps the trench in plan view.

4. The semiconductor device according to any one of claims 1 to 3, wherein the height of the upper surface of the gate electrode in the cell portion is lower than the height of the upper surface of the gate electrode at the boundary portion.

5. The semiconductor device according to any one of claims 1 to 3, wherein the height of the upper surface of the gate electrode in the cell portion is higher than the height of the upper surface of the gate electrode at the boundary portion.

6. The semiconductor device according to any one of claims 1 to 5, wherein the depth of the trench at the boundary portion is deeper than the depth of the trench in the cell portion.

7. The semiconductor device according to claim 6, wherein the width of the trench at the boundary portion is wider than the width of the trench in the cell portion.

8. A semiconductor device according to any one of claims 1 to 7, wherein a first recess is formed at an upper end portion of the gate electrode at the boundary portion.

9. A semiconductor device according to claim 8, wherein a second recess is formed at an upper end portion of the gate electrode in the cell portion, and the depth of the second recess is shallower than the depth of the first recess.

10. A method of manufacturing a semiconductor device, comprising providing a base region of a second conductivity type on a surface layer of a drift layer of a first conductivity type, providing a plurality of source regions of the first conductivity type on a surface layer of the base region, providing a plurality of trenches reaching from an upper surface of the source region through the base region into the drift layer, providing a gate insulating film provided along at least an inside of each of the trenches, providing a gate electrode provided in the trench surrounded by the gate insulating film, providing a source electrode electrically connected to the source region adjacent to the trench, providing a pull-up electrode provided across the plurality of trenches and electrically connecting the gate electrodes in each of the trenches, setting a thickness of the gate insulating film in a cell portion where the source electrode is provided as a first thickness, setting a thickness of the gate insulating film in a pull-up portion where the pull-up electrode is provided as a second thickness, the second thickness being thicker than the first thickness, and at a boundary portion between the cell portion and the pull-up portion, a height of an upper surface of the gate electrode being lower than a height of an upper surface of the drift layer.

11. A method of manufacturing a semiconductor device according to claim 10, wherein the height of the upper surface of the gate electrode is formed at a position lower than the height of the upper surface of the drift layer by etch-back.

12. A method of manufacturing a semiconductor device according to claim 10 or 11, wherein after etching back the gate electrode, the gate electrode is oxidized to make an upper end portion of the upper surface of the gate electrode concave.

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