Gate drive control device and power conversion device

Abstract

This gate drive control device drives a gate of a first semiconductor element and comprises: a mirror clamp circuit for retaining a gate voltage of the first semiconductor element at a low level when the gate voltage has fallen to less than a predetermined control threshold value; and a gate monitor circuit for sensing that the gate voltage of the first semiconductor element has fallen below a predetermined sensing threshold value for positive potential. In the gate drive control device, when the first semiconductor element is turned off, the gate monitor circuit senses that the gate voltage of the first semiconductor element has fallen below the sensing threshold value either at the same time as the start of operation of the mirror clamp circuit or later than the start of operation.

Description

Gate drive control device and power conversion device

[0001] The present invention relates to a gate drive control device that drives the gate of a semiconductor element, and a power conversion device using the same.

[0002] Power conversion devices have functions such as AC-DC conversion, DC-AC conversion, AC power frequency conversion, and DC power voltage conversion. To perform these conversion functions, power conversion devices are equipped with a power conversion circuit that converts power by the on / off operation of a power semiconductor module with a switching function. The power semiconductor module is turned on by controlling the gate voltage between the gate terminal and source terminal (or emitter terminal) to high (positive voltage) by the gate drive circuit, and turned off by controlling it to low (0 V or negative voltage). The gate drive circuit is further controlled by a higher-level controller.

[0003] Power semiconductor modules include 1-in-1 modules equipped with single or multiple parallel-connected semiconductor switching elements (hereinafter referred to as "switching elements"), and 2-in-1 modules in which two switching elements are connected in series inside the module to form a half-bridge circuit in one module.

[0004] Patent Document 1 describes a power semiconductor drive circuit. Patent Document 1 describes that the power semiconductor drive circuit includes "a parallel circuit configured with at least two transistors connected to the gate side of a power semiconductor element and setting the gate resistance of the power semiconductor element, and a gate voltage monitoring circuit connected to the gate side of the power semiconductor element and the parallel circuit and set to a predetermined monitoring voltage for monitoring the gate voltage of the power semiconductor element," and "a signal delay circuit that delays an output signal from the gate voltage monitoring circuit, and a gate control circuit that switches the magnitude of the combined resistance of the parallel circuit based on the output signal output from the signal delay circuit."

[0005] Until now, silicon (Si) elements have been used as switching elements. In recent years, silicon carbide (SiC) elements, which offer low on-resistance, high-speed switching, and high-temperature operation, have become popular in order to improve the performance of power conversion circuits. Hereinafter, semiconductor elements using SiC will be referred to as "SiC elements."

[0006] To shorten the dead time for high-speed SiC drive, an active dead time configuration has been proposed in which the dead time is controlled by a gate driver IC (GDIC). In this configuration, the gate monitor signal of the GDIC is input to the GDIC of the opposing arm, which determines that the SiC element of the opposing arm is off, and the SiC element of the own arm can be turned on.

[0007] Japanese Patent Application Laid-Open No. 2019-080359

[0008] In an active dead time configuration, each arm is connected to a Miller clamp circuit that controls the gate with low impedance and a gate voltage monitoring circuit that monitors the gate voltage of the semiconductor element. The Miller clamp circuit maintains the gate voltage of the semiconductor element at a low level when the gate voltage falls below a predetermined control threshold. The gate voltage monitoring circuit determines whether the gate is off when the gate voltage of the semiconductor element falls below an off-detection threshold and whether the gate is on when the gate voltage exceeds an on-detection threshold. Conventionally, the off-detection threshold of a GDIC is set higher than the operating threshold of the Miller clamp circuit. With this setting, the gate monitor signal may detect the SiC element of the corresponding arm as off even when it is in a half-on state. Furthermore, if switching noise from another phase arm is superimposed on the gate voltage during the half-on state, the SiC element of the corresponding arm may turn on again. This poses a risk of short-circuiting the upper and lower arms in an active dead time configuration.

[0009] The present invention has been made in view of the above circumstances, and has an object to prevent short circuits between the upper and lower arms while driving semiconductor elements that constitute the arms at high speed in a gate drive control device that includes a Miller clamp circuit and a gate voltage monitoring circuit.

[0010] To achieve the above object, one aspect of the present invention provides a gate drive control device that drives a gate of a first semiconductor element, and includes: a Miller clamp circuit that holds the gate voltage of the first semiconductor element at a low level when the gate voltage falls below a predetermined control threshold; and a gate monitor circuit that detects that the gate voltage of the first semiconductor element has fallen below a predetermined detection threshold of positive potential. In the gate drive control device, when the first semiconductor element is turned off, the gate monitor circuit is configured to detect that the gate voltage of the first semiconductor element has fallen below the detection threshold simultaneously with or after the Miller clamp circuit starts operating.

[0011] According to at least one aspect of the present invention, the gate monitor circuit detects gate-off after the Miller clamp circuit operates and the gate-off of the semiconductor element of its own arm is confirmed. This operation allows for more accurate gate-off detection results. If the control computer generates dead time using the gate-off detection result, it is possible to prevent short circuits between the upper and lower arms while driving the semiconductor elements that make up the arms at high speed. Other issues, configurations, and advantages will become clear from the following description of the embodiments.

[0012] FIG. 1 is a block diagram showing an example of the configuration of an inverter device equipped with a gate drive control device according to a first embodiment of the present invention. FIG. 2 is a diagram showing an example of the configuration of a gate monitor unit according to the first embodiment of the present invention. FIG. 3 is an example of a timing chart schematically showing a gate detection operation by the gate monitor unit according to the first embodiment of the present invention. FIG. 4 is a diagram showing an example of a minimum configuration of a gate monitor unit according to the first embodiment of the present invention. FIG. 5 is a diagram showing an example of the configuration of an inverter device according to a second embodiment of the present invention. FIG. 6 is an example of a timing chart schematically showing a gate drive operation of the inverter device according to the second embodiment of the present invention. FIG. 7 is a diagram showing an example (part 1) of the configuration of an inverter device according to a third embodiment of the present invention. FIG. 8 is a diagram showing an example (part 2) of the configuration of an inverter device according to the third embodiment of the present invention. FIG. 9 is an example of a timing chart schematically showing a gate drive operation in the third embodiment of the present invention. FIG. 10 is a diagram showing an example of the configuration of a gate monitor unit according to a fourth embodiment of the present invention. FIG. 11 is a diagram showing an example of a timing chart schematically showing a threshold value changing operation in the fourth embodiment of the present invention. FIG. 12 is a diagram showing a modified configuration of the gate monitor unit according to an embodiment of the present invention (separate configuration). FIG. 13 is a diagram showing a modified configuration of the gate monitor unit according to an embodiment of the present invention (configuration in which some threshold values ​​are shared).

[0013] Hereinafter, examples of modes for carrying out the present invention (hereinafter referred to as "embodiments") will be described with reference to the accompanying drawings. In this specification and the accompanying drawings, identical or similar components are given the same reference numerals, and redundant explanations may be omitted or only explanations focusing on the differences may be given. Furthermore, when there are multiple identical or similar components, they may be described using the same reference numerals with different subscripts. Note that when it is not necessary to distinguish between these multiple components, the subscripts may be omitted in the description. The number of each component may be singular or plural unless otherwise specified.

[0014] Before describing the present invention, we will provide additional explanation as to why the off-detection threshold of a conventional GDIC was set higher than the operation threshold of a Miller clamp circuit. Conventional gate monitor results were used only as a monitor function for diagnostic purposes. In order to reduce the error between the on / off detection timing of an actual power device and the on / off operation timing of the actual power device, the conventional off-detection threshold was set to a value close to the gate threshold of the actual power device.

[0015] However, in the active dead time configuration of the present invention, which will be described later, the gate monitor result must be used not only as a monitor function but also as a gate input signal for the paired arm. Therefore, if a power device is turned off once and then falsely turned on again due to noise or other factors generated when the gate is turned off, the paired arm will turn on as a result of the first gate off, causing a short circuit between the upper and lower arms with the arm being falsely turned on. To avoid this, in the present invention, gate off is determined after Miller clamp operation (gate completely off).

[0016] Furthermore, conventionally, it is assumed that the device will be driven by an IGBT (Insulated Gate Bipolar Transistor).SiC, which can be driven at high speed, has a shorter gate voltage transition time (delay time) than an IGBT, and is less affected by the difference between the actual gate threshold and the off-detection threshold.

[0017] In inverters, large currents are passed intermittently through power devices (semiconductor elements), which generates large noise when the gates of the self-phase and other-phase arms are turned on and off. In fact, common mode noise generated when the gate of the other-phase arm is driven can cause the gate of the self-phase arm to turn on again erroneously after it has been turned off once. If the aforementioned false on occurs in an inverter with an active dead time configuration, the first gate off turns on the power device of the opposing arm, causing the power device of the self-arm to turn on erroneously, resulting in a short circuit between the upper and lower arms.

[0018] If the gate drive control device can detect gate-off more reliably, it will be possible to avoid the above-mentioned short circuit of the upper and lower arm circuits in an inverter with an active dead time configuration, which will improve the reliability of the inverter and lead to further enhancement of automobile safety.

[0019] First Embodiment First, a gate drive control device and a power conversion device according to a first embodiment of the present invention will be described.

[0020] [Configuration of Inverter Device] Fig. 1 is a block diagram showing an example of the configuration of an inverter device equipped with a gate drive control device according to a first embodiment of the present invention. The inverter device 100 (an example of a power conversion device) shown in Fig. 1 includes a first semiconductor element 31 that functions as an upper arm and a second semiconductor element 32 that functions as a lower arm. In Fig. 1, the first semiconductor element 31 and the second semiconductor element 32 are n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) made of SiC. However, the first semiconductor element 31 and the second semiconductor element 32 are not limited to this example. For example, the first semiconductor element 31 and the second semiconductor element 32 are suitable for use in transistors with excellent high-speed switching capabilities, such as transistors made of SiC.

[0021] The inverter device 100 supplies power to a load by controlling the switching operation of a first semiconductor element 31 and a second semiconductor element 32 based on commands from an MCU (Micro-Control Unit) 1. One example of the load is a motor. The MCU 1 is a microcontroller and an example of a control computer. In the MCU 1, an arithmetic processing unit (e.g., a CPU), a memory unit (RAM and ROM), an input / output circuit (I / O), a timer circuit, and the like are implemented in a single integrated circuit.

[0022] The inverter device 100 includes a gate drive control device 10 that controls the switching operation of a first semiconductor element 31, and a gate drive control device 20 that controls the switching operation of a second semiconductor element 32. The gate drive control device 10 controls the gate voltage supplied to the first semiconductor element 31, and the gate drive control device 20 controls the gate voltage supplied to the second semiconductor element 32.

[0023] The MCU 1 and the gate drive control device 10 are electrically insulated by a signal transmission unit 2_1. The input side and output side of the signal transmission unit 2_1 are magnetically coupled, and transmit signals while maintaining an electrically isolated state between the input side and the output side. Signals are exchanged between the MCU 1 and the gate drive control device 10 via the signal transmission unit 2_1. Examples of the signal transmission unit 2_1 include a signal transmission unit that uses magnetic coupling using a transformer, and an optical signal transmission unit that uses a photocoupler.

[0024] The following describes the gate drive control device 10, but the same applies to the gate drive control device 20. The gate drive control device 10 includes a gate state determination circuit 14, a Miller clamp circuit 15, and a reference voltage generation circuit 13. The gate state determination circuit 14 detects gate-off of the first semiconductor element 31 simultaneously with or after the Miller clamp circuit 15 starts operating. The configuration and operation of this gate drive control device 10 will be described.

[0025] The gate drive control device 10 is composed of a gate drive unit 11 and a gate monitor unit 12. The gate drive unit 11 controls the gate G1 of the first semiconductor element 31 based on a drive command cmd1 input from the MCU 1 via a signal transmission unit 2_1. The gate monitor unit 12 determines the gate state from the gate G1 voltage and outputs the gate state determination result as a gate monitor signal Mon_g1. Furthermore, the gate monitor unit 12 controls the gate G1 with low impedance based on the gate state determination result.

[0026] (Gate Driver) The gate driver 11 includes a transistor Mp1, a transistor Mn1, and a NOT circuit INV1_1. The transistor Mp1 is a p-channel MOSFET, and the transistor Mn1 is an n-channel MOSFET. The NOT circuit INV1_1 inverts the logical level of the drive command cmd1 and outputs it. The output signal of the NOT circuit INV1_1 is input to the gates of the transistors Mp1 and Mn1 as a switching control signal cnt1.

[0027] When the drive command cmd1 becomes a logical high level (hereinafter referred to as "High"), the NOT circuit INV1_1 causes the switching control signal cnt1 to become a logical low level (hereinafter referred to as "Low"). As a result, the transistor Mp1 is turned on and the transistor Mn1 is turned off. The gate G1 is High, and the first semiconductor element 31 is turned on.

[0028] On the other hand, when the drive command cmd1 goes low, the NOT circuit INV1_1 causes the switching control signal cnt1 to go high. This turns the transistor Mp1 off and the transistor Mn1 on. The gate G1 goes low, turning the first semiconductor element 31 off.

[0029] A resistor Ron1 provided between the drain and gate G1 of the transistor Mp1 and a resistor Roff1 provided between the drain and gate G1 of the transistor Mn1 are provided to adjust the charging and discharging speed of the gate G1 voltage.

[0030] (Gate Monitor Unit) The gate monitor unit 12 includes a gate state determination circuit 14 , a Miller clamp circuit 15 , and a reference voltage generation circuit 13 .

[0031] The gate state determination circuit 14 (an example of a gate monitor circuit) compares the gate G1 voltage with a gate state determination threshold (hereinafter referred to as "Vth_mon") to determine the on / off state of the first semiconductor element 31 and outputs the result as a gate monitor signal Mon_g1. The gate state determination threshold corresponds to the on determination threshold described above. Furthermore, since this embodiment relates to the timing of detecting the off state of the semiconductor element, the gate state determination threshold can also be considered an off determination threshold. The Miller clamp circuit 15 controls the gate G1 with low impedance when the gate G1 voltage is less than a Miller clamp operation threshold (hereinafter referred to as "Vth_mc"). In other words, the Miller clamp circuit 15 is a circuit that holds the gate voltage of the semiconductor element at a low level when the gate voltage falls below a predetermined control threshold. The reference voltage generation circuit 13 generates a reference voltage that determines Vth_mon and Vth_mc.

[0032] A gate monitor signal Mon_g1 including the gate state determination result is input to the MCU 1 via the signal transmission unit 2_1. Then, when the gate state determination result of the first semiconductor element 31 is an OFF determination, the MCU 1 outputs an ON command to the gate drive control device 20 in the opposite arm via the signal transmission unit 2_2. The gate state determination result of the first semiconductor element 31 input to the MCU 1 is used to adjust the drive timing of the second semiconductor element 32, etc.

[0033] The gate drive control device 20, like the gate drive control device 10, includes a gate drive unit 21 and a gate monitor unit 22. The operation of the gate drive control device 20 is the same as that of the gate drive control device 10, and therefore a description thereof will be omitted.

[0034] Although the gate driver 11 of this embodiment shows an example configuration in which the output terminal of the transistor Mp1 and the output terminal of the transistor Mn1 are separated into two, the outputs of the transistors Mp1 and Mn1 may be a single terminal. Furthermore, the gate driver 11 may have not only a p-channel MOS-n-channel MOS configuration, but also a p-channel MOS-p-channel MOS configuration or an n-channel MOS-n-channel MOS configuration. Furthermore, when a negative voltage is not generated, the source potential (VSS1_1) of the transistor Mn1 is connected to the same potential as the source potential. When a negative voltage is generated, the source potential (VSS1_1) of the transistor Mn1 is connected to the same potential as the source potential or to a potential lower than the source potential (for example, a negative power supply voltage).

[0035] [Configuration of Gate Monitor Unit] The gate monitor unit 12 according to this embodiment will be described in more detail with reference to Fig. 2. Fig. 2 is a diagram showing an example of the configuration of the gate monitor unit 12.

[0036] (Reference Voltage Determination Circuit) The reference voltage generation circuit 13 generates a voltage Vth_mon (gate state determination threshold) and a voltage Vth_mc (Miller clamp operation threshold). In this embodiment, it is assumed that Vth_mon and Vth_mc have the same value. FIG. 2 shows a configuration in which a common reference voltage is used for Vth_mon and Vth_mc. Note that, in cases where Vth_mon and Vth_mc have different values, a configuration in which separate reference voltages are generated may be used, as shown in FIGS. 12 and 13, which will be described later.

[0037] (Gate State Determination Circuit) The gate state determination circuit 14 includes a comparator CMP1_1 that receives the voltage Vth_mon and the voltage of the gate G1 as two inputs, and a NOT circuit INV1_2 that inverts the logic output from CMP1_1. As an example, the comparator CMP1_1 receives the voltage Vth_mon at its non-inverting input terminal and the voltage of the gate G1 at its inverting input terminal, and outputs a gate state determination result to the NOT circuit INV1_2. If the voltage of the gate G1 is less than Vth_mon, the comparator CMP1_1 outputs an OFF determination (Low in this embodiment) indicating a gate OFF state to the gate monitor signal Mon_g1 via INV1_2. If the gate G1 voltage is equal to or greater than Vth_mon, the comparator CMP1_1 outputs an ON determination (High in this embodiment) indicating a gate ON state to the gate monitor signal Mon_g1 via INV1_2.

[0038] Note that a configuration may be adopted in which the gate G1 is connected to the non-inverting input terminal of CMP1_1 and Vth_mon is connected to the inverting input terminal of CMP1_1, in which case the NOT circuit INV1_2 is not necessary.

[0039] (Miller Clamp Circuit) The Miller clamp circuit 15 includes a comparator CMP2_1 and a Miller clamp transistor Q1.

[0040] The comparator CMP2_1 has two inputs: the voltage Vth_mc and the voltage at the gate G1. For example, the voltage Vth_mc is input to the non-inverting input terminal, and the voltage at the gate G1 is input to the inverting input terminal. If the gate G1 voltage is less than Vth_mc, the comparator CMP2_1 outputs a low-impedance control command (High in this embodiment) to the mirror clamp control signal cnt1_mc. If the gate G1 voltage is equal to or greater than Vth_mc, the comparator CMP2_1 outputs a high-impedance control command (Low in this embodiment) to the mirror clamp control signal cnt1_mc.

[0041] The reference potentials (VSS3_1) of Vth_mon and Vth_mc are connected to the same potential as the source potential, and the source potential (VSS2_1) of the Miller clamp transistor Q1 is connected to the same potential as the source potential or a potential (e.g., a negative power supply voltage) lower than the source potential.

[0042] The Miller clamp transistor Q1 controls the gate G1 of the first semiconductor element 31 at low impedance based on the Miller clamp control signal cnt1_mc, which is the output of the comparator CMP2_1. The Miller clamp transistor Q1 is turned on when the Miller clamp control signal cnt1_mc is a low impedance control command (High). Conduction between the drain and source of the Miller clamp transistor Q1 creates a low impedance between the gate G1 and the source (VSS2_1). This holds the voltage of the gate G1 at a low level. As an example, the Miller clamp transistor Q1 can be an n-channel MOSFET, but is not limited to this.

[0043] [Gate Detection Operation] Next, the gate detection operation in the gate drive control device 10 including the gate monitor unit 12 will be described with reference to FIG.

[0044] 3 is an example timing chart outlining the gate detection operation by the gate monitor unit 12. At time t1, while an OFF command is input to the drive command cmd1, an OFF command (Low) is input to the drive command cmd2. Transistor Mp2 (not shown) in the gate drive control device 20 turns OFF and transistor Mn2 (not shown) turns ON, causing the potential of the gate G2 of the second semiconductor element 32 to begin to decrease. Transistors Mp2 and Mn2 correspond to transistors Mp1 and Mn1 in the gate drive control device 10, respectively.

[0045] At time t2, the gate G2 voltage reaches the mirror voltage of the second semiconductor element 32, and the gate G2 potential becomes constant. At time t3, the drain D2 voltage of the second semiconductor element 32 increases, and then the gate G2 potential begins to decrease.

[0046] At time t4: The gate G2 potential falls below Vth_mc, and the Miller clamp circuit 15 starts operating, controlling the impedance between the gate G2 and VSS2_2 at low level, causing the gate G2 potential to fall to the VSS2_2 potential. At the same time, the gate G2 potential falls below Vth_mon, causing an off-determination (Low) result to be output to the gate monitor signal Mon_g2. During the period from time t1, when the gate G2 potential starts to fall, to time t4, when the gate G2 potential has fallen completely to VSS2_2, the second semiconductor element 32 is in a half-on state.

[0047] At time t5, when the gate monitor signal Mon_g2 goes low, the MCU1 outputs an ON command (High) to the drive command cmd1. The period from time t4, when the gate monitor signal Mon_g2 goes low, to the time Tdelay has elapsed, when the gate G1 voltage begins to rise, is the dead time. When the ON command (High) is input to the drive command cmd1, after a delay time (Tdelay), the transistor Mp1 in the gate drive control device 10 turns on and the transistor Mn1 turns off. As a result, the voltage of the gate G1 of the first semiconductor element 31 begins to rise.

[0048] At time t6, when the potential of the gate G1 of the second semiconductor element 32 becomes equal to or higher than Vth_mon, an on-state determination (High) is output to the gate monitor signal Mon_g1. At the same time, the Miller clamp transistor Q1 stops operating.

[0049] At time t7: the potential of the gate G1 of the first semiconductor element 31 rises to VCC1 (FIG. 1), and the first semiconductor element 31 enters the ON state.

[0050] In the gate monitor unit 12 according to the above-described embodiment, the detection threshold (Vth_mon) of the gate state determination circuit 14 is set to the same value as the control threshold (Vth_mc) of the Miller clamp circuit 15 .

[0051] With this configuration, in this embodiment, gate-off detection is performed simultaneously with or after the Miller clamp circuit starts operating, thereby increasing the accuracy of gate-off detection compared to conventional techniques. Furthermore, by sharing the reference voltage as shown in Figure 2, the circuit area can be reduced compared to conventional techniques, resulting in lower costs and a smaller size.

[0052] The Miller clamp circuit may be configured to stop operating simultaneously with the input of an ON command to the gate driver of the arm in question.

[0053] [Minimum Configuration of Gate Monitor Unit] Here, an example of the minimum configuration of the gate monitor unit in this embodiment will be described with reference to FIG.

[0054] Fig. 4 is a diagram showing an example of the minimum configuration of the gate monitor unit. In the gate monitor unit 12A shown in Fig. 4, the comparators CMP1_1 and CMP2_1 shown in Fig. 2 are shared, thereby reducing the number of comparators by one. Note that the following description of the gate monitor unit 12A will focus on the configuration that differs from the gate monitor unit 12 shown in Fig. 2.

[0055] 2, the gate monitor unit 12A includes a comparator CMP3_1 instead of the comparators CMP1_1 and CMP2_1. Furthermore, the gate monitor unit 12A includes a buffer circuit BUF1 on the output line of the comparator CMP3_1. A NOT circuit INV3_1 is connected between the input side of the buffer circuit BUF1 and the output side of the comparator CMP3_1.

[0056] The comparator CMP3_1 compares two inputs, the voltage of the gate G1 and the voltage of Vth_mon (=Vth_mc), and outputs the comparison result to the Miller clamp control signal cnt1A_mc. The comparator CMP3_1 operates in the same way as the comparator CMP2_1, so a detailed explanation of its operation will be omitted. Also, the NOT circuit INV3_1 operates in the same way as the NOT circuit INV1_2, so a detailed explanation of its operation will be omitted.

[0057] The buffer circuit BUF1 adjusts the logic level output by the NOT circuit INV3_1 to a desired logic level (a voltage level whose logic can be determined by the signal transmission unit 2_1), and outputs the adjusted level as the gate monitor signal Mon_g1.

[0058] Here, it is assumed that the logic determination threshold (Vdet_st1) for determining the logic level of the signal transmission unit 2_1 and the High output voltage (Vinv_h) of the NOT circuit INV3_1 have the relationship shown in the following formula (1). Furthermore, the High output voltage (Vbuf1_h) of the buffer circuit BUF1 is set to satisfy the following formula (1).

[0059] Vinv_h<Vdet_st1<Vbuf1_h...(1)

[0060] When the potential of the High voltage (Vinv_h) of the NOT circuit INV3_1 is less than a logic determination threshold (Vdet_buf1) for determining the logic level of the buffer circuit BUF1, the buffer circuit BUF1 outputs a Low monitor signal Mon_g1. Information (that the gate monitor signal Mon_g1 is at a Low level) is transmitted to the MCU1 via the signal transmission unit 2_1.

[0061] On the other hand, when the potential of the High voltage (Vinv_h) of the NOT circuit INV3_1 is equal to or higher than Vdet_buf1, a High (Vbuf1_h) is output as the gate monitor signal Mon_g1. Therefore, the signal transmission unit 2_1 identifies the signal transmitted from the gate monitor unit 12A as High and transmits the signal to the MCU1.

[0062] Note that when Vdet_st1 and Vinv_h satisfy the following formula (2), the High output voltage (Vinv_h) of the NOT circuit INV3_1 is sufficiently large. In this case, the buffer circuit BUF1 may not be provided.

[0063] Vdet_st1<Vinv_h...(2)

[0064] According to the gate monitor unit 12A shown in FIG. 4, the terminals and some of the internal circuits are shared, thereby reducing the circuit scale and cost.

[0065] (Modification of Gate Monitor Section (Separate Configuration)) Here, a modification of the configuration of the gate monitor section in this embodiment will be further described.

[0066] 12 shows a modified example (separate configuration) of the gate monitor unit in this embodiment. The gate monitor unit 12C shown in FIG. 12 is configured to generate reference voltages individually for Vth_mon (gate state determination threshold) and Vth_mc (Miller clamp operation threshold).

[0067] The comparator CMP1_1 receives two inputs: a voltage Vth_mon and a voltage at the gate G1. A reference voltage generation circuit 1310 generates the voltage Vth_mon and inputs it to an input terminal (e.g., a non-inverting input terminal) of the comparator CMP1_1. The comparator CMP2_1 receives two inputs: a voltage Vth_mc and a voltage at the gate G1. A reference voltage generation circuit 1320 generates the voltage Vth_mc and inputs it to an input terminal (e.g., a non-inverting input terminal) of the comparator CMP2_1.

[0068] (Modification of Gate Monitor Unit (Configuration with Some Thresholds Shared)) Fig. 13 shows a modification of the configuration of the gate monitor unit in this embodiment (configuration with some thresholds shared). The gate monitor unit 12D shown in Fig. 13 is configured to generate reference voltages individually for Vth_mon (gate state determination threshold) and Vth_mc (Miller clamp operation threshold). However, some threshold voltages are shared.

[0069] A series circuit of a reference voltage generation circuit 1410 and a reference voltage generation circuit 1420 is connected between the reference potential (VSS3_1) and an input terminal (e.g., non-inverting input terminal) of the comparator CMP2_1. The connection point between the reference voltage generation circuit 1410 and the reference voltage generation circuit 1420 is connected to an input terminal (e.g., non-inverting input terminal) of the comparator CMP1_1.

[0070] The comparator CMP1_1 receives two inputs: the voltage Vth_mon and the voltage at the gate G1. The reference voltage generation circuit 1410 generates the voltage Vth_mon and inputs it to an input terminal (e.g., a non-inverting input terminal) of the comparator CMP1_1. The comparator CMP2_1 receives two inputs: the voltage Vth_mc and the voltage at the gate G1. The voltage Vth_mc is the voltage Vth_mon generated by the reference voltage generation circuit 1410 plus the voltage generated by the reference voltage generation circuit 1420.

[0071] In the gate monitor unit shown in Figures 12 and 13, the gate state determination threshold (Vth_mon) of the gate state determination circuit 14 is set to the same value as the mirror clamp operation threshold (Vth_mc) of the mirror clamp circuit 15, or to a value smaller than the mirror clamp operation threshold (Vth_mc).

[0072] As described above, the gate drive device (gate drive control device 10) according to this embodiment is a gate drive control device that drives the gate of a first semiconductor element (first semiconductor element 31). This gate drive control device includes a Miller clamp circuit (Miller clamp circuit 15) that holds the gate voltage of the first semiconductor element at a low level when the gate voltage of the first semiconductor element falls below a predetermined control threshold (Vth_mc), and a gate monitor circuit (gate state determination circuit 14) that detects that the gate voltage of the first semiconductor element has fallen below a predetermined detection threshold (Vth_mon) of positive potential. In this gate drive control device, when the first semiconductor element is turned off, the gate monitor circuit is configured to detect that the gate voltage of the first semiconductor element has fallen below the detection threshold simultaneously with or after the Miller clamp circuit starts operating.

[0073] According to the embodiment described above, the gate monitor circuit detects gate-off after the Miller clamp circuit operates and the gate-off of the semiconductor element of its own arm is confirmed. This makes it possible to obtain a more accurate gate-off detection result, and more accurate gate information can be used for gate drive control. If the gate-off detection result is used to generate dead time in an MCU or the like, it is possible to drive the semiconductor elements that make up the arms at high speed while preventing short circuits between the upper and lower arms.

[0074] Furthermore, by setting the detection threshold (Vth_mon) to a positive potential relative to GND (FIG. 3), the gate potential can be set to a low level more quickly, and gate-off can be detected more quickly. Accordingly, the dead time set by the active dead time control unit (described later) can also be shortened. Furthermore, by setting each threshold to a positive potential, the generation circuitry required for generating negative potentials and the negative potential diagnostic circuitry can be reduced, resulting in lower costs.

[0075] Second Embodiment Next, the configuration of an inverter device according to a second embodiment of the present invention will be described with reference to FIG.

[0076] [Configuration of Inverter Device] Fig. 5 is a diagram showing an example of the configuration of an inverter device according to a second embodiment of the present invention. The following describes an inverter device 600 shown in Fig. 5, focusing on the configuration that is different from the configuration of the inverter device 100 according to the first embodiment shown in Fig. 1.

[0077] The inverter device 600 includes an active dead time control unit 40 in addition to the configuration of the inverter device 100 according to the first embodiment. The active dead time control unit 40 corresponds to the active dead time configuration described in the Background Art section. The active dead time control unit 40 is provided between the signal transmission units 2_1 and 2_2 and the gate drive control devices 10 and 20. The active dead time control unit 40 generates dead times for the first semiconductor element 31 and the second semiconductor element 32 by turning off one semiconductor element and then turning on the other semiconductor element using the gate state determination results from the gate monitor units 12 and 22 in the gate drive control devices 10 and 20.

[0078] The active dead time control unit 40 includes a NOT circuit INV2, a NOT circuit INV3, an AND circuit 41, and an AND circuit 42.

[0079] The NOT circuit INV2 outputs the inverted logic of the gate monitor signal Mon_g2 to the AND circuit 41. The NOT circuit INV3 outputs the inverted logic of the gate monitor signal Mon_g1 to the AND circuit .

[0080] The AND circuit 41 receives two inputs, each of which is the inverted logic of the drive command cmd1 and the gate monitor signal Mon_g2, and outputs the logical product of the two inputs as the drive command cmd3 to the gate driver 11. The AND circuit 42 receives two inputs, each of which is the inverted logic of the drive command cmd2 and the gate monitor signal Mon_g1, and outputs the logical product of the two inputs as the drive command cmd4 to the gate driver 21.

[0081] The operation of the AND circuit 41 will be described. When the drive command cmd1 is an ON command (High) and the inverted logic of the gate monitor signal Mon_g2 is an OFF determination (High), the AND circuit 41 outputs an ON command (High) as the drive command cmd3. On the other hand, when at least one of the drive command cmd1 or the inverted logic of the gate monitor signal Mon_g2 is Low, the AND circuit 41 outputs an OFF command (Low) as the drive command cmd3.

[0082] The AND circuit 42 operates in the same manner as the AND circuit 41, except for the signal lines to which it is connected, and therefore a description of the operation will be omitted.

[0083] [Gate Detection Operation] Next, the gate drive operation of the inverter device 600 including the active dead time control unit 40 will be described with reference to FIG.

[0084] 6 is an example of a timing chart that schematically illustrates the gate drive operation of an inverter device 600 that includes an active dead time control unit 40. The following describes the timing chart shown in FIG. 6, focusing on differences from the timing chart according to the first embodiment shown in FIG.

[0085] At time t1, when an OFF command (Low) is input to the drive command cmd2 while an OFF command is input to the drive command cmd1, the drive command cmd4 also becomes an OFF command (Low) via the AND circuit 42.

[0086] At time t5: The processing volume of MCU1 increases, the dead time cannot be secured in MCU1, and an ON command (High) is input to the drive command cmd1 when the second semiconductor element 32 is half ON. However, the gate monitor signal Mon_g2 is determined to be ON (High), and the operation of the AND circuit 41 causes the drive command cmd3 to maintain an OFF command (Low).

[0087] At time t4, the gate G2 potential falls below Vth_mc, and the Miller clamp circuit 15 starts operating, controlling the connection between the gate G2 and VSS2_2 at low impedance, causing the gate G2 potential to drop to the VSS2_2 potential. At the same time, the gate G2 potential falls below Vth_mon, causing an OFF determination (Low) to be output to the gate monitor signal Mon_g2. As a result, the AND circuit 41 determines that the drive command cmd1 is an ON command (High), and the NOT circuit INV2 inverts the gate monitor signal Mon_g2, causing the AND circuit 41 to output an ON command (High) to the drive command cmd3. Then, after a delay time (Tdelay), the transistor Mp2 in the gate drive control device 20 turns ON, and the transistor Mn2 turns OFF. As a result, the potential of the gate G1 of the first semiconductor element 31 begins to rise, causing the first semiconductor element 31 to transition to the ON state.

[0088] During the period from when the gate G1 potential starts to rise after the delay time Tdelay has elapsed from time t4 until time t7 when the gate G1 potential has fully risen, the first semiconductor element 31 is in a half-on state.

[0089] As described above, the gate driving device according to this embodiment includes an active dead time control unit (active dead time control unit 40) that turns on the second semiconductor element (second semiconductor element 32) of the paired arm connected in series with the first semiconductor element after the gate monitor circuit (gate state determination circuit 14) detects that the gate voltage of the first semiconductor element (first semiconductor element 31) has fallen below the detection threshold (Vth_mon).

[0090] According to the present embodiment described above, the active dead time control unit 40 turns off one semiconductor element and then turns on the other semiconductor element using the gate state determination results from the gate monitor units 12, 22 in the gate drive control devices 10, 20. As a result, in this embodiment, it is possible to drive the semiconductor elements that make up the arms at a higher speed than in the first embodiment while preventing short circuits between the upper and lower arms.

[0091] Furthermore, according to this embodiment, even if the MCU1 (microcontroller) cannot ensure sufficient dead time, the gate drive control device (GDIC) can ensure the dead time.

[0092] For example, the inverter device 600 according to the present embodiment described above can prevent vehicle failure due to a short circuit between the upper arm and the lower arm in an active dead time configuration. Furthermore, it can detect with higher accuracy that the gate of a semiconductor element has been turned off without adding any additional circuitry to the conventional circuit.

[0093] Third Embodiment Next, the configuration of an inverter device according to a third embodiment of the present invention will be described with reference to FIG.

[0094] [Configuration of Inverter Device] Fig. 7 is a diagram showing an example (part 1) of the configuration of an inverter device according to a third embodiment of the present invention. Fig. 8 is a diagram showing an example (part 2) of the configuration of an inverter device according to a third embodiment of the present invention. The difference between Fig. 7 and Fig. 8 is the difference in the logic level of the signal flowing through the signal line. Below, the inverter device 800 shown in Figs. 7 and 8 will be described, focusing on the configuration that differs from the configuration of the inverter device 600 according to the second embodiment shown in Fig. 5.

[0095] The inverter device 800 includes a simultaneous-on prevention circuit 50 in addition to the configuration of the inverter device 600 according to the second embodiment. The simultaneous-on prevention circuit 50 is provided between the signal transmission units 2_1 and 2_2 and the active dead time control unit 40.

[0096] The simultaneous on prevention circuit 50 is a circuit that prevents simultaneous on in response to simultaneous on commands from the MCU 1 in the gate drive control devices 10 and 20. When an on command (High) is received in one drive command, the simultaneous on prevention circuit 50 masks the on command received in the other drive command, thereby preventing the upper and lower arms from being turned on simultaneously.

[0097] The simultaneous-on prevention circuit 50 includes resistors R1, R2, diodes Di1, and Di2. The resistor R1 transmits the drive command cmd1 to the NOT circuit INV3 as a simultaneous-on prevention command c2_onp. The resistor R2 transmits the drive command cmd2 to the NOT circuit INV2 as a simultaneous-on prevention command c1_onp. The diode Di1 transmits the gate monitor signal Mon_g1 to the NOT circuit INV3 as a simultaneous-on prevention command c2_onp. The diode Di2 transmits the gate monitor signal Mon_g2 to the NOT circuit INV2 as a simultaneous-on prevention command c1_onp.

[0098] Here, the resistor R1 and diode Di1 determine which logic level is output as the simultaneous-on prevention command c2_onp when the logic levels of the drive command cmd1 and the gate monitor signal Mon_g1 differ. For example, if the gate monitor signal Mon_g1 is low and the drive command cmd1 is high, the diode Di1 has a reverse voltage. Therefore, the logic level of the drive command cmd1 is output as the simultaneous-on prevention command c2_onp.

[0099] On the other hand, if the gate monitor signal Mon_g1 is High and the drive command cmd1 is Low, the diode Di1 will have a forward voltage, and therefore the logic of the gate monitor signal Mon_g1 is output as the simultaneous-on prevention command c2_onp.

[0100] Resistor R1 is provided to prioritize the logic of either the drive command cmd1 or the gate monitor signal Mon_g1, whichever is High. When the drive command cmd1 is High and the gate monitor signal Mon_g1 is Low, diode Di1 is reverse biased and turned OFF, and simultaneous on-state prevention command c2_onp is set to High (FIG. 7). Even if the drive command cmd2 is set to High (simultaneous on control), simultaneous on-state prevention command c2_onp is set to High (prohibition command), preventing simultaneous on-state.

[0101] 8, when the drive command cmd1 is Low and the gate monitor signal Mon_g1 is High, the diode Di1 is forward biased and turned ON, and the simultaneous-on prevention command c2_onp is set to High. Even if a High level is input to the drive command cmd2, simultaneous ON is prevented in the same manner as in the operation of the inverter device 600 shown in FIG.

[0102] Resistor R1 is set to a value that maintains the logic of the simultaneous on prevention command c2_onp and the drive command cmd1 even if their logic differs. For example, if the value of resistor R1 is too large, the logic may be inverted. Note that resistor R2 and diode Di2 operate in the same way as resistor R1 and diode Di1, except for the signal lines to which they are connected, so a description of their operation will be omitted.

[0103] As described above, in the inverter device 800 according to this embodiment, the gate monitor circuit (e.g., gate state determination circuit 14) detects that the gate voltage of the first semiconductor element 31 and the gate voltage of the second semiconductor element 32 have fallen below a predetermined detection threshold. The inverter device 800 also includes gate drive units (gate drive units 11, 12) that drive the gates of the first semiconductor element 31 and the second semiconductor element 32, and a simultaneous-on prevention circuit (simultaneous-on prevention circuit 50) that, when the gate monitor circuit has not detected that the gate voltage of one semiconductor element has fallen below the predetermined detection threshold, prohibits the gate drive unit from driving the gate of the other semiconductor element.

[0104] According to the present embodiment having the above configuration, an active dead time that can prevent the upper and lower arms from being turned on simultaneously can be realized with a small number of parts.

[0105] [Gate Driving Operation] Next, the gate driving operation of the inverter device 800 including the simultaneous on-prevention circuit 50 will be described with reference to FIG.

[0106] FIG. 9 is an example of a timing chart that schematically illustrates the gate drive operation of an inverter device 800 that includes a simultaneous-on prevention circuit 50. The following description of the timing chart shown in FIG. 9 will focus on differences from the timing chart according to the second embodiment shown in FIG. 6 . In FIG. 9 , only the semiconductor elements that are driven are different from time t8 to time t11, and the operation itself is the same as that from time t4 to time t7, so a description of the operation will be omitted. The example in FIG. 9 assumes a case in which the drive commands cmd1 and cmd2 mistakenly become ON commands (High) simultaneously.

[0107] At time t1: When the inverted logic of the simultaneous on-prevention command c1_onp is in the on-permitted state (high), if an on-command (high) is input to the drive command cmd1, the drive command cmd3 becomes an on-command (high). This causes the gate G1 voltage to start rising. At the same time, the inverted logic of the simultaneous on-prevention command c2_onp becomes on-prohibited (low) via resistor R1.

[0108] At time t2, even if an ON command (High) is input to the drive command cmd2, ON prohibition (Low) is input via the resistor R1 as the inverted logic of the simultaneous ON prevention command c2_onp. Therefore, the AND circuit 42 maintains the OFF command (Low) of the drive command cmd4.

[0109] At time t3, the potential of the gate G1 becomes equal to or higher than Vth_mon, and the gate monitor signal Mon_g1 is determined to be ON. In the example of Fig. 9, an OFF command (Low) is input to the drive command cmd2 before time t4.

[0110] At time t4, an ON command (High) is input to the drive command cmd2 after the OFF command, but ON prohibition (Low) is input to the inverted logic of the simultaneous ON prevention command c2_onp via the diode Di1. Therefore, the AND circuit 42 maintains the OFF command (Low) of the drive command cmd4.

[0111] Time t5: An OFF command (Low) is input to the drive command cmd1, and the potential of the gate G1 starts to decrease.

[0112] At time t6: The potential of gate G1 falls below Vth_mc, the Miller clamp circuit 15 starts operating, and the potential of gate G1 drops to the VSS2_1 potential. At the same time, the potential of gate G1 falls below Vth_mon, and an off-determination (Low) result is output to the gate monitor signal Mon_g1. As a result, the inverted logic of the simultaneous on-prevention command c2_onp becomes on-permitted (High). At this point, because an on command has been input to the drive command cmd2, the potential of gate G2 begins to rise. At the same time, the inverted logic of the simultaneous on-prevention command c1_onp becomes on-prohibited (Low) via diode Di2.

[0113] Time t7: When the gate G2 potential becomes equal to or higher than Vth_mon, the gate monitor signal Mon_g2 is determined to be ON.

[0114] As described above, in the inverter device 800 according to this embodiment, the simultaneous-on prevention circuit 50 is connected to the gate drive control device 10 via the active dead time control unit 40. In this embodiment, by providing the simultaneous-on prevention circuit 50, when the gate state determination circuit 14 does not detect that the gate voltage of one semiconductor element has fallen below a predetermined detection threshold, the other semiconductor element is prohibited from being turned on.

[0115] According to this embodiment having the above configuration, even if a command to turn on the upper and lower arms simultaneously is input due to a software abnormality in the microcontroller (MCU1), the simultaneous on-state prevention circuit 50 (GDIC) can prevent the upper and lower arms from turning on simultaneously.

[0116] Fourth Embodiment Next, the configuration of an inverter device according to a fourth embodiment of the present invention will be described with reference to FIG.

[0117] FIG. 10 shows an example of the configuration of a gate monitor unit included in an inverter device according to a fourth embodiment of the present invention. The gate monitor unit 12B shown in FIG. 10 is an example of a configuration in which the values ​​of Vth_mon and Vth_mc can be rewritten via SPI communication. The following describes the gate monitor unit 12B, focusing on the configuration that differs from the configuration of the gate monitor unit 12 according to the first embodiment shown in FIG. 2. The gate monitor unit 12B includes a buffer circuit BUF1, but as described with reference to FIG. 4, the buffer circuit BUF1 may not be provided if the conditions are met.

[0118] The gate monitor unit 12A includes an SPI communication circuit 1100 and a memory 1110 in addition to the configuration of the gate monitor unit 12 according to the first embodiment. SPI (Serial Peripheral Interface) is one of the standards for data transmission paths. SPI is a bus-type connection method in which multiple devices share a single transmission path, and employs a serial communication method that uses a single signal line for unidirectional communication.

[0119] The SPI communication circuit 1100 operates in accordance with a command input via the SPI communication Com_s1. For example, the SPI communication circuit 1100 rewrites the value of Vth_mon stored in the memory 1110 by inputting a command to change the value of Vth_mon via the SPI communication Com_s1. Furthermore, the SPI communication circuit 1100 may use the SPI communication Com_s1 to transmit information on whether or not the gate is being driven (the state of the drive commands cmd1 and cmd2). Note that the SPI communication may be configured to allow bidirectional data exchange by adding a signal line.

[0120] The memory 1110 reflects the stored information in Vth_mon or Vth_mc. When gate driving of the semiconductor element is stopped (when the drive commands cmd1 and cmd2 are both in the OFF command state), the memory 1110 changes the value of Vth_mon based on the value recorded inside the memory 1110. The memory 1110 can be a nonvolatile storage such as a ROM, a RAM, or an SSD (Solid State Drive).

[0121] [Threshold Changing Operation] Next, the threshold changing operation of the gate monitor unit 12B will be described with reference to Fig. 11. Fig. 11 shows an example of a timing chart that outlines the threshold changing operation of the gate monitor unit 12B. Fig. 11 shows an example of a startup operation in the gate drive control device 10 that includes the gate monitor unit 12B shown in Fig. 10.

[0122] Time t1: Power supply from the power supply VCC1 (FIG. 1) begins, and the potential of the power supply VCC1 begins to rise.

[0123] At time t2: After the potential of the power supply VCC1 rises, the SPI communication circuit 1100 sets the memory rewrite enable signal to enable (High in this embodiment) for the memory 1110. The memory 1110 reflects the initial value (Vth_L) of Vth_mon recorded in the memory 1110 in Vth_mon.

[0124] At time t3, command 1 is input via SPI communication Com_s1 to change the Vth_mon value to the Vth_H value. In response to command 1, the SPI communication circuit 1100 rewrites the initial value (Vth_L) in the memory 1110 to the SPI write value (Vth_H).

[0125] At time t4: The memory 1110 reflects the newly recorded Vth_H in Vth_mon.

[0126] At time t5: The MCU1 inputs a drive command cmd1 to the SPI communication circuit 1100, and gate driving is initiated based on the ON / OFF command of the drive command cmd1. At this time, the SPI communication circuit 1100 receives command 2 (gate driving in progress) via the SPI communication Com_s1. In accordance with command 2, the SPI communication circuit 1100 sets the memory rewrite enable signal to "prohibited" (low in this embodiment).

[0127] The gate monitor unit 12B according to the present embodiment described above includes a reference voltage that determines the control threshold (Vth_mc) and the detection threshold (Vth_mon). The reference voltage can be set before gate driving begins. The reference voltage can be generated by, for example, the reference voltage generation circuit 13 (FIG. 2).

[0128] In this embodiment having such a configuration, Miller clamp operation and gate-off detection can be performed at the optimal timing depending on the control threshold (Vth_mc) and detection threshold (Vth_mon) of the power device to be driven (first semiconductor element 31, second semiconductor element 32).

[0129] Furthermore, in this embodiment, an example has been shown in which Vth_mon is changed via SPI communication Com_s1 when the gate drive control device is started up, but Vth_mon may also be changed according to the system state if the gate drive is stopped after startup. For example, consider a case in which the gate voltage threshold of the power devices (first semiconductor element 31, second semiconductor element 32) has decreased due to long-term use. In such a case, a microcontroller such as MCU1 may detect deterioration of the power devices and change Vth_mon to an appropriate value as needed via SPI communication Com_s1.

[0130] In the gate monitor unit 12B according to this embodiment, at least one of the control threshold (Vth_mc) and the detection threshold (Vth_mon) can be set by an external signal, and can be changed according to the system state after being set before gate driving starts.

[0131] In this embodiment having such a configuration, by setting the control threshold and detection threshold using the SPI or an external port (not shown) when starting up the inverter device, it is possible to set the optimum threshold for the power device to be driven without changing the circuit configuration.

[0132] As described above, the present invention is not limited to the above-described embodiments, and various other modifications and applications are possible without departing from the spirit of the invention as defined in the claims. For example, the above-described embodiments have been described in detail and specifically to clearly explain the present invention, and the present invention is not necessarily limited to those including all of the components described. Furthermore, it is possible to replace part of the configuration of one embodiment with a component of another embodiment. It is also possible to add a component of another embodiment to the configuration of one embodiment. It is also possible to add, replace, or delete other components from part of the configuration of each embodiment.

[0133] For example, the configurations of the gate monitor units 12, 12A, 12C, and 12D shown in Figures 2, 4, 12, and 13 are applicable not only to the first embodiment but also to the second to fourth embodiments. Also, the gate monitor unit 12B in the fourth embodiment is applicable to the first to third embodiments.

[0134] Furthermore, for the purpose of reducing delay time due to signal transmission, some of the configurations, circuits, and functions described in each embodiment may be integrated into a single semiconductor device. That is, one or more of the gate driver, Miller clamp circuit, gate monitor circuit (e.g., gate state determination circuit 14), active dead time control unit (active dead time control unit 40), and simultaneous on prevention circuit may be integrated into a single semiconductor device. The semiconductor device may then be configured to output to the outside the semiconductor device the fact that the gate voltage of either the first semiconductor element or the second semiconductor element has fallen below a predetermined detection threshold.

[0135] In this configuration, the wiring length of the wiring for transmitting each signal can be shortened by integration, and the delay time of signal transmission can be reduced.

[0136] Furthermore, the above-described configurations, functions, processing units, etc. may be partially or entirely implemented in hardware by, for example, designing them as integrated circuits, etc. As the hardware, a broad processor device such as an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit) may be used.

[0137] In the above-described embodiment, the control lines and information lines are those that are considered necessary for the explanation, and not all control lines and information lines in the product are necessarily shown. In reality, it can be considered that almost all components are connected to each other.

[0138] REFERENCE SIGNS LIST 10, 20... Gate drive control device, 11... Gate drive unit, 12, 12A to 12D... Gate monitor unit, 13... Reference voltage generation circuit, 14... Gate state determination circuit, 15... Miller clamp circuit, 21... Gate drive unit, 22... Gate monitor unit, 31... First semiconductor element, 32... Second semiconductor element, 40... Active dead time control unit, 50... Simultaneous on prevention circuit, 100, 600, 800... Inverter device, G1, G2... Gate

Claims

1. A gate drive control device for driving a gate of a first semiconductor element, comprising: a mirror clamp circuit that holds the gate voltage at a low level when the gate voltage of the first semiconductor element becomes lower than a predetermined control threshold; and a gate monitor circuit that detects that the gate voltage of the first semiconductor element has fallen below a predetermined detection threshold of a positive potential. When the first semiconductor element is turned off, the gate monitor circuit is configured to detect that the gate voltage of the first semiconductor element has fallen below the detection threshold simultaneously with or after the start of operation of the mirror clamp circuit. Gate drive control device.

2. An active dead time control unit that turns on a second semiconductor element of a pair of arms connected in series with the first semiconductor element after it is detected by the gate monitor circuit that the gate voltage of the first semiconductor element has fallen below the detection threshold. The gate drive control device according to claim 1.

3. The gate drive control device according to claim 2, wherein the detection threshold of the gate monitor circuit is set to the same value as the control threshold of the mirror clamp circuit or a value smaller than the control threshold.

4. The gate drive control device according to claim 3, wherein when the gate monitor circuit does not detect that the gate voltage of one semiconductor element has fallen below a predetermined detection threshold, turning on of the other semiconductor element is prohibited.

5. The gate monitor circuit detects that the gate voltages of the first semiconductor element and the second semiconductor element have fallen below a predetermined detection threshold, a gate drive unit that drives the gates of the first semiconductor element and the second semiconductor element, and when the gate monitor circuit does not detect that the gate voltage of one semiconductor element has fallen below a predetermined detection threshold, a simultaneous on prevention circuit that prohibits driving of the gate of the other semiconductor element by the gate drive unit. The gate drive control device according to claim 4.

6. A reference voltage for determining the control threshold and the detection threshold, wherein the reference voltage is set before the start of gate drive. The gate drive control device according to claim 3.

7. The gate drive control device according to claim 3, wherein at least one of the detection threshold value or the control threshold value is configured to be settable based on information of an external signal, and after being set before the start of gate driving, it is changed according to the information of the external signal according to the state of the first semiconductor element.

8. The gate drive control device according to any one of claims 1 to 7, wherein any one or more of the gate drive unit, the mirror clamp circuit, the gate monitor circuit, the active dead time control unit, and the simultaneous turn-on prevention circuit are integrated into one semiconductor device, and are configured to output to the outside of the semiconductor device that the gate voltage of either the first semiconductor element or the second semiconductor element has fallen below a predetermined detection threshold value.

9. A power conversion device including: a gate drive unit that drives the gates of the first semiconductor element and the second semiconductor element constituting the upper arm and the lower arm; a mirror clamp circuit that holds the gate voltage of the corresponding semiconductor element at a low level when the gate voltage of the first semiconductor element and the gate voltage of the second semiconductor element become lower than a predetermined control threshold value; and a gate monitor circuit that detects that the gate voltage of the first semiconductor element and the gate voltage of the second semiconductor element have fallen below a predetermined detection threshold value of a positive potential. When one of the semiconductor elements is turned off, the gate monitor circuit is configured to detect that the gate voltage of one of the semiconductor elements has fallen below the detection threshold value simultaneously with or after the start of operation of the mirror clamp circuit.

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