Cell multiplex inverter

Abstract

In this cell multiplexing inverter in which a plurality of cells are connected in multiplexed form to each phase of an AC system through star connection, even when an imbalance has occurred in AC voltages or when an imbalanced AC voltage is to be intentionally outputted, providing a cell to a corresponding phase or increasing a cell DC voltage only in the corresponding phase is no longer necessary, and furthermore, a common mode current is suppressed. In the present invention, DC components are extracted by converting phase voltage detection signals vU, vV, vW or voltage command values vU*, vV*, vW* into values on rotating coordinates synchronous with a system frequency and values on rotating coordinates rotating in the reverse direction to the system frequency. A zero-phase-voltage d-axis component V0d and a zero-phase-voltage q-axis component V0q are calculated on the basis of a normal-phase d-axis component V1d, a normal-phase q-axis component V1q, a reverse-phase d-axis component V2d, and a reverse-phase q-axis component V2q, all of which are DC components. The zero-phase-voltage d-axis component V0d and the zero-phase-voltage q-axis component V0q are multiplied by a cosine wave and by a sine wave, then the results are added together, and the resulting value is added to the voltage command values vU*, vV*, vW*, to thereby obtain corrected voltage command values vU*', vV*', vW*'.

Description

Cell-multiplexed inverter

[0001] The present invention relates to a multi-cell inverter in which a plurality of cells are connected in a star connection to each phase of an AC system.

[0002] One example of a multi-cell inverter is a modular multilevel cascade converter (MMCC) with single-star bridge cells (SSBC) connected to a three-phase AC grid. Also known is a configuration in which a separate power supply or DC / DC converter is connected to the DC side of the MMCC-SSBC full-bridge cell.

[0003] A major example of this configuration is the solid-state transformer (SST) described in Patent Document 1. Figure 1 shows an SST consisting of three cells per phase, which combines an MMCC-SSBC and a dual active bridge (DAB) type bidirectional isolated DC / DC converter.

[0004] High-voltage AC power is converted into DC power using series-connected cells, and the DC power is converted into high-frequency AC power, which is then insulated and rectified using a transformer to convert back into DC power. Reverse power interchange is also possible. Because SST uses a high-frequency transformer, it can be made smaller than conventional commercial frequency transformers.

[0005] Another application is the high-voltage multiple inverter disclosed in Patent Document 2.

[0006] When an SST is connected to an unbalanced three-phase AC system, or when a high-voltage multiple inverter intentionally outputs an unbalanced three-phase AC voltage, the phase voltage amplitude of a certain phase increases, and the AC voltage that the cell connected to that phase should output also increases.

[0007] To address this, it is necessary to increase the DC voltage of the cells, but this also requires that the withstand voltage of the components be increased, which leads to increased costs and size.Using switching devices with high withstand voltage for the cells also leads to increased losses.

[0008] Furthermore, some equipment may be required to continue operating even if some cells fail.

[0009] Patent Document 1 discloses the main circuit configuration of an SST, and Patent Document 2 discloses the configuration of a high-voltage multiple inverter.

[0010] Patent Documents 3 and 4 disclose methods for continuing operation when a cell fails. In both documents, the failed cell is first short-circuited. However, this alone reduces the AC voltage amplitude that can be output from the phase containing the failed cell. Therefore, Patent Document 3 inserts a spare cell prepared in advance into the corresponding phase. Patent Document 4 increases the DC voltage of the non-failed cells in the corresponding phase.

[0011] Patent Documents 5 and 6 disclose techniques for dealing with voltage imbalances in an MMCC-SSBC by using a zero-phase sequence voltage. The purpose of this technique is to balance the capacitor voltages of each cell.

[0012] Patent Document 7 describes a technology for lowering the peak voltage command value by superimposing a zero-phase sequence voltage on the voltage command value of a single three-phase inverter that does not use cell multiplexing. This technology can also be used when an unbalanced three-phase AC voltage is output, making the peak voltage command value of each phase equal. The technology described in Patent Document 7 can be applied to MMCC-SSBC and high-voltage multiplexed inverters.

[0013] JP 10-75580 JP 11-122943 JP 2012-147613 WO 2017 / 094379 A1 JP 2013-5694 JP 2021-19481 JP 3-107373

[0014] However, Patent Documents 1 and 2 do not particularly mention connection to an unbalanced system, output of an unbalanced voltage, or how to deal with a cell failure.

[0015] In Patent Document 3, it is necessary to incorporate a spare cell into the device, and a switch for turning on the spare cell is also required, which increases costs and size. If no failure occurs, the spare cell will not be used and may be wasted.

[0016] In Patent Document 4, the DC voltage of the other cells in the corresponding phase is increased, which requires the cell to be designed taking this into account, resulting in problems of increased cost, size, and loss. Furthermore, neither Patent Document 3 nor Patent Document 4 describes a method for dealing with voltage imbalance.

[0017] In Patent Documents 5 and 6, only a capacitor is connected to the DC side of each cell, and applications that do not handle active power, such as reactive power compensators, are envisioned. However, high-voltage multiplex inverters and SSTs have separate active power paths, which can be used to exchange power between cells and balance capacitor voltages. This reduces the importance of the technologies in Patent Documents 5 and 6. Furthermore, neither Patent Document 5 nor 6 describes a method for dealing with cell failures.

[0018] In Patent Document 7, harmonics of odd multiples of three are superimposed as the zero-phase voltage. However, the higher the frequency of the superimposed zero-phase voltage, the larger the common-mode current that flows through the stray capacitance of the circuit. This can cause many problems, such as increased heat generation in components, reduced efficiency, malfunction of ground fault detectors, insulation breakdown in high-frequency transformers, and electromagnetic interference to other equipment. Therefore, it is necessary to lower the frequency of the superimposed zero-phase voltage. Furthermore, Patent Document 7 does not disclose a method for dealing with cell failure.

[0019] As described above, in a cell-multiplexed inverter in which multiple cells are connected in a star connection to each phase of an AC system, even when an imbalance occurs in the AC voltage or when an unbalanced AC voltage is intentionally output, the challenge is to eliminate the need to input a cell to the relevant phase or to increase the DC voltage of the cell only in the relevant phase, and to suppress the common-mode current.

[0020] The present invention has been devised in view of the above-mentioned problems in the related art, and one aspect thereof is a multi-cell inverter including: a plurality of cells connected in multiplex with star connection to each phase of an AC system, each cell having a full-bridge circuit on the AC system side; a correction voltage command value generation unit that generates a correction voltage command value by superimposing a zero-phase sequence voltage having the same frequency as a fundamental wave on a voltage command value; and a gate signal generation unit that generates a gate signal for the full-bridge circuit based on the correction voltage command value, wherein the correction voltage command value generation unit superimposes the zero-phase sequence voltage having the same frequency as the fundamental wave on the voltage command value so as to reduce an amplitude difference between the correction voltage command values ​​for each phase.

[0021] In another aspect, there is provided a multi-cell inverter including a plurality of cells connected in a star connection to each phase of an AC system in multiplexed fashion and having a full-bridge circuit on the AC system side; a correction voltage command value generation unit that generates a correction voltage command value by superimposing a zero-phase sequence voltage of the same frequency as the fundamental wave on a voltage command value; and a gate signal generation unit that generates a gate signal for the full-bridge circuit based on the correction voltage command value, wherein the correction voltage command value generation unit superimposes the zero-phase sequence voltage of the same frequency as the fundamental wave so that the difference between the amplitude of the correction voltage command value for each phase multiplied by the number of cells in each phase and divided by the number of cells in each phase that are operating without failure is small among the three phases.

[0022] In one aspect, the corrected voltage command value generation unit includes a phase output unit that outputs a phase ωt synchronized with the AC voltage of the grid; a first dq converter that converts a value obtained by multiplying the phase voltage detection signal or the voltage command value, or the phase voltage detection signal or the voltage command value, by a coefficient obtained by dividing the number of cells in each phase by the number of cells in each phase that are operating without a fault, into a value on a rotating coordinate system synchronized with the grid frequency; a second dq converter that converts a value obtained by multiplying the phase voltage detection signal or the voltage command value, or the phase voltage detection signal or the voltage command value, by a coefficient obtained by dividing the number of cells in each phase by the number of cells in each phase that are operating without a fault, into a value on a rotating coordinate system that rotates in a direction opposite to the grid frequency; and a positive-phase d-axis component that extracts a DC component from the output of the first dq converter. a computing unit that computes a zero-phase-sequence voltage d-axis component and a zero-phase-sequence voltage q-axis component that equalize the AC side output voltage of each of the cells based on the positive-phase-sequence q-axis component and the negative-phase-sequence d-axis component and the negative-phase-sequence q-axis component obtained by extracting a DC component from the output of the second dq converter; a first multiplier that multiplies the zero-phase-sequence voltage d-axis component by cosωt or sinωt; a second multiplier that multiplies the zero-phase-sequence voltage q-axis component by sinωt when the first multiplier multiplies the zero-phase-sequence voltage by cosωt, and multiplies the zero-phase-sequence voltage q-axis component by cosωt when the first multiplier multiplies the zero-phase-sequence voltage by sinωt; a first adder that adds the output of the first multiplier and the output of the second multiplier; and a second adder that adds the output of the first adder to the voltage command value and outputs the result as the corrected voltage command value.

[0023] In one aspect, the computing unit calculates the d-axis component of the zero-phase-sequence voltage and the q-axis component of the zero-phase-sequence voltage based on equation (3).

[0024]

[0025] V ０ｄ : Zero-phase voltage d-axis component V ０ｑ : Zero-phase voltage q-axis component V １ｄ : Positive sequence voltage d-axis component V １ｑ : Positive sequence voltage q-axis component V ２ｄ : Negative sequence voltage d-axis component V ２ｑ : negative sequence voltage q-axis component.

[0026] In another aspect, the computing unit calculates the d-axis component of the zero-phase-sequence voltage and the q-axis component of the zero-phase-sequence voltage based on equation (4).

[0027]

[0028] V ０ｄ : Zero-phase voltage d-axis component V ０ｑ : Zero-phase voltage q-axis component V １ｄ : Positive sequence voltage d-axis component V １ｑ : Positive sequence voltage q-axis component V ２ｄ : Negative sequence voltage d-axis component V ２ｑ : negative sequence voltage q-axis component.

[0029] In another aspect, the computing unit calculates the d-axis component of the zero-phase-sequence voltage and the q-axis component of the zero-phase-sequence voltage based on equation (5).

[0030]

[0031] V ０ｄ : Zero-phase voltage d-axis component V ０ｑ : Zero-phase voltage q-axis component V ２ｄ : Negative sequence voltage d-axis component V ２ｑ : negative sequence voltage q-axis component V １ : Voltage positive-sequence component.

[0032] In one aspect, the correction voltage command value generating unit generates the negative-phase d-axis component V ２ｄ =V １ｄ , and the reverse phase q-axis component is V ２ｑ = 0, the zero-phase voltage d-axis component V ０ｄ =-V １ｄ / 2, the zero-phase voltage q-axis component V ０ｑ = 0, and the negative phase d-axis component V ２ｄ =-V １ｄ / 2, and the reverse phase q-axis component is V ２ｑ = -√3V １ｄ In the case of / 2, the zero-phase voltage d-axis component V ０ｄ =V １ｄ / 4, the zero-phase voltage q-axis component V ０ｑ =√3V １ｄ / 4, and the reverse-phase d-axis component V ２ｄ =-V １ｄ / 2, and the reverse phase q-axis component is V２ｑ =√3V １ｄ In the case of / 2, the zero-phase voltage d-axis component V ０ｄ =V １ｄ / 4, the zero-phase voltage q-axis component V ０ｑ = -√3V １ｄ / 4.

[0033] According to the present invention, in a cell-multiplexed inverter in which a plurality of cells are connected in a star connection to each phase of an AC system, even when an imbalance occurs in the AC voltage or when an unbalanced AC voltage is intentionally output, it is not necessary to input a cell to the relevant phase or to increase the DC voltage of the cell only in the relevant phase, and it is also possible to suppress common-mode current.

[0034] 1 is a circuit diagram showing a main circuit configuration of embodiments 1 to 3. A circuit diagram showing another example of a cell. A block diagram showing a correction voltage command value generating unit of embodiment 1. A block diagram showing a correction voltage command value generating unit of embodiment 2. A diagram showing operation when one U-phase cell fails. A block diagram showing a correction voltage command value generating unit of embodiment 3.

[0035] Hereinafter, first to third embodiments of the multi-cell inverter of the present invention will be described in detail with reference to FIGS.

[0036] First Embodiment First, the main circuit configuration of an MMCC-SSBC shown in FIG. 1 will be described as an example of a cell multiplexing inverter.

[0037] As shown in Figure 1(a), cells cellu1, cellu2, and cellu3 are connected in series to the U phase of the AC system AC via a reactor Lu. Similarly, cells cellv1, cellv2, and cellv3 are connected in series to the V phase of the AC system AC via a reactor Lv, and cells cellw1, cellw2, and cellw3 are connected in series to the W phase of the AC system AC via a reactor Lw. Here, the AC phase voltage (phase voltage detection signal) is V Ｕ , v Ｖ , v Ｗ Let's say.

[0038] The DC terminals of cells cellu1, cell cellu2, cell cellu3, cell cellv1, cell cellv2, cell cellv3, cell cellw1, cell cellw2, and cell cellw3 are connected in parallel. The DC voltages of cells cellu1 to cellw3 are V ＤＣ Let's say.

[0039] Figure 1(b) shows the configuration of one cell. One end of switching devices S1 and S3 is connected to one AC terminal of the cell. One end of switching devices S2 and S4 is connected to the other AC terminal of the cell. The other ends of switching devices S1 and S2 are connected to one end of first capacitor C1. The other ends of switching devices S3 and S4 are connected to the other end of first capacitor C1. The above switching devices S1, S2, S3, and S4 form a full bridge circuit provided on the AC side of the AC system.

[0040] Switching devices S5 and S6 are connected in series between one end and the other end of the first capacitor C1, and switching devices S7 and S8 are connected in series between one end and the other end of the first capacitor C1.

[0041] One end of a reactor L1 is connected to the connection point of switching devices S5 and S6. One end of a reactor L2 is connected to the connection point of switching devices S7 and S8. A primary winding of a transformer Tr is connected between the other end of the reactor L1 and the other end of the reactor L2.

[0042] A second capacitor C2 is connected between one DC terminal and the other DC terminal of the cell. Switching devices S9 and S11 are connected in series between one end and the other end of the second capacitor C2. Furthermore, switching devices S10 and S12 are connected in series between one end and the other end of the second capacitor C2.

[0043] One end of a reactor L3 is connected to the connection point of switching devices S9 and S11. One end of a reactor L4 is connected to the connection point of switching devices S10 and S12. A secondary winding of a transformer Tr is connected between the other end of reactor L3 and the other end of reactor L4. Note that reactors L1 to L4 in FIG. 1(b) may be omitted.

[0044] 1(b) adjusts the phase difference between the inverter output voltages on both sides of the transformer Tr to adjust the interchanged active power. Gate signals for switching devices S5 to S12 are generated so that the phase difference between the inverter output voltages on both sides of the transformer Tr becomes the desired phase difference (i.e., so that the interchanged active power becomes the desired). Since the gate signals for switching devices S5 to S12 of the inverters on both sides of the transformer Tr are not directly related to the present invention, detailed explanations are omitted here, and a conventionally known method is used.

[0045] The gate signal "gate" of the switching devices S1 to S4 of the full bridge circuit provided on the AC side of the alternating current system AC receives a gate signal generated in accordance with the first embodiment, which will be described later.

[0046] Another example of a circuit diagram for one cell is shown in Figure 2. In this example, an LLC resonant converter is used as the bidirectional isolated DC / DC converter.

[0047] 2, a third capacitor C3 is connected between the connection point of switching devices S5 and S6 and reactor L1. A fourth capacitor C4 is connected between the connection point of switching devices S7 and S8 and reactor L2. A fifth capacitor C5 is connected between the connection point of switching devices S9 and S11 and reactor L3. A sixth capacitor C6 is connected between the connection point of switching devices S10 and S12 and reactor L4.

[0048] The NOT circuit 26 inverts the 50% duty cycle signal. The dead time unit 27 inserts dead time into the 50% duty cycle signal and the inverted signal of the 50% duty cycle signal, and outputs the resulting signals as gate signals to the switching devices S5 to S12 of the inverters on both sides of the transformer Tr. The remaining circuit configuration is the same as in FIG. 1(b).

[0049] In FIG. 2, third to sixth capacitors C3 to C6 are connected in series to a transformer (high-frequency transformer) Tr. This causes resonance between the leakage inductance of the transformer Tr and reactors L1 to L4 connected in series. The inverters on both sides of the transformer Tr output AC voltages at this resonant frequency. The duty ratio of the gate signals driving the inverters on both sides of the transformer Tr is fixed at 50%. This allows active power corresponding to the difference in DC voltage between the two sides of the transformer Tr to be diverted through the transformer Tr. The gate signals of the switching devices S5 to S12 of the inverters on both sides of the transformer Tr are not directly related to the present invention, so a detailed description thereof will be omitted here.

[0050] The gate signal "gate" of the switching devices S1 to S4 of the full bridge circuit provided on the AC side of the alternating current system AC receives a gate signal generated in accordance with the first embodiment, which will be described later.

[0051] 3 shows a block diagram of the corrected voltage command value generating unit of the present embodiment 1. In the present embodiment 1, the voltage responsibilities of the cells are equalized in an application where it is not necessary to equalize the power responsibilities of the cells.

[0052] A phase output unit (for example, a PLL: Phase-Locked Loop) 1 outputs a phase voltage detection signal v Ｕ , v Ｖ , v Ｗ The phase ωt synchronized with the AC voltage of the system is output from the inverter.

[0053] Phase voltage detection signal V Ｕ , v Ｖ , v Ｗ The phase voltage detection signal v may be converted into a phase voltage by calculation after detecting the line voltage. Ｕ , v Ｖ , v Ｗ Instead of this, the voltage command value v Ｕ *, v Ｖ *, v Ｗ * may be input to the phase output unit 1. Furthermore, the system AC voltage input to the phase output unit 1 may be only one representative phase.

[0054] In a motor drive application of a high-voltage multiple inverter, the phase ωt may be detected from a rotary encoder or resolver, or may be estimated by an observer, etc. In the following, the phase output unit 1 indicates the PLL 1.

[0055] The first low-pass filter 2 receives the phase voltage detection signal v Ｕ , v Ｖ , v Ｗ (voltage command value v Ｕ *, v Ｖ *, v Ｗ *) to remove switching noise and other noise.

[0056] The first dq converter 3 converts the phase voltage detection signal v Ｕ , v Ｖ , v Ｗ is converted into a value on a rotating coordinate system synchronized with the system frequency based on the phase ωt.

[0057] The second low-pass filters 4 and 5 extract only the DC component from the output of the first dq converter 3. The d-axis component of the output of the second low-pass filters 4 and 5 is used as the phase voltage detection signal v Ｕ , v Ｖ , v Ｗ The positive phase d-axis component V １ｄ , the q-axis component is the positive-phase q-axis component V １ｑ If the PLL 1 is operating normally, the positive phase q-axis component V １ｑ is zero and is therefore not used.

[0058] The second dq converter 6 converts the phase voltage detection signal v Ｕ , v Ｖ , v Ｗ is converted into a value on a rotating coordinate system that rotates in the opposite direction to the system frequency based on the phase −ωt.

[0059] The third low-pass filters 7 and 8 extract only the DC component from the output of the second dq converter 6. The outputs of the third low-pass filters 7 and 8 are respectively the phase voltage detection signals v Ｕ , v Ｖ , v Ｗ The negative phase d-axis component V ２ｄ , reverse phase q-axis component V ２ｑ This becomes:

[0060] The calculator 9 calculates the positive phase d-axis component V １ｄ , positive phase q-axis component V １ｑ , reverse-phase d-axis component V ２ｄ , reverse phase q-axis component V ２ｑ Using equation (3) described later, the zero-phase voltage d-axis component V ０ｄ , zero-phase voltage q-axis component V ０ｑ The d-axis component of the zero-phase voltage V can be calculated by using equations (4) and (5) instead of equation (3). ０ｄ and the zero-phase voltage q-axis component V ０ｑ In this calculator 9, when the amplitudes of the positive and negative phase components of the AC voltage are approximately equal, V ０ｄ =V ０ｑ =0 is output.

[0061] The oscillator 10 outputs a sine wave sinωt and a cosine wave cosωt from a phase ωt.

[0062] The first multiplier 11 multiplies the zero-phase voltage d-axis component V ０ｄ and the cosine wave cosωt. The second multiplier 12 calculates the product of the zero-phase voltage q-axis component V ０ｑ and the sine wave sinωt.

[0063] The first adder 13 multiplies the V output from the first multiplier 11 by ０ｄ cosωt and V output by the second multiplier 12 ０ｑ Find the sum of sinωt.

[0064] The second adders 14, 15, and 16 calculate the voltage command value v Ｕ *, v Ｖ *, v Ｗ *The V calculated by the first adder 13 is added to each ０ｄ cosωt+V ０ｑ sinωt is added. Voltage command value v Ｕ *, v Ｖ *, v Ｗ * may be given as a fixed sine wave or may be obtained by feedback control of voltage or current. Ｕ *',v Ｖ *',v Ｗ *' is the corrected voltage command value.

[0065] Corrected voltage command value vＵ *',v Ｖ *',v Ｗ *' generates a gate signal (on / off command signal) by comparing carrier triangular waves in the subsequent stage (gate signal generation section) and inputs it to the switching devices S1 to S4 of the full bridge circuit provided on the AC side of the AC system of each cell in Figures 1(b) and 2. The above gate signal generation method is disclosed in Patent Document 6.

[0066] In the first embodiment, the correction voltage command value v Ｕ *',v Ｖ *',v Ｗ *' are equal (the difference is small), the three-phase voltage command value v Ｕ *, v Ｖ *, v Ｗ *A zero-phase sequence voltage with the same frequency as the fundamental wave is superimposed on the voltage command value v. The zero-phase sequence voltage required for this purpose is calculated. Ｕ *, v Ｖ *, v Ｗ * is the AC phase voltage (phase voltage detection signal) v Ｕ , v Ｖ , v Ｗ The AC phase voltage (phase voltage detection signal) v Ｕ , v Ｖ , v Ｗ is defined as the following equation (1).

[0067]

[0068] Here, V １ｄ is the positive d-axis component of the AC voltage, V ２ｄ is the negative phase d-axis component, V ２ｑ is the negative-phase q-axis component. １ｑ is a positive phase q-axis component, but is zero if the PLL 1 is operating normally.

[0069] V ０ｄ , V ０ｑ are the d-axis component and q-axis component of the zero-phase-sequence voltage superimposed in the first embodiment. Since the purpose is to make the amplitudes of the defined AC voltages equal, the d-axis component of the zero-phase-sequence voltage V that satisfies the formula (2) is ０ｄ , zero-phase voltage q-axis component V ０ｑ Ask for.

[0070]

[0071] By solving this equation, equation (3) is obtained.

[0072]

[0073] Positive phase q-axis component V １ｑ If is close to zero, equation (3) can be approximated to equation (4).

[0074]

[0075] Positive phase q-axis component V １ｑ If is equal to zero, then equation (3) can be simplified to equation (5). In equation (5), V １ indicates the positive sequence component of the AC voltage.

[0076]

[0077] In the first embodiment, the required zero-phase voltage d-axis component V is calculated based on the equation (3). ０ｄ , zero-phase voltage q-axis component V ０ｑ Calculate the voltage command value v Ｕ *, v Ｖ *, v Ｗ First, the AC phase voltage detection signal v Ｕ , v Ｖ , v Ｗ or detects the voltage command value v Ｕ *, v Ｖ *, v Ｗ * is directly input, converted into a value on a rotating coordinate system synchronized with the system frequency, and the DC component is extracted to obtain the positive-phase d-axis component V １ｄ , positive phase q-axis component V １ｑ In addition, by extracting the DC component from the value on the rotating coordinate system that rotates in the opposite direction to the system frequency, the negative-phase d-axis component V ２ｄ , reverse phase q-axis component V ２ｑ You can get.

[0078] Then, using equation (3), the zero-phase voltage d-axis component V ０ｄ , zero-phase voltage q-axis component V ０ｑ The zero-phase sequence voltage to be superimposed is calculated from the product of the cosine wave cosωt and the sine wave sinωt, and the voltage command value v Ｕ *, v Ｖ *, v ＷIn grid-connected applications, if the PLL is operating normally, the positive-phase q-axis component V １ｑ is zero, so the zero-phase voltage d-axis component V ０ｄ , zero-phase voltage q-axis component V ０ｑ may be calculated.

[0079] In equations (3), (4), and (5), when the denominator is zero, that is, when the amplitudes of the positive and negative voltages are equal, there is no solution, and the voltage command value v Ｕ *, v Ｖ *, v Ｗ * cannot be made equal. Therefore, when the amplitudes of the positive and negative sequence voltages are almost equal, the zero-sequence voltage d-axis component V ０ｄ , zero-phase voltage q-axis component V ０ｑ Set to zero.

[0080] According to the first embodiment, in a star-connected cell-multiplexed inverter such as an MMCC-SSBC, the AC output voltages of the cells can be equalized even when an AC voltage imbalance occurs or when an intentionally unbalanced AC voltage is output. This eliminates the need to insert a cell into a phase or to raise the cell DC voltage of only that phase when the voltage amplitude of that phase increases. Furthermore, because the superimposed zero-phase voltage is only the fundamental wave component, common-mode current can be suppressed.

[0081] In the first embodiment, the DC voltage of all cells needs to be increased or raised in advance, but the increase in DC voltage can be significantly suppressed compared to the conventional technology, and the increase in the cell's withstand voltage can be minimized, thereby reducing costs and size.

[0082] Furthermore, since the zero-phase sequence voltage to be superimposed in the first embodiment is determined by feedforward, fluctuations in the AC voltage can be quickly followed, and the device is theoretically highly stable.

[0083] 4 shows a block diagram of a correction voltage command value generating unit of the second embodiment. The second embodiment differs from the first embodiment in the following points.

[0084] In the coefficient multiplier 17, the phase voltage detection signal v Ｕ , v Ｖ , vＷ (or voltage command value v Ｕ *, v Ｖ *, v Ｗ *) with coefficient N / n Ｕ , N / n Ｖ , N / n Ｗ The numerator of the coefficient, N, is the number of cells in each phase. In the example of Figure 1, N = 3. The denominator of the coefficient, n Ｕ , n Ｖ , n Ｗ is the number of cells in each phase that are operating without failure. The phase voltage detection signal v Ｕ , v Ｖ , v Ｗ (or voltage command value v Ｕ *, v Ｖ *, v Ｗ *) uses the value multiplied by this coefficient.

[0085] In the second embodiment, a function for reducing the voltage duty of a phase in which a faulty cell exists is added to the first embodiment. The required zero-phase sequence voltage should normally be found by solving equation (6).

[0086]

[0087] However, in equation (6), the number of variables increases, making it difficult to derive a solution, and the derived equation becomes very complex, making it difficult to implement in a control program.

[0088] Therefore, the phase voltage detection signal v Ｕ , v Ｖ , v Ｗ is multiplied by a coefficient, and the AC voltage of the phase including the faulty cell is made larger according to the number of faulty cells, and the positive-phase d-axis component V １ｄ , positive phase q-axis component V １ｑ , reverse-phase d-axis component V ２ｄ , reverse phase q-axis component V ２ｑ is calculated and substituted into equation (3) to obtain the approximately required zero-phase voltage d-axis component V ０ｄ , zero-phase voltage q-axis component V ０ｑ get.

[0089] This zero-phase voltage d-axis component V ０ｄ , zero-phase voltage q-axis component V ０ｑ voltage command value v Ｕ *, vＶ *, v Ｗ By superimposing *, the amplitude of the voltage command value of a phase in which a faulty cell exists can be reduced. Here, as an example of the coefficient, N / n Ｕ , N / n Ｖ , N / n Ｗ was used.

[0090] The effect of the second embodiment will be explained with reference to Fig. 5. Fig. 5(a) shows a case where the number of cells in each phase is N=3, the AC voltage is three-phase balanced, and there is no negative-phase voltage (V ２ｄ =V ２ｑ 10 is a phasor diagram of the voltage command value when Vout is set to 0.

[0091] Here, one U-phase cell fails and Ｕ = 2. Figure 5(b) shows the case where the line voltage is maintained by applying Patent Document 4, and the remaining two U-phase cells need to output 1.5 times the AC voltage. To accommodate this, the DC voltage of the U-phase cell also needs to be increased by 1.5 times.

[0092] FIG. 5C shows the case where the technique of the second embodiment is applied. Ｕ *, v Ｖ *, v Ｗ * is the zero-phase voltage d-axis component V ０ｄ , zero-phase voltage q-axis component V ０ｑ By superimposing this, the output voltage of the U-phase cell can be reduced. Although the cell output voltages of the V-phase and W-phase cells increase, the same line voltage can be maintained by multiplying the AC voltage of all cells, including the U-phase, by approximately 1.15 times.

[0093] That is, the correction voltage command value v Ｕ *',v Ｖ *',v Ｗ *' amplitude multiplied by the number of cells in each phase N to get the number of cells in each phase that are operating without failure n Ｕ , n Ｖ , n Ｗ A zero-phase voltage of the same frequency as the fundamental wave is superimposed so that the difference between the values ​​obtained by dividing by is small among the three phases.

[0094] Note that the gate signals generated based on Figure 4 are for healthy cells that are not faulty. For a faulty cell, the AC system turns on switching devices S1 and S3, or turns on switching devices S2 and S4 to output zero voltage, or performs short-circuit treatment using an external switch. Switching devices S5 to S12 are turned off.

[0095] In addition to the effects of embodiment 1, embodiment 2 can equalize the AC output voltages of the cells even when some of the cells fail and short-circuit treatment is performed. Operation can be continued even when more cells than in the prior art fail.

[0096] 6 shows a block diagram of a correction voltage command value generating unit of the present embodiment 3. The configuration before the calculator 9 is the same as that of the first or second embodiment. The present embodiment 3 differs from the first or second embodiment in the following points.

[0097] In this third embodiment, the zero-phase voltage d-axis component V ０ｄ , zero-phase voltage q-axis component V ０ｑ In the calculator 9 for calculating the above, the equation (5) is used.

[0098] The comparator 18 detects the negative phase d-axis component V ２ｄ is the positive phase d-axis component V １ｄ The comparator 19 determines whether the negative-phase d-axis component V ２ｄ Ga-V １ｄ The comparator 20 determines whether the negative phase q-axis component V ２ｑ The comparator 21 determines whether the negative phase q-axis component V ２ｑ is -√3V １ｄ The comparator 22 determines whether the negative phase q-axis component V ２ｑ is √3V １ｄ Determine whether it is equal to / 2.

[0099] The comparator 18 is configured to set a threshold value in advance and calculate the negative phase d-axis component V ２ｄ and the positive d-axis component V １ｄ If the difference between these two is smaller than a threshold value, they may be considered equal. The threshold value may have a hysteresis characteristic. The same applies to the comparators 19 to 22.

[0100] The AND element 23 outputs the negative-phase d-axis component V ２ｄ Ga-V １ｄ / 2 and the negative-phase q-axis component V ２ｑ is √3V １ｄ If the output of the AND element 23 is 1, the switch SW1 outputs 1, and if the output of the AND element 23 is 1, the switch SW1 outputs 0. ０ｄ As V １ｄ If the output of the AND element 23 is 1, the switch SW2 outputs the zero-phase voltage q-axis component V ０ｑ As a result, it is -√3V １ｄ If it is 0, the result of equation (5) is output.

[0101] The AND element 24 outputs the negative-phase d-axis component V ２ｄ Ga-V １ｄ / 2 and the negative-phase q-axis component V ２ｑ is -√3V １ｄ If the output of the AND element 24 is 1, the switch SW3 outputs 1, and if the output of the AND element 24 is 1, the switch SW3 outputs 0. ０ｄ As V １ｄ If the output of the AND element 24 is 1, the switch SW4 outputs the zero-phase voltage q-axis component V ０ｑ As a result, １ｄ If the result is 0, the result of switch SW2 is output.

[0102] The AND element 25 outputs the negative d-axis component V ２ｄ is the positive phase d-axis component V １ｄ and the negative-phase q-axis component V ２ｑ is equal to 0, the switch SW5 outputs 1, otherwise it outputs 0. If the output of the AND element 25 is 1, the switch SW5 outputs the zero-phase voltage d-axis component V ０ｄ As -V １ｄ If the output of the AND element 25 is 1, the switch SW6 outputs the zero-phase voltage q-axis component V ０ｑ If it is 0, the result of the switch SW4 is output.

[0103] Table 1 shows the zero-phase voltage d-axis component V ０ｄ, the zero-phase voltage q-axis component V output by the switch SW6 ０ｑ Shows.

[0104]

[0105] In the equations (3), (4), and (5) used in the first and second embodiments, when the amplitudes of the positive-sequence voltage and the negative-sequence voltage are equal, the denominators become zero and there is no solution. However, if the numerators are also zero, there is a possibility that there will be a solution. Therefore, for simplification, when a grid-connected application is assumed and conditions are found in which both the numerator and denominator become zero in equation (5), one such condition is obtained: equation (7).

[0106]

[0107] Substituting equation (7) into equation (1), V １ｑ If the zero-phase sequence voltage that satisfies equation (2) is calculated again under the condition of =0, equation (8) is obtained.

[0108]

[0109] At this time, the zero-phase voltage q-axis component V ０ｑ can be any value, and there are an infinite number of solutions. Among these infinite solutions, the one that minimizes the amplitude of the zero-phase voltage is given by equation (9).

[0110]

[0111] In addition to equation (7), there are two other conditions under which both the numerator and denominator become zero. The combinations of conditions and solutions are shown in equations (10) and (11).

[0112]

[0113]

[0114] Examples of the conditions of the formulas (7), (10), and (11) are a line-to-line short circuit and a two-phase ground fault. In the third embodiment, the voltage conditions of the formulas (7), (10), and (11) are detected, and a zero-phase sequence voltage is superimposed to equalize the amplitude of the voltage command value of each phase. In grid interconnection, there are applications where operation continuity is required even in the event of a short circuit or ground fault as a fault-return (FRT) requirement, and the third embodiment can also be used for such applications.

[0115] According to the third embodiment, even when a line-to-line short circuit or a two-phase ground fault occurs in the AC system, the effects of the first and second embodiments can be obtained.

[0116] Although the present invention has been described in detail above only with respect to the specific examples, it will be apparent to those skilled in the art that various modifications and variations are possible within the scope of the technical concept of the present invention, and it is natural that such modifications and variations fall within the scope of the claims.

[0117] AC... Alternating current system 1... PLL (Phase-Locked Loop) 2, 4, 5, 7, 8... First to third low-pass filters 3... First dq converter 6... Second dq converter 9... Calculator 10... Oscillator 11, 12... First and second multipliers 13 to 16... First and second adders 17... Coefficient calculator 18 to 22... Comparators 23 to 25... AND elements SW1 to SW6... Switches

Claims

1. A multi-cell inverter comprising: a plurality of cells connected in a star connection to each phase of an AC system and having a full-bridge circuit on the AC system side; a correction voltage command value generation unit that generates a correction voltage command value by superimposing a zero-sequence voltage of the same frequency as a fundamental wave on a voltage command value; and a gate signal generation unit that generates a gate signal for the full-bridge circuit based on the correction voltage command value, wherein the correction voltage command value generation unit superimposes the zero-sequence voltage of the same frequency as the fundamental wave on the voltage command value so as to reduce the amplitude difference of the correction voltage command values ​​for each phase.

2. A multi-cell inverter comprising: a plurality of cells connected in a star connection to each phase of an AC system in multiplex; the cells having a full-bridge circuit on the AC system side; a correction voltage command value generation unit that generates a correction voltage command value by superimposing a zero-phase sequence voltage of the same frequency as the fundamental wave on a voltage command value; and a gate signal generation unit that generates a gate signal for the full-bridge circuit based on the correction voltage command value, wherein the correction voltage command value generation unit superimposes the zero-phase sequence voltage of the same frequency as the fundamental wave so that the difference between the amplitude of the correction voltage command value for each phase multiplied by the number of cells in each phase and divided by the number of cells in each phase that are operating without failure is small among the three phases.

3. The corrected voltage command value generating unit comprises: a phase output unit that outputs a phase ωt synchronized with the AC voltage of the system; a first dq converter that converts the phase voltage detection signal or the voltage command value, or the phase voltage detection signal or the voltage command value, multiplied by a coefficient obtained by dividing the number of cells in each phase by the number of cells in each phase that are operating without failure, into a value on a rotating coordinate system synchronized with the system frequency; and a second dq converter that converts the phase voltage detection signal or the voltage command value, or the phase voltage detection signal or the voltage command value, multiplied by a coefficient obtained by dividing the number of cells in each phase by the number of cells in each phase that are operating without failure, into a value on a rotating coordinate system that rotates in the opposite direction to the system frequency.

3. The multi-cell inverter according to claim 1, further comprising: a calculator that calculates a zero-phase voltage d-axis component and a zero-phase voltage q-axis component that make the AC side output voltage of each of the cells uniform, based on a positive-phase d-axis component and a positive-phase q-axis component obtained by extracting DC components from the output of the first dq converter and a negative-phase d-axis component and a negative-phase q-axis component obtained by extracting DC components from the output of the second dq converter; a first multiplier that multiplies the zero-phase voltage d-axis component by cosωt or sinωt; a second multiplier that multiplies the zero-phase voltage q-axis component by sinωt when the first multiplier multiplies by cosωt, and multiplies the zero-phase voltage q-axis component by cosωt when the first multiplier multiplies by sinωt; a first adder that adds an output of the first multiplier and an output of the second multiplier; and a second adder that adds the output of the first adder to the voltage command value and outputs the result as the corrected voltage command value.

4. The multi-cell inverter according to claim 3, wherein the computing unit calculates the d-axis component of the zero-phase-sequence voltage and the q-axis component of the zero-phase-sequence voltage based on equation (3). V ０ｄ :Zero-phase voltage d-axis component V ０ｑ :Zero-phase voltage q-axis component V １ｄ :Positive sequence voltage d-axis component V １ｑ : Positive sequence voltage q-axis component V ２ｄ :Negative sequence voltage d-axis component V ２ｑ : negative sequence voltage q-axis component 5. The multi-cell inverter according to claim 3, wherein the computing unit calculates the d-axis component of the zero-phase-sequence voltage and the q-axis component of the zero-phase-sequence voltage based on equation (4). V ０ｄ :Zero-phase voltage d-axis component V ０ｑ :Zero-phase voltage q-axis component V １ｄ :Positive sequence voltage d-axis component V １ｑ : Positive sequence voltage q-axis component V ２ｄ :Negative sequence voltage d-axis component V ２ｑ : negative sequence voltage q-axis component 6. The multi-cell inverter according to claim 3, wherein the computing unit calculates the d-axis component of the zero-phase-sequence voltage and the q-axis component of the zero-phase-sequence voltage based on equation (5). V ０ｄ :Zero-phase voltage d-axis component V ０ｑ :Zero-phase voltage q-axis component V ２ｄ :Negative sequence voltage d-axis component V ２ｑ :Q-axis component of negative sequence voltage V １ : Positive-sequence voltage component 7. The compensation voltage command value generating unit is configured to: ２ｄ = V １ｄ , and the negative phase q-axis component is V ２ｑ When V = 0, the zero-phase voltage d-axis component V ０ｄ = -V １ｄ / 2, the zero-phase voltage q-axis component V ０ｑ = 0, and the negative phase d-axis component V ２ｄ = -V １ｄ / 2, and the negative phase q-axis component is V ２ｑ = -√3V １ｄ In the case of / 2, the zero-phase voltage d-axis component V ０ｄ = V １ｄ / 4, the zero-phase voltage q-axis component V ０ｑ =√3V １ｄ / 4, and the negative phase d-axis component V ２ｄ = -V １ｄ / 2, and the negative phase q-axis component is V ２ｑ =√3V １ｄ In the case of / 2, the zero-phase voltage d-axis component V ０ｄ = V １ｄ / 4, the zero-phase voltage q-axis component V ０ｑ = -√3V １ｄ 7. The cell multiple inverter according to claim 6, wherein the ratio of said first and second cells is 4.

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