Cell multiplex inverter

Abstract

Provided is a cell multiplex inverter in which a plurality of cells are multiply connected in a star connection to each phase of an alternating-current system, wherein alternating-current output voltages of the cells are equalized even when an imbalance in alternating-current voltages occurs or unbalanced alternating voltages are intentionally output. When the amplitude of the voltage command value of a certain phase is greater than the amplitude of the voltage command value of another phase, a corrected voltage command value generation unit superimposes a sine wave of the opposite phase to the certain phase onto the voltage command value as a zero-phase voltage, and when the amplitude of the voltage command value of the certain phase is smaller than the amplitude of the voltage command value of the other phase, the corrected voltage command value generation unit superimposes a sine wave of the same phase as the certain phase onto the voltage command value as a zero-phase voltage.

Description

Cell-multiplexed inverter

[0001] The present invention relates to a multi-cell inverter in which a plurality of cells are connected in a star connection to each phase of an AC system.

[0002] One example of a multi-cell inverter is a modular multilevel cascade converter (MMCC) with single-star bridge cells (SSBC) connected to a three-phase AC grid. Also known is a configuration in which a separate power supply or DC / DC converter is connected to the DC side of the MMCC-SSBC full-bridge cell.

[0003] A major example of this configuration is the solid-state transformer (SST) described in Patent Document 1. Figure 1 shows an SST consisting of three cells per phase, which combines an MMCC-SSBC and a dual active bridge (DAB) type bidirectional isolated DC / DC converter.

[0004] High-voltage AC power is converted into DC power using series-connected cells, and the DC power is converted into high-frequency AC power, which is then insulated and rectified using a transformer to convert back into DC power. Reverse power interchange is also possible. Because SST uses a high-frequency transformer, it can be made smaller than conventional commercial frequency transformers.

[0005] Another application is the high-voltage multiple inverter disclosed in Patent Document 2.

[0006] When an SST is connected to an unbalanced three-phase AC system, or when a high-voltage multiple inverter intentionally outputs an unbalanced three-phase AC voltage, the phase voltage amplitude of a certain phase increases, and the AC voltage that the cell connected to that phase should output also increases.

[0007] To address this, it is necessary to increase the DC voltage of the cells, but this also requires that the withstand voltage of the components be increased, which leads to increased costs and size.Using switching devices with high withstand voltage for the cells also leads to increased losses.

[0008] Furthermore, some equipment may be required to continue operating even if some cells fail.

[0009] Patent Document 1 discloses the main circuit configuration of an SST, and Patent Document 2 discloses the configuration of a high-voltage multiple inverter.

[0010] Patent Documents 3 and 4 disclose methods for continuing operation when a cell fails. In both documents, the failed cell is first short-circuited. However, this alone reduces the AC voltage amplitude that can be output from the phase containing the failed cell. Therefore, Patent Document 3 inserts a spare cell prepared in advance into the corresponding phase. Patent Document 4 increases the DC voltage of the non-failed cells in the corresponding phase.

[0011] Patent Documents 5 and 6 disclose techniques for dealing with voltage imbalances in an MMCC-SSBC by using a zero-phase sequence voltage. The purpose of this technique is to balance the capacitor voltages of each cell.

[0012] Patent Document 7 describes a technology for lowering the peak voltage command value by superimposing a zero-phase sequence voltage on the voltage command value of a single three-phase inverter that does not use cell multiplexing. This technology can also be used when an unbalanced three-phase AC voltage is output, making the peak voltage command value of each phase equal. The technology described in Patent Document 7 can be applied to MMCC-SSBC and high-voltage multiplexed inverters.

[0013] JP 10-75580 JP 11-122943 JP 2012-147613 WO 2017 / 094379 A1 JP 2013-5694 JP 2021-19481 JP 3-107373

[0014] However, Patent Documents 1 and 2 do not particularly mention connection to an unbalanced system, output of an unbalanced voltage, or how to deal with a cell failure.

[0015] In Patent Document 3, it is necessary to incorporate a spare cell into the device, and a switch for turning on the spare cell is also required, which increases costs and size. If no failure occurs, the spare cell will not be used and may be wasted.

[0016] In Patent Document 4, the DC voltage of the other cells in the corresponding phase is increased, which requires the cell to be designed taking this into account, resulting in problems of increased cost, size, and loss. Furthermore, neither Patent Document 3 nor Patent Document 4 describes a method for dealing with voltage imbalance.

[0017] In Patent Documents 5 and 6, only a capacitor is connected to the DC side of each cell, and applications that do not handle active power, such as reactive power compensators, are envisioned. However, high-voltage multiplex inverters and SSTs have separate active power paths, which can be used to exchange power between cells and balance capacitor voltages. This reduces the importance of the technologies in Patent Documents 5 and 6. Furthermore, neither Patent Document 5 nor 6 describes a method for dealing with cell failures.

[0018] In Patent Document 7, harmonics of odd multiples of three are superimposed as the zero-phase voltage. However, the higher the frequency of the superimposed zero-phase voltage, the larger the common-mode current that flows through the stray capacitance of the circuit. This can cause many problems, such as increased heat generation in components, reduced efficiency, malfunction of ground fault detectors, insulation breakdown in high-frequency transformers, and electromagnetic interference to other equipment. Therefore, it is necessary to lower the frequency of the superimposed zero-phase voltage. Furthermore, Patent Document 7 does not disclose a method for dealing with cell failure.

[0019] As described above, in a cell-multiplexed inverter in which multiple cells are connected in a star connection to each phase of an AC system, the challenge is to equalize the AC output voltages of the cells even when an imbalance occurs in the AC voltage or when an unbalanced AC voltage is intentionally output.

[0020] The present invention has been devised in view of the above-described problems of the related art, and one aspect thereof is a multi-cell inverter including: a plurality of cells connected in multiplex with each phase of an AC system in a star connection, each cell having a full-bridge circuit on the AC system side; a correction voltage command value generation unit that generates a correction voltage command value by superimposing a zero-phase sequence voltage having the same frequency as a fundamental wave on a voltage command value; and a gate signal generation unit that generates a gate signal for the full-bridge circuit based on the correction voltage command value, wherein the correction voltage command value generation unit superimposes a sine wave of an opposite phase to the given phase as the zero-phase sequence voltage on the voltage command value if the amplitude of the voltage command value for a certain phase is larger than the amplitude of the voltage command value for another phase, and superimposes a sine wave of the same phase as the given phase as the zero-phase sequence voltage on the voltage command value if the amplitude of the voltage command value for a certain phase is smaller than the amplitude of the voltage command value for another phase.

[0021] In one aspect, the correction voltage command value generation unit includes a first adder that adds the zero-phase sequence voltage to the voltage command value and outputs the correction voltage command value, an amplitude detector that outputs the amplitude of the correction voltage command value for each phase, a first subtractor that calculates a deviation between a three-phase average value of the amplitude of the correction voltage command value and the amplitude of the correction voltage command value, an amplifier that amplifies the deviation between the three-phase average value and the amplitude, a third multiplier that multiplies an output of the amplifier by a sine wave having the same phase as the voltage command value, and a fourth adder that adds up outputs of the third multipliers for three phases and outputs the sum as the zero-phase sequence voltage.

[0022] In one aspect, the amplitude used in the first subtractor is a value obtained by multiplying the amplitude of the voltage command value by a coefficient based on the number of failed cells, and the three-phase average value is a three-phase average value of the amplitude after multiplication by the coefficient.

[0023] In one aspect, the amplitude of the voltage command value is set to an effective value of the voltage command value.

[0024] In another aspect, the amplitude of the voltage command value is a value obtained by extracting the amplitude of a fundamental wave component of the voltage command value.

[0025] In another aspect, the amplitude of the voltage command value is a peak value per one cycle of the voltage command value.

[0026] In one aspect, the sine wave having the same phase as the voltage command value has three phases, one of which has a phase obtained by a PLL, a rotary encoder, or a resolver, or a phase estimated by an observer, and the other phases have phases obtained by adding a fixed value to the phase of one of the three phases.

[0027] In another aspect, the correction voltage command value generation unit includes a phase output unit that outputs a phase ωt synchronized with the AC voltage of a grid, a fourth multiplier that multiplies the correction voltage command value by cosωt, a fifth multiplier that doubles the output of the fourth multiplier, a second low-pass filter that extracts a DC component from the output of the fifth multiplier and outputs an in-phase component synchronized with cosωt of the correction voltage command value, a sixth multiplier that multiplies the correction voltage command value by sinωt, a seventh multiplier that doubles the output of the sixth multiplier, a third low-pass filter that extracts a DC component from the output of the seventh multiplier and outputs a quadrature component synchronized with sinωt of the correction voltage command value, an eighth multiplier that multiplies the in-phase component by cosωt, a ninth multiplier that multiply the quadrature component by sinωt, and a fifth adder that adds the output of the eighth multiplier and the output of the ninth multiplier. and the output of the fifth adder is a sine wave having the same phase as the voltage command value.

[0028] In one aspect, the corrected voltage command value generating unit includes a phase output unit that outputs a phase ωt synchronized with the AC voltage of the system, a first dq converter that converts the phase voltage detection signal or the voltage command value into a value on a rotating coordinate system synchronized with the system frequency, a second dq converter that converts the phase voltage detection signal or the voltage command value into a value on a rotating coordinate system that rotates in a direction opposite to the system frequency, and a positive-phase d-axis component and a positive-phase q-axis component that are DC components extracted from the output of the first dq converter, and a negative-phase d-axis component and a negative-phase q-axis component that are DC components extracted from the output of the second dq converter. the voltage command value is provided with: a calculator that calculates a zero-phase-sequence voltage d-axis component and a zero-phase-sequence voltage q-axis component that equalize the AC side output voltages of the cells based on the calculated zero-phase-sequence voltage; a tenth multiplier that multiplies the zero-phase-sequence voltage d-axis component by cosωt; an eleventh multiplier that multiplies the zero-phase-sequence voltage q-axis component by sinωt; a seventh adder that adds an output of the tenth multiplier and an output of the eleventh multiplier; and an eighth adder that adds an output of the seventh adder to the voltage command value, wherein the first adder uses the voltage command value to which the output of the seventh adder has been added by the eighth adder.

[0029] In one aspect, the computing unit calculates the d-axis component of the zero-phase-sequence voltage and the q-axis component of the zero-phase-sequence voltage based on equation (1).

[0030]

[0031] V ０ｄ : Zero-phase voltage d-axis component V ０ｑ : Zero-phase voltage q-axis component V １ｄ : Positive sequence voltage d-axis component V １ｑ : Positive sequence voltage q-axis component V ２ｄ : Negative sequence voltage d-axis component V ２ｑ : negative sequence voltage q-axis component.

[0032] In another aspect, the computing unit calculates the d-axis component of the zero-phase-sequence voltage and the q-axis component of the zero-phase-sequence voltage based on equation (2).

[0033]

[0034] V ０ｄ : Zero-phase voltage d-axis component V ０ｑ : Zero-phase voltage q-axis component V １ｄ: Positive sequence voltage d-axis component V １ｑ : Positive sequence voltage q-axis component V ２ｄ : Negative sequence voltage d-axis component V ２ｑ : negative sequence voltage q-axis component.

[0035] In another aspect, the computing unit calculates the d-axis component of the zero-phase-sequence voltage and the q-axis component of the zero-phase-sequence voltage based on equation (3).

[0036]

[0037] V ０ｄ : Zero-phase voltage d-axis component V ０ｑ : Zero-phase voltage q-axis component V ２ｄ : Negative sequence voltage d-axis component V ２ｑ : negative sequence voltage q-axis component V １ : Voltage positive-sequence component.

[0038] In one aspect, the phase voltage detection signal or the voltage command value used in the first dq converter and the second dq converter is a value obtained by multiplying the phase voltage detection signal or the voltage command value by a coefficient obtained by dividing the number of cells in each phase by the number of cells in each phase that are operating without failure.

[0039] According to the present invention, in a cell-multiplexed inverter in which a plurality of cells are connected in a star connection to each phase of an AC system, it is possible to equalize the AC output voltages of the cells even when an imbalance occurs in the AC voltage or when an unbalanced AC voltage is intentionally output.

[0040] 1 is a circuit diagram showing a main circuit configuration of embodiments 1 to 4. FIG. 2 is a circuit diagram showing another example of a cell. FIG. 3 is a block diagram showing a correction voltage command value generator of embodiment 1. FIG. 4 is a block diagram showing a correction voltage command value generator of embodiment 2. FIG. 5 is a block diagram showing a correction voltage command value generator of embodiment 3. FIG. 6 is a block diagram showing a correction voltage command value generator of embodiment 4.

[0041] Hereinafter, first to fourth embodiments of the multi-cell inverter of the present invention will be described in detail with reference to FIGS.

[0042] First Embodiment First, the main circuit configuration of an MMCC-SSBC shown in FIG. 1 will be described as an example of a cell multiplexing inverter.

[0043] As shown in Figure 1(a), cells cellu1, cellu2, and cellu3 are connected in series to the U phase of the AC system AC via a reactor Lu. Similarly, cells cellv1, cellv2, and cellv3 are connected in series to the V phase of the AC system AC via a reactor Lv, and cells cellw1, cellw2, and cellw3 are connected in series to the W phase of the AC system AC via a reactor Lw. Here, the AC phase voltage (phase voltage detection signal) is V Ｕ , v Ｖ , v Ｗ Let's say.

[0044] The DC terminals of cells cellu1, cell cellu2, cell cellu3, cell cellv1, cell cellv2, cell cellv3, cell cellw1, cell cellw2, and cell cellw3 are connected in parallel. The DC voltages of cells cellu1 to cellw3 are V ＤＣ Let's say.

[0045] Figure 1(b) shows the configuration of one cell. One end of switching devices S1 and S3 is connected to one AC terminal of the cell. One end of switching devices S2 and S4 is connected to the other AC terminal of the cell. The other ends of switching devices S1 and S2 are connected to one end of first capacitor C1. The other ends of switching devices S3 and S4 are connected to the other end of first capacitor C1. The above switching devices S1, S2, S3, and S4 form a full bridge circuit provided on the AC side of the AC system.

[0046] Switching devices S5 and S6 are connected in series between one end and the other end of the first capacitor C1, and switching devices S7 and S8 are connected in series between one end and the other end of the first capacitor C1.

[0047] One end of a reactor L1 is connected to the connection point of switching devices S5 and S6. One end of a reactor L2 is connected to the connection point of switching devices S7 and S8. A primary winding of a transformer Tr is connected between the other end of the reactor L1 and the other end of the reactor L2.

[0048] A second capacitor C2 is connected between one DC terminal and the other DC terminal of the cell. Switching devices S9 and S11 are connected in series between one end and the other end of the second capacitor C2. Furthermore, switching devices S10 and S12 are connected in series between one end and the other end of the second capacitor C2.

[0049] One end of a reactor L3 is connected to the connection point of switching devices S9 and S11. One end of a reactor L4 is connected to the connection point of switching devices S10 and S12. A secondary winding of a transformer Tr is connected between the other end of reactor L3 and the other end of reactor L4. Note that reactors L1 to L4 in FIG. 1(b) may be omitted.

[0050] 1(b) adjusts the phase difference between the inverter output voltages on both sides of the transformer Tr to adjust the interchanged active power. Gate signals for switching devices S5 to S12 are generated so that the phase difference between the inverter output voltages on both sides of the transformer Tr becomes the desired phase difference (i.e., so that the interchanged active power becomes the desired). Since the gate signals for switching devices S5 to S12 of the inverters on both sides of the transformer Tr are not directly related to the present invention, detailed explanations are omitted here, and a conventionally known method is used.

[0051] The gate signal "gate" of the switching devices S1 to S4 of the full bridge circuit provided on the AC side of the alternating current system AC receives a gate signal generated in accordance with the first embodiment, which will be described later.

[0052] Another example of a circuit diagram for one cell is shown in Figure 2. In this example, an LLC resonant converter is used as the bidirectional isolated DC / DC converter.

[0053] 2, a third capacitor C3 is connected between the connection point of switching devices S5 and S6 and reactor L1. A fourth capacitor C4 is connected between the connection point of switching devices S7 and S8 and reactor L2. A fifth capacitor C5 is connected between the connection point of switching devices S9 and S11 and reactor L3. A sixth capacitor C6 is connected between the connection point of switching devices S10 and S12 and reactor L4.

[0054] The NOT circuit 37 inverts the 50% duty cycle signal. The dead time unit 38 inserts dead time into the 50% duty cycle signal and the inverted signal of the 50% duty cycle signal, and outputs the resulting signals as gate signals to the switching devices S5 to S12 of the inverters on both sides of the transformer Tr. The remaining circuit configuration is the same as in FIG. 1(b).

[0055] In FIG. 2, third to sixth capacitors C3 to C6 are connected in series to a transformer (high-frequency transformer) Tr. This causes resonance between the leakage inductance of the transformer Tr and reactors L1 to L4 connected in series. The inverters on both sides of the transformer Tr output AC voltages at this resonant frequency. The duty ratio of the gate signals driving the inverters on both sides of the transformer Tr is fixed at 50%. This allows active power corresponding to the difference in DC voltage between the two sides of the transformer Tr to be diverted through the transformer Tr. The gate signals of the switching devices S5 to S12 of the inverters on both sides of the transformer Tr are not directly related to the present invention, so a detailed description thereof will be omitted here.

[0056] The gate signal "gate" of the switching devices S1 to S4 of the full bridge circuit provided on the AC side of the alternating current system AC receives a gate signal generated in accordance with the first embodiment, which will be described later.

[0057] 3 shows a block diagram of the corrected voltage command value generating unit of the present embodiment 1. In the present embodiment 1, the voltage responsibilities of the cells are equalized in an application where it is not necessary to equalize the power responsibilities of the cells.

[0058] The first adders 1u, 1v, and 1w calculate the voltage command value v Ｕ *, vＶ *, v Ｗ * is superimposed with the zero-phase voltage obtained in the previous calculation cycle, and the corrected voltage command value v Ｕ *',v Ｖ *',v Ｗ *' is output. Voltage command value v Ｕ *, v Ｖ *, v Ｗ *It may be given as a sine wave of a fixed amplitude and frequency, or may be obtained by feedback control of voltage or current.

[0059] Corrected voltage command value v Ｕ *',v Ｖ *',v Ｗ *' generates a gate signal (on / off command signal) by comparing carrier triangular waves in the subsequent stage (gate signal generation section) and inputs it to the switching devices S1 to S4 of the full bridge circuit provided on the AC side of the AC system of each cell in Figures 1(b) and 2. The above gate signal generation method is disclosed in Patent Document 6.

[0060] The amplitude detectors 2u, 2v, and 2w detect the corrected voltage command value v Ｕ *',v Ｖ *',v Ｗ In the first embodiment, the amplitude detectors 2u, 2v, and 2w detect the amplitude of the corrected voltage command value v Ｕ *',v Ｖ *',v Ｗ As an example of calculating the effective value of *', the following is configured. In addition, as shown in the third embodiment described later, Ｕ *',v Ｖ *',v Ｗ The amplitude of the fundamental wave of *' may be calculated, or the corrected voltage command value v Ｕ *',v Ｖ *',v Ｗ The peak value per period of *' may be stored and output.

[0061] The first multipliers 3u, 3v, and 3w calculate the correction voltage command value v Ｕ *',v Ｖ *',v ＷThe first low-pass filters 4u, 4v, and 4w extract the DC component per cycle from the outputs of the first multipliers 3u, 3v, and 3w. The square root calculators 5u, 5v, and 5w calculate the square root of the outputs of the first low-pass filters 4u, 4v, and 4w. The outputs of the square root calculators 5u, 5v, and 5w are used as the correction voltage command value v Ｕ *',v Ｖ *',v Ｗ *' has an amplitude.

[0062] The square root calculators 5u, 5v, and 5w may be omitted because of their high calculation load. In this case, care must be taken to avoid excessive gain, since the target to be amplified by the amplifiers 9u, 9v, and 9w (described later) is the square of the effective value.

[0063] The second adder 6 calculates the correction voltage command value v Ｕ *',v Ｖ *',v Ｗ The second multiplier 7 calculates the sum of the amplitudes of the corrected voltage command value v Ｕ *',v Ｖ *',v Ｗ The sum of the amplitudes of *' (output of the second adder 6) is multiplied by 1 / 3 to obtain the three-phase average value. The first subtractors 8u, 8v, and 8w calculate the three-phase average value and the corrected voltage command value v Ｕ *',v Ｖ *',v Ｗ * Calculate the deviation between the amplitude of ' and .

[0064] The amplifiers 9u, 9v, and 9w amplify the outputs of the first subtractors 8u, 8v, and 8w (deviations between the three-phase average values ​​and the amplitudes). Here, proportional integrators are used as an example.

[0065] A phase output unit (for example, a PLL: Phase-Locked Loop) 10 outputs a phase voltage detection signal v Ｕ , v Ｖ , v Ｗ The phase ωt synchronized with the AC voltage of the system is output from the inverter.

[0066] Phase voltage detection signal V Ｕ , v Ｖ , v Ｗ The phase voltage detection signal v may be converted into a phase voltage by calculation after detecting the line voltage. Ｕ , v Ｖ , vＷ Instead of the voltage command value v Ｕ *, v Ｖ *, v Ｗ * may be input. The system AC voltage input to the phase output unit 10 may be only one representative phase. In motor drive applications, the phase ωt may be detected from a rotary encoder or resolver, or a phase estimated by an observer or the like may be used. Hereinafter, the phase output unit 10 will be referred to as PLL 10.

[0067] The oscillator 11u calculates the voltage command value v from the phase ωt. Ｕ The second subtractor 12v subtracts 2π / 3 from the phase ωt. The oscillator 11v calculates the voltage command value v from the phase ωt-2π / 3. Ｖ The third adder 12w adds 2π / 3 to the phase ωt. The oscillator 11w calculates the voltage command value v from the phase ωt+2π / 3. Ｗ *Outputs a sine wave with the same phase and amplitude as *.

[0068] The third multipliers 13u, 13v, and 13w multiply the outputs of the amplifiers 9u, 9v, and 9w of each phase by the voltage command value v Ｕ *, v Ｖ *, v Ｗ * is multiplied by a sine wave (output from oscillators 11u, 11v, 11w) synchronized with the signal.

[0069] The fourth adder 14 calculates the sum of the three third multipliers 13u, 13v, and 13w as the voltage command value v Ｕ *, v Ｖ *, v Ｗ The output of the fourth adder 14 is temporarily stored in the buffer 15, and is used as the voltage command value v Ｕ *, v Ｖ *, v Ｗ * is added to the corrected voltage command value v Ｕ *',v Ｖ *',v Ｗ *' is obtained.

[0070] In the first embodiment, the three-phase voltage command value v Ｕ *, v Ｖ *, v ＷThe purpose is to make the amplitude of the voltage command value of each phase equal by superimposing a zero-phase sequence voltage on *.

[0071] In the first embodiment, the correction voltage command value v Ｕ *',v Ｖ *',v Ｗ The amplitude of *' is detected and the deviation from the three-phase average value is calculated. Ｕ If the amplitude of *' is smaller than the three-phase average value, the corrected voltage command value v Ｕ *' is added as a zero-phase voltage, and the corrected voltage command value v Ｕ *'. The amplitude of the corrected voltage command value v Ｕ If the amplitude of *' is greater than the three-phase average value, the corrected voltage command value v Ｕ *' is added as a zero-phase voltage, and the corrected voltage command value v Ｕ *' amplitude is decreased.

[0072] This is performed for three phases, and the zero-phase sequence voltage to be superimposed is the sum of the three phases. In the next calculation cycle, the correction voltage command value v Ｕ *',v Ｖ *',v Ｗ *' amplitude is detected, and if there is an integral element in the amplifier, the deviation becomes zero and the correction voltage command value v Ｕ *',v Ｖ *',v Ｗ Repeat until the amplitudes of *' become equal. If there is no integral element, repeat until the deviation becomes small enough to correspond to the gain.

[0073] By the above operation, when there is an imbalance in the AC voltage or when an unbalanced AC voltage is intentionally output, the correction voltage command value v Ｕ *',v Ｖ *',v Ｗ The amplitudes of *' can be made equal.

[0074] In the first embodiment, one of the three phases of the sine wave having the same phase as the voltage command value is a phase obtained by a PLL, a rotary encoder, or a resolver, or a phase estimated by an observer, and the other phases are phases obtained by adding a fixed value to the phase of one of the three phases. That is, the corrected voltage command value v Ｕ *',v Ｖ*',v Ｗ It is assumed that *' are synchronized with cosωt, cos(ωt-2π / 3), and cos(ωt+2π / 3), respectively.

[0075] This holds true as long as the PLL 10 is operating normally. If the phase of the AC voltage changes suddenly due to a malfunction or a sudden load change, synchronization may be lost temporarily.

[0076] The larger the phase difference, the greater the correction voltage command value v Ｕ *',v Ｖ *',v Ｗ It takes time for the amplitudes of *' to become equal, and especially when the phase difference exceeds π / 2, the correction voltage command value v Ｕ *',v Ｖ *',v Ｗ This results in the superposition of a zero-phase voltage that increases the amplitude of *'.

[0077] However, for example, the FRT (Fault to Rest) requirement requires that operation be continued for a phase jump of 41° or less, and under this condition, even if the first embodiment is applied, instability will not occur.

[0078] As described above, according to the first embodiment, in a star-connected cell-multiplexed inverter such as an MMCC-SSBC, the AC output voltages of the cells can be made equal even when an imbalance occurs in the AC voltage or when an intentionally unbalanced AC voltage is output. This eliminates the need to insert a cell into a certain phase or to raise the cell DC voltage of only that phase, even when the voltage amplitude of that phase increases.

[0079] Furthermore, since the superimposed zero-phase voltage is only the fundamental wave component, the common mode current can be suppressed.

[0080] In the first embodiment, the DC voltage of all cells needs to be increased or raised in advance, but the increase in DC voltage can be significantly suppressed compared to the conventional technology, and the increase in the cell's withstand voltage can be minimized, thereby reducing costs and size.

[0081] Furthermore, since the zero-phase sequence voltage to be superimposed is determined by feedback, the first embodiment can equalize the AC output voltages of the cells even if there is a disturbance, such as an error in detecting the AC voltage.

[0082] 4 shows a block diagram of a correction voltage command value generating unit of the second embodiment. The second embodiment differs from the first embodiment in the following points.

[0083] The coefficient multipliers 16u, 16v, and 16w calculate the correction voltage command value v Ｕ *',v Ｖ *',v Ｗ *' (output of amplitude detectors 2u, 2v, 2w) by a coefficient N / n Ｕ , N / n Ｖ , N / n Ｗ The numerator N of the coefficient is the number of cells in each phase. The denominator n of the coefficient Ｕ , n Ｖ , n Ｗ is the number of cells in each phase that are operating without failure.

[0084] The amplitudes used in the first subtractors 8u, 8v, and 8w are values ​​obtained by multiplying the amplitudes by coefficients, and the three-phase average values ​​are the three-phase average values ​​of the amplitudes after multiplication by the coefficients.

[0085] In the second embodiment, a function for reducing the voltage duty of a phase in which a faulty cell exists is added to the first embodiment. Ｕ *',v Ｖ *',v Ｗ The amplitude of *' is multiplied by a coefficient, and the AC voltage of the phase containing the faulty cell is made to appear larger according to the number of faulty cells, and the average value and deviation are calculated.

[0086] By amplifying this deviation and superimposing the resulting zero-phase sequence voltage, the amplitude of the voltage command value for the phase in which the faulty cell is located can be reduced.

[0087] Note that the gate signals generated based on Figure 4 are for healthy cells that are not faulty. For a faulty cell, the AC system turns on switching devices S1 and S3, or turns on switching devices S2 and S4 to output zero voltage, or performs short-circuit treatment using an external switch. Switching devices S5 to S12 are turned off.

[0088] As described above, in addition to the effects of embodiment 1, embodiment 2 can equalize the AC output voltages of the cells even when some of the cells fail and short-circuit treatment is performed. Operation can be continued even when more cells than in the prior art fail.

[0089] 5 shows a block diagram of a correction voltage command value generating unit of the present embodiment 3. The present embodiment 3 differs from the second embodiment in the following points.

[0090] The oscillator 17 receives the phase ωt output from the PLL 10 and outputs a sine wave sinωt. The oscillator 18 receives the phase ωt output from the PLL 10 and outputs a cosine wave cosωt.

[0091] In the first embodiment, the voltage command value v Ｕ * is synchronized with cosωt, and the voltage command value v Ｖ * is synchronized with cos(ωt-2π / 3), v Ｗ * is assumed to be synchronized with cos(ωt+2π / 3), but in the third embodiment, a sine wave synchronized (in phase) with the voltage command value of each phase is prepared by the following blocks.

[0092] The fourth multiplier 19u calculates the correction voltage command value v Ｕ The fifth multiplier 20u multiplies the output of the fourth multiplier 19u by two. The second low-pass filter 4u multiplies the output of 2v Ｕ *'cosωt. The output of the second low-pass filter 4u is the corrected voltage command value v Ｕ *', the component synchronized with the cosine wave cosωt (v Ｕ *In-phase components)

[0093] The sixth multiplier 21u calculates the correction voltage command value v Ｕ The seventh multiplier 22u doubles the output of the sixth multiplier 21u. The third low-pass filter 4u multiplies the output of 2v Ｕ The output of the third low-pass filter 4u is the corrected voltage command value v Ｕ *', the component synchronized with the sine wave sinωt (v Ｕ *orthogonal components).

[0094] The eighth multiplier 23u is Ｕ * The ninth multiplier 24u calculates the product of the in-phase component and the cosine wave cosωt. Ｕ *The product of the quadrature component and the sine wave sinωt is calculated. The fifth adder 25u adds the outputs of the eighth and ninth multipliers 23u and 24u. The output of the fifth adder 25u is calculated as the voltage command value v Ｕ The third multiplier 13u multiplies this sine wave by the output of the U-phase amplifier 9u instead of cosωt. The same applies to the V-phase and W-phase.

[0095] Accordingly, the corrected voltage command value v Ｕ *',v Ｖ *',v Ｗ The amplitude detectors 2u, 2v, and 2w of *' are modified to the following configuration, which uses the values ​​of the above blocks to determine the amplitude of the fundamental wave. As in the second embodiment, the effective value may be used, or the peak value per period may be stored and output.

[0096] The tenth multiplier 26u is Ｕ * In-phase component and v Ｕ *The square of each quadrature component is calculated. The sixth adder 27u adds the outputs of the two tenth multipliers 26. The square root calculator 28u calculates the square root of the output of the sixth adder 27u. The square root calculator 28u may be omitted because of its high calculation load. The points to note in this case are the same as those in the first embodiment. The same applies to the V phase and the W phase.

[0097] In the third embodiment, the correction voltage command value v Ｕ *',v Ｖ *',v Ｗ This differs from the first embodiment in that a sine wave synchronized with *' is accurately obtained. As a result, when a phase jump occurs frequently in the grid, and when operation is required to continue with a phase jump exceeding the FRT requirement, the corrected voltage command value v Ｕ *',v Ｖ *',v Ｗ This has the effect of shortening the time until the amplitudes of *' become equal and preventing the feedback control from becoming unstable.

[0098] Furthermore, in synchronous motor drive applications, a rotary encoder or the like is used to detect the phase ωt, but the phase of the rotary encoder and the voltage phase do not necessarily coincide. In the first and second embodiments, correction is required if the difference is large, but in the third embodiment, correction is not required even if the difference is large.

[0099] According to the third embodiment, when the system is unstable and phase jumps occur frequently, and when operation must be continued even in the presence of large phase jumps, the convergence time can be shortened and instability can be prevented more than in the first and second embodiments. The third embodiment can also be easily applied to motor drive applications. However, the calculation load is smaller in the first and second embodiments.

[0100] 6 shows a block diagram of a correction voltage command value generating unit of the fourth embodiment. The fourth embodiment is a combination of the third embodiment with feedforward control.

[0101] The input for feedforward control is the voltage command value v Ｕ *, v Ｖ *, v Ｗ *, but it is necessary to use the value before adding the zero-phase voltage. Phase voltage detection signal v Ｕ , v Ｖ , v Ｗ The input of the feedback control must be the sum of the zero-phase sequence voltage due to the feedforward control in addition to the zero-phase sequence voltage due to the feedback control in the previous calculation period.

[0102] In the second coefficient multipliers 29u, 29v, and 29w, the voltage command value v Ｕ *, v Ｖ *, v Ｗ * (or phase voltage detection signal v Ｕ , v Ｖ , v Ｗ ) with coefficient N / n Ｕ , N / n Ｖ , N / n Ｗ The numerator of the coefficient, N, is the number of cells in each phase. In the example of Figure 1, N = 3. The denominator of the coefficient, n Ｕ , n Ｖ , n Ｗis the number of cells in each phase that are operating without failure. The voltage command value v Ｕ *, v Ｖ *, v Ｗ * (or phase voltage detection signal v Ｕ , v Ｖ , v Ｗ ) uses the value multiplied by this coefficient.

[0103] The first dq converter 30 converts the coefficient N / n Ｕ , N / n Ｖ , N / n Ｗ The voltage command value v Ｕ *, v Ｖ *, v Ｗ * is converted into a value on a rotating coordinate system synchronized with the system frequency based on the phase ωt.

[0104] When only the DC component is extracted from the output of the first dq converter 30, the d-axis component is the voltage command value v Ｕ *, v Ｖ *, v Ｗ * Positive phase d-axis component V １ｄ , the q-axis component is the positive-phase q-axis component V １ｑ If the PLL 10 is operating normally, the positive phase q-axis component V １ｑ is zero and is therefore not used.

[0105] The second dq converter 31 is a multiplier with a coefficient N / n Ｕ , N / n Ｖ , N / n Ｗ The voltage command value v Ｕ *, v Ｖ *, v Ｗ * is converted into a value on a rotating coordinate system that rotates in the opposite direction to the system frequency based on the phase -ωt.

[0106] When only the DC component is extracted from the output of the second dq converter 31, the voltage command value v Ｕ *, v Ｖ *, v Ｗ * The negative-phase d-axis component V ２ｄ , reverse phase q-axis component V ２ｑ This becomes:

[0107] The calculator 32 calculates the positive phase d-axis component V １ｄ , positive phase q-axis component V １ｑ, reverse-phase d-axis component V ２ｄ , reverse phase q-axis component V ２ｑ Using equation (1) described later, the zero-phase voltage d-axis component V ０ｄ , zero-phase voltage q-axis component V ０ｑ The zero-phase voltage d-axis component V can be calculated by using equations (2) and (3) instead of equation (1). ０ｄ and the zero-phase voltage q-axis component V ０ｑ In this calculator 32, when the amplitudes of the positive and negative phase components of the AC voltage are approximately equal, V ０ｄ =V ０ｑ =0 is output.

[0108] The eleventh multiplier 33 multiplies the zero-phase voltage d-axis component V ０ｄ and the cosine wave cosωt. The twelfth multiplier 34 calculates the product of the zero-phase voltage q-axis component V ０ｑ and the sine wave sinωt.

[0109] The seventh adder 35 multiplies the V output from the eleventh multiplier 33 by ０ｄ cosωt and V output by the 12th multiplier 34 ０ｑ Find the sum of sinωt.

[0110] The eighth adders 36u, 36v, and 36w calculate the voltage command value v Ｕ *, v Ｖ *, v Ｗ * Each of these is V calculated by the seventh adder 35 ０ｄ cosωt+V ０ｑ In the fourth embodiment, the outputs of the eighth adders 36u, 36v, and 36w are output to the first adders 1u, 1v, and 1w. The first adders 1u, 1v, and 1w superimpose the zero-phase sequence voltage obtained in the previous calculation cycle on the outputs of the eighth adders 36u, 36v, and 36w to obtain the corrected voltage command value v Ｕ *',v Ｖ *',v Ｗ *' is output.

[0111] Equations (1) to (3) are shown below.

[0112]

[0113] Positive phase q-axis component V １ｑ If is close to zero, equation (1) can be approximated by equation (2).

[0114]

[0115] Positive phase q-axis component V １ｑ If is equal to zero, then equation (1) can be simplified to equation (3). In equation (3), V １ indicates the positive sequence component of the AC voltage.

[0116]

[0117] In contrast to the third embodiment, the fourth embodiment uses a feedforward correction voltage command value v Ｕ *',v Ｖ *',v Ｗ *' are made equal, and deviations due to detection errors etc. are corrected by feedback. Therefore, even if the feedback gain is small, the corrected voltage command value v Ｕ *',v Ｖ *',v Ｗ This shortens the time it takes for the amplitudes of *' to become equal, improving stability. In addition to the effect of feedback, which can reduce deviation (it can be reduced to zero by using an integrating amplifier), the effect of feedforward can also be obtained.

[0118] As described above, according to the fourth embodiment, the zero-phase sequence voltage to be superimposed is determined by using both feedforward and feedback. Even if the feedback gain is reduced, the response to voltage fluctuations is fast, and the AC output voltages of the cells can be made uniform even in the presence of disturbances while improving stability.

[0119] Although the present invention has been described in detail above only with respect to the specific examples, it will be apparent to those skilled in the art that various modifications and variations are possible within the scope of the technical concept of the present invention, and it is natural that such modifications and variations fall within the scope of the claims.

[0120] AC...AC system 1u, 1v, 1w...first adder 2u, 2v, 2w...amplitude detector 3u, 3v, 3w...first multiplier 4u, 4v, 4w...first low-pass filter 5u, 5v, 5w...square root calculator 6...second adder 7...second multiplier 8u, 8v, 8w...first subtractor 9u, 9v, 9w...amplifier 10...phase output unit (PLL) 11u, 11v, 11w...oscillator 12v...second subtractor 12w...third adder 13u, 13v, 13w...second multiplier 14...fourth adder 15...buffer

Claims

1. A multi-cell inverter comprising: a plurality of cells connected in a star connection to each phase of an AC system in multiplexed fashion, the cells having a full-bridge circuit on the AC system side; a correction voltage command value generation unit that generates a correction voltage command value by superimposing a zero-sequence voltage of the same frequency as a fundamental wave on a voltage command value; and a gate signal generation unit that generates a gate signal for the full-bridge circuit based on the correction voltage command value, wherein the correction voltage command value generation unit superimposes a sine wave of an opposite phase to the certain phase as the zero-sequence voltage on the voltage command value if the amplitude of the voltage command value for a certain phase is larger than the amplitude of the voltage command value for another phase, and superimposes a sine wave of the same phase as the certain phase as the zero-sequence voltage on the voltage command value if the amplitude of the voltage command value for a certain phase is smaller than the amplitude of the voltage command value for the other phase.

2. The cell-multiplexing inverter according to claim 1, characterized in that the correction voltage command value generation unit comprises: a first adder that adds the zero-phase voltage to the voltage command value and outputs the correction voltage command value; an amplitude detector that outputs the amplitude of the correction voltage command value for each phase; a first subtractor that calculates a deviation between a three-phase average value of the amplitude of the correction voltage command value and the amplitude of the correction voltage command value; an amplifier that amplifies the deviation between the three-phase average value and the amplitude; a third multiplier that multiplies the output of the amplifier by a sine wave of the same phase as the voltage command value; and a fourth adder that adds together outputs of the third multiplier for three phases and outputs the result as the zero-phase voltage.

3. The cell-multiplexing inverter according to claim 2, characterized in that the amplitude used in the first subtractor is a value obtained by multiplying the amplitude of the voltage command value by a coefficient based on the number of failed cells, and the three-phase average value is a three-phase average value of the amplitude after multiplication by the coefficient.

4. The multi-cell inverter according to claim 1, wherein the amplitude of the voltage command value is an effective value of the voltage command value.

5. The multi-cell inverter according to claim 1, wherein the amplitude of the voltage command value is a value obtained by extracting the amplitude of a fundamental wave component of the voltage command value.

6. The multi-cell inverter according to claim 1, wherein the amplitude of the voltage command value is a peak value per one period of the voltage command value.

7. A cell-multiplexing inverter as described in claim 2, characterized in that one of the three phases of the sine wave having the same phase as the voltage command value is a phase obtained by a PLL, a rotary encoder or a resolver, or a phase estimated by an observer, and the other phase is a phase obtained by adding a fixed value to the phase of one of the three phases.

8. The correction voltage command value generation unit includes: a phase output unit that outputs a phase ωt synchronized with the AC voltage of a system; a fourth multiplier that multiplies the correction voltage command value by cosωt; a fifth multiplier that doubles the output of the fourth multiplier; a second low-pass filter that extracts a DC component from the output of the fifth multiplier and outputs an in-phase component synchronized with cosωt of the correction voltage command value; a sixth multiplier that multiplies the correction voltage command value by sinωt; a seventh multiplier that doubles the output of the sixth multiplier; a third low-pass filter that extracts a DC component from the output of the seventh multiplier and outputs a quadrature component synchronized with sinωt of the correction voltage command value; an eighth multiplier that multiplies the in-phase component by cosωt; a ninth multiplier that multiplies the quadrature component by sinωt; and a fifth adder that adds the output of the eighth multiplier and the output of the ninth multiplier.

3. The multi-cell inverter according to claim 2, further comprising: a fifth adder for outputting an output of the fifth adder that is a sine wave having the same phase as the voltage command value.

9. The correction voltage command value generating unit includes: a phase output unit that outputs a phase ωt synchronized with the AC voltage of the system; a first dq converter that converts a phase voltage detection signal or the voltage command value into a value on a rotating coordinate synchronized with a system frequency; a second dq converter that converts the phase voltage detection signal or the voltage command value into a value on a rotating coordinate rotating in a direction opposite to the system frequency; a calculator that calculates a zero-phase voltage d-axis component and a zero-phase voltage q-axis component that make the AC side output voltage of each of the cells uniform, based on a positive-phase d-axis component and a positive-phase q-axis component obtained by extracting DC components from an output of the first dq converter, and a negative-phase d-axis component and a negative-phase q-axis component obtained by extracting DC components from an output of the second dq converter; a tenth multiplier that multiplies the zero-phase voltage d-axis component by cosωt; an eleventh multiplier that multiplies the zero-phase voltage q-axis component by sinωt; and a seventh adder that adds an output of the tenth multiplier and an output of the eleventh multiplier.

3. The multi-cell inverter according to claim 2, further comprising: an eighth adder that adds the output of the seventh adder to the voltage command value; and wherein the first adder uses the voltage command value to which the output of the seventh adder has been added by the eighth adder.

10. The multi-cell inverter according to claim 9, wherein the calculator calculates the d-axis component of the zero-phase-sequence voltage and the q-axis component of the zero-phase-sequence voltage based on equation (1). V ０ｄ :Zero-phase voltage d-axis component V ０ｑ :Zero-phase voltage q-axis component V １ｄ :Positive sequence voltage d-axis component V １ｑ : Positive sequence voltage q-axis component V ２ｄ :Negative sequence voltage d-axis component V ２ｑ : negative sequence voltage q-axis component 11. The multi-cell inverter according to claim 9, wherein the calculator calculates the d-axis component of the zero-phase-sequence voltage and the q-axis component of the zero-phase-sequence voltage based on equation (2). V ０ｄ :Zero-phase voltage d-axis component V ０ｑ :Zero-phase voltage q-axis component V １ｄ :Positive sequence voltage d-axis component V １ｑ : Positive sequence voltage q-axis component V ２ｄ :Negative sequence voltage d-axis component V ２ｑ : negative sequence voltage q-axis component 12. The multi-cell inverter according to claim 9, wherein the calculator calculates the d-axis component of the zero-phase-sequence voltage and the q-axis component of the zero-phase-sequence voltage based on equation (3). V ０ｄ :Zero-phase voltage d-axis component V ０ｑ :Zero-phase voltage q-axis component V ２ｄ :Negative sequence voltage d-axis component V ２ｑ :Q-axis component of negative sequence voltage V １ : Positive-sequence voltage component 13. The cell-multiplexing inverter according to claim 9, characterized in that the phase voltage detection signal or the voltage command value used in the first dq converter and the second dq converter is a value obtained by multiplying the phase voltage detection signal or the voltage command value by a coefficient obtained by dividing the number of cells in each phase by the number of cells in each phase that are operating without failure.

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