Method for manufacturing semiconductor device, and mesa diode

Abstract

Provided is a method for manufacturing a semiconductor device which is manufactured using lead-free glass but without using a photolithography step and a large amount of chemicals. The present invention is a semiconductor device manufacturing method in which: insulating films 12a, 12b are formed on an upper surface 11a and a lower surface 11b of a silicon wafer 11 including a PN junction 10; the upper surface of the silicon wafer 11 is cut using a dicing blade to form a groove 13 having a depth that exceeds the PN junction 10; an inner surface of the groove 13 is wet-etched to set the surface roughness Ra of the inner surface of the groove 13 to 0.1 μm or less; a silicon oxide film 16 is formed on the inner surface of the groove 13; a lead-free glass layer 14 is formed on the silicon oxide film 16 on the inner surface of the groove 13; the insulating films 12a, 12b are removed; metal films 15a, 15b are formed on the upper surface 11a and the lower surface 11b of the silicon wafer 11; and the lead-free glass layer 14 and the silicon wafer 11 are cut along the center of a bottom surface 13a of the groove 13.

Description

Semiconductor device manufacturing method and mesa diode

[0001] The present invention relates to a method for manufacturing a semiconductor device and a mesa diode.

[0002] A conventional method for manufacturing a mesa diode with glass passivation includes a process for forming a groove in a silicon wafer. In this process, an insulating film is formed on the top surface of a silicon wafer having a PN junction, a photoresist film is formed on the insulating film, the photoresist film is exposed and developed to form a resist pattern, the insulating film is etched using the resist pattern as a mask, and then a groove is formed by wet etching to a depth exceeding the PN junction. This process for forming a groove in a silicon wafer involves steps that use large amounts of chemicals during the photolithography and wet etching, which tends to increase costs. A related technology is disclosed in Patent Document 1. It is also necessary to comply with the lead restrictions in glass under the European RoHS regulation. Therefore, there is a need for a mesa diode that can be manufactured using lead-free glass without the photolithography process or large amounts of chemicals. Prior Art Documents

[0003] WO2014 / 155739 publication

[0004] Various aspects of the present invention aim to provide a method for manufacturing a mesa diode and a semiconductor device that are manufactured using lead-free glass without using a photolithography process or a large amount of chemicals.

[0005] Various aspects of the present invention will be described below: [1] A method for manufacturing a semiconductor device, comprising: (a) a step of forming an insulating film on an upper surface and a lower surface of a silicon wafer having a PN junction; (b) a step of cutting the upper surface of the silicon wafer with a dicing blade to form a groove having a depth exceeding the PN junction; (c) a step of wet-etching the inner surface of the groove to reduce the surface roughness of the inner surface of the groove to 0.1 μm or less; (d) a step of forming a silicon oxide film on the inner surface of the groove; (e) a step of forming a lead-free glass layer on the silicon oxide film on the inner surface of the groove; (f) a step of removing the insulating film; (g) a step of forming a metal film on the upper surface and the lower surface of the silicon wafer; and (h) a step of cutting the lead-free glass layer and the silicon wafer along the center of the bottom surface of the groove. In the semiconductor device manufacturing method according to one aspect of the present invention, when the top surface of a silicon wafer having a PN junction is cut with a dicing blade to form a groove deeper than the PN junction, the inner surface of the groove becomes rough and uneven. Therefore, in step (c), the inner surface of the groove is wet-etched to reduce the surface roughness of the inner surface of the groove to 0.1 μm or less. A silicon oxide film is then formed on the inner surface of the groove, and a lead-free glass layer is formed on the silicon oxide film on the inner surface of the groove as passivation. By using a lead-free glass layer and cutting with a dicing blade, it is possible to manufacture a semiconductor device without using a photolithography process or large amounts of chemicals. Furthermore, because the lead-free glass layer reduces the surface roughness of the inner surface of the groove to 0.1 μm or less, the semiconductor device can achieve high breakdown voltage characteristics. [2] In the semiconductor device manufacturing method according to the above item [1], the silicon oxide film formed in step (d) is an oxide film having a thickness of 100 nm or less. According to the method for manufacturing a semiconductor device described above in [2] according to one aspect of the present invention, the silicon oxide film is an oxide film having a thickness of 100 nm or less, which makes it possible to form lead-free glass by electrophoretic deposition.[3] In the method for manufacturing a semiconductor device according to [1] or [2] above, the angle formed between the bottom and side surfaces of the groove in the cross section formed in step (b) is 60° to 90° (preferably 76° to 90°). According to the method for manufacturing a semiconductor device according to [3] above, the angle formed between the bottom and side surfaces of the groove in the cross section formed in step (b) is 60° to 90° (preferably 76° to 90°). An angle of 90° or close to 90° eliminates the need for beveling the dicing blade, or only requires a small amount of beveling. Compared to a beveled dicing blade, a non-beveled dicing blade is less susceptible to deformation in cross section, allowing the dicing blade to be used for a longer period of time and reducing manufacturing costs. [4] In the method for manufacturing a semiconductor device according to [1] or [2] above, the wet etching solution in step (c) is a mixture of hydrofluoric acid, nitric acid, sulfuric acid, phosphoric acid, and water. According to the semiconductor device manufacturing method of [4] above, the inner surface of the trench is wet-etched using a mixed solution of hydrofluoric acid, nitric acid, sulfuric acid, phosphoric acid, and water as a wet etching solution, thereby easily reducing the surface roughness of the inner surface of the trench to 0.1 μm or less. [5] The semiconductor device manufacturing method of [1] or [2] above, wherein the insulating film in step (a) is a silicon oxide film formed by thermal oxidation. According to the semiconductor device manufacturing method of [5] above, according to one aspect of the present invention, using a silicon oxide film formed by thermal oxidation as the insulating film in step (a) makes it possible to easily form insulating films on the upper and lower surfaces of the silicon wafer. [6] The semiconductor device manufacturing method of [2] above, wherein the lead-free glass layer in step (e) is formed on the silicon oxide film on the inner surface of the trench by electrophoretic deposition. According to the semiconductor device manufacturing method of [6] above, according to one aspect of the present invention, by forming the silicon oxide film on the inner surface of the trench to a thickness of 100 nm or less, it is possible to easily form a lead-free glass layer on the silicon oxide film by electrophoretic deposition.[7] The method for manufacturing a semiconductor device according to the above [1], wherein the lead-free glass layer in the step (e) is formed on the silicon oxide film on the inner surface of the groove by a printing method. [8] A mesa diode comprising: a semiconductor layer of a first conductivity type; a semiconductor layer of a second conductivity type in contact with the semiconductor layer of the first conductivity type; a silicon oxide film formed on a side surface of the semiconductor layer of the second conductivity type, an edge of the interface between the semiconductor layer of the second conductivity type and the semiconductor layer of the first conductivity type, and a lead-free glass layer disposed on the silicon oxide film, wherein the side surface of the semiconductor layer of the second conductivity type, the edge of the interface between the semiconductor layer of the second conductivity type and the semiconductor layer of the first conductivity type, and a part of the side surface of the semiconductor layer of the first conductivity type each have a surface roughness of 0.1 μm or less. According to the mesa diode of [8] above according to one aspect of the present invention, the surface roughness of the side surface of the second conductivity type semiconductor layer, the edge of the interface between the second conductivity type semiconductor layer and the first conductivity type semiconductor layer, and a portion of the side surface of the first conductivity type semiconductor layer is 0.1 μm or less. A silicon oxide film is formed on the side surface of the second conductivity type semiconductor layer, the edge of the interface between the second conductivity type semiconductor layer and the first conductivity type semiconductor layer, and a portion of the side surface of the first conductivity type semiconductor layer, each of which has a surface roughness of 0.1 μm or less, and a lead-free glass layer is disposed on the silicon oxide film. In other words, because the lead-free glass layer is formed on a surface with a surface roughness of 0.1 μm or less, the mesa diode can achieve high breakdown voltage characteristics. [9] A mesa diode comprising: a semiconductor layer of a first conductivity type; a semiconductor layer of a second conductivity type in contact with the semiconductor layer of the first conductivity type; a silicon oxide film formed on a side surface of the semiconductor layer of the first conductivity type, an edge of the interface between the semiconductor layer of the first conductivity type and the semiconductor layer of the second conductivity type, and a part of the side surface of the semiconductor layer of the second conductivity type; and a lead-free glass layer disposed on the silicon oxide film, wherein the surface roughness of the side surface of the semiconductor layer of the first conductivity type, the edge of the interface between the semiconductor layer of the first conductivity type and the semiconductor layer of the second conductivity type, and a part of the side surface of the semiconductor layer of the second conductivity type are each 0.1 μm or less.

[10] The mesa diode according to the above [8] or [9], wherein the silicon oxide film has a thickness of 100 nm or less. According to various aspects of the present invention, it is possible to provide a method for manufacturing a mesa diode and a semiconductor device that are manufactured using lead-free glass and without using a photolithography process or a large amount of chemicals.

[0006] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 2A to 2C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 3A is an optical microscope photograph of the inner surface of groove 13, 3B is a photograph showing a cross section of groove 13, 3C is a graph showing the characteristics of the lead-free glass layer, and 3D is a graph showing the device characteristics of sample B of the example shown in Table 1. 3D is a graph showing the device characteristics of sample A of the comparative example shown in Table 1.

[0007] The following describes in detail embodiments of the present invention with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art will readily understand that various modifications in form and detail are possible without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the following description of the embodiments. (First Embodiment) FIGS. 1A-1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention. The method for manufacturing a semiconductor device according to [1] above according to one aspect of the present invention includes, as shown in FIG. 1A, step (a) of forming insulating films 12a and 12b on the upper surface 11a and lower surface 11b of a silicon wafer 11 having a PN junction 10. The insulating films 12a and 12b are preferably silicon oxide films formed by thermal oxidation. Using silicon oxide films formed by thermal oxidation as the insulating films 12a and 12b makes it possible to easily form the insulating films 12a and 12b on the upper surface 11a and lower surface 11b of the silicon wafer 11. Furthermore, prior to step (A), N − It is advisable to simultaneously diffuse, for example, boron and phosphorus onto the entire surface of the silicon wafer from both sides. −Phosphorus is diffused from the entire upper surface of the silicon wafer 11, and simultaneously, N − Boron is diffused from the entire lower surface of the silicon wafer 11. − The mold silicon wafer 11 is provided with P ＋ N-type semiconductor layer (also referred to as a first conductivity type semiconductor layer) 22, − type semiconductor layer 32 and N ＋ The N-type semiconductor layer 33 is formed. − type semiconductor layer 32 and N ＋ The N-type semiconductor layer 33 is also referred to as the second conductivity type semiconductor layer 23. ＋ The N-type semiconductor layer 33 − The impurity concentration is higher than that of the N-type semiconductor layer 32. ＋ The N-type semiconductor layer 33 − The N-type semiconductor layer 32 is in contact with the N-type semiconductor layer 32. − The P-type semiconductor layer 32 ＋ The P ＋ type semiconductor layer 22 and N − A PN junction 10 is formed at the surface where the N-type semiconductor layer 32 is bonded. ＋ A P type semiconductor layer 33 is formed on the upper surface. ＋ The P type semiconductor layer 22 is formed on the lower surface side. ＋ An N-type semiconductor layer is formed on the upper surface. ＋ A type semiconductor layer 33 may be formed on the lower surface side. After that, the upper surface of the silicon wafer 11 is cut with a dicing blade to form grooves 13 having a depth exceeding that of the PN junctions 10 (step (b)). ＋ From the top surface of the silicon wafer 11 on the side of the N-type semiconductor layer 33 − P beyond the semiconductor layer 32 ＋A groove 13 is formed by cutting a dicing blade (not shown) to a depth reaching partway through the semiconductor layer 22. The angle 21 formed by the bottom surface 13a and the side surface 13b of the groove 13 in the cross section of the mesa structure groove 13 is preferably 60° to 90°, and more preferably 76° to 90°. An angle 21 of 90° or close to 90° eliminates the need for beveling the dicing blade, or requires only a small amount of beveling. Compared to a beveled dicing blade, a non-beveled dicing blade is less susceptible to deformation in cross section, allowing for longer use and lower manufacturing costs. Next, the inner surface of the groove 13 formed by the dicing process is wet-etched to reduce the surface roughness Ra of the inner surface of the groove 13 to 0.1 μm or less (step (c)). A mixture of hydrofluoric acid, nitric acid, sulfuric acid, phosphoric acid, and water is preferably used as the wet etching solution. By wet-etching the inner surface of the groove 13 using such a mixed wet etching solution, it is possible to easily flatten the surface roughness Ra of the inner surface of the groove 13 to 0.1 μm or less. Thereafter, as shown in FIG. 1B , a silicon oxide film 16 is formed on the inner surface of the groove 13 (step (d)). This silicon oxide film 16 may be, for example, a thermal oxide film. The thickness of this silicon oxide film 16 may be 100 nm or less, with a lower limit of 5 nm being preferred. This allows the lead-free glass layer 14, described below, to be formed by electrophoretic deposition. Furthermore, when the lead-free glass layer 14 is formed by a printing method, there is no limit to the thickness of the silicon oxide film 16, and a silicon oxide film 16 thicker than 100 nm may be used. Next, a lead-free glass layer 14 is formed on the silicon oxide film 16 on the inner surface of the groove 13 (step (e)). Specifically, the following two methods can be used to form this lead-free glass layer 14. First, a lead-free glass layer 14 is formed on the silicon oxide film 16 on the inner surface of the groove 13 by electrophoretic deposition.Specifically, a layer made of a glass composition for protecting semiconductor junctions is formed on the inner surface of the groove 13 and on the surface of the silicon wafer 11 in the vicinity thereof by electrophoretic deposition, and the layer made of the glass composition for protecting semiconductor junctions is then fired to form a lead-free glass layer 14 for passivation with high chemical resistance (see FIG. 1(B)). Therefore, the exposed PN junction portion inside the groove 13 is directly covered with the lead-free glass layer 14. The glass composition for protecting semiconductor junctions contains at least SiO. ２ And B ２ O ３ And, Al ２ O ３The insulating film 12a contains ZnO, oxides of all alkaline earth metals selected from CaO, MgO, and BaO, and nickel oxide, but is substantially free of Pb, As, Sb, Li, Na, and K. In this case, by forming the silicon oxide film 16 on the inner surface of the groove 13 to a thickness of 100 nm or less, the lead-free glass layer 14 can be easily formed on the silicon oxide film 16 by electrophoretic deposition. The second method involves forming the lead-free glass layer 14 on the silicon oxide film 16 on the inner surface of the groove 13 by a printing method. Specifically, a glass paste is applied to the inner surface of the groove 13 by a printing method, and then the glass paste is fired to form the lead-free glass layer 14. This lead-free glass layer 14 functions as a passivation layer. The insulating films 12a and 12b are then removed (step (f)). Specifically, the insulating films 12a and 12b on the upper and lower surfaces of the silicon wafer 11 are removed by wet etching with a chemical solution (buffered hydrofluoric acid) or by mechanical processing (e.g., sandblasting). This exposes the electrode formation surfaces on the front and back surfaces of the silicon wafer 11. Next, metal films 15a and 15b are formed on the upper and lower surfaces 11a and 11b of the silicon wafer 11 (step (g)). Specifically, by forming Ni-plated layers as the metal films 15a and 15b on the upper and lower surfaces of the silicon wafer 11, a Ni-plated layer is formed on the entire lower surface of the silicon wafer 11, and multiple first electrode layers 15a made of the Ni-plated layer are formed on the upper surface of the silicon wafer 11 (see FIG. 1(C)). Note that, although plating is used to form the metal films 15a and 15b in this embodiment, vapor deposition or sputtering may also be used to form the metal films 15a and 15b. Thereafter, the lead-free glass layer 14 and the silicon wafer 11 are cut along the center of the bottom surface 13a of the groove 13 (step (h)). According to this embodiment, when the top surface 11a of the silicon wafer 11 having the PN junction 10 is cut with a dicing blade to form grooves 13 having a depth greater than that of the PN junction 10, the inner surface of the groove 13 becomes a rough surface having irregularities. Therefore, the inner surface of the groove 13 is wet-etched in the above step (c) to reduce the surface roughness Ra of the inner surface of the groove 13 to 0.1 μm or less.A silicon oxide film 16 is then formed on the inner surface of the groove 13, and a lead-free glass layer 14 is formed on the silicon oxide film 16 on the inner surface of the groove 13 as passivation. By using the lead-free glass layer 14 and cutting with a dicing blade, it is possible to manufacture a semiconductor device without using a photolithography process or a large amount of chemicals. Furthermore, since the lead-free glass layer 14 has a surface roughness Ra of 0.1 μm or less on the inner surface of the groove 13, the semiconductor device can achieve high breakdown voltage characteristics. Furthermore, according to this embodiment, the semiconductor device can be manufactured without using a photolithography process or a large amount of chemicals, thereby significantly reducing manufacturing costs. Furthermore, using the lead-free glass layer 14 as passivation enables compliance with the European RoHS regulation on lead in glass, thereby contributing to environmental protection. (Second Embodiment) A mesa diode according to [8] above according to one aspect of the present invention will be described. This mesa diode is a mesa diode formed into a chip by cutting the lead-free glass layer 14 and the silicon wafer 11 along the center of the bottom surface 13a of the groove 13 in the step (h) shown in Fig. 1(C) of the first embodiment. As shown in Fig. 1(C), this mesa diode has a first conductivity type semiconductor layer (P. ＋ The semiconductor layer 23 has a first conductivity type semiconductor layer 22 and a second conductivity type semiconductor layer 23 in contact with the first conductivity type semiconductor layer 22. ＋ On the N-type semiconductor layer 22 − The N-type semiconductor layer 32 is formed. − On the N-type semiconductor layer 32 ＋ A second conductivity type semiconductor layer 33 (e.g., N − N-type semiconductor layer 32 and the N-type semiconductor layer thereon ＋ the side of the second conductivity type semiconductor layer 23 and the first conductivity type semiconductor layer (e.g., P ＋ The end of the interface (PN junction surface) 10 with the first conductivity type semiconductor layer (P ＋ A silicon oxide film 16 is formed on a part of the side surface of the second conductivity type semiconductor layer 22. A lead-free glass layer 14 is disposed on the silicon oxide film 16. A second conductivity type semiconductor layer 23 (N −N-type semiconductor layer 32 and the N-type semiconductor layer thereon ＋ the side of the second conductivity type semiconductor layer 23 and the first conductivity type semiconductor layer (P ＋ The end of the interface (PN junction surface) 10 with the first conductivity type semiconductor layer (P ＋ The surface roughness Ra of each part of the side surface of the P type semiconductor layer 22 is 0.1 μm or less. ＋ A part of the side surface of the N-type semiconductor layer 22 − type semiconductor layer 32 and N ＋ The surface roughness Ra of each side surface of the P type semiconductor layer 33 is set to 0.1 μm or less, and the P type semiconductor layer 33 has a surface roughness Ra of 0.1 μm or less. ＋ A part of the side surface of the N-type semiconductor layer 22 − N-type semiconductor layer 32 ＋ A silicon oxide film 16 is formed on the side surface of the mesa-type semiconductor layer 33 and on the end of the interface (PN junction surface) 10, and a lead-free glass layer 14 is disposed on the silicon oxide film 16. In other words, since the lead-free glass layer 14 is formed on a surface with a surface roughness Ra of 0.1 μm or less, the mesa-type diode can achieve high breakdown voltage characteristics. The thickness of the silicon oxide film 16 may be 100 nm or less. In this case, as described in the first embodiment, the lead-free glass layer 14 can be formed by electrophoretic deposition. (Third Embodiment) FIGS. 2A to 2C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention. FIG. 2 illustrates an embodiment in which the first conductivity type and the second conductivity type shown in FIG. 1 are reversed. Specifically, the first conductivity type semiconductor layer 22a is formed as a P-type semiconductor layer. ＋ the second conductivity type semiconductor layer 23a is an N − N-type semiconductor layer 32a and the N-type semiconductor layer thereon ＋ The second embodiment has a PN-type semiconductor layer 33a, and the upper surface 11a and the lower surface 11b of the silicon wafer 11 are reversed. Except for this point, the second embodiment is the same as the first embodiment, so the same parts are given the same reference numerals and the description of the same parts will be omitted. The method for manufacturing a semiconductor device according to one aspect of the present invention [1] includes a step (a) of forming insulating films 12a, 12b on the upper surface 11a and the lower surface 11b of a silicon wafer 11 having a PN junction 10a, as shown in FIG. 2(A). Furthermore, before the above step (A), N −It is advisable to simultaneously diffuse, for example, boron and phosphorus onto the entire surface of the silicon wafer from both sides. − Phosphorus is diffused from the entire lower surface of the silicon wafer 11, and simultaneously, N − Boron is diffused from the entire upper surface of the silicon wafer 11. − The mold silicon wafer 11 is provided with P ＋ N-type semiconductor layer (also referred to as a first conductivity type semiconductor layer) 22a, − -type semiconductor layer 32a and N ＋ The N-type semiconductor layer 33a is formed. − The N-type semiconductor layer 32a ＋ The N-type semiconductor layer 33a is also referred to as the second conductivity type semiconductor layer 23a. − The P-type semiconductor layer 32a ＋ The P ＋ The N-type semiconductor layer 22a − A PN junction 10a is formed on the surface where the silicon wafer 11 is bonded to the silicon semiconductor layer 32a. After that, the upper surface of the silicon wafer 11 is cut with a dicing blade to form a groove 13 having a depth exceeding the PN junction 10a (step (b)). ＋ The upper surface of the silicon wafer 11, which is the N-type semiconductor layer 22a side, − N-type semiconductor layer 32a ＋A groove 13 is formed by cutting a dicing blade (not shown) to a depth reaching partway through the silicon semiconductor layer 33a. Next, the inner surface of the groove 13 is wet-etched to reduce the surface roughness Ra of the inner surface of the groove 13 to 0.1 μm or less (step (c)). A mixture of hydrofluoric acid, nitric acid, sulfuric acid, phosphoric acid, and water is preferably used as the wet etching solution. Wet-etching the inner surface of the groove 13 using such a wet etching solution makes it possible to easily flatten the surface roughness Ra of the inner surface of the groove 13 to 0.1 μm or less. This embodiment also achieves the same effects as the first embodiment. (Fourth Embodiment) A mesa diode according to the above [8] according to one aspect of the present invention will be described. This mesa diode is a mesa diode chip obtained by cutting the lead-free glass layer 14 and the silicon wafer 11 along the center of the bottom surface 13a of the groove 13 using the process shown in FIG. 2(C) of the third embodiment. As explained in the third embodiment, the same parts in Fig. 2(C) as those in Fig. 1(C) are denoted by the same reference numerals, and the explanation of the same parts will be omitted. As shown in Fig. 2(C), this mesa type diode has a first conductivity type semiconductor layer (P ＋ The semiconductor layer 22a has a first conductivity type and a second conductivity type. The semiconductor layer 23a is in contact with the first conductivity type semiconductor layer 22a. ＋ Under the N-type semiconductor layer 22a − The N-type semiconductor layer 32a is formed. − Under the N-type semiconductor layer 32a ＋ The first conductivity type semiconductor layer 33a is formed on the first conductivity type semiconductor layer (P ＋ the side of the first conductivity type semiconductor layer) 22a, ＋ The end of the interface (PN junction surface) 10a between the second conductivity type semiconductor layer 22a and the second conductivity type semiconductor layer 23a, and the second conductivity type semiconductor layer (e.g., N − N-type semiconductor layer 32a and the N-type semiconductor layer thereon ＋ A silicon oxide film 16 is formed on a part of the side surface of the first conductivity type semiconductor layer (P ＋ the side of the first conductivity type semiconductor layer) 22a, ＋The end of the interface (PN junction surface) 10a between the second conductivity type semiconductor layer 22a and the second conductivity type semiconductor layer 23a, and the second conductivity type semiconductor layer (e.g., N − N-type semiconductor layer 32a and the N-type semiconductor layer thereon ＋ The surface roughness Ra of each part of the side surface of the type semiconductor layer 33a) 23a is 0.1 μm or less. In this embodiment, the same effects as in the first embodiment can be obtained.

[0008] 3A and 3B, two samples, Sample A of the comparative example and Sample B of the example, were prepared by adjusting the surface roughness Ra of the inner surface of the groove 13 as shown in Table 1 by changing the etching solution used for wet etching the inner surface of the groove 13. The measurement results of the surface roughness Ra and device characteristics of these samples are shown in Table 1. These samples (mesa diodes) were manufactured by the same manufacturing method as in the third embodiment, except that the etching solution was different. Etching solution A is a mixture of hydrofluoric acid, nitric acid, acetic acid, and water. Etching solution B is a mixture of hydrofluoric acid, nitric acid, sulfuric acid, phosphoric acid, and water. The surface roughness was measured as follows: Equipment used: KEYENCE laser microscope, magnification x100. Measurement value: Ra (arithmetic mean roughness). Ra: Arithmetic mean roughness (Za) represents the average absolute value of Z(x) over a reference length. When the profile curve is a roughness curve, Ra is referred to as the conventional term "arithmetic mean roughness." When the profile curve is a waviness curve, Wa is referred to as the "arithmetic mean waviness." Even if there are large irregularities such as scratches, the numerical value is not easily affected, allowing for relatively stable surface roughness measurements. The device characteristics shown in Table 1 were evaluated as follows. After etching, the reverse characteristics of devices (diodes) that had undergone passivation and electrode formation were evaluated. The evaluation threshold was a reverse voltage VR-1 kV. When the device characteristics are marked "○," a reverse voltage of 1 kV or more can be ensured (see FIG. 3(C)). When the device characteristics are marked "×," a reverse voltage of 1 kV or more cannot be ensured (see FIG. 3(D)). As shown in Table 1, good device characteristics can be obtained when the surface roughness Ra is 0.1 μm or less. FIG. 3(A) is a planar photograph of a silicon wafer after etching the inside of the groove of Sample B shown in Table 1, and FIG. 3(B) is a cross-sectional photograph of the silicon wafer after etching the inside of the groove of Sample B shown in Table 1. FIG. 3(C) is a graph showing the device characteristics of Sample B of the Example shown in Table 1, where the vertical axis represents reverse current and the horizontal axis represents reverse voltage. FIG. 3(D) is a graph showing the device characteristics of Sample A of the Comparative Example shown in Table 1, where the vertical axis represents reverse current and the horizontal axis represents reverse voltage. As shown in FIG. 3(C), it can be seen that the breakdown voltage is approximately 1200 V even when a lead-free glass layer is used as passivation. Furthermore, as shown in FIG. 3B, there are no dicing marks at the bottom of the groove, and the shape of the groove has not changed significantly.

[0009] 10, 10a PN junction (interface between a semiconductor layer of a second conductivity type and a semiconductor layer of a first conductivity type) 11 silicon wafer 11a upper surface of silicon wafer 11b lower surface of silicon wafer 12a, 12b insulating film (silicon oxide film) 13 groove 13a bottom surface of groove 13b side surface of groove 14 lead-free glass layer 15a, 15b metal film 16 silicon oxide film 21 angle formed by bottom surface and side surface of groove 22, 22a semiconductor layer of a first conductivity type (P ＋ Type semiconductor layer) 23, 23a Second conductivity type semiconductor layer Ra Surface roughness

Claims

1. A method for manufacturing a semiconductor device comprising the steps of: (a) forming an insulating film on an upper surface and a lower surface of a silicon wafer having a PN junction; (b) cutting the upper surface of the silicon wafer with a dicing blade to form a groove having a depth greater than the PN junction; (c) wet etching the inner surface of the groove to reduce the surface roughness of the inner surface of the groove to 0.1 μm or less; (d) forming a silicon oxide film on the inner surface of the groove; (e) forming a lead-free glass layer on the silicon oxide film on the inner surface of the groove; (f) removing the insulating film; (g) forming a metal film on the upper surface and the lower surface of the silicon wafer; and (h) cutting the lead-free glass layer and the silicon wafer along the center of the bottom surface of the groove.

2. A method for manufacturing a semiconductor device according to claim 1, wherein the silicon oxide film formed in step (d) is an oxide film having a thickness of 100 nm or less.

3. A method for manufacturing a semiconductor device according to claim 1 or 2, wherein the angle formed by the bottom and side surfaces of the groove in the cross section formed in step (b) is between 60° and 90°.

4. A method for manufacturing a semiconductor device according to claim 1 or 2, wherein the wet etching solution used in the step (c) is a mixture of hydrofluoric acid, nitric acid, sulfuric acid, phosphoric acid and water.

5. A method for manufacturing a semiconductor device according to claim 1 or 2, wherein the insulating film in the step (a) is a silicon oxide film formed by a thermal oxidation method.

6. A method for manufacturing a semiconductor device according to claim 2, wherein the lead-free glass layer in step (e) is formed on the silicon oxide film on the inner surface of the groove by electrophoretic deposition.

7. A method for manufacturing a semiconductor device according to claim 1, wherein the lead-free glass layer in step (e) is formed on the silicon oxide film on the inner surface of the groove by a printing method.

8. A mesa type diode comprising: a semiconductor layer of a first conductivity type; a semiconductor layer of a second conductivity type in contact with the semiconductor layer of the first conductivity type; a silicon oxide film formed on a side surface of the semiconductor layer of the second conductivity type, an end portion of the interface between the semiconductor layer of the second conductivity type and the semiconductor layer of the first conductivity type, and a part of the side surface of the semiconductor layer of the first conductivity type; and a lead-free glass layer disposed on the silicon oxide film, wherein the surface roughness of the side surface of the semiconductor layer of the second conductivity type, the end portion of the interface between the semiconductor layer of the second conductivity type and the semiconductor layer of the first conductivity type, and a part of the side surface of the semiconductor layer of the first conductivity type are each 0.1 μm or less.

9. A mesa type diode comprising: a semiconductor layer of a first conductivity type; a semiconductor layer of a second conductivity type in contact with the semiconductor layer of the first conductivity type; a silicon oxide film formed on a side surface of the semiconductor layer of the first conductivity type, an end portion of the interface between the semiconductor layer of the first conductivity type and the semiconductor layer of the second conductivity type, and a part of the side surface of the semiconductor layer of the second conductivity type; and a lead-free glass layer disposed on the silicon oxide film, wherein the surface roughness of each of the side surface of the semiconductor layer of the first conductivity type, the end portion of the interface between the semiconductor layer of the first conductivity type and the semiconductor layer of the second conductivity type, and a part of the side surface of the semiconductor layer of the second conductivity type is 0.1 μm or less.

10. A mesa diode according to claim 8 or 9, wherein the silicon oxide film has a thickness of 100 nm or less.

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