Configurable dram chiplet

Abstract

A configurable assembly comprises a stack of dynamic random access memory (DRAM) die stacked with a base die. The assembly is configurable in order to be stacked with different system-on-a-chip (SoC) die that may have multiple different memory interface locations that are to interface with different size and memory performance requirements. The DRAM die layers provide core DRAM functions (e.g., read, write, activate, precharge) and are organized into "cubes" of memory array tiles and supporting circuitry that can be operated independently or in lockstep. The base die layer provides the configurability, external connectivity (e.g., to SoC), and common operations (e.g., refresh). In an embodiment, the base layer comprises a configurable mesh network that allows signals to be communicated between external interfaces and the "cubes". The mesh network is configurable via the external interfaces.

Description

CONFIGURABLE DRAM CHIPLETBRIEF DESCRIPTION OF THE DRAWINGS

[0001] Figure 1 is an isometric illustration of a stacked memory chiplet mounted on a system-on-a-chip (SoC).

[0002] Figures 2A-2B are isometric illustrations of a stacked memory assembly.

[0003] Figures 3 A-3B illustrate a chiplet architecture.

[0004] Figure 4 illustrates an example configuration / partitioning of a stacked memory assembly.

[0005] Figure 5 illustrates an example switching arrangement for configuring the operation of multiple layers of dynamic random access memory (DRAM).

[0006] Figures 6A-6C illustrate example switching configurations for multiple layers of DRAM.

[0007] Figure 7 illustrates an example switching matrix for configuring a stacked memory device base die.

[0008] Figure 8 illustrates an example configurable switching circuit for a base die switching matrix.

[0009] Figures 9A-9G illustrate an example of configuring a base die switching matrix.

[0010] Figure 10 is a flowchart illustrating a method of configuring a base die switching matrix.

[0011] Figures 11 A-l 1C illustrate example base die configurations.

[0012] Figures 12A-12C illustrate example external address to internal cube address mappings.

[0013] Figure 13 illustrates example cube address matching circuitry.

[0014] Figure 14 is a flowchart illustrating an example method of configuring base die cube control circuitry.

[0015] Figures 15A-15B illustrate an example distribution and configuration of shared function circuitry.

[0016] Figure 16 illustrates an example configuration of refresh operation circuitry.

[0017] Figure 17 is a flowchart illustrating a method of performing refresh operations.

[0018] Figure 18 is a flowchart illustrating a method of accessing groups of memory cubes independently.

[0019] Figure 19 is a block diagram illustrating an external interface block.

[0020] Figure 20 is a block diagram illustrating cube control circuitry.

[0021] Figure 21 is a block diagram illustrating a processing system.DETAILED DESCRIPTION OF THE EMBODIMENTS

[0022] In an embodiment, a configurable assembly comprises a stack of dynamic random access memory (DRAM) die stacked with a base die. The assembly is configurable in order to be stacked with different system-on-a-chip (SoC) die that may have multiple different memory interface locations that are to interface with different size and memory performance requirements. The DRAM die layers provide core DRAM functions (e.g., read, write, activate, precharge) and are organized into “cubes” of memory array tiles and supporting circuitry that can be operated independently or in lockstep. The base die layer provides the configurability, external connectivity (e.g., to SoC), and common operations (e.g., refresh). In an embodiment, the base layer comprises a configurable mesh network that allows signals to be communicated between external interfaces and the “cubes”. The mesh network is configurable via the external interfaces.

[0023] Figure 1 is an isometric illustration of a stacked memory chiplet mounted on a system-on-a-chip (SoC). In Figure 1, processing system 100 comprises memory array tile (MAT) array integrated circuit die 111, base die 131, and SoC die 190. MAT array die 111, base die 131, and SoC die 190 are stacked with each other. MAT array die 111, base die 131, and SoC die 190 may communicate with one or more of the other of MAT array die 111, base die 131, and SoC die 190 in the vertical direction using through-silicon vias (TSVs).

[0024] MAT array die includes DRAM MAT array regions 11 laa-11 led. Each of MAT array regions 11 laa-1 l ied comprises an array of DRAM MATs (e.g., a 4x4 array of MAT s), associated row circuitry (e.g., row decoders, wordline drivers, etc.), column circuitry (e.g., sense amplifiers, column decoders, etc.), and optionally, additional circuitry. Each MAT array region 11 laa-11 led also includes TSVs so that each of MAT array region 11 laa-11 led may, independent of the other of MAT array regions 11 laa-11 led, be controlled by (e.g., accessed, refreshed, etc.), and communicate with (e.g., commands, addresses, data), base die 131.

[0025] MAT array die 111 is illustrated in Figure 1 as having a two-dimensional array with 3 rows and 4 columns of MAT array regions 11 laa-11 led. It should be understood that the selection of 3 rows and 4 columns is merely for the purposes of illustration. Any number of rows and / or columns of MAT array regions is contemplated.

[0026] Base die 131 is illustrated with a two-dimensional array with 3 rows and 4 columns of configuration, communication, and common function (CCC) circuitry regions 13 laa-13 led. It should be understood that the selection of 3 rows and 4 columns is merely forthe purposes of illustration. Any number of rows and / or columns of CCC circuitry regions are contemplated. In addition, each CCC region may comprise the same or different circuitry. For example, CCC circuitry region 13 laa may include circuitry to refresh one or more of MAT array regions 11 laa- 11 led while CCC circuitry region 13 lab does not. Note that in Figure 1, some CCC circuitry regions (e.g., CCC circuitry regions 131ca-131cc 132ca- 132cc) are obscured by MAT array die 111 and are therefore not visible in Figure 1.

[0027] In an embodiment of processing system 100, each CCC circuitry region 131aa- 13 led of base die 131 may be configured to be intercoupled to its nearest neighbors in the left and right directions and the front and back directions. Thus, a two-dimensional array of CCC circuitry regions 131aa-131cd is illustrated in Figure 1 as being on integrated circuit die 131. The intercoupling may comprise configurable intercoupling circuitry that includes, but is not limited to, input and / or output (I / O) circuitry, buffer circuitry, parallel buses, serial busses, through-silicon via (TSV) connections, and the like. Thus, for example, CCC circuitry region 13 Ibb lies between CCC circuitry region 131ba and CCC circuitry region 131bc in the left and right directions, respectively. CCC circuitry region 13 Ibb therefore may be configured to be intercoupled with both CCC circuitry region 131ba and CCC circuitry region 131bc. Also, as an example, CCC circuitry region 13 Ibb lies between CCC circuitry region 13 1 ab and CCC circuitry region 131cb in the front and back directions, respectively. CCC circuitry region 13 Ibb may therefore also be configured to be intercoupled with CCC circuitry region 13 leb and CCC circuitry region 13 lab. This pattern of being configured to be intercoupled with zero, one, or more, of the respective adjacent left-to-right (if present) and front-to-back (if present) CCC circuitry regions 131aa-131cd may be repeated for any number of, and combinations of, CCC circuitry regions 131aa-131cd.

[0028] In an embodiment, CCC circuitry regions 131aa-131cd and MAT array regions 11 laa-1 l ied have the same (or substantially similar) size such that each MAT array region 11 laa- 11 led on integrated circuit die 111 lies above a respective CCC circuitry region 131aa-131cd on base die 131. Each CCC circuitry region 131aa-131cd is also intercoupled with the corresponding MAT array region 11 laa-11 led that are above (or in another embodiment, below) that respective CCC circuitry region 13 laa- 13 led. In other words, CCC circuitry region 13 laa lies directly below MAT array region 11 laa and is intercoupled with CCC circuitry region 13 laa; CCC circuitry region 13 1 ab lies directly below MAT array region 11 lab and is intercoupled with MAT array region 11 lab, and so on. This vertical intercoupling is illustrated in Figure 1 by the bidirectional arrows running from MAT array regions 11 laa-11 lad on MAT array die 111 to corresponding CCC circuitry regions 13 laa-13 led on base die 131. It should be understood that CCC circuitry regions 131ba-131cd on base die 231 are intercoupled to corresponding MAT array regions 11 lba-11 led on MAT array die 111. However, these arrows have been omitted from Figure 1 because MAT array die 111 is at least partially obscuring them in the isometric view of Figure 1.

[0029] It should be understood that, for the sake of brevity and clarity, only three dies 111, 131, and 190 are illustrated in Figure 1. One or more additional MAT array dies, with additional two-dimensional arrays of MAT array regions, may be stacked with dies 111, 131, and 190 and intercoupled with CCC circuitry regions 13 laa- 13 led in a like manner. These additional dies may form additional layers of memory devices so that the resulting three- dimensional memory device array has more than one layer of MAT array dies in the vertical direction.

[0030] SoC die 190 includes a plurality of processing elements (PEs) 192a-192d with controllers. In other words, SoC die 190, and processing elements 192-a-192d, in particular, include memory controller circuitry and other processing circuitry (e.g., an ALU, a CPU, a GPU, DSP, etc.). SoC die 190 also includes a plurality of host memory channel interface regions 191a-191d. In Figure 1, processing elements 192a-192d are respectively operatively coupled with host interface regions 191a-191d. Host interface regions 191a-191d are illustrated in Figure 1 as being respectively operatively coupled with CCC circuitry regions 131aa-131ad.

[0031] Processing elements 192a-192d are operatively coupled with host interface regions 191 a- 191 d, and host interface regions 191a-191d are operatively coupled with CCC circuitry regions 13 laa- 13 lad to allow CCC circuitry regions to be configured in a manner that allows respective processing elements 192a-192d to access respective ones or more of MAT array regions 11 laa-11 led. In other words, for example, CCC circuitry region 13 laa and CCC circuitry region 131ba may be configured (e.g., by SoC die 190, and processing element 192a, in particular) such that processing element 192a may access the DRAM arrays of MAT array region 11 laa and MAT array region 11 Iba via host interface 191a, CCC circuitry region 13 laa, and CCC circuitry region 13 Iba. In another example, CCC circuitry region B lab, CCC circuitry region 13 lac, and CCC circuitry region 131bc may be configured (e.g., by SoC die 190, and processing element 192b, in particular) such that processing element 192b may access the DRAM arrays of MAT array region 11 Ibc via host interface 191b, CCC circuitry region B lab, CCC circuitry region 13 lac, and CCC circuitry region 13 Ibc.

[0032] It should be understood from the foregoing that, base die 131, and CCC circuitry regions 131aa-131ad, in particular, may be configured to allow any of processing elements 192a-192d to access any of MAT array regions 11 laa-11 led. Furthermore, base die 131, and CCC circuitry regions 131aa-131ad, in particular, may be configured to accommodate different locations for each of host interface regions 191a-191d. Thus, for example, if host interface 191c was located underneath (or in another embodiment, above) CCC circuitry region 13 led, CCC circuitry region 13 led and CCC circuitry region 13 Ibd could be configured to allow processing element 192d to access the DRAM arrays of MAT array region 11 Ibd via host interface 191 d, CCC circuitry region 13 led and CCC circuitry region 13 Ibd. In an embodiment, CCC circuitry regions 13 laa-13 led may be configured by commands that set values in soft registers and / or latches. In an embodiment, CCC circuitry regions 13 laa-13 led may be configured by setting values in one-time programmable registers and / or latches (e.g., fuses, nonvolatile memory, etc.)

[0033] The ability for CCC circuitry regions 13 laa-13 led to be configured to allow access to any of MAT array regions 11 laa-11 led via host interface regions 191a-191d that may not have fixed locations relative to base die 131 allows for different SoC die 190 to be used with the chiplet stack of base die 131 and MAT array die 111. In other words, SoC die 190 may be different die designs that include different location of host interface regions 191a-191d and base die 131 may be configured in appropriate manners to accommodate the differing locations of host interface regions 191a- 191 d. Similarly, processing elements 192a- 192d may have differing memory requirements (e.g., capacity, data bus width, etc.) and base die 131 (and CCC circuitry regions 13 laa-13 led, in particular) may be configured to accommodate these differing memory requirements - both between processing elements on the same SoC die 190, and between processing elements on different SoC dies that may be stacked with base die 131.

[0034] In an embodiment, one or more of CCC circuitry regions 13 laa-13 led may include error detection and correction (EDC) circuitry. CCC circuitry regions 13 laa-13 led may be configured to route data and EDC information to / from the EDC circuitry. In an embodiment, base die 131 is manufactured using a low voltage (i.e., logic) type manufacturing process. In an embodiment, level shifters may be included in MAT array regions 11 laa-11 led for the wordlines of the MATs of MAT array regions 11 laa-11 led. Level shifters may be included in CCC circuitry regions 13 laa-13 led for data signals. In an embodiment, CCC circuitry regions 13 laa-13 led and MAT array regions 11 laa-11 led may communicate signals using a clocked interface utilizing single data rate (SDR) signaling.Host interface regions 191a-191d may communicate signals with CCC circuitry regions 13 laa-13 led using a clocked interface utilizing double data rate (DDR) signaling.

[0035] Figures 2A-2B are isometric illustrations of a stacked memory assembly. In Figure 2A, a first portion of assembly 200 having MAT array die 211 stacked with base die 231 is illustrated. In Figure 2B, a second portion of assembly 200 having base die 231 stacked with SoC die 290 is illustrated. It should be understood that additional MAT array dies are included in assembly 200. However, these are not illustrated in Figures 2A-2B because of illustration constraints. Assembly 200 may be, for example, an implementation of system 100.

[0036] MAT array die 211 includes MAT array regions 21 la-21 Id. MAT array regions 21 la-21 Id include and / or are coupled to TSV connections 217a-217d, respectively. In an embodiment, MAT array regions 21 la-21 Id are, or correspond to, at least a portion of MAT array regions 11 laa-1 l ied. Thus, for example, die 211 may be an implementation and / or example of die 111.

[0037] Base die 231 includes CCC circuitry regions 23 la-23 Id. CCC circuitry regions 23 la-23 Id include and / or are coupled to TSV connections 237a-237d, respectively. In an embodiment, each CCC circuitry regions include circuitry to configure the interconnection of CCC circuitry regions 23 la-23 Id, configure connections to, and / or drive TSV connections 237a-237d. CCC circuitry region 231b also includes and / or is coupled to TSV connections. However, in Figures 2A-2B, these TSV connections are obscured by MAT array die 211 and are therefore not illustrated in Figures 2A-2B.

[0038] TSV connections 217a, 217c, and 217d of MAT array region 21 la, 211c, and 21 Id of MAT array die 211 are aligned with TSV connections 237a, 237c, and 237d of CCC circuitry regions 231a, 231c, and 23 Id of base die 231, respectively and the TSV connections of the other MAT array dies in assembly 200. Likewise, TSV connections 217b of MAT array region 211b of MAT array die 211 are aligned with the obscured (in Figures 2A-2B) TSV connections of CCC circuitry region 231b. Thus, when base die 231, MAT array die 211, and the other MAT array dies in assembly 200 are stacked with each other, TSV connections 237a-237d of CCC circuitry regions 23 la-23 Id of base die 231 are electrically connected to TSV connections (e.g., 217a, 217c, and 217d) of MAT array regions 21 la-21 Id of MAT array die 211 and the TSV connections of the other MAT array dies in assembly 200. This is illustrated in Figure 2A by TSV representations 215a, 215c, and 215d.

[0039] CCC circuitry regions 23 la-231c also include and / or are coupled to TSV connections 238a-238d, respectively. In an embodiment, CCC circuitry regions 23 la-231care, or correspond to, at least a portion of CCC circuitry regions 13 laa-13 led. Thus, for example, base die 231 may be an implementation and / or example of base die 131.

[0040] SoC die 290 includes host interface regions 29 la-29 Id. Host interface regions 29 la-29 Id include and / or are coupled to TSV connections 297a-297d, respectively. Host interface region 291b also includes and / or is coupled to TSV connections. However, in Figure 2B, these TSV connections are obscured by base die 231 and are therefore not illustrated in Figures 2A-2B.

[0041] TSV connections 238a, 238c, and 238d of CCC circuitry regions 231a, 231c, and 23 Id of base die 231 are aligned with TSV connections 297a, 297c, and 297d of host interface regions 291a, 291c, and 29 Id of SoC die 290, respectively. Likewise, TSV connections 238b of CCC circuitry region 231b of base die 231 are aligned with the obscured (in Figures 2A-2B) TSV connections of host interface region 291b. Thus, when base die 231 and SoC die 290 are stacked with each other, TSV connections 238a-238d of CCC circuitry regions 23 la-23 Id of base die 231 are electrically connected to TSV connections host interface regions 29 la-29 Id of SoC die 290. This is illustrated in Figure 2B by TSV representations 235a, 235c, and 235d.

[0042] Figures 3A-3B illustrate a chiplet architecture. In Figures 3A-3B, a chiplet 300 stack having a base die and four DRAM die layers is illustrated. The top die of chiplet 300 is MAT array die 311a. Figure 3 A is an isometric view with a breakout to illustrate CCC circuitry region 391a of the base die and the MAT array regions 31 laa-31 Ida stacked on top of CCC circuitry region 391a. The broken out portion of chiplet 300 is one of a plurality of CCC circuitry regions and the MAT array regions stacked on top of that CCC circuitry region (hereinafter a “cube of MAT s”, “memory cube”, or “cube”).

[0043] In Figure 3A, memory cube 350 of chiplet 300 comprises CCC circuitry region 391a and the MAT array regions 31 laa-31 Ida stacked on top of CCC circuitry region 391a and vertically interconnected (e.g., TSVs) by vertical interconnect 335a-335b. Thus, memory cube 350 is illustrated comprising MAT array regions 31 laa-31 Ida, CCC circuitry region 391a of the base die. MAT array region 31 laa of top MAT array die 31 la, MAT array region 31 Iba of the next die down from top MAT array die 31 la, MAT array region 31 lea of the second die down from top MAT array die 311a, and MAT array region 31 Ida of the die that is on top of the base die, and CCC circuitry region 391a of the base die is illustrated as a broken out lower lefthand corner portion of chiplet 300.

[0044] In Figure 3B, a top view of chiplet 300 is illustrated. As is illustrated in Figure 3B, MAT array region 31 laa of MAT array die 311a includes an NxN array MAT array 312.In an embodiment, N is equal to four. MAT array region 31 laa also includes TSV region 313aa, row logic and / or TSV region 314aa, column logic and / or TSV region 316aa, and an additional region 315aa for optional additional logic and / or TSVs. In addition to TSVs, row logic 314aa may comprise row decoder circuitry, wordline drivers, etc. for performing DRAM row operations on MAT array 312. In addition to TSVs, column logic 316aa may comprise sense amplifiers, decoder circuitry, etc. for performing DRAM column operations of MAT array 312.

[0045] In an embodiment, the unit for configuration of chiplet 300 is a cube of MATs. Each cube of MATs is configurable for page size and access width. Cubes of MATs can be addressed and controlled independent of other cubes of MATs or operated in lockstep. Each DRAM layer (i.e., respective MAT array regions 31 laa- 31 Ida), sets of DRAM layers, or all DRAM layers of a memory cube may be operated as one bank. The layers can be accessed concurrently or sequentially.

[0046] Figure 4 illustrates an example configuration / partitioning of a stacked memory assembly. Figure 4 is a top-view (or map) of a configured chiplet 400. Configured chiplet 400 may represent, for example, a configured version of chiplet 300 after chiplet 300 has been configured. In Figure 4, chiplet 400 is illustrated as a two-dimensional array of memory cubes with 16 columns of memory cubes and 16 rows of memory cubes. The 16x16 array of memory cubes has been partitioned (configured) into groups of memory cubes (hereinafter “memory units”) that are independently operated to perform various memory functions with (possibly) different performance, bandwidth, capacity, and addressing characteristics. The example memory units illustrated in Figure 4 include a main memory unit 401, a scene buffer memory unit 402, a machine learning and / or artificial intelligence engine (ML / Al) memory unit 403, a video memory unit 404, an audio memory unit 406, and a simultaneous localization and mapping (SLAM) buffer memory unit 405.

[0047] Table 1 illustrates several example configurations for main memory unit 401.

[0048] Figure 5 illustrates an example switching arrangement for configuring the operation of multiple layers of dynamic random access memory (DRAM). In Figure 5, switching circuitry 500 comprises configuration control circuitry 501, switching function S10, switching function Si l, switching function S20, switching function S21, switching function S30, switching function S31, and switching function S32. Switching circuitry 500 may be considered example circuitry to configure the vertical interconnects 335a-335b illustrated in Figure 3 A. Configuration control circuitry 501 may include programmable registers to hold a configuration state and / or mode. Switching circuitry 500 may be implemented in the base die of a chiplet (e.g., in one or more, or all, of CCC circuitry regions 131aa-131cd). Switching functions S10, SI 1, S20, S21, S30, S31, and S32 are schematically illustrated as switches. However, it should be understood that this is merely for illustration purposes. One of more of switching functions S10, Si l, S20, S21, S30, S31, and S32 maybe, comprise, or be implemented using, one or more of field-effect transistors (e.g., NFET, PFET), multiplexers, logic gates, buffers, tri-state buffers, etc.

[0049] In Figure 5, configuration control circuitry 501 is operatively coupled to switching functions S10, SI 1, S20, S21, S30, S31, and S32. Configuration control circuitry 501 is operatively coupled to switching functions S10, Si l, S20, S21, S30, S31, and S32 to determine whether each of switching functions S10, SI 1, S20, S21, S30, S31, and S32 is in a pass-through (a.k.a., conducting) state or a blocking (a.k.a., non-conducting) state. When in the pass through state, each of switching functions S10, SI 1, S20, S21, S30, S31, and S32 communicates signals between one of base layers signals B0-B3 and a one of layer signals L0-L3. Each of layer signals L0-L3 is respectively coupled to a signal on a different MAT array die in the chiplet stack. For example, L0 may be coupled (e.g., via TSVs) to a signal in the corresponding MAT array region (e.g., MAT array region 31 Ida) of the lowest (first) MAT array die that is closest to the base die; LI may be coupled (e.g., via TSVs) to a corresponding signal in the corresponding MAT array region (e.g., MAT array region 31 lea) of the next (second) MAT array die from the base die; L2 may be coupled (e.g., via TSVs) to the corresponding signal in the corresponding MAT array region (e.g., MAT array region 31 Iba) of the second from the top (third) MAT array die from the base die; and, L3 may be coupled (e.g., via TSVs) to the corresponding signal in the corresponding MAT array region (e.g., MAT array region 31 laa) of the top (fourth) MAT array die.

[0050] In Figure 5, base die signal B0 is always communicated with L0. Switching function S10 may be configured to passthrough or block communication between base die signal B0 and LI. Switching function SI 1 may be configured to passthrough or block communication between base die signal Bl and LI. Switching function S20 may be configured to passthrough or block communication between base die signal B0 and L2. Switching function S21 may be configured to passthrough or block communication between base die signal B2 and L2. Switching function S30 may be configured to passthrough or block communication between base die signal B0 and L3. Switching function S31 may be configured to passthrough or block communication between base die signal B2 and L3. Switching function S32 may be configured to passthrough or block communication between base die signal B3 and L3.

[0051] Switching circuitry 500 may be used, for example, to configure the routing of various signals (e.g., a row address bit, column address bit, a data bit, etc.) between the base die and the MAT array dies of a chiplet. The configurations of switching circuitry 500 may be used, for example, to configure the MAT array dies of a chiplet to operate independently,to operate in tandem with one other MAT array die mutually independent of the other two MAT array dies, or to have all four MAT array dies operate in lockstep. Table 2 illustrates example configurations of switching circuitry 500 that may be used.

[0052] Figures 6A-6C illustrate example switching configurations for multiple layers of DRAM. In Figures 6A-6C, chiplet circuitry 600 comprises row decoder (DCDR) circuitry 610-613 on each of layers 0-3, respectively and base die 631. Base die 631 includes row control circuitry 632, configuration control circuitry 635, and switching circuitry 636. Switching circuitry 636 may be an implementation of switching circuitry 500. Thus, switching circuitry 636 has base die ports B0-B3 and layer ports L0-L3. Base die ports BOBS are operatively coupled to row control circuitry 632. In Figures 6A-6B, row control circuitry 632 receives row address signals (RA[]). In Figure 6C, row control circuitry 632 receives two sets of independent row address signals (RAA[], RAB[]).

[0053] In Figure 6B, switching circuitry 600 has been configured to operate the row decoders for all of layers 0-3 in lockstep. Accordingly, switching circuitry 636 had been configured (e.g., by configuration control circuitry 635) to passthrough the signal at the B0 port to each of the L0-L3 ports such that the same row control signal is provided to row decoder circuitry 610-613 on each of layers 0-3. This is illustrated in Figure 6B by the arrowrunning from row control circuitry 632 into switching circuitry 636 where it splits into four arrows that respectively run to row decoder circuitry 610-613.

[0054] In Figure 6C, switching circuitry 600 has been configured to operate row decoder circuitry 610-611 on layer 0 and layer 1, respectively in lockstep with each other and also operate row decoder circuitry 612-613 on layer 2 and layer 3, respectively, in lockstep with each other, but independent of layer 0 and layer 1 row decoder circuitry 610-611. Accordingly, switching circuitry 636 had been configured (e.g., by configuration control circuitry 635) to passthrough the signal at the B0 port to the L0 and LI ports such that the same row control signal is provided to row decoder circuitry 610-611 on layer 0 and layer 1, and to also passthrough the signal at the B2 port to the L2 and L3 ports such that the same row control signal is provided to row decoder circuitry 612-613 on layer 2 and layer 3. This is illustrated in Figure 6C by a first arrow running from row address RAA[] through row control circuitry 632 into switching circuitry 636 where it splits into two arrows that respectively run to row decoder circuitry 610 and 611, and is further illustrated by a second arrow running from row address RAB[] through row control circuitry 632 into switching circuitry 636 where it splits into two arrows that respectively run to row decoder circuitry 612 and 613.

[0055] Figure 7 illustrates an example switching matrix for configuring a stacked memory device base die. In Figure 7, base die 700 is overlaid with a matrix of busses that run horizontally and vertically. The busses are spaced to correspond the size, as viewed from above, of the memory cubes. Thus, it should be understood that the matrix of busses correspond to, for example, the intercoupled of each CCC circuitry region 131aa-131cd to its nearest neighbors in the left and right directions and the front and back directions discussed with reference to Figure 1. For each signal in the matrix of buses, each node (i.e., CCC region) includes configurable switching circuitry that allows signals arriving from any direction to be relayed to every other direction (i.e., in the top view of Figure 7: up the page, down the page, left on the page, and right on the page, or equivalently, back, front, left, right in the isometric views of Figure 1 and Figures 2A-2B).

[0056] In the Figure 7, the matrix of busses is illustrated interconnecting rectangular regions. However, it should be understood that the interconnection of other region shapes or tiles are contemplated. For example, triangular regions or hexagonal regions and corresponding interconnect patterns having switches that interconnect adjacent edges of regions are contemplated.

[0057] Figure 8 illustrates an example configurable switching circuit for a base die switching matrix. In Figure 8, switching circuitry 800 comprises tri-stateable redrivers 801- 806, and tri-stateable redrivers 811-816, and configuration circuitry 825. Configuration circuitry 825 controls the tri-state control inputs of redrivers 801-806 and redrivers 811-816. In some embodiments, the tri-state control inputs of redrivers 801-806 and redrivers 811-816 may be controlled dynamically to implement bidirectional and / or shared signals (or busses) using the matrix of busses on a base die.

[0058] Switching circuit 800 has the ports UP, DOWN, LEFT, and RIGHT. These ports corresponding to the direction of neighboring switching circuitry (i.e., the ports couple to signal conductors leading to the switching circuitry 800 of another CCC circuitry region in the direction of the port name). When active (i.e., not in the undriven state - a.k.a., not tristated), redrivers relay signals from one of the ports UP, DOWN, LEFT, and RIGHT to a different one of the ports UP, DOWN, LEFT, or RIGHT.

[0059] In particular, redriver 801 may relay the DOWN port to the RIGHT port based on the D2R signal. Redriver 802 may relay the RIGHT port to the LEFT port based on the R2L signal. Redriver 803 may relay the LEFT port to the UP port based on the L2U signal. Redriver 804 may relay the DOWN port to the LEFT port based on the D2L signal. Redriver 805 may relay the RIGHT port to the UP port based on the R2U signal. Redriver 806 may relay the DOWN port to the UP port based on the D2U signal.

[0060] Redriver 811 may relay the UP port to the LEFT port based on the U2L signal. Redriver 812 may relay the LEFT port to the RIGHT port based on the L2R signal. Redriver 813 may relay the RIGHT port to the DOWN port based on the R2D signal. Redriver 814 may relay the UP port to the RIGHT port based on the U2R signal. Redriver 815 may relay the LEFT port to the DOWN port based on the L2D signal. Redriver 816 may relay the UP port to the DOWN port based on the U2D signal.

[0061] Figures 9A-9G illustrate an example of configuring a base die switching matrix. The configuration illustrated by Figures 9A-9G may be performed and executed by, for example, system 100, assembly 200, and / or their components. In Figure 9, memory system 900 comprises base die 931 and SoC die 990. Memory system 900 also includes a stack of MAT array dies stacked with base die 931 and SoC die 990. However, for the examples detailed in Figures 9A-9G, these MAT array dies are omitted for the sake of clarity and brevity. Base die 931 comprises mesh network 901 and mesh network interface 937. SoC die 990 comprises control circuitry 995 and mesh network interface 997. SoC die 990 is operatively coupled to base die 931 via mesh network interface 997 and mesh networkinterface 937. SoC die 990 is operatively coupled to base die 931 using signaling 950 that may include commands, data, clocks, etc.

[0062] In Figures 9A-9G, base die 931 comprises mesh network 901 and mesh network interface 937. Mesh network 901 is comprised of bus switches 93 laa-93 lee arranged in a 3x3 two-dimensional array. Each of bus switches 931aa-931cc represent a plurality switching circuits (e.g., switching circuitry 800). In particular, bus switches 93 laa-93 lee represent at least enough switching circuits to switch three busses a[], b[], and c[] that are presented for the purposes of these examples. Thus, for example, if example bus a[] has 20 signals, example bus b [] hasl6 signals, and example bus c[]has 32 signals, bus switches 93 laa-93 lee would each be representing at least 20+16+32=68 switching circuits. Furthermore, in Figures 9A-9G, switches 93 laa-93 lee represent a portion of the larger mesh network 901. For example, mesh network 901 may comprise a 16x16, 10x10, 8x10 etc. two- dimensional array with each switching circuit 931aa-931cc being part of, and providing access to, a corresponding memory cube.

[0063] Each of switching circuits 93 laa-93 lee has UP, DOWN, LEFT, and RIGHT ports for each of bus a[], bus b[], and bus c[]. These are shown in Figures 9A-9G as au, bu, and cu for the UP ports; as ad, bd, cd for the DOWN ports; as al, bl, and dl for the LEFT ports; and ar, br, and cr for the RIGHT ports. Thus, it should be understood that each switching circuit 93 laa-93 lee of mesh network 901 may be configured to be intercoupled to its nearest neighbors (if present) in the left and right directions and the up and down directions. Also in Figures 9A-9G, the DOWN ports ad, bd, and cd of bus switches 93 lab are operatively coupled to network interface 937. It should be understood, however, that this is merely for the purposes of illustrating the examples. Network interface 937 of base die 931 (or other network interfaces of base die 931 — not shown in Figures 9A-9G) that may be coupled to SoC die 990 may couple to other ports (UP, LEFT, etc.) of other bus switches 93 laa-93 lee.

[0064] At the start of initialization, as illustrated in Figure 9 A, mesh network 901 has been reset and all bus switches 93 laa-93 lee are configured to block all signals received (i.e., all ports are tri-stated and not relaying any of bus a[], bus b[], or bus c[] signals). In Figure 9B, a first step to configure mesh network 901 is illustrated. In Figure 9B, SoC die 990, under the control of control circuitry 995, signals 951, via interface 997 and interface 937, bus switch 93 lab to enable the down-to-up passthrough of buses a[], b[], and c[]. This is illustrated in Figure 9B by the arrows running to ports ad, bd, and cd from network interface 937 to bus switch 93 lab that are labeled “D2U” (down-to-up). The down-to-up configuration signaling received by bus switch 93 lab enables (e.g., by asserting the D2U control signal)bus switch 93 lab to transmit, on its au, bu, and cu bus ports, signals received at its ad, bd, and cd bus ports. This is illustrated in Figures 9B-9G by the dotted lines running from the ad, bd, and cd bus ports of bus switch 93 lab to its au, bu, and cu bus ports, respectively. Once configured, bus switch 93 lab enters a mode where bus switch 93 lab will not respond to further forward configuration signaling from SoC die 990.

[0065] In Figure 9C, SoC die 990, under the control of control circuitry 995, signals 952, via interface 997 and interface 937, bus switch 931bb to enable the down-to-right passthrough of buses a[], b[], and c[]. This is illustrated in Figure 9C by the arrows running to ports ad, bd, and cd from network interface 937 to bus switch 93 lab that are labeled “D2R” (down-to-right).

[0066] Because bus switch 93 lab is in a mode where bus switch 93 lab will not respond to further forward configuration signaling from SoC die 990, bus switch 93 lab ignores the down-to-right configuration signaling. Further, because bus switch 93 lab is configured to transmit signals received at the ad, bd, and cd bus ports via the au, bu, and cu bus ports, the down-to-right configuration signaling received by bus switch 93 lab is relayed by bus switch 93 lab to the ad, bd, and cd bus ports of bus switch 93 Ibb. This is illustrated in Figure 9C by the arrows running from bus switch 93 lab to ports ad, bd, and cd of bus switch 93 Ibb that are labeled “D2R” (down-to-right). The down-to-right configuration signaling received by bus switch 93 Ibb enables (e.g., by asserting the D2R control signal) bus switch 93 Ibb to transmit, on its ar, br, and cr bus ports, signals received at its ad, bd, and cd bus ports. This is illustrated in Figures 9D-9G by the dotted lines running from the ad, bd, and cd bus ports of bus switch 93 Ibb to its ar, br, and cr bus ports, respectively. Once configured, bus switch 93 Ibb enters the mode where bus switch 93 Ibb will not respond to further forward configuration signaling from SoC die 990 and / or bus switch 93 lab.

[0067] In Figure 9D, SoC die 990, under the control of control circuitry 995, signals 953, via interface 997 and interface 937, bus switch 93 Ibc to enable the left-to-right passthrough of buses a[], b[], and c[]. This is illustrated in Figure 9D by the arrows running to ports al, bl, and cl from network interface 937 to bus switch 93 Ibc that are labeled “L2R” (down-to- right).

[0068] Because bus switch 93 lab and bus switch 93 Ibb are in the mode where bus switch 93 lab and bus switch 93 Ibb will not respond to further forward configuration signaling from SoC die 990, bus switch 93 lab and bus switch 93 Ibb ignore the left-to-right configuration signaling. Further, because bus switch 93 lab and bus switch 93 Ibb are configured to relay signals, the left-to-right configuration signaling received by bus switch 93 lab is relayed tothe al, bl, and cl bus ports of bus switch 93 Ibc. This is illustrated in Figure 9D by the arrows running from interface 937 to ports al, bl, and cl of bus switch 93 Ibc that are labeled “L2R” (left-to-right). The left-to-right configuration signaling received by bus switch 93 Ibc enables (e.g., by asserting the L2R control signal) bus switch 93 Ibc to transmit, on its ar, br, and cr bus ports, signals received at its al, bl, and cl bus ports. This is illustrated in Figures 9E-9G by the dotted lines running from the al, bl, and cl bus ports of bus switch 93 Ibc to its ar, br, and cr bus ports, respectively. Once configured, bus switch 93 Ibc enters the mode where bus switch 93 Ibc will not respond to further forward configuration signaling from SoC die 990 and / or bus switch 93 Ibb.

[0069] In Figure 9E, mesh network 901 is configured to relay signals 954 (e.g., address data, clocks, etc.) received by network interface 937 to the ar, br, and cr ports of bus switch 93 Ibc. This is illustrated in Figure 9E by the arrows running from network interface 937 to the OUTPUT[a,b,c] label via bus switch 93 lab, bus switch 93 Ibb, and bus switch 93 Ibc.

[0070] In Figure 9F, SoC die 990, under the control of control circuitry 995, signals 955, via interface 997 and interface 937, bus switch 93 lab, bus switch 93 Ibb, and bus switch 93 Ibc to reverse the direction of bus a[] and to configure bus c[] to be tri-statable based on local signaling. This is illustrated in Figure 9F by the arrows running from network interface 937 to bus switch 93 Ibc that are labeled “REV-A” (reverse bus A signals) and “TRI-C” (enable bus C signals to tri-state). In an embodiment, each of bus switch 93 lab, bus switch 93 Ibb, and bus switch 93 Ibc may, after relaying the reverse-A and tri-state-C signaling to the next bus switch, perform the configuration. This is illustrated in Figure 9G by the arrows along the bus a[] signals pointing in the direction running from the ar port of bus switch 93 Ibc to network interface 937, and double headed arrows (bidirectional) along the bus c[] signals.

[0071] In an embodiment, after the reverse-A and tri-state-C signaling has propagated to the extent of the configured network, each bus switch reverses the direction of the specified bus signals one at a time in the reverse direction. For example, after the reverse-A and tri- state-C signaling has propagated to bus switch 93 Ibc, bus switch 93 Ibc reconfigures bus a[] in the reverse direction, then bus switch 93 Ibb reconfigures bus a[] in the reverse direction, and finally bus switch 93 lab reconfigures bus a[] in the reverse direction. In an embodiment, after the reverse-A and tri-state-C signaling has propagated to the extent of the configured network, each bus switch reverses the direction of the specified bus signals concurrently (or simultaneously) in the reverse direction and, if correspondingly configured as such, tri-state enabled.

[0072] Figure 10 is a flowchart illustrating a method of configuring a base die switching matrix. One or more steps illustrated in Figure 10 may be performed by, for example, system 100, assembly 200, chiplet 300, chiplet 400, base die 700, switching circuitry 800, system 900, and / or their components. The base die is reset (1002). For example, after power-up, or other reset event (host reset), all the redrivers (e.g., redrivers 801-806 and redrivers 811-816) of the bus switches (e.g., bus switches 931aa-931cc) are off (i.e., tri-stated), all flip-flops and latches (e.g., in configuration circuitry 825) are in defined states, and configuration registers (e.g., in configuration circuitry 825) are writable (i.e., the bus switches the mode where they will not respond to further configuration signaling).

[0073] The bus switch with its input coupled to the SoC interface is set as the current bus switch (1004). For example, bus switch 93 lab, which has its DOWN inputs coupled to interface 937, may be set as the initial current bus switch. To the current bus switch, redriver configuration information for the current bus switch is transmitted. For example, as illustrated in Figure 9B, when bus switch 93 lab is the current bus switch, down-to-up (D2U) configuration signaling may be transmitted to bus switch 93 lab via interface 997 and interface 937. In another example, as illustrated in Figure 9D, when bus switch 93 Ibc is the current bus switch, left-to-right configuration signaling may be transmitted to bus switch 93 Ibc via interface 997, interface 937, bus switch 93 lab, and bus switch 931bb.

[0074] The current bus switch stores the received configuration, sets a redriver write-once indicator, and starts redriving signals to a new current bus switch according to the received configuration (1008). For example, when bus switch 93 lab is the current bus switch, and bus switch receives down-to-up (D2U) configuration information, bus switch 93 lab enables (e.g., by asserting the D2U control signal) bus switch 93 lab to transmit, on its au, bu, and cu bus ports, signals received at its ad, bd, and cd bus ports and then bus switch 93 lab enters the mode (i.e., by setting a write-once indicator) where bus switch 93 lab will not respond to further forward configuration signaling from SoC die 990. In another example, when bus switch 93 Ibc is the current bus switch, and bus switch 93 Ibc receives left-to-right configuration information, bus switch 93 Ibc enables (e.g., by asserting the L2R control signal) bus switch 93 Ibc to transmit, on its ar, br, and cr bus ports, signals received at its al, bl, and cl bus ports and then bus switch 93 Ibc enters the mode (i.e., by setting a write-once indicator) where bus switch 93 lab will not respond to further forward configuration signaling from SoC die 990.

[0075] In box 1010, if forward bus configuration is not complete, flow proceeds to box 1006. If the forward bus configuration is complete, flow proceeds to box 1012 (1010). Forexample, as illustrated in Figure 9E, bus switch 93 Ibc is the last bus switch that SoC is to configure in the forward direction. Reverse signal configuration information and dynamic signal disable (tri-state) configuration information is transmitted to all bus switches on the configured bus (1012). For example, as illustrated in Figure 9F, bus switch 93 lab, bus switch 93 Ibb, and bus switch 93 Ibc (i.e., all of the bus switches in the example bus of Figures 9A-9G) receive configuration information (i.e., REV-A, TRI-C) to reverse the direction of bus a[] and to configure bus c[] to be tri-stateable based on local signaling.

[0076] The bus switch on the configured bus store the received reverse configuration and received tri-state configuration, and set reverse configuration and tri-state configuration write-once indictors (1014). For example, bus switch 93 lab, bus switch 93 Ibb, and bus switch 93 Ibc (i.e., all of the bus switches in the example bus of Figures 9A-9G) store the received configuration information (i.e., REV-A, TRI-C) to reverse the direction of bus a[] and to configure bus c[] to be tri-stateable based on local signaling and set reverse direction configuration and tri-state configuration write-once indicators. The bus switches on the configured bus enter mission mode by reversing redriver and enabling tri-stating according to the stored configurations. For example, bus switch 93 Ibc may enter mission mode by disabling the forward configuration (e.g., by deasserting the L2R control signal) and enabling the reverse direction (e.g., by asserting the R2L control signal) thus configuring bus switch 93 Ibc to transmit, on its al bus port, signals received at its ar bus port. Bus switch 93 Ibc may also enter mission mode by enabling the local tri-stating of its bus ports cr and cl.

[0077] Figures 11 A-l 1C illustrate example base die configurations. Figure 11 A illustrates base die circuitry underlying a 1x4 bank of memory cubes with an external interface. In Figure 11 A, bank 1100a comprises two types of base die circuitry (e.g., CCC circuitry) underlying each memory cube. A first type of base die circuitry 1111a includes configuration and control circuitry 1135a, connections (e.g., TSVs) to the DRAM layers of the memory cube above the control circuitry 1137a, and SoC connections (e.g., TSVs) 1138a, and bus switching circuitry 1139a. A second type of base die circuitry 1111b includes configuration and control circuitry 1135b, connections (e.g., TSVs) to the DRAM layers of the memory cube above the control circuitry 1137b, and bus switching circuitry 1139b. Figure 1 IB illustrates base die circuitry underlying a 1x4 bank of memory cubes without an external interface. In Figure 1 IB, bank 1100b comprises the second type of base die circuitry 1111b but not the first type of base die circuitry 1111a.

[0078] Figure 11C illustrates a memory unit comprising eight (8) columns of 1x4 cube banks. In Figure 11C, memory unit 1100c comprises seven 1x4 cube banks without externalinterfaces (e.g., base die bank circuitry 1100b), and one 1x4 cube bank with an external interface (e.g., base die bank circuitry 1111b illustrated by example in Figure 11C by base die circuity 111 Ibx). The cube bank with an external interface is illustrated in Figure 11C by base die circuitry 111 laa. Base die circuitry 111 laa is also adjacent to another region of base die circuitry 111 lab that also has an external interface.

[0079] In Figure 11C, the bus switches (e.g., 1139a and 1139b) of memory unit 1100c have been configured to form bus 1170, bus 1171, and busses 1172a-l 172h. Bus 1170 (illustrated running vertically with horizontal hashing) couples the external interfaces of base die circuitry 111 lab and base die circuitry 111 laa to bus 1171 (illustrated running horizontally with vertical hashing). Bus 1171 couples the signals from base die circuitry 111 laa to each of the 1x4 banks of memory unit 1100c. Each 1x4 bank of memory unit is coupled together with one of busses 1172a-l 172h (illustrated by example by bus 1172a running vertically with diagonal hashing and bus 1172b running vertically with cross hashing).

[0080] It should be understood that commands / addresses / data from any of the memory cubes of memory unit 1100c may be communicated with the external interfaces of base die circuitry 111 laa and base die circuitry 111 lab. In an embodiment, some command / address signals may couple to the SoC via base die circuitry 111 laa and other may couple to the SoC via base die circuitry 111 lab. In an embodiment, each cube control circuitry (e.g., control circuitry 1135a and control circuitry 1135b) snoops the bus it is coupled with to determine whether a command is addressed to it. In an embodiment, bus 1170, bus 1171, and busses 1172a-l 172h comprise 64 write data signals, 64 read data signals, and 32 command / address signals.

[0081] Figures 12A-12C illustrate example external address to internal cube address mappings. In the examples of Figures 12A-12C, the commands comprise 32 external command / address signals where the most-significant five (5) bits are command bits. In Figures 12A-12C, external (i.e., SoC to base die) bank addresses are mapped to internal (i.e., base die to DRAM die layers) addresses. In the example mapping illustrated in Figure 12 A, the bank address portion of the external address is mapped to a base die address that specifies the memory cube being addressed (INT CUBE ADDR) and the layer being addressed (LA). In the example mapping illustrated in Figure 12B, the row address portion of the external address is mapped to a base die address that specifies the memory cube being addressed (CUBE ADDR), the layer being addressed (LA), and an internal row address (INT ROW ADDR). In the example mapping illustrated in Figure 12C, the column address portion of theexternal address is mapped to a base die address that specifies the layer being addressed (LA), and an internal column address (INT COL ADDR). In an embodiment, the base die circuitry (e.g., CCC circuitry) may be configured for one or more, or all, of the address mapping illustrated by Figures 12A-12C. In an embodiment, the base die circuitry (e.g., CCC circuitry) may be configured for one or more, or all, of the address mapping illustrated by Figures 12A-12C on a memory unit by memory unit (e.g., memory units 401-406) basis.

[0082] Figure 13 illustrates example cube address matching circuitry. In Figure 13, address mapping circuitry 1300 comprises bitwise enable register 1302, match value register 1304, comparison circuitry 1306, and control circuitry 1350. Control circuitry 1350 is operatively coupled to bitwise enable register 1302, match value register 1304, and comparison circuitry 1306. Control circuitry 1350 is operatively coupled to bitwise enable register 1302 to set the value stored by bitwise enable register 1302. Control circuitry 1350 is operatively coupled to match value register 1304 to set the value stored by match value register 1304.

[0083] The m-n bits stored by bitwise enable register 1302 each correspond to one of m-n address bits. If the bit in bitwise enable register 1302 is a first logical value (e.g., “0”), then comparison circuitry 1306 will not consider that bit when comparing the address stored by the m-n bits of match value register 1304 to a received address (e.g., CA[m:n]). If the bit in bitwise enable register 1302 is a second logical value (e.g., “1”), then comparison circuitry 1306 will consider that bit when comparing the address stored by the m-n bits of match value register 1304 to a received address (e.g., CA[m:n]). The output of comparison circuitry is the signal CMATCH. CMATCH indicates whether the bits of the received address CA[m:n] that are enabled to be compared match the values of the bits of the address stored by match value register 1304. In an embodiment, m equals 26 and n equals 18.

[0084] Tables 3-5 illustrate several example address mappings. The mapping illustrated by Table 3 may be, for example, used by video memory unit 404. The mapping illustrated by Table 4 may be, for example, used by main memory unit 401. In Tables 3-5: “CMD[]” represents external command bits; iCMD[] represents internal (i.e., base die to memory cube) command bits; RFU represent “reserved for future use”; BA[] represents bank address bits; iLA[] represents internal layer address bits; RA[] represents row address bits; iRA[] represents internal row address bits; COL[] represents column address bits; and iCA[] represent internal column address bits.

[0085] Figure 14 is a flowchart illustrating an example method of configuring base die cube control circuitry. One or more steps illustrated in Figure 14 may be performed by, for example, system 100, assembly 200, chiplet 300, chiplet 400, base die 700, switching circuitry 800, system 900, memory unit 1100c, and / or their components. A broadcast mode register set (MRS) command is used to place all base die cube control circuitry into absolute address mode (1402). For example, Soc die 190 may transmit a broadcast mode register set command via base die circuitry 111 laa and / or base die circuitry 111 lab to place all of the base die control circuitry of memory unit 1100c into a mode that responds to absolute (i.e., predetermined at manufacturer) addresses.

[0086] The absolute addresses are iterated through to write associated match values and enable values to corresponding base die control circuitry (1404). For example, Soc die 190 may transmit a series of register set commands individually addressed to each of the base die control circuitry of memory unit 1100c to write the bitwise enable (e.g., stored by bitwise enable register 1302) and match values (e.g., stored by match value register 1304) to all of base die control circuitry of memory unit 1100c.

[0087] A broadcast mode register set command is used to place all base die cube control circuitry into use stored (a.k.a., mapped) address mode (1406). For example, Soc die 190may transmit a broadcast mode register set command via base die circuitry 111 laa and / or base die circuitry 111 lab to place all of the base die control circuitry of memory unit 1100c into a mode that responds to the mapped (e.g., by mapping circuitry 1300) addresses.

[0088] Figures 15A-15B illustrate an example distribution and configuration of shared function circuitry. Figures 15A-15B are top-views (or maps) of a configured chiplet 1500. Configured chiplet 1500 may represent, for example, a configured version of chiplet 300 after chiplet 300 has been configured. In Figures 15A-15B, chiplet 1500 is illustrated as a two- dimensional array of memory cubes with 16 columns of memory cubes and 16 rows of memory cubes. The 16x16 array of memory cubes has been partitioned into memory units. The example memory units illustrated in Figures 15A-15B include memory units 401-406.

[0089] In Figures 15A-15B, some shared function memory cubes 1510a-15al0h include circuitry for functions that may be shared with other memory cubes. For example, the circuitry to implement voltage generators and / or refresh operations may be centralized at a few cubes and distributed to other cubes. In Figures 15A-15B, shared function memory cubes 1510a-l 5 lOd are part of memory unit 1501. Shared function memory cube 1510e is part of memory unit 1506. Shared function memory cube 151 Of and shared function memory cube 15 lOh are part of memory unit 1502. Shared function memory cube 1510g is part of memory unit 1504.

[0090] In an example, shared function memory cubes 1510a-1510h include main refresh circuitry that implement one or more of refresh functions such as a refresh address counter, a timer for refresh row cycle timing, and / or a temperature monitoring circuit. The non-shared function memory cubes of chiplet 1500 implement refresh command replication circuitry. In Figures 15A-15B, memory unit 1501, memory unit 1502, memory unit 1504, and memory unit 1506 include cubes with main refresh circuitry. Accordingly, each of memory unit 1501, memory unit 1502, memory unit 1504, and memory unit 1506 may be refreshed using the refresh functions provided by a selected one of the shared function memory cubes that are part of that memory unit. In other words, for example, memory unit 1501 may be refreshed under the control of shared function memory cube 1510a, memory unit 1502 by shared function memory cube 15 lOf memory unit 1504 by shared function memory cube 1510g, and memory unit 1506 by shared function memory cube 1510e. This is illustrated in Figure 15B by shared function memory cube 1510a, shared function memory cube 1510e, shared function memory cube 1510f, and shared function memory cube 1510g being illustrated with diagonal hashing to indicate the main memory refresh circuitry is configured to be used.

[0091] In Figures 15A-15B, memory unit 1503, and memory unit 1505 do not include cubes with main refresh circuitry. Accordingly, in an embodiment, shared function memory cubes in a different memory unit may be used to provide the refresh functions to memory unit 1503 and memory unit 1505. To provide the refresh functions to memory unit 1503 and memory unit 1505, the selected shared function memory cubes in the different memory units are coupled with the refresh command replication circuitry of a selected memory cube in the memory unit 1503 and memory unit 1505. The refresh command replication circuitry then relays the commands from the main refresh circuitry to the memory cubes of the memory unit 1503 and memory unit 1505. This is illustrated in Figure 15B for memory unit 1503 by shared function memory unit 151 Od in memory unit 1501 (which is illustrated with diagonal hashing) being coupled with memory cube 1512 (which is illustrated with cross-hatching) via bus 1515. This is illustrated in Figure 15B for memory unit 1505 by shared function memory unit 15 lOh in memory unit 1502 (which is illustrated with diagonal hashing) being coupled with memory cube 1511 (which is illustrated with cross-hatching) via bus 1516.

[0092] Figure 16 illustrates an example configuration of refresh operation circuitry. In Figure 16, refresh configuration 1600 comprises memory unit A 1601 (e.g., memory unit 1501 of Figures 15A-15B) and memory unit B 1603 (e.g., memory unit 1503 of Figures 15A- 15B). Memory unit A includes a shared function memory cube 1610 with main refresh circuitry 1610a, refresh control circuitry 1610b, and DRAM interface circuitry 1610c (i.e., interface circuitry with DRAM layers). Memory unit B includes at least memory cube #1 1611, memory cube #2 1612, and command / address bus 1604a. Memory cube #1 1611 includes refresh command replication circuitry 1611a, refresh control circuitry 1611b, and DRAM interface circuitry 1611c. Memory cube #2 1612 includes refresh command replication circuitry 1612a, refresh control circuitry 1612b, and DRAM interface circuitry 1612c.

[0093] In Figure 16, main refresh circuitry 1610a of memory cube #1 1610 is operatively coupled to refresh command replication circuitry 161 la of memory cube #1 1611 via bus 1615. Refresh command replication circuitry 1611a receives refresh commands (or indicators thereof) via bus 1615 and places the received refresh commands onto command / address bus 1604a. Refresh control circuitry 161 lb- 1612b, and the refresh control circuitry of the rest of memory unit B’s memory cubes, receive the refresh commands via CA bus 1604b. In response to these refresh commands, refresh control circuitry 161 lb- 1612b, via DRAM interface 1611c-1612c, respectively, perform refresh operations on the DRAM layers of their respective memory cubes.

[0094] Figure 17 is a flowchart illustrating a method of performing refresh operations. One or more steps illustrated in Figure 17 may be performed by, for example, system 100, assembly 200, chiplet 300, chiplet 400, base die 700, switching circuitry 800, system 900, banks HOOa-l lOOb, memory unit 1100c, chiplet 1500, configuration 1600, and / or their components. A network is configured to couple main refresh circuitry in first cube control circuitry of a first memory unit with refresh replication circuitry in second cube control circuitry of a second memory unit (1702). For example, a base die mesh network (e.g., mesh network 901) may be configured to form a bus (e.g., bus 1615) to couple main refresh circuitry (e.g., main refresh circuitry 1610a) in a first memory unit (e.g., memory unit A 1601) with refresh command replication circuitry (e.g., refresh command replication circuitry 161 la) of a memory cube (e.g., memory cube #1 1611) in a second memory unit (e.g., memory unit B 1603).

[0095] By the second cube control circuitry, a first refresh command is detected (1704). For example, refresh command replication circuitry 1611a may detect a refresh command (e.g., by monitoring command / address bus 1604a). By the second cube control circuitry, a first indicator of the first refresh command is transmitted to the first cube control circuitry (1706). For example, refresh command replication circuitry 1611a may transmit, to main refresh circuitry 1610a, an indicator of the detected refresh command.

[0096] Based on the first indicator and by the first cube control circuitry, a first refresh command is generated (1708). For example, based on the indicator that refresh command replication circuitry 1611a has detected a refresh command, main refresh circuitry 1610a may generate a refresh command. By the first cube control circuitry, a second indicator of the second refresh command is transmitted to the second cube control circuitry (1710). For example, main refresh circuitry 1610a may transmit, to refresh command replication circuitry 1611a and via bus 1615, an indicator of the generated refresh command.

[0097] By the second cube control circuitry, a third indicator of the refresh command is transmitted to a plurality of cubes of the second memory unit (1712). For example, refresh command replication circuitry 1611a may transmit, via command / address bus 1604a and to a plurality (or all) of the memory cubes of memory unit B 1603, an indicator of the refresh command generated by main refresh circuitry 1610a. In response to the third indicator and by the plurality of cubes of the second memory unit, a refresh operation is performed (1714). For example, in response to the refresh command indicator transmitted via command / address bus 1604a and received by memory cube #1 1611, memory cube #2 1612, and the rest of the memory cubes in memory unit B 1603, memory cube #1 1611, memory cube #2 1612, andthe rest of the memory cubes in memory unit B 1603may perform the refresh operation corresponding the refresh command indicator memory cube #1 1611, memory cube #2 1612, and the rest of the memory cubes in memory unit B 1603, memory cube #1 1611 received from refresh command replication circuitry 1611a.

[0098] Figure 18 is a flowchart illustrating a method of accessing groups of memory cubes independently. Example memory access operations that may be independently performed include, but are not limited to, activate, read, write, precharge, refresh. One or more steps illustrated in Figure 18 may be performed by, for example, system 100, assembly 200, chiplet 300, chiplet 400, base die 700, switching circuitry 800, system 900, banks 1100a- 1100b, memory unit 1100c, chiplet 1500, configuration 1600, and / or their components. A base die is configured to couple a first group of memory array tiles to a first interface with a host die, the first group of memory array tiles being stacked and interconnected (1802). For example, chiplet 400 may be configured, using a mesh network, to group memory cubes into memory unit 401 that is coupled to an SoC via TSVs in at least one of the memory cubes of memory unit 401.

[0099] The base die is configured to couple a second group of memory array tiles to a second interface with the host die, the second group of memory array tiles being stacked and interconnected (1804). For example, chiplet 400 may be configured, using the mesh network, to group memory cubes into memory unit 402 that is coupled to an SoC via TSVs in at least one of the memory cubes of memory unit 402. Independent of accesses to the second group of memory array tiles and in response to a first command received from the host die via the first interface, the first group of memory array tiles is accessed (1806). For example, the SoC may access memory unit 401 independent of memory unit 402 using a first command transmitted to memory unit 401.

[0100] Independent of accesses to the first group of memory array tiles and in response to a second command received from the host die via the second interface, the second group of memory array tiles is accessed (1808). For example, the SoC may access memory unit 402 independent of memory unit 401 using a second command transmitted to memory unit 402.

[0101] Figure 19 is a block diagram illustrating an external interface block. In Figure 19, external interface bloc 1900 comprises control circuitry 1901, optional serializer 1902, optional deserializer 1903, optional deserializer 1904, tri-state buffers 1906, tri-state buffers 1907, tri-state buffers 1908, and external connections 1938. Control circuitry 1901 includes mode registers 1901a. Control circuitry 1901 may transmit reset signals RSTA and RSTB to reset mesh network configurations. External connections 1938 include connections forcommand / address signals, data signals, and power supplies. External connections may comprise a field of bumps, landing pads for hybrid bonding, or wirebond pads. External interface block 1900 may be an example of circuitry and / or connections that may be part of, for example, base die circuitry 1111a illustrated in Figure 11 A.

[0102] Internal read data signals (RDQI[]) are coupled to the input of tri-state buffers 1906. Internal write data signals (WDQI[]) are coupled to the output of tri-state buffers 1907. Internal command / address signals (CAI[]) are coupled to the output of tri-state buffers 1908. The output of tri-state buffers 1906 is operatively coupled to external connections 1938 (optionally via serializer 1902). The input of tri-state buffers 1907 is operatively coupled to external connections 1938 (optionally via deserializer 1903). Control circuitry 1901 and the input of tri-state buffers 1908 is operatively coupled to external connections 1938 (optionally via deserializer 1904). Tri-state buffers 1906-1908 (and serializer 1902, and deserializers 1903-1904, if present) are individually controlled by control circuitry 1901.

[0103] External interface block 1900 may snoop command / address signals for mode register set commands that are addressed to external interface block 1900. External interface block 1900 may control the configuration of a mesh network (e.g., mesh network 700) by forwarding configuration signals to the mesh network and by issuing reset indicators (e.g., via RSTA and RSTB). Thus, external interface block 1900 may reset mesh network switches in itself and in neighboring cube control circuitry.

[0104] Figure 20 is a block diagram illustrating cube control circuitry. In Figure 20, cube control block 2000 comprises control circuitry 2001, optional serializer 2002, optional deserializer 2003, switch control circuitry 2004, error detection and correction circuitry 2005, layer 0 interface 2030, layer 1 interface 2031, layer 2 interface 2032, and layer 3 interface 2033. Control circuitry 2001 include mode registers 2001a. Layer interfaces 2030-2033 respectively communicate with memory array die layers, predecoded row signals (LOPDROW[]-L3PDROW[]), predecoded column signals (LOPDCOL[]-L3PDCOL[]), data signals (L0DQ[]-L3DQ[]), and parity / error correcting code signals (L0ECC[]-L3ECC[]). Internal read data signals (RDQI[]) are operatively coupled to error detection and correction circuitry (EDC) 2005 and layer interfaces 2030-2033 (optionally via serializer 2002). Internal write data signals (WDQI[]) are operatively coupled to EDC 2005 and layer interfaces 2030-2033 (optionally via deserializer 2003). EDC 2005 is operatively coupled to layer interfaces 2030-2033. In an embodiment, EDC implements a single error correct (SEC) encoding / decoding (e.g., a 128 data bit, 8 ECC bit code).

[0105] Control circuitry 2001 is operatively coupled to layer interfaces 2030-2033, switch control circuitry 2004, and EDC circuitry 2005. Control circuitry 2001 is operatively coupled to internal command / address signals (CAI[]). Control circuitry 2001 snoops CAI[] for commands addressed to cube control block 2000. Control circuitry 2001 generates predecoded row and column addresses and provides them to the appropriate layer(s) depending on the command and address that were received. Mode registers 2001a may store mapping information to translate addresses received via CAI[] to addresses to be transmitted via layer interfaces 2030-2033.

[0106] Switch control circuitry 2004, under the control of control circuitry 2001 and based on information (e.g., commands, addresses, etc.) received via CAI[], controls tri-state buffers of the local switching circuitry for the memory cube. Thus, switch control circuitry 2004 transmits, a reset signal (RST), a tri-state command / address signals indicator (TCA), a tri-state write data signals indicator (TWDQ), and a tri-state read data signals indicator (TRDQ).

[0107] In an embodiment, one or more of system 100, assembly 200, chiplet 300, chiplet 400, base die 700, switching circuitry 800, system 900, banks HOOa-l lOOb, memory unit 1100c, chiplet 1500, configuration 1600, external interface block 1900, cube control block 2000, and / or their components may be operated in a faster mode or a lower power mode. In the faster mode, command / address signals and write data signals are broadcast to all memory cubes. In this mode, the switching circuitry on the CAI[] signals and WDQI[] signals are not tri-stated. However, the RDQI[] are tri-stated at appropriate intervals and cubes to avoid drive fights.

[0108] In the lower power mode, write commands (and optionally activate and / or precharge commands) are made in three steps. The first step is setting some of the switching circuitry on the CAI[] and WDQI[] to be tri-stated such that only the targeted and necessary pass-throughs to communicate the command and data are used. The second step is to transmit the command and communicate the data. The third step is to reset the switching circuitry to be ready for the next command.

[0109] The methods, systems and devices described above may be implemented in computer systems, or stored by computer systems. The methods described above may also be stored on a non-transitory computer readable medium. Devices, circuits, and systems described herein may be implemented using computer-aided design tools available in the art, and embodied by computer-readable files containing software descriptions of such circuits. This includes, but is not limited to one or more elements of system 100, assembly 200,chiplet 300, chiplet 400, base die 700, switching circuitry 800, system 900, banks 1100a- 1100b, memory unit 1100c, chiplet 1500, configuration 1600, external interface block 1900, cube control block 2000, and their components. These software descriptions may be: behavioral, register transfer, logic component, transistor, and layout geometry -level descriptions. Moreover, the software descriptions may be stored on storage media or communicated by carrier waves.

[0110] Data formats in which such descriptions may be implemented include, but are not limited to: formats supporting behavioral languages like C, formats supporting register transfer level (RTL) languages like Verilog and VHDL, formats supporting geometry description languages (such as GDSII, GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and languages. Moreover, data transfers of such files on machine-readable media may be done electronically over the diverse media on the Internet or, for example, via email. Note that physical files may be implemented on machine-readable media such as: 4 mm magnetic tape, 8 mm magnetic tape, 3-1 / 2 inch floppy media, CDs, DVDs, and so on.

[0111] Figure 21 is a block diagram illustrating one embodiment of a processing system 2100 for including, processing, or generating, a representation of a circuit component 2120. Processing system 2100 includes one or more processors 2102, a memory 2104, and one or more communications devices 2106. Processors 2102, memory 2104, and communications devices 2106 communicate using any suitable type, number, and / or configuration of wired and / or wireless connections 2108.

[0112] Processors 2102 execute instructions of one or more processes 2112 stored in a memory 2104 to process and / or generate circuit component 2120 responsive to user inputs 2114 and parameters 2116. Processes 2112 may be any suitable electronic design automation (EDA) tool or portion thereof used to design, simulate, analyze, and / or verify electronic circuitry and / or generate photomasks for electronic circuitry. Representation 2120 includes data that describes all or portions of system 100, assembly 200, chiplet 300, chiplet 400, base die 700, switching circuitry 800, system 900, banks HOOa-l lOOb, memory unit 1100c, chiplet 1500, configuration 1600, external interface block 1900, cube control block 2000, and their components, as shown in the Figures.

[0113] Representation 2120 may include one or more of behavioral, register transfer, logic component, transistor, and layout geometry-level descriptions. Moreover, representation 2120 may be stored on storage media or communicated by carrier waves.

[0114] Data formats in which representation 2120 may be implemented include, but are not limited to: formats supporting behavioral languages like C, formats supporting registertransfer level (RTL) languages like Verilog and VHDL, formats supporting geometry description languages (such as GDSII, GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and languages. Moreover, data transfers of such files on machine-readable media may be done electronically over the diverse media on the Internet or, for example, via email

[0115] User inputs 2114 may comprise input parameters from a keyboard, mouse, voice recognition interface, microphone and speakers, graphical display, touch screen, or other type of user interface device. This user interface may be distributed among multiple interface devices. Parameters 2116 may include specifications and / or characteristics that are input to help define representation 2120. For example, parameters 2116 may include information that defines device types (e.g., NFET, PFET, etc.), topology (e.g., block diagrams, circuit descriptions, schematics, etc.), and / or device descriptions (e.g., device properties, device dimensions, power supply voltages, simulation temperatures, simulation models, etc.).

[0116] Memory 2104 includes any suitable type, number, and / or configuration of non- transitory computer-readable storage media that stores processes 2112, user inputs 2114, parameters 2116, and circuit component 2120.

[0117] Communications devices 2106 include any suitable type, number, and / or configuration of wired and / or wireless devices that transmit information from processing system 2100 to another processing or storage system (not shown) and / or receive information from another processing or storage system (not shown). For example, communications devices 2106 may transmit circuit component 2120 to another system. Communications devices 2106 may receive processes 2112, user inputs 2114, parameters 2116, and / or circuit component 2120 and cause processes 2112, user inputs 2114, parameters 2116, and / or circuit component 2120 to be stored in memory 2104.

[0118] Implementations discussed herein include, but are not limited to, the following examples:

[0119] Example 1: A device, comprising: a first memory die comprising a first plurality of memory arrays, the first plurality of memory arrays including a first memory array, a second memory array, and a third memory array, accesses of each of the first plurality of memory arrays to operate independently of accesses of the other of the first plurality of memory arrays; a configuration die, stacked with the first memory die, comprising a plurality of interfaces to communicate with a die; the configuration die configurable to, in response to first commands and first addresses communicated with the die and via a first interface of the plurality of interfaces, access the first memory array and the second memory array and toalso, in response to second commands and second addresses communicated with the die and via a second interface of the plurality of interfaces, concurrently with concurrently accessing the first memory array and the second memory array, access the third memory array; and the configuration die also configurable to, in response to the first commands and the first addresses communicated with the die via the first interface, access the first memory array and to, in response to the second commands and the second addresses communicated with the die via the second interface and concurrently with accessing the first memory array, access at least one of the second memory array and the third memory array.

[0120] Example 2: The device of example 1, further comprising: a second memory die stacked with the first memory die and the configuration die, the second memory die comprising a second plurality of memory arrays, the second plurality of memory arrays including a fourth memory array, a fifth memory array, and a sixth memory array, accesses of each of the second plurality of memory arrays to operate independently of accesses of the other of the first plurality of memory arrays and the second plurality of memory arrays.

[0121] Example 3: The device of example 2, wherein: the configuration die is further configurable to, in response to the first commands and the first addresses, access the fourth memory array and the fifth memory array and to also, in response to the second commands and the second addresses, concurrently with concurrently accessing the first memory array, the second memory array, the third memory array, and the fourth memory array, access the sixth memory array; and the configuration die also configurable to, in response to the first commands and the first addresses communicated with the die via the first interface, access the fourth memory array and to, in response to the second commands and the second addresses concurrently with accessing the first memory array and the fourth memory array, access at least one of the fifth memory array and the sixth memory array.

[0122] Example 4: The device of example 1, wherein the configuration die comprises a mesh network that is configurable to couple the first interface to the first memory array, the second memory array, and the third memory array and is also configurable to couple the second interface to the first memory array, the second memory array, and the third memory array.

[0123] Example 5: The device of example 1, wherein the configuration die comprises decode circuitry to at least partially decode the first addresses and the second addresses before providing partially decoded first addresses and partially decoded second addresses to a configured at least two of the first memory array, the second memory array, and the third memory array.

[0124] Example 6: The device of example 1, wherein the configuration die comprises refresh circuitry to cause the first memory array, the second memory array, and the third memory array to perform refresh operations.

[0125] Example 7: The device of example 1, wherein the configuration die comprises voltage generation circuitry to provide at least one operating voltage, derived from a voltage received from the die, to the first memory array, the second memory array, and the third memory array.

[0126] Example 8: The device of example 1, wherein the configuration die comprises error detection and correction (EDC) circuitry to detect and correct errors in data stored by the first memory array, the second memory array, and the third memory array.

[0127] Example 9: A device, comprising: a plurality of stacked DRAM memory die arranged and connected to form a plurality of memory cubes, the plurality of memory cubes arranged in a two-dimensional array, the plurality of memory cubes each comprising a three- dimensional array of memory array tiles; and a base die, stacked with the plurality of stacked DRAM memory die, to configure groups of memory cubes to be accessed and to share at least one external interface to communicate with a host die.

[0128] Example 10: The device of example 9, wherein the base die configures interconnect to place each of the plurality of memory cubes in one of the groups of memory cubes.

[0129] Example 11: The device of example 10, wherein the interconnect is configurable to allow the host die to access memory array tiles of a first group of the groups of memory cubes via a first base die interface and to access memory array tiles of a second group of the groups of memory cubes via a second base die interface.

[0130] Example 12: The device of example 11 wherein the base die receives addresses via the first interface and the second interface and comprises decode circuitry to at least partially decode the addresses and provide partially decoded addresses to the plurality of memory cubes.

[0131] Example 13: The device of example 8, wherein the base die comprises refresh circuitry to cause plurality of memory cubes to perform refresh operations.

[0132] Example 14: The device of example 8, wherein the base die comprises error detection and correction (EDC) circuitry to detect and correct errors in data stored by the plurality of memory cubes.

[0133] Example 15: The device of example 8, wherein the base die comprises voltage generation circuitry to provide at least one operating voltage, derived from a voltage received from the host die, to the plurality of memory cubes.

[0134] Example 16: A method of operating a device, comprising: configuring a base die to couple a first group of memory array tiles to a first interface with a host die, the first group of memory array tiles being stacked and interconnected with the base die; configuring the base die to couple a second group of memory array tiles to a second interface with a host die, the second group of memory cubes being stacked and interconnected with the base die; accessing, independent of accesses to the second group of memory array tiles and in response to a first command received from the host die via the first interface, the first group of memory array tiles; and accessing, independent of accesses to the first group of memory array tiles and in response to a second command received from the host die via the second interface, the second group of memory array tiles.

[0135] Example 17: The method of example 16, further comprising: refreshing, by the base die, the first group of memory array tiles; and refreshing, by the base die, the second group of memory array tiles.

[0136] Example 18: The method of example 16, further comprising: receiving, from the first group of memory array tiles and by the base die, a first block of data having an error; correcting, by the base die, the first block of data to generate a corrected block of data; transmitting the corrected block of data to the host die via the first interface.

[0137] Example 19: The method of example 16, further comprising: configuring the first group of memory array tiles to communicate data in parallel with the base die using a first number of bits; configuring the second group of memory array tiles to communicate data in parallel with the base die using a second number of bits, where the first number of bits and the second number of bits are not equal.

[0138] Example 20: The method of example 16, further comprising: configuring the first group of memory array tiles to utilize a first page size having a first number of bits; configuring the second group of memory array tiles to utilize a first page size having a second number of bits, where the first number of bits and the second number of bits are not equal.

[0139] The foregoing description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and other modifications and variations may be possible in light of the above teachings. The embodiment was chosen and described in order to best explain the principles of the invention and its practical application to thereby enable others skilled in theart to best utilize the invention in various embodiments and various modifications as are suited to the particular use contemplated. It is intended that the appended claims be construed to include other alternative embodiments of the invention except insofar as limited by the prior art.

Claims

CLAIMSWhat is claimed is:

1. A device, comprising: a first memory die comprising a first plurality of memory arrays, the first plurality of memory arrays including a first memory array, a second memory array, and a third memory array, accesses of each of the first plurality of memory arrays to operate independently of accesses of the other of the first plurality of memory arrays; a configuration die, stacked with the first memory die, comprising a plurality of interfaces to communicate with a die; the configuration die configurable to, in response to first commands and first addresses communicated with the die and via a first interface of the plurality of interfaces, access the first memory array and the second memory array and to also, in response to second commands and second addresses communicated with the die and via a second interface of the plurality of interfaces, concurrently with concurrently accessing the first memory array and the second memory array, access the third memory array; and the configuration die also configurable to, in response to the first commands and the first addresses communicated with the die via the first interface, access the first memory array and to, in response to the second commands and the second addresses communicated with the die via the second interface and concurrently with accessing the first memory array, access at least one of the second memory array and the third memory array.

2. The device of claim 1, further comprising: a second memory die stacked with the first memory die and the configuration die, the second memory die comprising a second plurality of memory arrays, the second plurality of memory arrays including a fourth memory array, a fifth memory array, and a sixth memory array, accesses of each of the second plurality of memory arrays to operate independently of accesses of the other of the first plurality of memory arrays and the second plurality of memory arrays.

3. The device of claim 2, wherein:the configuration die is further configurable to, in response to the first commands and the first addresses, access the fourth memory array and the fifth memory array and to also, in response to the second commands and the second addresses, concurrently with concurrently accessing the first memory array, the second memory array, the third memory array, and the fourth memory array, access the sixth memory array; and the configuration die also configurable to, in response to the first commands and the first addresses communicated with the die via the first interface, access the fourth memory array and to, in response to the second commands and the second addresses concurrently with accessing the first memory array and the fourth memory array, access at least one of the fifth memory array and the sixth memory array.

4. The device of claim 1, wherein the configuration die comprises a mesh network that is configurable to couple the first interface to the first memory array, the second memory array, and the third memory array and is also configurable to couple the second interface to the first memory array, the second memory array, and the third memory array.

5. The device of claim 1, wherein the configuration die comprises decode circuitry to at least partially decode the first addresses and the second addresses before providing partially decoded first addresses and partially decoded second addresses to a configured at least two of the first memory array, the second memory array, and the third memory array.

6. The device of claim 1, wherein the configuration die comprises refresh circuitry to cause the first memory array, the second memory array, and the third memory array to perform refresh operations.

7. The device of claim 1, wherein the configuration die comprises voltage generation circuitry to provide at least one operating voltage, derived from a voltage received from the die, to the first memory array, the second memory array, and the third memory array.

8. The device of claim 1, wherein the configuration die comprises error detection and correction (EDC) circuitry to detect and correct errors in data stored by the first memory array, the second memory array, and the third memory array.

9. A device, comprising: a plurality of stacked DRAM memory die arranged and connected to form a plurality of memory cubes, the plurality of memory cubes arranged in a two- dimensional array, the plurality of memory cubes each comprising a three- dimensional array of memory array tiles; and a base die, stacked with the plurality of stacked DRAM memory die, to configure groups of memory cubes to be accessed and to share at least one external interface to communicate with a host die.

10. The device of claim 8, wherein the base die configures interconnect to place each of the plurality of memory cubes in one of the groups of memory cubes.

11. The device of claim 10, wherein the interconnect is configurable to allow the host die to access memory array tiles of a first group of the groups of memory cubes via a first base die interface and to access memory array tiles of a second group of the groups of memory cubes via a second base die interface.

12. The device of claim 11 wherein the base die receives addresses via the first interface and the second interface and comprises decode circuitry to at least partially decode the addresses and provide partially decoded addresses to the plurality of memory cubes.

13. The device of claim 8, wherein the base die comprises refresh circuitry to cause plurality of memory cubes to perform refresh operations.

14. The device of claim 8, wherein the base die comprises error detection and correction (EDC) circuitry to detect and correct errors in data stored by the plurality of memory cubes.

15. The device of claim 8, wherein the base die comprises voltage generation circuitry to provide at least one operating voltage, derived from a voltage received from the host die, to the plurality of memory cubes.

16. A method of operating a device, comprising:configuring a base die to couple a first group of memory array tiles to a first interface with a host die, the first group of memory array tiles being stacked and interconnected with the base die; configuring the base die to couple a second group of memory array tiles to a second interface with a host die, the second group of memory cubes being stacked and interconnected with the base die; accessing, independent of accesses to the second group of memory array tiles and in response to a first command received from the host die via the first interface, the first group of memory array tiles; and accessing, independent of accesses to the first group of memory array tiles and in response to a second command received from the host die via the second interface, the second group of memory array tiles.

17. The method of claim 16, further comprising: refreshing, by the base die, the first group of memory array tiles; and refreshing, by the base die, the second group of memory array tiles.

18. The method of claim 16, further comprising: receiving, from the first group of memory array tiles and by the base die, a first block of data having an error; correcting, by the base die, the first block of data to generate a corrected block of data; transmitting the corrected block of data to the host die via the first interface.

19. The method of claim 16, further comprising: configuring the first group of memory array tiles to communicate data in parallel with the base die using a first number of bits; configuring the second group of memory array tiles to communicate data in parallel with the base die using a second number of bits, where the first number of bits and the second number of bits are not equal.

20. The method of claim 16, further comprising: configuring the first group of memory array tiles to utilize a first page size having a first number of bits;configuring the second group of memory array tiles to utilize a first page size having a second number of bits, where the first number of bits and the second number of bits are not equal.

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