Display module and display apparatus

Abstract

A display module and a display apparatus. The display module comprises a display substrate (10) and a first structure layer (11); on the plane parallel to the display substrate (10), the display substrate (10) comprises a display area (AA) and a frame area (BB), the frame area (BB) is located around the display area (AA), the frame area (BB) is provided with at least one type of first gate driving circuits (GOA1), there are a plurality of first gate driving circuits (GOA1) of the same type, and the first gate driving circuits (GOA1) comprise a plurality of transistors; in a direction (Z) perpendicular to the plane where the display substrate is located, the first structure layer (11) is provided on a backlight side (S2) of the display substrate (10), the orthographic projection of the first structure layer (11) on the display substrate (10) at least covers part of the display area (AA), and at least some transistors in the plurality of first gate driving circuits (GOA1) of the same type have the same range covered by the orthographic projection of the first structure layer (11) on the display substrate (10).

Description

Display module, display device Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technology, and in particular to a display module and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, display devices using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] In a first aspect, an embodiment of the present disclosure provides a display module, comprising a display substrate and a first structural layer, wherein on a surface parallel to the display substrate, the display substrate comprises a display area and a border area, the border area being located around the display area, the border area being provided with at least one type of first gate drive circuit, the number of first gate drive circuits of the same type being multiple, and the first gate drive circuit comprising multiple transistors; in a direction perpendicular to the surface of the display substrate, the display substrate comprises a light-emitting side and a backlight side, the first structural layer being arranged on the backlight side of the display substrate, the orthographic projection of the first structural layer on the display substrate covering at least part of the display area, and at least part of the transistors in multiple first gate drive circuits of the same type being covered by the same range of the orthographic projection of the first structural layer on the display substrate.

[0006] In an exemplary embodiment, a plurality of first gate driving circuits of the same type are arranged along an extending direction of the border area.

[0007] In an exemplary embodiment, the display area includes multiple rows of sub-pixels, the sub-pixels include at least a pixel driving circuit, the pixel driving circuit includes at least one oxide transistor, and the first gate driving circuit is electrically connected to the control electrode of at least one oxide transistor in at least one row of sub-pixels, and is configured to provide a scanning signal to the at least one oxide transistor in the at least one row of sub-pixels.

[0008] In an exemplary embodiment, the plurality of transistors in the first gate driving circuit include at least a low-level output transistor and a low-level output control transistor, the low-level output transistor being configured to output a low-level signal to at least one oxide transistor in the at least one row of sub-pixels under the control of the low-level output control transistor;

[0009] The low-level output transistors in multiple first gate driving circuits of the same type have a consistent range covered by the orthographic projection of the first structural layer on the display substrate; the low-level output control transistors in multiple first gate driving circuits of the same type have a consistent range covered by the orthographic projection of the first structural layer on the display substrate.

[0010] In an exemplary embodiment, an orthographic projection of the first structure layer on the display substrate does not have an overlapping area with at least one type of the plurality of first gate driving circuits.

[0011] In an exemplary embodiment, an orthographic projection of an edge of the first structure layer on the display substrate is located in a first region. On a plane parallel to the display substrate, the first region is located between an edge of the at least one type of multiple first gate driving circuits close to the display area and an edge of the display area close to the border area. The orthographic projection of the first structure layer on the display substrate covers the display area.

[0012] Alternatively, the orthographic projection of the first structure layer on the display substrate does not overlap with the frame area, and the orthographic projection of the first structure layer on the display substrate is within the display area or overlaps with the display area.

[0013] In an exemplary embodiment, on a surface parallel to the display substrate, along the direction from the display area to the border area, the distance between the edge of the first structural layer and the edge of the display substrate is 700 microns to 1200 microns, which is greater than the distance between the edge of at least one type of first gate drive circuit close to the display area and the edge of the display substrate.

[0014] In an exemplary embodiment, an orthographic projection of the first structure layer on the display substrate covers the display area and a plurality of first gate driving circuits of at least one type.

[0015] In an exemplary embodiment, the border area is further provided with at least one type of second gate driving circuit, and the number of the same type of second gate driving circuits is multiple. On a surface parallel to the display substrate, the multiple second gate driving circuits of the same type are arranged along the extension direction of the border area, and along the direction from the display area to the border area, the multiple second gate driving circuits of at least one type are located between the multiple first gate driving circuits of at least one type and the display area.

[0016] In an exemplary embodiment, on a surface parallel to the display substrate, in a direction from the display area to the border area, the distance between the edge of the first structural layer and the edge of the display substrate is 100 microns to 350 microns, which is less than the distance between the edge of at least one type of first gate drive circuit away from the display area and the edge of the display substrate.

[0017] In an exemplary embodiment, the border area is further provided with at least one type of second gate driving circuit, and the number of the same type of second gate driving circuits is multiple. On a surface parallel to the display substrate, the multiple second gate driving circuits of the same type are arranged along the extension direction of the border area, and along the direction from the display area to the border area, the multiple second driving circuits of at least one type are located on the side of the multiple first driving circuits of at least one type away from the display area.

[0018] In an exemplary embodiment, on a surface parallel to the display substrate, in a direction from the display area to the border area, the distance between the edge of the first structural layer and the edge of the display substrate is 500 microns to 700 microns, which is less than the distance between the edge of at least one type of first gate drive circuit away from the display area and the edge of the display substrate.

[0019] In an exemplary embodiment, the first structure layer includes a first connection structure layer, a buffer structure layer and a heat dissipation structure layer arranged in sequence on the backlight side, and the orthographic projection of the heat dissipation structure layer on the display substrate does not have an overlapping area with at least one type of multiple first gate driving circuits, or the orthographic projection of the heat dissipation structure layer on the display substrate covers at least one type of multiple first gate driving circuits.

[0020] In an exemplary embodiment, an orthographic projection of the first structure layer on the display substrate covers at least at least one of the low-level output transistors and the low-level output control transistors in at least one type of a plurality of first gate driving circuits.

[0021] In an exemplary embodiment, on a surface parallel to the display substrate, along a direction from the display area to the border area, the low-level output control transistor is located on a side of the low-level output transistor away from the display area, a length of at least one type of first gate driver circuit is 120 microns to 150 microns, and the low-level output control transistor and the low-level output transistor are located on both sides of a midline of the first gate driver circuit along a direction in which the border area extends;

[0022] In a structure in which an orthographic projection of the first structure layer on the display substrate covers at least the low-level output transistors and the low-level output control transistors in at least one type of a plurality of first gate driving circuits, a length along a direction from the display area to the border area in which the orthographic projection of the first structure layer on the display substrate covers the at least one type of first gate driving circuit is 100 micrometers to 150 micrometers;

[0023] In the structure in which the orthographic projection of the first structural layer on the display substrate covers at least the low-level output transistors in a plurality of first gate driving circuits of at least one type, the length dimension of the orthographic projection of the first structural layer on the display substrate covering the at least one type of first gate driving circuit along the direction from the display area to the border area is 40 microns to 95 microns.

[0024] In an exemplary embodiment, the border area is further provided with at least one type of second gate driving circuit, and a plurality of second gate driving circuits of the same type are arranged along an extension direction of the border area on a surface parallel to the display substrate;

[0025] Along the direction from the display area to the border area, at least one type of multiple second gate driving circuits is located on a side of at least one type of multiple first gate driving circuit away from the display area, or at least one type of multiple second gate driving circuits is located between at least one type of multiple first gate driving circuits and the display area.

[0026] In an exemplary embodiment, the display substrate includes a blocking structure layer, which is located on a side of the first gate driving circuit away from the light-emitting side in a direction perpendicular to a surface of the display substrate, and the blocking structure layer includes at least one of a first blocking structure and a second blocking structure;

[0027] There are multiple first shielding structures, and the multiple first shielding structures are respectively configured to shield the low-level output control transistors in at least one type of multiple first gate drive circuits; there are multiple second shielding structures, and the multiple second shielding structures are respectively configured to shield the low-level output transistors in at least one type of multiple first gate drive circuits.

[0028] In the second aspect, the embodiments of the present disclosure also provide a display module, including a display substrate. On a surface parallel to the display substrate, the display substrate includes a display area and a border area, the border area is located around the display area, and the border area is provided with at least one type of first gate driving circuit, and the number of first gate driving circuits of the same type is multiple, and the first gate driving circuit includes multiple transistors; in a direction perpendicular to the surface of the display substrate, the display substrate includes a light-emitting side and a backlight side, and a shielding structure layer is provided on the side of the first gate driving circuit away from the light-emitting side, and the multiple first gate driving circuits of the same type are shielded in the same range by the shielding structure layer.

[0029] In an exemplary embodiment, a plurality of first gate driving circuits of the same type are arranged along an extending direction of the border area.

[0030] In an exemplary embodiment, the display area includes multiple rows of sub-pixels, the sub-pixels include at least a pixel driving circuit, the pixel driving circuit includes at least one oxide transistor, and the first gate driving circuit is electrically connected to the control electrode of at least one oxide transistor in at least one row of sub-pixels, and is configured to provide a scanning signal to the at least one oxide transistor in the at least one row of sub-pixels.

[0031] In an exemplary embodiment, the plurality of transistors in the first gate driver include at least a low-level output transistor and a low-level output control transistor, wherein the low-level output transistor is configured to output a low-level signal to at least one oxide transistor in the at least one row of sub-pixels under the control of the low-level output control transistor;

[0032] The low-level output transistors in multiple first gate drive circuits of the same type are blocked by the blocking structure layer to the same extent; the low-level output control transistors in multiple first gate drive circuits of the same type are blocked by the blocking structure layer to the same extent.

[0033] In an exemplary embodiment, the shielding structure layer includes at least one of a first shielding structure and a second shielding structure;

[0034] There are multiple first shielding structures, and the multiple first shielding structures are respectively configured to shield the low-level output control transistors in at least one type of multiple first gate drive circuits; there are multiple second shielding structures, and the multiple second shielding structures are respectively configured to shield the low-level output transistors in at least one type of multiple first gate drive circuits.

[0035] In a third aspect, an embodiment of the present disclosure further provides a display device, comprising the display module described in any of the above embodiments.

[0036] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The accompanying drawings are intended to provide a further understanding of the technical solutions of the embodiments of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of each component in the drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0038] FIG1 is a schematic structural diagram of a display device;

[0039] FIG2 is a schematic diagram of a planar structure of a display substrate;

[0040] FIG3 is a schematic diagram of a cross-sectional structure of a display in a display substrate;

[0041] FIG4 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0042] FIG5 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0043] FIG6 is a schematic structural diagram of a display substrate provided by an exemplary embodiment of the present disclosure;

[0044] FIG7 is a schematic diagram of a cross-sectional structure at position A1-A1 in FIG6 ;

[0045] FIG8 a is a schematic structural diagram of a display substrate provided by an exemplary embodiment of the present disclosure;

[0046] FIG8b is a schematic diagram of a cross-sectional structure at position A2-A2 in FIG8a;

[0047] FIG9 is a schematic diagram of a cross-sectional structure at position A1-A1 in FIG6 ;

[0048] FIG10 is a schematic diagram of a cross-sectional structure at position A1-A1 in FIG6 ;

[0049] FIG11 is a schematic diagram of a cross-sectional structure at position A1-A1 in FIG6 ;

[0050] FIG12 is a schematic diagram of a cross-sectional structure at position A1-A1 in FIG6 ;

[0051] FIG13 is a schematic diagram of a cross-sectional structure at position A1-A1 in FIG6 ;

[0052] FIG14 is a schematic diagram of a cross-sectional structure at position A1-A1 in FIG6 ;

[0053] FIG15 is a schematic diagram of a cross-sectional structure at position A1-A1 in FIG6 ;

[0054] FIG16 is a schematic diagram of a cross-sectional structure at position A1-A1 in FIG6 ;

[0055] 17a to 17e are equivalent circuit diagrams of several first gate driving circuits provided by exemplary embodiments of the present disclosure;

[0056] FIG18 is a schematic diagram of a shielding structure layer provided by an exemplary embodiment of the present disclosure;

[0057] FIG19 is a schematic diagram of a cross-sectional structure at position A3-A3 in FIG6 ;

[0058] FIG20 a is a schematic structural diagram of a first gate driving circuit provided by an exemplary embodiment of the present disclosure;

[0059] FIG20 b is a schematic diagram showing a planar structure after forming an active layer in a first gate driving circuit according to an exemplary embodiment of the present disclosure;

[0060] FIG20c is a schematic diagram showing a planar structure after forming a first conductive layer in a first gate driving circuit according to an exemplary embodiment of the present disclosure;

[0061] FIG20 d is a schematic diagram showing a planar structure after forming a second conductive layer in a first gate driving circuit according to an exemplary embodiment of the present disclosure;

[0062] FIG20e is a schematic diagram showing a planar structure after forming a first via layer in a first gate driving circuit according to an exemplary embodiment of the present disclosure;

[0063] FIG20 f is a schematic diagram showing a planar structure after forming a third conductive layer in a first gate driving circuit according to an exemplary embodiment of the present disclosure;

[0064] FIG20g is a schematic diagram showing a planar structure after forming a second via layer in a first gate driving circuit according to an exemplary embodiment of the present disclosure;

[0065] FIG20h is a schematic diagram showing a planar structure after forming a fourth conductive layer in a first gate driving circuit according to an exemplary embodiment of the present disclosure;

[0066] FIG20i is a schematic planar structural diagram of a first gate driving circuit provided by an exemplary embodiment of the present disclosure;

[0067] FIG20j is a schematic diagram showing a planar structure after an active layer in a first gate driving circuit is formed on a shielding structure layer, provided by an exemplary embodiment of the present disclosure;

[0068] FIG21 is a characteristic curve diagram of a first transistor in a first gate driving circuit provided by an exemplary embodiment;

[0069] FIG22 a is a characteristic curve diagram of a first transistor in a first gate driving circuit provided by an exemplary embodiment;

[0070] FIG22 b is a graph showing a change in current of a first transistor in a first gate driving circuit as a function of temperature, provided by an exemplary embodiment;

[0071] FIG22 c is a characteristic curve diagram of the tenth transistor in the first gate driving circuit provided by an exemplary embodiment;

[0072] FIG22 d is a graph showing a change in current of the tenth transistor in the first gate driving circuit as a function of temperature, provided by an exemplary embodiment;

[0073] FIG. 23 shows a diagram of an edge structure of a display substrate.

[0074] FIG. 24 shows a display effect diagram of a display area. DETAILED DESCRIPTION

[0075] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a number of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. Unless there is a conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and known components. The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure. Other structures can refer to the general design

[0076] The scales of the figures in this disclosure are intended to serve as a reference for actual processes, but are not intended to be limiting. For example, the thickness and spacing of each film layer, and the width and spacing of each signal line, can be adjusted based on actual conditions. The figures described in this disclosure are merely schematic diagrams of the structures, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0077] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0078] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced depending on the circumstances.

[0079] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0080] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0081] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or the first electrode can be a source electrode and the second electrode can be a drain electrode. In cases where transistors with opposite polarities are used or the direction of current changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchangeable. Therefore, in this specification, "source electrode" and "drain electrode" can be interchangeable, and "source terminal" and "drain terminal" can be interchangeable. In the disclosed embodiments, the gate electrode can be referred to as the control electrode.

[0082] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0083] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0084] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0085] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0086] The term "about" in the embodiments of the present disclosure does not strictly define the limits and allows for numerical values ​​within the range of process and measurement errors.

[0087] FIG1 is a schematic diagram of the structure of a display device. A display substrate may include a timing controller, a data signal driver, a scan signal driver, a light emitting signal driver, and a pixel array. The timing controller is connected to the data signal driver, the scan signal driver, and the light emitting signal driver, respectively. The data signal driver is connected to a plurality of data signal lines (D1 to Dn), the scan signal driver is connected to a plurality of scan signal lines (S1 to Sm), and the light emitting signal driver is connected to a plurality of light emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light emitting device connected to the circuit unit. The circuit unit may include at least one scan signal line, at least one data signal line, at least one light emitting signal line, and a pixel driving circuit. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data signal driver to the data signal driver, may provide a clock signal, a scan start signal, etc. suitable for the specifications of the scan signal driver to the scan signal driver, and may provide a clock signal, an emission stop signal, etc. suitable for the specifications of the light emitting signal driver to the light emitting signal driver. The data signal driver can generate data voltages to be supplied to data signal lines D1, D2, D3, ..., and Dn using grayscale values ​​and control signals received from a timing controller. For example, the data signal driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a pixel row basis, where n can be a natural number. The scan signal driver can generate scan signals to be supplied to scan signal lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, and the like from the timing controller. For example, the scan signal driver can sequentially supply scan signals having on-level pulses to scan signal lines S1 to Sm. For example, the scan signal driver can be configured as a shift register and can sequentially transmit scan start signals provided in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. The emission signal driver can generate emission signals to be supplied to emission signal lines E1, E2, E3, ..., and Eo by receiving clock signals, emission stop signals, and the like from the timing controller. For example, the light emitting signal driver may sequentially provide emission signals having off-level pulses to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be configured in the form of a shift register and may generate emission signals in a manner such that emission stop signals provided in the form of off-level pulses are sequentially transmitted to the next stage circuit under the control of a clock signal. o may be a natural number.

[0088] Figure 2 is a schematic diagram of a planar structure of a display substrate. As shown in Figure 2, the display substrate may include a plurality of pixel units P arranged in a matrix. At least one of the plurality of pixel units P includes a first subpixel P1 that emits a first color light, a second subpixel P2 that emits a second color light, and a third subpixel P3 that emits a third color light. The first subpixel P1, the second subpixel P2, and the third subpixel P3 each include a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first subpixel P1, the second subpixel P2, and the third subpixel P3 are respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuits are configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting devices in the first subpixel P1, the second subpixel P2, and the third subpixel P3 are respectively connected to the pixel driving circuit of the subpixel. The light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the subpixel.

[0089] In an exemplary embodiment, a pixel unit P may include a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel. In an exemplary embodiment, the sub-pixels in the pixel unit may be rectangular, diamond-shaped, pentagonal, or hexagonal, and the three sub-pixels may be arranged horizontally, vertically, or in a triangular pattern, which is not limited in this disclosure.

[0090] Figure 3 is a schematic cross-sectional view of a display substrate, illustrating the structure of three sub-pixels of an OLED display substrate. As shown in Figure 3, in a plane perpendicular to the display substrate, the display substrate may include a drive circuit layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on the side of the drive circuit layer 102 facing away from the substrate 101, and an encapsulation layer 104 disposed on the side of the light-emitting structure layer 103 facing away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as spacers, etc., which are not limited in this disclosure.

[0091] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The driving circuit layer 102 of each sub-pixel may include multiple transistors and storage capacitors that constitute the pixel driving circuit. The light-emitting structure layer 103 may include an anode 301, an organic light-emitting layer 302, and a cathode 303. The anode 301 is connected to the drain electrode of the driving transistor 210 through a via, the organic light-emitting layer 302 is connected to the anode 301, and the cathode 303 is connected to the organic light-emitting layer 302. The organic light-emitting layer 302 emits light of a corresponding color under the drive of the anode 301 and the cathode 303. The encapsulation layer 104 may include a stacked first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403. The first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, and the second encapsulation layer 402 may be made of organic materials. The second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403 to ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0092] In an exemplary embodiment, the organic light-emitting layer 302 may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron block layer (EBL), an emitting layer (EML), a hole block layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the electron transport layers of all sub-pixels may be a common layer connected together, and the hole blocking layers of all sub-pixels may be a common layer connected together. The light-emitting layers of adjacent sub-pixels may have a small overlap or may be isolated, and the electron blocking layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0093] In an exemplary embodiment, the pixel driving circuit may have a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. FIG4 is a schematic diagram of an equivalent circuit of a pixel driving circuit. As shown in FIG4 , the pixel driving circuit may include seven transistors (a first transistor T1 to a seventh transistor T7) and a storage capacitor C. The pixel driving circuit may be connected to seven signal lines (a data signal line D, a first scan signal line S1, a second scan signal line S2, a light emitting signal line E, an initial signal line INIT, a first power line VDD, and a second power line VSS).

[0094] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the second electrode of the fifth transistor T5, respectively. The second node N2 is connected to the second electrode of the first transistor T1, the first electrode of the second transistor T2, the control electrode of the third transistor T3, and the second end of the storage capacitor C, respectively. The third node N3 is connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, respectively.

[0095] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first power line VDD, and a second end of the storage capacitor C is connected to the second node N2 , ie, the second end of the storage capacitor C is connected to the control electrode of the third transistor T3 .

[0096] The control electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the initialization signal line INIT, and the second electrode of the first transistor is connected to the second node N2. When an on-level scan signal is applied to the second scan signal line S2, the first transistor T1 transmits an initialization voltage to the control electrode of the third transistor T3, thereby initializing the charge amount of the control electrode of the third transistor T3.

[0097] The control electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. When the on-level scan signal is applied to the first scan signal line S1, the second transistor T2 connects the control electrode of the third transistor T3 to the second electrode.

[0098] The control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C. The first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called a driving transistor. The third transistor T3 determines the amount of driving current flowing between the first power line VDD and the second power line VSS based on the potential difference between the control electrode and the first electrode.

[0099] The control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be called a switching transistor, a scan transistor, etc. When an on-level scan signal is applied to the first scan signal line S1, the fourth transistor T4 inputs the data voltage of the data signal line D to the pixel driving circuit.

[0100] The control electrode of the fifth transistor T5 is connected to the light-emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the light-emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting device. The fifth transistor T5 and the sixth transistor T6 can be referred to as light-emitting transistors. When an on-level light-emitting signal is applied to the light-emitting signal line E, the fifth transistor T5 and the sixth transistor T6 form a drive current path between the first power line VDD and the second power line VSS, causing the light-emitting device to emit light.

[0101] The control electrode of the seventh transistor T7 is connected to the first scan signal line S1, the first electrode of the seventh transistor T7 is connected to the initialization signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting device. When the on-level scan signal is applied to the first scan signal line S1, the seventh transistor T7 transmits an initialization voltage to the first electrode of the light-emitting device to initialize or release the charge accumulated in the first electrode of the light-emitting device.

[0102] In an exemplary embodiment, the second electrode of the light-emitting device is connected to a second power line VSS. The signal on the second power line VSS is a low-level signal, while the signal on the first power line VDD is a continuously high-level signal. The first scan signal line S1 is a scan signal line in the pixel driving circuit of the current display row, and the second scan signal line S2 is a scan signal line in the pixel driving circuit of the previous display row. That is, for the nth display row, the first scan signal line S1 is S(n), and the second scan signal line S2 is S(n-1). The second scan signal line S2 of the current display row is the same as the first scan signal line S1 in the pixel driving circuit of the previous display row. This can reduce the number of signal lines on the display panel and achieve a narrow bezel on the display panel.

[0103] In an exemplary embodiment, the first scan signal line S1, the second scan signal line S2, the emission signal line E, and the initial signal line INIT extend in a horizontal direction, and the second power line VSS, the first power line VDD, and the data signal line D extend in a vertical direction.

[0104] In an exemplary embodiment, the light emitting device may be an organic light emitting diode (OLED) including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked.

[0105] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be a P-type transistor (as shown in FIG4 ), or may be an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include a P-type transistor and an N-type transistor. As shown in FIG5 , it is a schematic diagram of an equivalent circuit of a pixel driving circuit, in which the second transistor T2 is an N-type transistor (i.e., an oxide thin film transistor), the first transistor T1, the third transistor T3 to the eighth transistor T8 are P-type transistors (i.e., low-temperature polycrystalline silicon thin film transistors), the active layer of the low-temperature polycrystalline silicon thin film transistor adopts low-temperature polysilicon (Low Temperature Poly-Silicon, abbreviated as LTPS), and the active layer of the oxide thin film transistor adopts oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality. As shown in Figure 5, the pixel driving circuit may include 8 transistors (first transistor T1 to eighth transistor T8) and 1 storage capacitor C. The pixel driving circuit may be connected to 7 signal lines (data signal line D, first scan signal line S1, second scan signal line S2, light-emitting signal line E, initial signal line INIT, first power line VDD, and second power line VSS). Compared with Figure 4, the difference of Figure 5 is that: an eighth transistor T8, a third initial signal line INIT3, a third scan signal line S3 and a fourth scan signal line S4 are newly added, the third scan signal line S3 is connected to the control electrode of the second transistor T2, and the fourth scan signal line S4 is connected to the control electrode of the fourth transistor T4; the second transistor T2 is an N-type transistor, the first scan signal line S1 is also electrically connected to the control electrode of the eighth transistor T8, the first electrode of the eighth transistor T8 is connected to the third initial signal line INIT3, and the second electrode of the eighth transistor T8 is connected to the first node N; the first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the third node N3.

[0106] The display panel usually has a protective film layer (such as a protective layer SCF) on the backlight side (the side of the non-display surface) to improve the impact resistance of the display panel. The protective film layer SCF is usually composed of three film layers: a glue layer (which may include Embo glue), a buffer layer (which may include a foam layer), and a heat dissipation layer (which may include one or more layers of metal copper foil, graphite, etc.), which can play the role of buffering, heat conduction, and light shielding. The display panel includes a display area and a frame area located around the display area. The frame area is usually provided with a variety of gate drive circuits. The gate drive circuit usually adopts an array substrate row drive (Gate Driver on Array, abbreviated as GOA) circuit. Each GOA circuit is electrically connected to at least one row of sub-pixels in the display area. The transistors in the GOA circuit are greatly affected by light and temperature. When multiple GOA circuits of the same type are subjected to inconsistent light or temperature, the scanning signals output by multiple GOA circuits of the same type to the display area are often inconsistent. Since the alignment accuracy of the protective film layer SCF is not high, the protective film layer SCF is often offset, resulting in the gate drive circuit on one side of the display panel being covered by the protective film layer SCF and the gate drive circuit on the other side not being covered by the protective film layer SCF. There are multiple gate drive circuits of the same type, part of which is covered by the protective film layer SCF and the other part is not covered by the protective film layer SCF, resulting in inconsistent transistor characteristics in multiple GOA circuits of the same type, making the scan signals output by multiple GOA circuits of the same type covered by the protective film layer SCF and not covered by the protective film layer SCF inconsistent, making the brightness of multiple sub-pixel rows located in the display area that receive the scan signals output by this gate drive circuit uneven; in addition, in order to avoid the alignment mark, the protective film layer SCF is usually There is a certain distance between the edge of the film layer SCF and the edge of the display panel. Usually, an opening (SCF opening for short) is set in the protective film layer at the alignment mark position to avoid blocking the alignment mark. When the bonding accuracy of the protective film layer SCF is poor, one or more GOA circuits are often not covered by the protective film layer SCF only at the SCF opening position, and the same type of GOA circuits are covered by the protective film layer SCF at other positions, resulting in inconsistent output scanning signals of multiple GOA circuits of the same type covered and not covered by the protective layer. The sub-pixel rows in the display area corresponding to the GOA circuits not covered by the protective film layer SCF often have uneven brightness, such as mura defects (for example, horizontal bright stripes or horizontal dark stripes).

[0107] An exemplary embodiment of the present disclosure provides a display module, which may include a display substrate and a first structural layer. On a surface parallel to the display substrate, the display substrate may include a display area and a border area. The border area is located around the display area. The border area is provided with at least one type of first gate driving circuit, and there are multiple first gate driving circuits of the same type. The first gate driving circuit includes multiple transistors. In a direction perpendicular to the surface of the display substrate, the display substrate includes a light-emitting side and a backlight side. The first structural layer is arranged on the backlight side of the display substrate. The orthographic projection of the first structural layer on the display substrate covers at least part of the display area. At least part of the transistors in multiple first gate driving circuits of the same type are covered by the same range of the orthographic projection of the first structural layer on the display substrate.

[0108] The display module provided by the embodiment of the present disclosure includes a display substrate and a first structural layer. The first structural layer is located on the backlight side of the display substrate. At least some transistors in multiple first gate driving circuits of the same type located in the border area of ​​the display substrate have the same range covered by the orthographic projection of the first structural layer on the display substrate, which can overcome the technical problem of uneven brightness of the display module.

[0109] In an exemplary embodiment, the surface on which the display substrate is located may be a flat surface or a curved surface.

[0110] As shown in Figures 6 and 7, Figure 7 is a cross-sectional schematic diagram of the position A1-A1 in Figure 6. The display module provided by the embodiment of the present disclosure may include a display substrate 10 and a first structure layer 11. On a surface parallel to the display substrate 10, the display substrate 10 may include a display area AA and a frame area BB. The frame area BB is located around the display area AA. The frame area BB is provided with at least one type of first gate drive circuit GOA1. There are multiple first gate drive circuits GOA1 of the same type, and the first gate drive circuit GOA1 includes multiple transistors. In a direction Z perpendicular to the surface of the display substrate, the display substrate 10 may include a light-emitting side S1 and a backlight side S2. The first structure layer 11 is provided on the backlight side S2 of the display substrate 10. The orthographic projection of the first structure layer 11 on the display substrate 10 covers at least part of the display area AA. At least part of the transistors in the multiple first gate drive circuits GOA1 of the same type are covered by the same range of the orthographic projection of the first structure layer 11 on the display substrate 10.

[0111] In an exemplary embodiment, a plurality of first gate driving circuits GOA1 of the same type may be arranged along an extending direction of the border area BB.

[0112] In an exemplary embodiment, at least some transistors in multiple first gate drive circuits GOA1 of the same type are covered by the same range of the orthographic projection of the first structural layer 11 on the display substrate 10. The coverage range may be absolutely consistent, or the coverage range may be roughly consistent. For example, the coverage range may have a deviation of about 5%-15%.

[0113] In an exemplary embodiment, as shown in FIG6 , the display area AA may include multiple rows of sub-pixels Pxij. Each sub-pixel Pxij includes at least a pixel driver circuit, which includes at least one oxide transistor. A first gate driver circuit GOA1 is electrically connected to a control electrode of the at least one oxide transistor in at least one row of sub-pixels Pxij and is configured to provide a scan signal to the at least one oxide transistor in the at least one row of sub-pixels. In an exemplary embodiment, as shown in FIG6 , each row of sub-pixels may include multiple sub-pixels Pxij arranged sequentially along a row direction X, and the display area AA may include multiple rows of sub-pixels arranged along a column direction Y.

[0114] In an exemplary embodiment, each pixel driving circuit may include at least one oxide transistor. As shown in FIG5 , each pixel driving circuit may include an oxide transistor (i.e., a second transistor T2 serving as a compensation transistor). Then, the first gate driving circuit GOA1 may be of one type, configured to provide a scan signal to the second transistor T2 in FIG5 (provide a scan signal to the control electrode of the second transistor T2 via a third scan signal line S3). In a case where each pixel driving circuit includes multiple oxide transistors, the control electrodes of multiple oxide transistors in the same pixel driving circuit may be provided with scan signals through one type of first gate driving circuit (in this case, the type of the first gate driving circuit GOA1 may be set to one type), or the control electrodes of multiple oxide transistors in the same pixel driving circuit may be provided with scan signals through multiple types of first gate driving circuits (in this case, the type of the first gate driving circuit GOA1 may be set to multiple types, and each type of first gate driving circuit provides a scan signal to the corresponding oxide transistor).

[0115] In an exemplary embodiment, as shown in FIG5 , the second transistor T2 in the pixel driving circuit is an oxidation transistor, which can control the leakage current of the second node N2 (try to avoid the leakage current of the second node N2). Since the control electrode of the oxide transistor is greatly affected by the change of the scanning signal output by the GOA circuit (the oxide transistor is relatively sensitive to the change of the scanning signal output by the GOA circuit, and the low-temperature polysilicon thin-film transistor is relatively insensitive to the change of the scanning signal output by the GOA circuit), it is necessary to make the scanning signal output by the GOA circuit that provides the scanning signal to the oxide transistors in multiple rows of sub-images as consistent as possible, so as to improve the display uniformity of the display substrate.

[0116] In an exemplary embodiment, the plurality of transistors in the first gate driving circuit GOA1 include at least a low-level output transistor and a low-level output control transistor, the low-level output transistor being configured to output a low-level signal to at least one oxide transistor in at least one row of sub-pixels under the control of the low-level output control transistor;

[0117] The low-level output transistors in multiple first gate drive circuits GOA1 of the same type have the same range covered by the orthographic projection of the first structural layer 11 on the display substrate; the low-level output control transistors in multiple first gate drive circuits GOA1 of the same type have the same range covered by the orthographic projection of the first structural layer 11 on the display substrate.

[0118] In an exemplary embodiment, the range covered by the first structural layer 11 of multiple first gate driving circuits GOA1 of the same type is consistent, so that the multiple first gate driving circuits GOA1 of the same type are basically consistent in the influence of factors such as light and temperature, and thus the scanning signals provided by the multiple first gate driving circuits GOA1 of the same type to the multiple sub-pixel rows in the display area AA are as consistent as possible, thereby improving the display uniformity of the display substrate and avoiding the occurrence of horizontal bright stripes or horizontal dark stripes due to inconsistent output signals of multiple first gate driving circuits GOA1 of the same type.

[0119] In an exemplary embodiment, as shown in FIG7 , the first structural layer 11 blocks the multiple first gate driving circuits GOA1 of the same type in a consistent manner, so that the output signals of the multiple first gate region circuits GOA1 of the same type will not have too much difference due to factors such as temperature and light, thereby making the scanning signals provided by the multiple first gate driving circuits GOA1 of the same type to the multiple rows of sub-pixels Pxij in the display area AA as consistent as possible, which can largely overcome the problem of horizontal bright stripes or horizontal dark stripes in the display area AA.

[0120] In an exemplary embodiment, as shown in FIG7 , there is no overlapping area between the orthographic projection of the first structural layer 11 on the display substrate 10 and the multiple first gate driving circuits GOA1 of at least one type, so that the multiple first gate driving circuits GOA1 of the same type are basically consistent in the effects of light and temperature, and the signals output by the multiple first gate driving circuits GOA1 of the same type will not have too much difference due to the influence of light and temperature.

[0121] In an exemplary embodiment, as shown in FIG7 , the orthographic projection of the edge of the first structure layer 11 on the display substrate 10 is located in the first area BB1. On a plane parallel to the display substrate 10, the first area BB1 may be located between the edge of at least one type of multiple first gate driving circuits GOA1 close to the display area AA and the edge of the display area AA close to the border area BB. The orthographic projection of the first structure layer 11 on the display substrate 10 covers the display area AA.

[0122] In an exemplary embodiment, as shown in Figures 8a and 8b, Figure 8b is a cross-sectional schematic diagram taken at position A2-A2 in Figure 8a. The orthographic projection of the first structure layer 11 on the display substrate does not overlap with the border area BB, and the orthographic projection of the first structure layer 11 on the display substrate 10 is located within or overlaps with the display area AA, so that the first structure layer 11 does not block multiple first gate driver circuits GOA1 of the same type. For example, the orthographic projection of an edge of the first structure layer 11 on the display substrate may be located near an edge of the display area AA (for example, the orthographic projection of an edge of the first structure layer 11 on the display substrate may overlap with an edge of the display area AA), or the orthographic projection of the first structure layer 11 on the display substrate may be located within the display area AA.

[0123] In an exemplary embodiment, as shown in Figures 7 to 8b , on a plane parallel to the display substrate, along the direction from the display area AA to the border area BB, the distance D1 between the edge of the first structure layer 11 and the edge of the display substrate is 700 to 1200 microns, which is greater than the distance D2 between the edge of the at least one type of multiple first gate driver circuits GOA1 on the side closest to the display area AA and the edge of the display substrate (such that the first structure layer 11 does not block the at least one type of multiple first gate driver circuits GOA1). The distance D2 between the edge of the at least one type of multiple first gate driver circuits GOA1 on the side closest to the display area AA and the edge of the display substrate can generally be set to 500 to 800 microns. For example, the distance D2 between the edge of the at least one type of multiple first gate driver circuits GOA1 on the side closest to the display area AA and the edge of the display substrate can be 622 microns.

[0124] In an exemplary embodiment, as shown in FIG7 , on a surface parallel to the display substrate, along the direction from the display area AA to the border area BB, the distance D1 between the edge of the protective structure 110 and the edge of the display substrate can be 700 μm to 1000 μm. For example, the distance D1 between the edge of the first structure layer 11 and the edge of the display substrate 10 can be 872 μm. The bonding accuracy of the first structure layer 11 is ±230 μm, and the absolute value of the bonding accuracy is less than the difference between D2 and D1 (approximately 250 μm). The first structure layer 11 will not be offset, resulting in a situation where part of multiple first gate drive circuits GOA1 of the same type are blocked by the first structure layer 11 and the other part are not blocked by the first structure layer 11.

[0125] In an exemplary embodiment, as shown in Figures 8a and 8b, on a surface parallel to the display substrate, along the direction from the display area AA to the border area BB, the distance D1 between the edge of the first structure layer 11 and the edge of the display substrate is 1000 microns to 1200 microns. For example, the distance D1 between the edge of the first structure layer 11 and the edge of the display substrate can be 1150 microns. The fitting accuracy of the first structure layer 11 is ±250 microns, and the absolute value of the fitting accuracy is less than the difference between D2 and D1 (about 528 microns). The first structure layer 11 will not be offset, resulting in a situation where part of the multiple first gate drive circuits GOA1 of the same type are blocked by the first structure layer 11 and the other part are not blocked by the first structure layer 11.

[0126] In an exemplary embodiment, as shown in Figures 9 and 10, which are two schematic cross-sectional views taken at position A-A1 in Figure 6, the orthographic projection of the first structure layer 11 on the display substrate covers the display area AA and at least one type of multiple first gate driver circuits GOA1. That is, the at least one type of multiple first gate driver circuits GOA1 are located within the range of the orthographic projection of the first structure layer 11 on the display substrate, so that the first structure layer 11 shields all of the at least one type of multiple first gate driver circuits GOA1. The signals output by the at least one type of multiple first gate driver circuits GOA1 are substantially consistent, thus overcoming the defect of inconsistent output signals from multiple first gate driver circuits GOA1 of the same type due to misalignment of the first structure layer 11. This also largely overcomes the defect of horizontal stripes caused by inconsistent shielding of the multiple first gate driver circuits GOA1 by the first structure layer 11.

[0127] In an exemplary embodiment, as shown in Figure 9, the border area BB is further provided with a plurality of second gate driving circuits GOA2 of at least one type, and the number of second gate driving circuits GOA2 of the same type is multiple. On a surface parallel to the display substrate, the plurality of second gate driving circuits GOA2 of the same type are arranged along the extension direction of the border area BB, and along the direction from the display area AA to the border area BB, the plurality of second gate driving circuits GOA2 of at least one type are located between the plurality of first gate driving circuits GOA1 of at least one type and the display area AA.

[0128] In an exemplary embodiment, the pixel driving circuit may include at least one low-temperature polysilicon transistor, and each second gate driving circuit GOA2 is configured to provide a scan signal to at least part of the low-temperature polysilicon transistors of at least one row of sub-pixel circuits located in the display area AA. As shown in Figure 5, the first transistor T1 and the third transistor T3 to the eighth transistor T8 are all low-temperature polysilicon transistors, wherein the first transistor T1 can receive a scan signal from one type of the second gate driving circuit GOA2 through the second scan signal line S2, the fifth transistor T5 and the sixth transistor T6 can receive a light-emitting control signal from the same type of second gate driving circuit GOA2 (the light-emitting control signal can be received through the light-emitting signal line E), the seventh transistor T7 and the eighth transistor T8 can receive a scan signal from the same type of second gate driving circuit GOA2 (the scan signal can be received through the first scan signal line S1), and the fourth transistor T4 can receive a scan signal from one type of the second gate driving circuit GOA2 through the fourth scan signal line S4. That is, the types of the second gate drive circuit GOA2 that provides signals to the control electrodes of the low-temperature polysilicon transistors in the pixel drive circuit shown in Figure 5 can include four types, two types of second gate drive circuits GOA2 respectively provide scan signals to the control electrodes of the first transistor T1 and the fourth transistor T4, one type of second gate drive circuit GOA2 respectively provides light-emitting control signals to the fifth transistor T5 and the sixth transistor T6, and one type of second gate drive circuit GOA2 provides scan signals to the control electrodes of the seventh transistor T7 and the eighth transistor T8, but the embodiments of the present disclosure are not limited to this. For example, the control electrodes of the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 can be provided with scan signals by the same type of second gate drive circuit GOA2.

[0129] In an exemplary embodiment, as shown in FIG9 , on a surface parallel to the display substrate, in the direction from the display area AA to the border area BB, the distance D1 between the edge of the first structure layer 11 and the edge of the display substrate 10 can be 100 μm to 350 μm, which is smaller than the distance D3 between the edge of at least one type of multiple first gate drive circuits GOA1 away from the display area AA and the edge of the display substrate 10, so that the first structure layer 11 blocks at least one type of multiple first gate drive circuits GOA1. For example, the distance D1 between the edge of the first structure layer 11 and the edge of the display substrate can be 100 microns to 250 microns, and the distance D3 between the edge of at least one type of multiple first gate drive circuits GOA1 away from the side of the display area AA and the edge of the display substrate 10 can be 300 microns to 500 microns (for example, D1 can be set to 250 microns, D3 can be set to 482 microns, the fitting accuracy of the first structure layer 11 is ±230 microns, and the absolute value of the fitting accuracy is less than the difference between D3 and D1. The first structure layer 11 will not be offset, resulting in a situation where part of the multiple first gate drive circuits GOA1 of the same type are blocked by the first structure layer 11 and the other part are not blocked by the first structure layer 11).

[0130] In an exemplary embodiment, as shown in Figure 10, the border area BB is further provided with at least one type of second gate driving circuit GOA2, and the number of the same type of second gate driving circuits GOA2 is multiple. On a surface parallel to the display substrate, the multiple second gate driving circuits GOA2 of the same type are arranged along the extension direction of the border area BB, and along the direction from the display area AA to the border area BB, the multiple second gate driving circuits GOA2 of at least one type are located on the side of the multiple first driving circuits GOA1 of at least one type away from the display area AA.

[0131] In an exemplary embodiment, as shown in FIG10 , on a plane parallel to the display substrate, in the direction from the display area AA to the border area BB, the distance D1 between the edge of the first structure layer 11 and the edge of the display substrate is 500 to 700 microns, which is less than the distance D3 between the edge of at least one type of first gate driver circuit GOA1 on the side away from the display area AA and the edge of the display substrate 10. This allows the first structure layer 11 to block all of the at least one type of first gate driver circuit GOA1. For example, the distance D1 between the edge of the first structure layer 11 and the edge of the display substrate is 600 microns, and the distance D3 between the edge of at least one type of first gate driver circuit GOA1 on the side away from the display area AA and the edge of the display substrate 10 is 622 microns.

[0132] In an exemplary embodiment, as shown in Figures 11 to 14 , which are schematic cross-sectional views of the structure at position A1-A1 in Figure 6 , the first structural layer 11 may include a first connection structural layer 111, a buffer structural layer 112, and a heat dissipation structural layer 113, sequentially disposed on the backlight side S2. As shown in Figures 12 and 13 , the orthographic projection of the heat dissipation structural layer 113 on the display substrate 10 does not overlap with the plurality of first gate drive circuits GOA1 of at least one type. The heat dissipation structural layer 113 may be made of metal (e.g., copper) and may dissipate heat (facilitating lowering the temperature of the display substrate 10). In Figures 12 and 13 , the heat dissipation structural layer 113 does not block the plurality of first gate drive circuits GOA1 of at least one type, ensuring that the heat dissipation structural layer 113 uniformly affects the plurality of first gate drive circuits GOA1 of at least one type, thereby preventing inconsistent output signals from the plurality of first gate drive circuits GOA1 of the same type due to inconsistent coverage of the heat dissipation structural layer 113. In an exemplary embodiment, as shown in FIG12 , the orthographic projection of the edge of the heat dissipation structure layer 113 on the display substrate may be located between the edge of the display area AA on the side close to the frame area BB and the edge of the at least one type of first gate driving circuit GOA1 on the side close to the display area AA, that is, the orthographic projection of the edge of the heat dissipation structure layer 113 on the display substrate 10 may cover the display area AA, and the orthographic projection of the edge of the heat dissipation structure layer 113 on the display substrate 10 does not overlap with the at least one type of first gate driving circuit GOA1; or, as shown in FIG13 , the orthographic projection of the heat dissipation structure layer 113 on the display substrate 10 may be located within the range of the display area AA; as shown in FIG14 , the orthographic projection of the edge of the heat dissipation structure layer 113 on the display substrate may be located within the range of at least one type of multiple second gate driving circuits GOA2, that is, the orthographic projection of the edge of the heat dissipation structure layer 113 on the display substrate 10 may cover the display area AA and at least part of the second gate driving circuit GOA2, and the orthographic projection of the edge of the heat dissipation structure layer 113 on the display substrate 10 does not overlap with the at least one type of first gate driving circuit GOA1.

[0133] In an exemplary embodiment, as shown in Figure 11, the orthographic projection of the heat dissipation structure layer 113 on the display substrate 10 can cover multiple first gate driving circuits GOA1 of at least one type, that is, the heat dissipation structure layer 113 can block multiple first gate driving circuits GOA1 of at least one type, so that the heat dissipation structure layer 113 has a consistent effect on multiple first gate driving circuits GOA1 of the same type, thereby avoiding inconsistent output signals of multiple first gate area circuits GOA1 of the same type due to inconsistent blocking of multiple first gate driving circuits GOA1 of the same type by the heat dissipation structure layer 113, thereby avoiding the defect of uneven brightness of the display area AA.

[0134] In an exemplary embodiment, as shown in Figures 11 and 12, the orthographic projections of the first connection structure layer 111 and the buffer structure layer 112 on the display substrate 10 can cover multiple first gate driver circuits GOA1 of at least one type, so that multiple first gate driver circuits GOA1 of the same type are uniformly affected by the first connection structure layer 111 and the buffer structure layer 112. As shown in Figures 13 and 14, the orthographic projections of the first connection structure layer 111 and the buffer structure layer 112 on the display substrate 10 uniformly cover multiple first gate driver circuits GOA1 of at least one type.

[0135] In an exemplary embodiment, as shown in Figures 11 to 14, the first structure layer 11 can serve as a protective film layer (SCF), the first connection structure layer 111 can be a glue layer in the protective film layer (SCF) (can include Embo glue), the buffer structure layer 112 can be a buffer layer in the protective film layer (SCF) (can include a foam layer), and the heat dissipation structure layer 113 can be a heat dissipation layer in the protective film layer (SCF) (can include one or more layers of metal copper foil, graphite, etc.). In the direction perpendicular to the surface of the display substrate 10, the size (i.e., thickness) of the first connection structure layer 111 is 0.01 microns to 0.05 microns (for example, it can be 0.03 microns), the size (i.e., thickness) of the buffer structure layer 112 is 0.05 microns to 0.11 microns (for example, it can be 0.08 microns), and the size (i.e., thickness) of the heat dissipation structure layer 113 is 0.03 microns to 0.07 microns (for example, it can be 0.05 microns).

[0136] In an exemplary embodiment, as shown in Figures 15 to 17a, Figures 15 and 16 are schematic diagrams of two cross-sectional structures at the A1-A1 position in Figure 1, and Figure 17a is an equivalent circuit schematic diagram of a first gate drive circuit GOA1. The first gate drive circuit GOA1 may include multiple transistors, and the orthographic projection of the first structure layer 11 on the display substrate 10 may cover at least some of the transistors in multiple first gate drive circuits GOA1 of the same type. At least some of the transistors (for example, low-level output transistors and low-level output control transistors) in different first drive circuits GOA1 of the same type are covered by the orthographic projection of the first structure layer 11 on the display substrate in a consistent manner, so that at least some of the transistors (low-level output transistors and low-level output control transistors) in multiple first gate drive circuits GOA1 of the same type will not be inconsistent due to the inconsistent blocking range of the first structure layer 11, resulting in inconsistent scan signals output by multiple first gate drive circuits of the same type.

[0137] In an exemplary embodiment, an orthographic projection of the first structure layer 11 on the display substrate covers at least at least one of the low-level output transistors and the low-level output control transistors in the plurality of first gate driving circuits GOA1 of at least one type. For example, the orthographic projection of the first structure layer 11 on the display substrate covers at least the low-level output transistors in at least one type of multiple first gate drive circuits GOA1, so that the low-level output transistors in at least one type of multiple first gate drive circuits GOA1 are all blocked by the first structure layer 11 (the low-level output control transistors in at least one type of multiple first gate drive circuits GOA1 are not blocked by the first structure layer 11); or, the orthographic projection of the first structure layer 11 on the display substrate covers at least the low-level output control transistors in at least one type of multiple first gate drive circuits GOA1, so that the low-level output control transistors in at least one type of multiple first gate drive circuits GOA1 are all blocked by the first structure layer 11 (the low-level output transistors in at least one type of multiple first gate drive circuits GOA1 are not blocked by the first structure layer 11); or, the orthographic projection of the first structure layer 11 on the display substrate covers at least the low-level output transistors and low-level output control transistors in at least one type of multiple first gate drive circuits GOA1, so that the low-level output transistors and low-level output control transistors in at least one type of multiple first gate drive circuits GOA1 are all blocked by the first structure layer 11.

[0138] In an exemplary embodiment, as shown in FIG. 17a to FIG. 17e , which are equivalent circuit schematics of several first gate drive circuits GOA1, the multiple transistors may include a first transistor T1 (which may serve as the low-level output control transistor) and a tenth transistor T10 (which may serve as the low-level output transistor). The orthographic projection of the first structure layer 11 on the display substrate covers at least one of the first transistor T1 and the tenth transistor T10 in at least one type of multiple first gate drive circuits GOA1. For example, the orthographic projection of the first structure layer 11 on the display substrate 10 covers at least the first transistor T1 in at least one type of multiple first gate drive circuits GOA1, so that the first transistors T1 in at least one type of multiple first gate drive circuits GOA1 are all blocked by the first structure layer 11 (the tenth transistor T10 in at least one type of multiple first gate drive circuits GOA1 is not blocked by the first structure layer 11); or, the orthographic projection of the first structure layer 11 on the display substrate covers at least the tenth transistor T10 in at least one type of multiple first gate drive circuits GOA1, so that The tenth transistor T10 in the multiple first gate drive circuits GOA1 of at least one type is blocked by the first structural layer 11 (the first transistor T1 in the multiple first gate drive circuits GOA1 of at least one type is not blocked by the first structural layer 11); or, the orthographic projection of the first structural layer 11 on the display substrate covers at least the first transistor T1 and the tenth transistor T10 in the multiple first gate drive circuits GOA1 of at least one type, so that the first transistor T1 and the tenth transistor T10 in the multiple first gate drive circuits GOA1 of at least one type are blocked by the first structural layer 11.

[0139] In an exemplary embodiment, as shown in Figures 17a to 17e, the first gate drive circuit GOA1 includes a plurality of transistors, and the low-level output control transistor (the first transistor T1 in Figures 17a to 17e) and the low-level output transistor (the tenth transistor T10 in Figures 17a to 17e) have a greater impact on the output signal of the output terminal OUT of the first gate drive circuit GOA1. The low-level output control transistors and the low-level output transistors in multiple first gate drive circuits GOA1 of the same type are blocked by the first structural layer 11 to an inconsistent range, and the display area AA will produce obvious horizontal stripes or uneven brightness during operation. Therefore, the first structural layer 11 is configured to have a consistent blocking range for the low-level output control transistors and the low-level output transistors in multiple first gate drive circuits GOA1 of the same type, which can largely overcome the defect of horizontal stripes or uneven brightness in the display area AA during operation.

[0140] In Figures 17a and 17b, the control electrode of the thirteenth transistor T13 is electrically connected to the power supply VEH. The power supply VEH is initially low, stabilizing the floating state of the output terminal OUT of the first gate drive circuit GOA1 to a high level before setting it high. This can make the signal at the output terminal OUT more stable and prevent the first frame from flickering. The fourteenth transistor T14 to the sixteenth transistor T16 in Figure 17a can reduce the disturbance of the output terminal OUT, eliminate the output waveform step signal of the output terminal OUT, and improve the stability of the output signal. In the embodiment of the present disclosure, by aligning the shielding ranges of the first transistor T1 and the tenth transistor T10 in multiple first gate drive circuits GOA1, the signals output from the output terminals OUT of the multiple first gate drive circuits GOA1 are kept consistent, thereby improving display uniformity and preventing horizontal stripe defects in the display area AA. In Figures 17a to 17e, the first transistor T1 mainly controls the potential of the seventh node N7 (that is, the potential of the control electrode of the tenth transistor T10), and the tenth transistor T10 mainly outputs a low-level VGL signal on the control line of the seventh node N7.

[0141] In an exemplary embodiment, as shown in Figures 17a to 17e, the control electrode of the first transistor T1 (low-level output control transistor) can be electrically connected to the clock signal terminal CK, the first electrode of the first transistor T1 can be electrically connected to the input signal terminal STV, and the second electrode of the first transistor T1 can be electrically connected to the first node N1 (the control electrode of the twelfth transistor T2 is electrically connected to the low-level signal terminal VGL and is in a normally-on state, so the potential of the seventh node N7 is substantially consistent with the potential of the first node N1, and therefore, the first transistor T1 can control the potential of the seventh node N7); the control electrode of the tenth transistor T10 (low-level output transistor) can be electrically connected to the seventh node N7, the first electrode of the tenth transistor T10 can be electrically connected to the low-level signal terminal VGL, and the second electrode of the tenth transistor T10 can be electrically connected to the output terminal OUT, and under the control of the seventh node N7, the signal of the low-level signal terminal VGL is transmitted to the output terminal OUT.

[0142] In an exemplary embodiment, as shown in FIG15 and FIG16 , on a surface parallel to the display substrate, along a direction from the display area AA to the border area BB, the low-level output control transistor is located on a side of the low-level output transistor away from the display area AA, a length of at least one type of first gate driver circuit GOA1 is 120 micrometers to 150 micrometers, the low-level output control transistor and the low-level output transistor are located on both sides of a midline of the first gate driver circuit GOA1 along an extending direction of the border area BB, and a distance between the low-level output control transistor and the low-level output transistor may be 40 micrometers to 50 micrometers;

[0143] In a structure in which the orthographic projection of the first structure layer 11 on the display substrate 10 covers at least the low-level output transistors and low-level output control transistors in at least one type of multiple first gate driver circuits GOA1, the orthographic projection of the first structure layer 11 on the display substrate 10 covers a length of 100 to 150 microns over the at least one type of first gate driver circuit GOA1 along the direction from the display area AA to the border area BB. The orthographic projection of the first structure layer 11 on the display substrate can cover 70% to 100% of the length of the first gate driver circuit GOA1, so that the first structure layer 11 can shield both the low-level output transistors and the low-level output control transistors. For example, the length of at least one type of first gate driver circuit GOA1 along the direction from the display area AA to the border area BB can be 138 microns, and the orthographic projection of the first structure layer 11 on the display substrate 10 covers a length of 100 microns over the first gate driver circuit GOA1.

[0144] In the structure in which the orthographic projection of the first structure layer 11 on the display substrate covers at least the low-level output transistors in at least one type of multiple first gate drive circuits GOA1, the length dimension of the orthographic projection of the first structure layer 11 on the display substrate covering at least one type of first gate drive circuit GOA1 along the direction from the display area AA to the border area BB is 40 microns to 95 microns; for example, the length dimension of at least one type of first gate drive circuit GOA1 along the direction from the display area AA to the border area BB can be 138 microns, and the length dimension of the orthographic projection of the first structure layer 11 on the display substrate 10 covering the first gate drive circuit GOA1 is 50 microns, so that the first structure layer 11 blocks the low-level output transistors in at least one type of multiple first gate drive circuits GOA1, and does not block the low-level output control transistors in at least one type of multiple first gate drive circuits GOA1.

[0145] In an exemplary embodiment, as shown in FIG15 and FIG16 , the border area BB may further be provided with a plurality of second gate driving circuits GOA2 of at least one type. The plurality of second gate driving circuits GOA2 of the same type are arranged along the extending direction of the border area BB on a surface parallel to the display substrate.

[0146] Along the direction from the display area AA to the border area BB, at least one type of multiple second driving circuits GOA2 can be located on the side of at least one type of multiple first driving circuits GOA1 away from the display area AA (as shown in Figure 16), or at least one type of multiple second gate driving circuits GOA2 are located between at least one type of multiple first gate driving circuits GOA1 and the display area AA (as shown in Figure 15).

[0147] In an exemplary embodiment, on a surface parallel to the display substrate, different types of first gate drive circuits GOA1 can be arranged along the direction from the display area AA to the border area BB, different types of second gate drive circuits GOA2 can be arranged along the direction from the display area AA to the border area BB, and the first gate drive circuit GOA1 and the second gate drive circuit GOA2 can be arranged along the direction from the display area AA to the border area BB.

[0148] In an exemplary embodiment, as shown in FIG18 , the display substrate 10 may further include a shielding structure layer 12. In a direction Z perpendicular to the surface of the display substrate, the shielding structure layer 12 is located on a side of the first gate driving circuit GOA1 away from the light-emitting side S1. The shielding structure layer 12 may include at least one of a first shielding structure 121 and a second shielding structure 122.

[0149] There are multiple first shielding structures 121, and the multiple first shielding structures 121 are respectively configured to shield at least one type of low-level output control transistors in multiple first gate drive circuits GOA1 (the first transistor T1 in Figure 17 can be used as a low-level output control transistor); there are multiple second shielding structures 122, and the multiple second shielding structures 122 are respectively configured to shield at least one type of low-level output transistors in multiple first gate drive circuits GOA1 (the tenth transistor T10 in Figure 17 can be used as a low-level output control transistor). The low-level output control transistors in different first gate drive circuits GOA1 of the same type are blocked by the first blocking structure 121 in a consistent manner, so that the characteristics of the low-level output control transistors in multiple first gate drive circuits GOA1 are kept as consistent as possible, avoiding the appearance of horizontal stripes in the display area AA due to inconsistent characteristics of the low-level output control transistors in multiple first gate drive circuits; the low-level output transistors in different first gate drive circuits GOA1 of the same type are blocked by the second blocking structure 122 in a consistent manner, so that the characteristics of the low-level output transistors in multiple first gate drive circuits GOA1 are kept as consistent as possible, avoiding the appearance of horizontal stripes in the display area AA due to inconsistent characteristics of the low-level output transistors in multiple first gate drive circuits GOA1.

[0150] In an exemplary embodiment, the display substrate may further include a base, and in a direction Z perpendicular to the surface of the display substrate, the blocking structure layer 12 may be located between the base and the first gate drive circuit GOA1, wherein the orthographic projection of the first blocking structure 121 on the base covers the orthographic projection of the corresponding low-level output control transistor on the base, and the orthographic projection of the second blocking structure 122 on the base covers the orthographic projection of the corresponding low-level output transistor on the base.

[0151] In an exemplary embodiment, as shown in FIG18 , the shielding structure layer 12 may further include a third shielding structure 123, the orthographic projection of which on the substrate covers the third transistor T3 in the pixel driver circuit (the third transistor T3 in FIG5 ). On a plane parallel to the display substrate, the first shielding structure 121 and the second shielding structure 122 are located in the border area BB, and the third shielding structure 123 is located in the display area AA. In the disclosed embodiment, the shielding structure located in the border area BB can be formed in the same process as the shielding structure located in the display area AA. Without increasing the process flow, providing the shielding structure in the border area BB can resolve the problem of uneven brightness in the display area caused by inconsistent transistor characteristics in the first gate driver circuit GOA1.

[0152] In an exemplary embodiment, as shown in FIG18 , the shielding structure layer 12 may further include a plurality of first connection structures L1, a plurality of second connection structures L2, a plurality of third connection structures L3, and a plurality of fourth connection structures L4, wherein the plurality of first connection structures L1 and the plurality of third connection structures L3 extend along the first direction X and are arranged along the second direction Y, the plurality of second connection structures L2 and the plurality of fourth connection structures L4 are arranged along the first direction X and extend along the second direction Y, and at least part of the first connection structures L1 is configured to connect two adjacent second connection structures L2, the first shielding structure 121, and the second shielding structure 122. 2 are connected as one, at least part of the first connection structure L1 is configured to connect two adjacent second connection structures L2 as one, at least part of the third connection structure L3 is configured to connect two adjacent third shielding structures 123 as one, at least part of the third connection structure L3 is configured to connect the third shielding structure 123 in the display area AA close to the frame area BB and the second connection structure L2 in the frame area BB close to the display area AA as one, the first shielding structure 121, the second shielding structure 122 and the third shielding structure 123 are connected to each other as an integrated structure through the first connection structure L1 to the fourth connection structure L4.

[0153] In an exemplary embodiment, the first blocking structure layer 12 can be electrically connected to the first power supply VDD, so that the third transistor T3 in the pixel driving circuit generates a negative bias (i.e., the threshold voltage of the third transistor T3 is negatively biased), or the first blocking structure layer 12 can be electrically connected to the second power supply VSS, so that the third transistor T3 in the pixel driving circuit generates a positive bias (i.e., the threshold voltage of the third transistor T3 is positively biased).

[0154] In an exemplary embodiment, as shown in FIG19, a cross-sectional structural diagram of the position A3-A3 in FIG6 is shown. As shown in FIG3, in the direction Z perpendicular to the surface where the display substrate 10 is located, the display substrate 10 may include a base 101, a driving circuit layer 102 (which may include a pixel driving circuit located in the display area AA, a first gate driving circuit GOA1 located in the frame area, and a second gate driving circuit GOA2), a light-emitting structure layer 103, and an encapsulation layer 104; as shown in FIG19, in the direction Z perpendicular to the surface where the display substrate 10 is located, the display module may include a first structure layer 11, a second structure layer 13 (which may be a back film layer of the display module), a second connection structure layer 14, a display The display module comprises a substrate 10, a third connecting structure layer 15, and a third structure layer 16, wherein the first structure layer 11 can be arranged on the side of the second structure layer 13 away from the display substrate 10 through the first connecting structure layer 111, the second structure layer 13 is arranged on the backlight side of the display substrate 10 through the second connecting structure layer 14, and the third structure layer 16 is arranged on the light-emitting side of the display substrate 10 through the third connecting structure layer 15 (which can be an optical adhesive layer). The second structure layer 13 can be the backplane layer of the display module, and the third structure layer 16 can be the cover layer of the display module, and the cover layer can be a transparent structure or a light-transmitting structure.

[0155] In an exemplary embodiment, as shown in FIG19 , on a surface parallel to the display base 10, the diameter of the circular display area AA may be 20 to 40 mm (for example, 32.1912 mm), the diameter of the circular first structure layer 11 may be 20 to 40 mm (for example, 33.29 mm), and the diameter of the circular display substrate 10 may be 25 to 45 mm (for example, 34.4912 mm). In the direction from the display area AA to the frame area BB, the distance D1 from the first structure layer 11 to the edge of the display substrate 10 may be 500 to 700 μm (for example, D1 may be 600 μm).

[0156] In an exemplary embodiment, as shown in Figures 6 and 19, a plurality of gate drive circuits GOA may be arranged on both sides of a midline of the display substrate 10 extending along the second direction Y, wherein one side is provided with a first gate drive circuit GOA1 and at least one type of second gate drive circuit GOA2 (such as GOA21), and a first area BB1 is provided between an edge of the display area AA and an edge of the gate drive circuit GOA close to the display area AA, and a third area BB3 is provided between an edge of the gate drive circuit GOA away from the display area AA and an edge of the display substrate 10, and the sizes of all gate drive circuits GOA located in the border area BB may be The size of the gate drive circuits GOA in the border area BB may be 0.2 mm to 0.4 mm (for example, 0.328 mm); at least one type of second gate drive circuit GOA2 (for example, GOA22, GOA23, GOA24) is provided on the other side, and a second area BB2 is provided between the edge of the display area AA and the edge of the gate drive circuit GOA close to the display area AA, and a fourth area BB4 is provided between the edge of the gate drive circuit GOA away from the display area AA and the edge of the display substrate 10. The size of all gate drive circuits GOA located in the border area BB may be 0.2 mm to 0.4 mm (for example, 0.372 mm). On a surface parallel to the display base 10, along the direction from the display area AA to the frame area BB, the size of the first area BB1 can be 0.2 mm to 0.5 mm (for example, 0.34 mm), the size of the second area BB2 can be 0.1 mm to 0.4 mm (for example, 0.296 mm), the size of the third area BB3 and the fourth area BB4 can be 0.3 mm to 0.6 mm (for example, 0.482 mm), and the size of the first gate drive circuit GOA1 can be 0.1 mm to 0.3 mm (for example, 0. For example, it can be 0.14 mm), the size of the second gate drive circuit GOA21 can be 0.1 mm to 0.3 mm (for example, it can be 0.188 mm), the size of the second gate drive circuit GOA22 can be 0.1 mm to 0.3 mm (for example, it can be 0.138 mm), the size of the second gate drive circuit GOA23 can be 0.05 mm to 0.2 mm (for example, it can be 0.094 mm), and the size of the second gate drive circuit GOA24 can be 0.1 mm to 0.3 mm (for example, it can be 0.14 mm).

[0157] In an exemplary embodiment, as shown in Figures 5 and 19, the first gate drive circuit GOA1 provides a scan signal to the second transistor T2 in Figure 5 through the third scan signal line S3; the second gate drive circuit GOA21 can provide a scan signal to the fourth transistor T4 in Figure 5 through the fourth scan signal line S4; the second gate drive circuit GOA22 can provide a scan signal to the first transistor T1 in Figure 5 through the second scan signal line S2; the second gate drive circuit GOA23 can provide a light emitting control signal to the fifth transistor T5 and the sixth transistor T6 in Figure 5 through the light emitting signal line E; and the second gate drive circuit GOA24 can provide a scan signal to the seventh transistor T7 and the eighth transistor T8 in Figure 5 through the first scan signal line S1.

[0158] In an exemplary embodiment, as shown in Figures 6 and 8a, a binding area B10 may be provided in the border area BB on one side of the display area AA, and the binding area B10 may be provided with a driving chip 100 (driving IC) configured to provide data signals to multiple columns of sub-pixels of the display substrate 10.

[0159] In an exemplary embodiment, as shown in FIG17a , the first gate drive circuit GOA1 may include multiple transistors and multiple capacitors. The multiple transistors may include first to sixteenth transistors T1 to T16, and the multiple capacitors may include first to third capacitors C1 to C3. FIG20a to FIG20j are schematic diagrams of a structure of the first gate drive circuit GOA1 shown in FIG17a . The structure of the first gate drive circuit GOA1 is described in detail below in conjunction with FIG20a to FIG20j :

[0160] As shown in FIG20 a , a schematic planar structure diagram of the first gate drive circuit GOA1 is shown. On a plane parallel to the display substrate, in a first direction X, the first transistor T1 and the ninth transistor T9 are located on both sides of the first capacitor C1, the fourteenth transistor T14 is located on a side of the first transistor T1 away from the ninth transistor T9, the second capacitor C2 is located between the first capacitor C1 and the ninth transistor T9, the seventh transistor T7 is located between the first capacitor C1 and the second capacitor C2, the second transistor T2, the third transistor T3, the fifth transistor T5 to the eighth transistor T8, the eleventh transistor T11, and the thirteenth transistor T13 are located on a side of the second capacitor C2 away from the ninth transistor T9, and the fifteenth transistor T15 and the tenth transistor T10 are located on the eleventh transistor T11. On both sides, the twelfth transistor T12 and the sixteenth transistor T16 are located between the eleventh transistor T11 and the tenth transistor T10, and the third capacitor C3 and the fourth transistor T4 are located on the side of the sixteenth transistor T16 away from the tenth transistor T10; in the second direction Y, the ninth transistor T9 and the tenth transistor T10 are arranged in the opposite direction of the second direction Y, the seventh transistor T7, the sixth transistor T6, the eighth transistor T8, the fifth transistor T5, the twelfth transistor T12, and the sixteenth transistor T16 are arranged in sequence in the opposite direction of the second direction Y, and the first transistor T1 and the fourteenth transistor T14, the third transistor T3, the fifteenth transistor T15 and the eleventh transistor T11, the third capacitor C3, and the fourth transistor T4 are arranged in sequence in the opposite direction of the second direction Y.

[0161] As shown in Figure 20b, it is a schematic diagram of the planar structure of the active layer of the first gate drive circuit GOA1 in the display substrate formed on the base, and the active layer may include: the active layer P01 of the first transistor T1 to the active layer P16 of the sixteenth transistor T16, wherein the active layer P09 of the ninth transistor T9 and the active layer P10 of the tenth transistor T10 may be an integrally formed structure, the active layer P02 of the second transistor T2 and the active layer P11 of the eleventh transistor T11 may be an integrally formed structure, the active layer P08 of the eighth transistor T8, the active layer P13 of the thirteenth transistor T13, and the active layer P16 of the sixteenth transistor T16 may be an integrally formed structure, and the active layer P01 of the first transistor T1, the active layer P03 of the third transistor T3 to the active layer P08 of the eighth transistor T8, the active layer P14 of the fourteenth transistor T14, and the active layer P15 of the fifteenth transistor T15 may be independently provided.

[0162] As shown in Figure 20c, it is a schematic diagram of the planar structure after the first conductive layer (which can be called the Gate1 layer) is formed. The first conductive layer may include: the control electrode G01 of the first transistor T1 to the control electrode G16 of the sixteenth transistor T16, the first plate C11 of the first capacitor C1, the first plate C21 of the second capacitor C2, and the first plate C31 of the third capacitor C3. The first plate C11 of the first capacitor C1 is connected to the control electrode GO6 of the sixth transistor T6, the first plate C21 of the second capacitor C2 is connected to the control electrode GO9 of the ninth transistor T9, the first plate C31 of the third capacitor C3 is connected to the control electrode G04 of the fourth transistor T4 and the control electrode G16 of the sixteenth transistor T16, the control electrode G01 of the fourteenth transistor T14 is respectively connected to the control electrode G01 of the first transistor T1 and the control electrode G03 of the third transistor T3, the control electrode G02 of the second transistor T2 is connected to the control electrode of the eighth transistor G08, and the control electrode G11 of the eleventh transistor T11 is connected to the control electrode G15 of the fifteenth transistor T15. In an exemplary embodiment, regions where the control electrodes G01 to G16 of the first to sixteenth transistors T1 to T16 overlap with the active layers P01 to P16 of the first to sixteenth transistors T1 to T16, respectively, form channels of the first to sixteenth transistors T1 to T16.

[0163] As shown in Figure 20d, it is a schematic diagram of the planar structure after the second conductive layer (which can be called Gate2 layer) is formed. The second conductive layer may include: the second plate C12 of the first capacitor C1, the second plate C22 of the second capacitor C2, and the second plate C32 of the third capacitor C3; the second plate C12 of the first capacitor C1 and the orthographic projection of the first plate C11 of the first capacitor C1 on the substrate at least partially overlap, the second plate C22 of the second capacitor C2 and the orthographic projection of the first plate C21 of the second capacitor C2 on the substrate at least partially overlap, and the second plate C32 of the third capacitor C3 and the orthographic projection of the first plate C31 of the third capacitor C3 on the substrate at least partially overlap.

[0164] As shown in Figure 20e, which is a schematic diagram of the planar structure of the first via layer, the first via layer may include: the first via V1 to the thirty-fourth via V34, the orthographic projections of the first via V1 to the sixteenth via V16 on the substrate respectively overlap with the orthographic projections of the active layer P11 of the first transistor T1 to the active layer P16 of the sixteenth transistor T16 on the substrate; the orthographic projections of the seventeenth via V17 to the nineteenth via V19 on the substrate respectively overlap with the orthographic projections of the second plate C12 of the first capacitor C1 to the second plate C32 of the third capacitor C3 on the substrate; the orthographic projection of the twentieth via V20 on the substrate overlaps with the orthographic projection of the second plate C32 of the third capacitor C3 on the substrate; the orthographic projections of the twenty-first via V21 to the thirtieth via V30 on the substrate overlap with the control electrode G01 of the first transistor T1, the control electrode G02 of the second transistor T2, and the control electrode G03 of the fifth transistor T3. The orthographic projections of the control electrode G05 of transistor T5, the control electrode G08 of the eighth transistor T8, the control electrode G09 of the ninth transistor T9, the control electrode G10 of the tenth transistor T10, the control electrode G11 of the eleventh transistor T11, the control electrode G12 of the twelfth transistor T12, the control electrode G13 of the thirteenth transistor T13, and the control electrode G16 of the sixteenth transistor T16 on the substrate at least partially overlap. The orthographic projections of the thirty-first via V31 and the thirty-second via V32 on the substrate at least partially overlap with the orthographic projections of the control electrode G06 of the sixth transistor T6 and the control electrode G07 of the seventh transistor T7 on the substrate, respectively. The orthographic projection of the thirty-third via V33 on the substrate at least partially overlaps with the orthographic projection of the first plate C31 of the third capacitor C3 on the substrate. The orthographic projection of the thirty-fourth via V34 on the substrate at least partially overlaps with the orthographic projection of the control electrode G07 of the seventh transistor T7 on the substrate.

[0165] As shown in FIG20f, it is a schematic diagram of the planar structure after the first via layer and the third conductive layer (which can be called SD1 layer) are formed. The third conductive layer may include: a first connecting electrode 31 to a twenty-third connecting electrode 323. The first connecting electrode 31 may be electrically connected to the active layer P11 of the first transistor T1 and the active layer P04 of the fourth transistor T4 through the first via V1 and the fourteenth via V14, respectively. The first connecting electrode 31 may serve as a signal input terminal (STV), as well as the first electrode of the first transistor T1 and the first electrode of the fourteenth transistor T14; the second connecting electrode 32 may be electrically connected to the active layer P11 of the first transistor T1 and the active layer P04 of the fourth transistor T4 through the first via V1 and the fourteenth via V14, respectively. The active layer P11 is electrically connected to the control electrode G02 of the second transistor T2, and the second electrode 32 can serve as the second electrode of the first transistor T1; the third connection electrode 33 can be electrically connected to the active layer P02 of the second transistor T2 and the control electrode G01 of the first transistor T1 through the second via hole V2 and the twenty-first via hole V21, respectively, and the third connection electrode 33 can serve as the first electrode of the second transistor T2; the fourth connection electrode 34 can be electrically connected to the active layer P03 of the third transistor T3, the active layer P11 of the eleventh transistor T11, and the control electrode G05 of the fifth transistor T5 through the third via hole V3, the eleventh via hole V11, and the twenty-third via hole V23, respectively. It can serve as the second electrode of the third transistor T3 and as the first electrode of the eleventh transistor T11; the fifth connection electrode 35 can be electrically connected to the active layer P03 of the third transistor T3, the control electrodes of the fifth transistor T5 and the eleventh transistor T11, and the control electrode G12 of the twelfth transistor T12 through the third via hole V3, the twenty-seventh via hole V27, and the twenty-eighth via hole V28 respectively. The fifth connection electrode 35 can serve as the first electrode of the third transistor T3 and as the input end of the low-level signal VGL; the sixth connection electrode 36 can be electrically connected to the active layer P04 of the fourth transistor T4 and the second plate C32 of the third capacitor C3 through the fourth via hole V4 and the ninth via hole V9 respectively. The sixth connection electrode 36 can serve as the second electrode of the fourth transistor T4; the seventh connection electrode 37 can be electrically connected to the active layer P04 of the fourth transistor T4 through the fourth via V4, and the seventh connection electrode 37 can serve as the first electrode of the fourth transistor T4; the eighth connection electrode 38 can be electrically connected to the active layer P05 of the fifth transistor T5 and the second electrode plate C32 of the third capacitor C3 through the fifth via V5 and the twentieth via V20, respectively, and the eighth connection electrode 38 can serve as the second electrode of the fifth transistor T5; the ninth connection electrode 39 can be electrically connected to the active layer P05 of the fifth transistor T5 through the fifth via V5, and the ninth connection electrode 39 can serve as the first electrode of the fifth transistor T5;The tenth connection electrode 310 can be electrically connected to the active layer P06 of the sixth transistor T6, the second electrode plate C12 of the first capacitor C1, and the active layer P07 of the seventh transistor T7 through the sixth via hole V6, the seventeenth via hole V17, and the seventh via hole V7, respectively. The tenth connection electrode 310 can serve as the second electrode of the sixth transistor T6 and the first electrode of the seventh transistor T7; the eleventh connection electrode 311 can be electrically connected to the active layer P06 of the sixth transistor T6 and the control electrode G07 of the seventh transistor T7 through the sixth via hole V6 and the thirty-second via hole V32, respectively. The eleventh connection electrode 311 can serve as the first electrode of the sixth transistor T6; the twelfth connection electrode 312 can be electrically connected to the active layer P06 of the sixth transistor T6 and the control electrode G07 of the seventh transistor T7 through the seventh via hole V 7. The twenty-fifth via hole V25 and the eighth via hole V8 are electrically connected to the active layer P07 of the seventh transistor T7, the control electrode of the ninth transistor T9, the first electrode plate C21 of the second capacitor C2, and the active layer P08 of the eighth transistor T8, respectively. The twelfth connecting electrode 312 can serve as the second electrode of the seventh transistor T7 and the first electrode of the eighth transistor T8. The thirteenth connecting electrode 313 can be electrically connected to the active layers of the twelfth transistor T12 and the thirteenth transistor T13, the control electrode of the second transistor T2, and the control electrode of the eighth transistor T8, respectively, through the twelfth via hole V12 and the twenty-ninth via hole V29. The thirteenth connecting electrode 313 can serve as the first electrode of the twelfth transistor T12 and the control electrode of the tenth transistor T8. The second electrode of the third transistor T13; the fourteenth connecting electrode 314 can be electrically connected to the active layer P09 of the ninth transistor T9, the active layer of the eighth transistor T8 and the active layer of the thirteenth transistor T13 through the ninth via hole V9 and the thirteenth via hole V13, respectively. The fourteenth connecting electrode 314 can serve as the first electrode of the eighth transistor T8, the ninth transistor T9 and the thirteenth transistor T13, and can serve as the input end of the high-level signal VGH; the fifteenth connecting electrode 315 can be electrically connected to the active layer P10 of the tenth transistor T10 and the active layer P09 of the ninth transistor T9 through the tenth via hole V10 and the ninth via hole V9, respectively. The fifteenth connecting electrode 315 can serve as the input end of the ninth transistor T9 The second electrode and the second electrode of the tenth transistor T10 can be used as a signal output terminal OUT, and the signal output terminal OUT is electrically connected to the signal input terminal STV of the next first gate driving circuit GOA1; the sixteenth connecting electrode 316 can be electrically connected to the active layer P10 of the tenth transistor T10 through the tenth via hole V10, and the sixteenth connecting electrode 316 can serve as the first electrode of the tenth transistor T10; the seventeenth connecting electrode 317 can be electrically connected to the active layer P11 of the eleventh transistor T11 and the control electrode G06 of the sixth transistor T6 through the eleventh via hole V11 and the thirty-first via hole V31, respectively, and the seventeenth connecting electrode 317 can serve as the second electrode of the eleventh transistor T11;The eighteenth connecting electrode 318 can be electrically connected to the active layer of the sixteenth transistor T16 and the twelfth transistor T12, and the control electrode G10 of the tenth transistor T10 through the twelfth via hole V12 and the twenty-sixth via hole V26, respectively. The eighteenth connecting electrode 318 can serve as the second electrode of the twelfth transistor T12 and the sixteenth transistor T16; the nineteenth connecting electrode 319 can be electrically connected to the fifteenth transistor T15 and the first electrode plate C31 of the third capacitor C3 through the fifteenth via hole V15 and the thirty-third via hole V33, respectively. The nineteenth connecting electrode 319 can serve as the second electrode of the fifteenth transistor T15; the twentieth connecting electrode 320 can be electrically connected to the active layer P14 of the fourteenth transistor T14 and the active layer P15 of the fifteenth transistor T15 through the fourteenth via hole V14 and the fifteenth via hole V15, respectively. The twentieth connecting electrode 320 can serve as the second electrode of the fourteenth transistor T14 and the first electrode plate C31 of the fifteenth transistor T15. The first electrode of the first transistor T16; the twenty-first connecting electrode 321 can be electrically connected to the active layer P16 of the sixteenth transistor T16 and the first plate C31 of the third capacitor C3 through the sixteenth via V16 and the thirtieth via V30, respectively. The twenty-first connecting electrode 321 can serve as the first electrode of the sixteenth transistor T16; the twenty-second connecting electrode 322 can be electrically connected to the control electrode G13 of the thirteenth transistor T13 through the twenty-ninth via V29, and the twenty-second connecting electrode 322 can serve as the input end of the voltage signal VEL; the twenty-third connecting electrode 323 can be electrically connected to the control electrode G07 of the seventh transistor T7 through the thirty-fourth via V34.

[0166] As shown in Figure 20g, which is a schematic diagram of the planar structure after the second via layer is formed, the second via layer may include: the thirty-fifth via V35 to the forty-first via V41; the orthographic projection of the thirty-fifth via V35 on the substrate is located within the range of the orthographic projection of the ninth connecting electrode 39 on the substrate, the orthographic projection of the thirty-sixth via V36 on the substrate is located within the range of the orthographic projection of the sixteenth connecting electrode 316 on the substrate, the orthographic projection of the thirty-seventh via V37 on the substrate is located within the range of the orthographic projection of the twenty-second connecting electrode 322 on the substrate, the orthographic projection of the thirty-eighth via V38 on the substrate is located within the range of the orthographic projection of the seventh connecting electrode 37 on the substrate, and the orthographic projection of the thirty-ninth via V39 on the substrate is located within the range of the orthographic projection of the twenty-third connecting electrode 323 on the substrate; the orthographic projection of the fortieth via V40 on the substrate is located within the range of the orthographic projection of the fifth connecting electrode 35 on the substrate; and the orthographic projection of the forty-first via V41 on the substrate is located within the range of the orthographic projection of the fourteenth connecting electrode 314 on the substrate.

[0167] As shown in FIG20h, it is a schematic diagram of a planar structure after the fourth conductive layer (which can be called the SD2 layer) is formed. The fourth conductive layer may include: an input signal line STV, a first low-level signal line VGL1, a first clock signal line CB, a second clock signal line CK, a first high-level signal line VGH1, a second level signal line VEL, a second high-level signal line VGH2, a third high-level signal line VGH3, and a second low-level signal line VGL2; the input signal line STV, the first low-level signal line VGL1, the first clock signal line CB, the second clock signal line CK, the first high-level signal line VGH1, the second level signal line VEL, the second high-level signal line VGH2, the third high-level signal line VGH3, and the second low-level signal line VGL2. The high-level signal line VGH1, the second-level signal line VEL, the second high-level signal line VGH2, the third high-level signal line VGH3, and the second low-level signal line VGL2 can be arranged at intervals along the first direction X and extend along the second direction Y; the input signal line STV is electrically connected to the input end of the first gate drive circuit GOA1 of the first stage, and provides an input signal to the input end of the first gate drive circuit GOA1 of the first stage; the first low-level signal line VGL2 can be electrically connected to the fifth connection electrode 35 through the fortieth via hole V40; the second low-level signal line VGL1 can be electrically connected to the fifth connection electrode 35 through the fortieth via hole V40; The thirty-sixth via hole V36 is electrically connected to the sixteenth connection electrode 316; the second level signal line VEL can be electrically connected to the twenty-second connection electrode 322 through the thirty-seventh via hole V37, and provides a voltage signal to the control electrode G13 of the thirteenth transistor T13; the first high level signal line VGH1 can be electrically connected to the ninth connection electrode 39 through the thirty-fifth via hole V35 to provide a voltage signal to the first electrode of the fifth transistor T5; the second high level signal line VGH2 and the third high level signal line VGH3 can be electrically connected to the fourteenth connection electrode 314 through the forty-first via hole V41 , providing a voltage signal to the first electrode of the ninth transistor T9. In FIG20h , the second high-level signal VGH2 can be electrically connected to the fourteenth connection electrode 314 of the first gate drive circuit GOA1 of the previous or next stage via the forty-first via V41. The first clock signal line CB can be electrically connected to the seventh connection electrode 37 via the thirty-eighth via V38 to provide a clock signal to the first electrode of the fourth transistor T4. The second clock signal line CK can be electrically connected to the twenty-third connection electrode 323 via the thirty-ninth via V39 to provide a clock signal to the control electrode of the seventh transistor T7. The first low-level signal line VGL1 and the second low-level signal line VGL2 can provide the same low-level signal VGL, and the first high-level signal line VGH1, the second high-level signal line VGH2, and the third high-level signal line VGH3 can provide the same high-level signal VGH.

[0168] FIG20i is a schematic diagram showing a structure in which a shielding structure layer 12 is provided between the substrate and the driving circuit layer, and FIG20j is a schematic diagram showing a planar structure in which an active layer is formed on the shielding structure layer 12. In an exemplary embodiment, a first insulating layer is provided between the shielding structure layer 12 and the active layer, a second insulating layer is provided between the active layer and the first conductive layer, a third insulating layer is provided between the first conductive layer and the second conductive layer, a fourth insulating layer is provided between the second conductive layer and the third conductive layer, and a fifth insulating layer is provided between the third conductive layer and the fourth conductive layer. In the first via layer, the first to sixteenth vias V1 to V16 penetrate the second to fourth insulating layers, the seventeenth to twentieth vias V17 to V20 penetrate the fourth insulating layer, and the twenty-first to thirty-fourth vias V21 to V34 penetrate the third and fourth insulating layers. In the second via layer, the thirty-fifth to fortieth vias V35 to V40 penetrate the fifth insulating layer.

[0169] In an exemplary embodiment, as shown in FIG21 , the characteristic curves of the first transistor T1 (the low-level output control transistor) are shown when it is shielded by the first structure layer 11 and when it is not shielded by the first structure layer 11. Curve W1 is the characteristic curve of the first transistor when the first transistor T1 is covered by the first structure layer 11; curve W2 is the characteristic curve of the first transistor T1 when it is not covered by the first structure layer 11. As can be seen from FIG21 , the characteristics of the first transistor T1 when it is shielded by the first structure layer 11 and when it is not shielded by the first structure layer 11 differ greatly. As can be seen from FIG21 , the threshold voltage Vth of the first transistor T1 fluctuates slightly over time in curve W1, with little change; while the threshold voltage Vth of the first transistor T1 fluctuates relatively more over time in curve W2. Therefore, when the shielding methods of the first transistors T1 in multiple first gate drive circuits GOA1 are inconsistent, the characteristics of the first transistor T1 vary greatly. The first structural layer 11 or the shielding structure (121, 122) in the above-mentioned embodiment can be used to block the first transistors T1 in multiple first gate drive circuits GOA1 in a consistent manner, thereby avoiding inconsistent scanning signals output by the multiple first gate drive circuits GOA1 to the oxide transistor T2 in the display area AA, thereby improving the display uniformity of the display area. In an exemplary embodiment, as shown in Figures 22a to 22d, the characteristic change curves of the first transistor T1 (the low-level output control transistor) and the tenth transistor T10 (the low-level output transistor) in Figures 17a to 17e are affected by temperature. Figure 22a shows a curve showing the change of the threshold voltage Vth of the first transistor T1 as the temperature changes, and the threshold voltage Vth of the first transistor T1 increases with increasing temperature; Figure 22b shows a curve showing the change of the current of the first transistor T1 as the temperature changes, and the current of the first transistor T1 increases with increasing temperature; Figure 22c shows a curve showing the change of the threshold voltage Vth of the tenth transistor T10 as the temperature changes, and the threshold voltage Vth of the tenth transistor T10 increases with increasing temperature; Figure 22d shows a curve showing the change of the current of the tenth transistor T10 as the temperature changes, and the current of the tenth transistor T10 increases with increasing temperature. As shown in Figures 22a to 22d, it can be seen that the characteristics of the first transistor T1 and the tenth transistor T10 are greatly affected by temperature.Therefore, when the shielding modes of the first transistor T1 and the tenth transistor T10 in the multiple first gate drive circuits GOA1 are inconsistent, the characteristics of the first transistor T1 and the tenth transistor T10 are very different. The first structural layer 11 or the shielding structure (121, 122) in the above-mentioned embodiment can be used to shield the first transistor T1 and the tenth transistor T10 in the multiple first gate drive circuits GOA1 in a consistent manner, thereby avoiding inconsistent scanning signals output by the multiple first gate drive circuits GOA1 to the oxide transistor T2 in the display area AA, thereby improving the display uniformity of the display area.

[0170] In an exemplary embodiment, as shown in FIG23 , in order to provide a cutting alignment mark (MARK) 200 on the display substrate, the first structural layer 11 is provided with an opening 1101 at the alignment mark position, which results in the first driving circuit GOA1 at the opening 1101 position not being covered by the first structural layer 11, while the first driving circuits GOA1 at other positions are all covered by the first structural layer 11, which can easily lead to the appearance of horizontal stripes 300 as shown in FIG24 . By adopting the above-mentioned solution, the protective structure 110 blocks the multiple first driving circuits GOA1 in a consistent manner, thereby avoiding the defect of horizontal stripes.

[0171] In an exemplary embodiment, as shown in FIG17 , the first transistor T1 and the tenth transistor T10 in the first gate drive circuit GOA1 are significantly affected by factors such as temperature and light. The first structural layer 11 or the shielding structures (121, 122) can be used to uniformly shield the plurality of first transistors T1 and the tenth transistor T10 to avoid the appearance of horizontal stripes. In an exemplary embodiment, the plurality of first gate drive circuits GOA1 are configured to provide scan signals to the second transistors T2 (oxide transistors) in the pixel circuits of multiple rows of sub-pixels in the display area AA. The oxide transistors T2 in the pixel drive circuits are significantly affected by variations in the scan signals output by the gate drive circuit GOA. For example, low-temperature polysilicon transistors in the drive circuits are less significantly affected by variations in the scan signals output by the gate drive circuit GOA. Therefore, in the disclosed embodiment, the plurality of first drive circuits GOA1 that provide scan signals to the oxide transistors T2 are uniformly shielded to avoid the appearance of horizontal stripes in the display area AA during operation.

[0172] The present disclosure also provides a display module, as shown in Figures 6, 8a, 18, 19 and 20i, which may include a display substrate 10. On a surface parallel to the display substrate, the display substrate 10 may include a display area AA and a border area BB. The border area BB may be located around the display area AA. The border area BB is provided with at least one type of first gate drive circuit GOA1. There are multiple first gate drive circuits GOA1 of the same type, and the first gate drive circuit GOA1 includes multiple transistors. In a direction Z perpendicular to the surface of the display substrate, the display substrate 10 may include a light-emitting side S1 and a backlight side S2. A shielding structure layer 12 is provided on a side of the first gate drive circuit GOA1 away from the light-emitting side S2. At least some of the transistors in the multiple first gate drive circuits GOA1 of the same type are shielded by the shielding structure layer 12 to the same extent.

[0173] In an exemplary embodiment, a plurality of first gate driving circuits GOA1 of the same type are arranged along the extending direction of the border area BB.

[0174] In an exemplary embodiment, at least some transistors in multiple first gate drive circuits GOA1 of the same type are shielded by the shielding structure layer 12 in the same range. The absolute shielding range may be consistent, or the approximate shielding range may be consistent. For example, the shielding range may have a deviation of about 5%-15%.

[0175] In an exemplary embodiment, the range in which the multiple first gate driving circuits GOA1 of the same type are blocked by the blocking structure layer 12 is consistent, and the area in which at least some transistors in the multiple first gate driving circuits GOA1 of the same type overlap with the positive projection of the blocking structure layer 12 on the substrate is consistent.

[0176] In an exemplary embodiment, the display area AA may include multiple rows of sub-pixels Pxij. Each sub-pixel Pxij includes at least one pixel driving circuit, which includes at least one oxide transistor. A first gate driving circuit GOA1 is electrically connected to the control electrode of the at least one oxide transistor in at least one row of sub-pixels and is configured to provide a scan signal to the at least one oxide transistor in the at least one row of sub-pixels. As shown in FIG. 5 , the second transistor T2 in the pixel driving circuit is an oxide transistor.

[0177] In an exemplary embodiment, the plurality of transistors in the first gate driving circuit GOA1 include at least a low-level output transistor (e.g., the tenth transistor T10 in FIG. 17 a to FIG. 17 e ) and a low-level output control transistor (e.g., the first transistor T1 in FIG. 17 a to FIG. 17 e ), the low-level output transistor being configured to output a low-level signal to at least one oxide transistor in at least one row of sub-pixels under the control of the low-level output control transistor;

[0178] The low-level output transistors in multiple first gate drive circuits of the same type are blocked by the blocking structure to the same extent; the low-level output control transistors in multiple first gate drive circuits of the same type are blocked by the blocking structure layer to the same extent.

[0179] In an exemplary embodiment, as shown in FIG18 , the shielding structure layer 12 may include at least one of a first shielding structure 121 and a second shielding structure 122 ;

[0180] There are multiple first shielding structures 121, and the multiple first shielding structures 121 are respectively configured to shield the low-level output control transistors in at least one type of multiple first gate drive circuits GOA1; there are multiple second shielding structures 122, and the multiple second shielding structures 122 are respectively configured to shield the low-level output transistors in at least one type of multiple first gate drive circuits GOA1.

[0181] In an exemplary embodiment, the low-level output control transistors in different first gate drive circuits GOA1 of the same type are shielded by the first shielding structure 121 in a consistent manner, so that the characteristics of the low-level output control transistors in multiple first gate drive circuits GOA1 are kept as consistent as possible, avoiding the appearance of horizontal stripes in the display area AA due to inconsistent characteristics of the low-level output control transistors in multiple first gate drive circuits; the low-level output transistors in different first gate drive circuits GOA1 of the same type are shielded by the second shielding structure 122 in a consistent manner, so that the characteristics of the low-level output transistors in multiple first gate drive circuits GOA1 are kept as consistent as possible, avoiding the appearance of horizontal stripes in the display area AA due to inconsistent characteristics of the low-level output transistors in multiple first gate drive circuits GOA1.

[0182] In an exemplary embodiment, the display substrate may further include a base, and in a direction Z perpendicular to the surface of the display substrate, the blocking structure layer 12 may be located between the base and the first gate drive circuit GOA1, wherein the orthographic projection of the first blocking structure 121 on the base covers the orthographic projection of the corresponding low-level output control transistor on the base, and the orthographic projection of the second blocking structure 122 on the base covers the orthographic projection of the corresponding low-level output transistor on the base.

[0183] In an exemplary embodiment, as shown in FIG18 , the shielding structure layer 12 may further include a third shielding structure 123, the orthographic projection of which on the substrate covers the third transistor T3 in the pixel driver circuit (the third transistor T3 in FIG5 ). On a plane parallel to the display substrate, the first shielding structure 121 and the second shielding structure 122 are located in the border area BB, and the third shielding structure 123 is located in the display area AA. In the disclosed embodiment, the shielding structure located in the border area BB can be formed in the same process as the shielding structure located in the display area AA. Without increasing the process flow, providing the shielding structure in the border area BB can resolve the problem of uneven brightness in the display area caused by inconsistent transistor characteristics in the first gate driver circuit GOA1.

[0184] The present disclosure also provides a display device comprising the display module of any of the aforementioned embodiments. The display device can be any product or component with a display function, such as a wearable device (e.g., a watch), a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigation system.

[0185] The display module and display device provided by the embodiments of the present disclosure include a display module including a display substrate and a first structural layer. The first structural layer is located on the backlight side of the display substrate. At least some transistors in multiple first gate driving circuits of the same type located in the border area of ​​the display substrate have the same range covered by the orthographic projection of the first structural layer on the display substrate, which can overcome the technical problem of uneven brightness of the display module.

[0186] In the absence of conflict, the embodiments of the present disclosure, i.e., features in the embodiments, can be combined with each other to form new embodiments.

[0187] Although the embodiments disclosed in the present disclosure are as described above, the contents are only embodiments adopted to facilitate understanding of the embodiments of the present disclosure and are not intended to limit the embodiments of the present disclosure. Any person skilled in the art in the field to which the embodiments of the present disclosure belong may make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the embodiments of the present disclosure, but the scope of patent protection of the embodiments of the present disclosure shall still be based on the scope defined by the attached claims.

Claims

1. A display module includes a display substrate and a first structure layer. On a plane parallel to the plane where the display substrate is located, the display substrate includes a display area and a border area. The border area is located around the display area, and at least one type of first gate driving circuit is provided in the border area. The number of the first gate driving circuits of the same type is multiple, and the first gate driving circuit includes multiple transistors. In a direction perpendicular to the plane where the display substrate is located, the display substrate includes a light-emitting side and a backlight side. The first structure layer is disposed on the backlight side of the display substrate, and a positive projection of the first structure layer on the display substrate covers at least part of the display area. The ranges of at least part of the transistors in multiple first gate driving circuits of the same type covered by the positive projection of the first structure layer on the display substrate are the same.

2. The display module according to claim 1, wherein, The display area includes multiple rows of sub-pixels. The sub-pixels at least include a pixel driving circuit. The pixel driving circuit includes at least one oxide transistor. The first gate driving circuit is electrically connected to the control electrodes of at least one oxide transistor in at least one row of sub-pixels, and is configured to provide a scanning signal to at least one oxide transistor in at least one row of sub-pixels.

3. The display module according to claim 2, wherein, The multiple transistors in the first gate driving circuit at least include a low-level output transistor and a low-level output control transistor. The low-level output transistor is configured to output a low-level signal to at least one oxide transistor in at least one row of sub-pixels under the control of the low-level output control transistor. The ranges of the low-level output transistors in multiple first gate driving circuits of the same type covered by the positive projection of the first structure layer on the display substrate are the same. The ranges of the low-level output control transistors in multiple first gate driving circuits of the same type covered by the positive projection of the first structure layer on the display substrate are the same.

4. The display module according to any one of claims 1 to 3, wherein, There is no overlapping area between the positive projection of the first structure layer on the display substrate and multiple first gate driving circuits of at least one type.

5. The display module according to claim 4, wherein, The positive projection of the edge of the first structure layer on the display substrate is located in a first area. On a plane parallel to the plane where the display substrate is located, the first area is located between the edge of multiple first gate driving circuits of at least one type close to the display area and the edge of the display area close to the border area. The positive projection of the first structure layer on the display substrate covers the display area. Alternatively, there is no overlapping area between the positive projection of the first structure layer on the display substrate and the border area, and the positive projection of the first structure layer on the display substrate is located within the display area or overlaps with the display area.

6. The display module according to claim 4, wherein On a plane parallel to the plane where the display substrate is located, along the direction from the display area to the border area, the distance between the edge of the first structure layer and the edge of the display substrate is 700 micrometers to 1200 micrometers, which is greater than the distance between the edge of multiple first gate driving circuits of at least one type close to the display area and the edge of the display substrate.

7. The display module according to claim 1, wherein, The orthographic projection of the first structural layer on the display substrate covers the display area and at least one type of multiple first gate driving circuits.

8. The display module according to claim 7, wherein, The border area is further provided with at least one type of second gate driving circuits. The number of the second gate driving circuits of the same type is multiple. On a plane parallel to the plane where the display substrate is located, the multiple second gate driving circuits of the same type are arranged along the extending direction of the border area. Along the direction from the display area to the border area, at least one type of multiple second gate driving circuits are located between at least one type of multiple first gate driving circuits and the display area.

9. The display module according to claim 8, wherein, On a plane parallel to the plane where the display substrate is located, in the direction from the display area to the border area, the distance between the edge of the first structural layer and the edge of the display substrate is 100 micrometers to 350 micrometers, which is less than the distance between the edge of at least one type of first gate driving circuit away from the display area side and the edge of the display substrate.

10. The display module according to claim 7, wherein, The border area is further provided with at least one type of second gate driving circuits. The number of the second gate driving circuits of the same type is multiple. On a plane parallel to the plane where the display substrate is located, the multiple second gate driving circuits of the same type are arranged along the extending direction of the border area. Along the direction from the display area to the border area, at least one type of multiple second driving circuits are located on the side of at least one type of multiple first driving circuits away from the display area.

11. The display module according to claim 10, wherein, On a plane parallel to the plane where the display substrate is located, in the direction from the display area to the border area, the distance between the edge of the first structural layer and the edge of the display substrate is 500 micrometers to 700 micrometers, which is less than the distance between the edge of at least one type of first gate driving circuit away from the display area side and the edge of the display substrate.

12. The display module according to any one of claims 1 to 3 and 10 to 11, wherein, The first structural layer includes a first connection structural layer, a buffer structural layer, and a heat dissipation structural layer sequentially arranged on the backlight side. The orthographic projection of the heat dissipation structural layer on the display substrate does not overlap with at least one type of multiple first gate driving circuits, or the orthographic projection of the heat dissipation structural layer on the display substrate covers at least one type of multiple first gate driving circuits.

13. The display module according to claim 3, wherein, The orthographic projection of the first structural layer on the display substrate at least covers at least one of the low-level output transistor and the low-level output control transistor in at least one type of multiple first gate driving circuits.

14. The display module according to claim 13, wherein, On a plane parallel to the plane where the display substrate is located, along the direction from the display area to the border area, the low-level output control transistor is located on the side of the low-level output transistor away from the display area. The length dimension of at least one type of first gate driving circuit is 120 micrometers to 150 micrometers. The low-level output control transistor and the low-level output transistor are located on both sides of the midline of the first gate driving circuit along the extending direction of the border area. In a structure where the orthographic projection of the first structural layer on the display substrate covers at least the low-level output transistor and the low-level output control transistor in at least one type of multiple first gate driving circuits, in a direction from the display area to the border area, the length dimension of the orthographic projection of the first structural layer on the display substrate covering the at least one type of first gate driving circuits is from 100 micrometers to 150 micrometers; In a structure where the orthographic projection of the first structural layer on the display substrate covers at least the low-level output transistor in at least one type of multiple first gate driving circuits, in a direction from the display area to the border area, the length dimension of the orthographic projection of the first structural layer on the display substrate covering the at least one type of first gate driving circuits is from 40 micrometers to 95 micrometers.

15. The display module according to claim 13 or 14, wherein, The border area is further provided with at least one type of second gate driving circuits. On a plane parallel to the plane where the display substrate is located, multiple second gate driving circuits of the same type are arranged along the extending direction of the border area; In a direction from the display area to the border area, at least one type of multiple second gate driving circuits are located on a side of at least one type of multiple first gate driving circuits away from the display area, or at least one type of multiple second gate driving circuits are located between at least one type of multiple first gate driving circuits and the display area.

16. The display module according to claim 3, wherein, The display substrate includes an occlusion structural layer. In a direction perpendicular to the plane where the display substrate is located, the occlusion structural layer is located on a side of the first gate driving circuit away from the light-emitting side, and the occlusion structural layer includes at least one of a first occlusion structure and a second occlusion structure; The number of the first occlusion structures is multiple, and the multiple first occlusion structures are respectively arranged to occlude the low-level output control transistors in at least one type of multiple first gate driving circuits; The number of the second occlusion structures is multiple, and the multiple second occlusion structures are respectively arranged to occlude the low- level output transistors in at least one type of multiple first gate driving circuits.

17. A display module includes a display substrate. On a plane parallel to the plane where the display substrate is located, the display substrate includes a display area and a border area, the border area is located around the display area, the border area is provided with at least one type of first gate driving circuits, the number of the first gate driving circuits of the same type is multiple, and the first gate driving circuits include multiple transistors; in a direction perpendicular to the plane where the display substrate is located, the display substrate includes a light-emitting side and a backlight side, and an occlusion structural layer is provided on a side of the first gate driving circuit away from the light-emitting side, and the range where at least some of the transistors in multiple first gate driving circuits of the same type are occluded by the occlusion structural layer is the same.

18. The display module according to claim 17, wherein, The display area includes multiple rows of sub-pixels. The sub-pixels at least include a pixel driving circuit. The pixel driving circuit includes at least one type of oxide transistor. The first gate driving circuit is electrically connected to the control electrodes of at least one type of oxide transistor in at least one row of sub-pixels, and is configured to provide a scanning signal to at least one type of oxide transistor in at least one row of sub-pixels.

19. The display module according to claim 18, wherein, Multiple transistors in the first gate driving circuit at least include a low-level output transistor and a low-level output control transistor. The low-level output transistor is configured to output a low-level signal to at least one type of oxide transistor in at least one row of sub-pixels under the control of the low-level output control transistor; The ranges of the low-level output transistors in multiple first gate driving circuits of the same type blocked by the shielding structure layer are the same; the ranges of the low-level output control transistors in multiple first gate driving circuits of the same type blocked by the shielding structure layer are the same.

20. The display module according to claim 19, wherein, The shielding structure layer at least includes at least one shielding structure of a first shielding structure and a second shielding structure; The number of the first shielding structures is multiple, and the multiple first shielding structures are respectively configured to shield the low-level output control transistors in multiple first gate driving circuits of at least one type; The number of the second shielding structures is multiple, and the multiple second shielding structures are respectively configured to shield the low-level output transistors in multiple first gate driving circuits of at least one type.

21. A display device, comprising the display module according to any one of claims 1 to 16, or comprising the display module according to any one of claims 17 to 20.

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