Display substrate and display apparatus

Abstract

Provided is a display substrate, comprising: a light-emitting element layer, wherein the light-emitting element layer comprises a plurality of light-emitting elements, which comprise a plurality of first light-emitting elements, a plurality of second light-emitting elements and a plurality of third light-emitting elements, and the light-emitting element layer comprises a first electrode layer, a light-emitting layer and a second electrode layer, the first electrode layer comprising a first electrode, the light-emitting layer comprising a light-emitting portion, and the second electrode layer comprising a second electrode; and a plurality of partition portions, wherein the second electrode layer comprises a first part, a second part and a third part, and at least one partition portion is disposed between any two of the first part, the second part and the third part; and the first part comprises the second electrode of at least one first light-emitting element and is configured to be connected to a first signal, the second part comprises the second electrode of at least one second light-emitting element and is configured to be connected to a second signal, and the third part comprises the second electrode of at least one third light-emitting element and is configured to be connected to a third signal, at least two of the first signal, the second signal and the third signal being different from each other.

Description

Display substrate and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] With the continuous advancement of display technology, organic light-emitting diode (OLED) displays have become a research hotspot and a key area of ​​technological development for major manufacturers due to their advantages, including wide color gamut, high contrast, thin and lightweight design, self-luminescence, and wide viewing angle. Further reducing the power consumption of OLED displays is a key concern for display product developers.

[0003] The above information disclosed in this section is only for understanding the background of the inventive concept of the present disclosure and therefore the above information may contain information that does not constitute prior art.

[0004] Summary of the Invention

[0005] In one aspect, a display substrate is provided, comprising:

[0006] A base substrate, comprising a display area and a peripheral area located outside the display area;

[0007] a light-emitting element layer located on the base substrate, the light-emitting element layer including a plurality of light-emitting elements located in the display area, the plurality of light-emitting elements being arranged in an array along a first direction and / or a second direction, the plurality of light-emitting elements including a plurality of first light-emitting elements, a plurality of second light-emitting elements, and a plurality of third light-emitting elements, the light-emitting element layer including a first electrode layer located on the base substrate, a light-emitting layer located on a side of the first electrode layer away from the base substrate, and a second electrode layer located on a side of the light-emitting layer away from the base substrate, the first electrode layer including a first electrode of each light-emitting element, the light-emitting layer including a light-emitting portion of each light-emitting element, and the second electrode layer including a second electrode of each light-emitting element; and

[0008] a partition layer, located between the first electrode layer and the second electrode layer, the partition layer comprising a plurality of partition portions;

[0009] The second electrode layer includes a first part, a second part and a third part which are spaced apart from each other, and at least one partition portion is provided between any two of the first part, the second part and the third part. The first part includes a second electrode of at least one of the first light-emitting elements and is configured to access a first signal. The second part includes a second electrode of at least one of the second light-emitting elements and is configured to access a second signal. The third part includes a second electrode of at least one of the third light-emitting elements and is configured to access a third signal. At least two of the first signal, the second signal and the third signal are different from each other.

[0010] According to some exemplary embodiments, the width of the partition portion at a side away from the base substrate is greater than the width of the partition portion at a side close to the base substrate.

[0011] According to some exemplary embodiments, the display substrate includes a spacer layer located between the first electrode layer and the second electrode, and the spacer layer includes spacers and the partition portion.

[0012] According to some exemplary embodiments, the display substrate includes a second power signal line at least partially located in the display area, and the second power signal line includes a first line, a second line, and a third line;

[0013] The first wiring is electrically connected to the first portion, and the first wiring is used to input the first signal to the first portion;

[0014] The second wiring is electrically connected to the second portion, and the second wiring is used to input the second signal to the second portion; and

[0015] The third wiring is electrically connected to the third portion, and the third wiring is used to input the third signal to the third portion.

[0016] According to some exemplary embodiments, the display substrate further includes a driving circuit layer located between the base substrate and the first electrode layer, the driving circuit layer includes a metal layer, and the second power signal line is located in the metal layer.

[0017] According to some exemplary embodiments, the first electrode layer includes a first connecting portion, a second connecting portion and a third connecting portion, the first portion is electrically connected to the first routing line through the first connecting portion, the second portion is electrically connected to the second routing line through the second connecting portion, and the third portion is electrically connected to the third routing line through the third connecting portion.

[0018] According to some exemplary embodiments, the driving circuit layer includes a third source-drain metal layer, the second power signal line is located in the third source-drain metal layer, and the third source-drain metal layer further includes a plurality of data signal lines and a plurality of first power signal lines extending along the second direction;

[0019] The second power signal line is located in the display area, at least part of the second power signal line is located between the adjacent data signal line and the first power signal line, and / or at least part of the second power signal line is located between two adjacent data signal lines.

[0020] According to some exemplary embodiments, the driving circuit layer further includes a second source-drain metal layer located on a side of the third source-drain metal layer close to the base substrate, and a first source-drain metal layer located on a side of the second source-drain metal layer close to the base substrate;

[0021] The peripheral area includes a first side area located outside the display area along the second direction, the first source-drain metal layer includes a first signal input portion, a second signal input portion, and a third signal input portion located in the first side area, and the second source-drain metal layer includes a first signal connection portion, a second signal connection portion, and a third signal connection portion located in the first side area;

[0022] The first signal input portion is electrically connected to the first wiring through the first signal connection portion, and the first signal input portion is used to input the first signal to the first wiring;

[0023] The second signal input portion is electrically connected to the second wiring through the second signal connection portion, and the second signal input portion is used to input the second signal to the second wiring; and

[0024] The third signal input portion is electrically connected to the third wiring through the third signal connection portion, and the third signal input portion is used to input the third signal to the third wiring.

[0025] According to some exemplary embodiments, the first signal connection portion, the second signal connection portion, and the third signal connection portion extend along the first direction and are spaced apart along the second direction, and the second power signal line extends along the second direction;

[0026] One end of the first wiring is overlapped with the first signal connection portion, one end of the second wiring is overlapped with the second signal connection portion, and one end of the third wiring is overlapped with the third signal connection portion.

[0027] According to some exemplary embodiments, a first insulating layer is provided between the first source-drain metal layer and the second source-drain metal layer, and a second insulating layer is provided between the second source-drain metal layer and the third source-drain metal layer;

[0028] The first insulating layer has a plurality of first via holes, the first signal connection portion is overlapped with the first signal input portion through a portion of the first via holes, the second signal connection portion is overlapped with the second signal input portion through a portion of the first via holes, and the third signal connection portion is overlapped with the third signal input portion through a portion of the first via holes;

[0029] The second insulating layer has a plurality of second vias, the first wiring passes through some of the second vias to overlap with the first signal connection portion, the second wiring passes through some of the second vias to overlap with the second signal connection portion, and the third wiring passes through some of the second vias to overlap with the third signal connection portion;

[0030] The orthographic projection of each of the first via holes on the base substrate is spaced apart from the orthographic projection of each of the second via holes on the base substrate.

[0031] According to some exemplary embodiments, a first portion includes the second electrode of a first light-emitting element, a second portion includes the second electrode of a second light-emitting element, and a third portion includes the second electrode of a third light-emitting element.

[0032] According to some exemplary embodiments, the partition layer is in a grid shape, and includes a first opening, a second opening, and a third opening. The first part is embedded in the first opening, the second part is embedded in the second opening, and the third part is embedded in the third opening.

[0033] According to some exemplary embodiments, the first portion includes a plurality of second electrodes spaced apart along the first direction, two adjacent second electrodes are electrically connected via a bridge portion, and the first portion serves as a plurality of second electrodes of a plurality of first light-emitting elements spaced apart along the first direction;

[0034] The second portion includes a plurality of second electrodes spaced apart along the first direction, two adjacent second electrodes are electrically connected via a bridge portion, and the second portion serves as a plurality of second electrodes of a plurality of second light-emitting elements spaced apart along the first direction; and

[0035] The third portion includes a plurality of second electrodes spaced apart along the first direction, two adjacent second electrodes are electrically connected via a bridge portion, and the third portion serves as a plurality of second electrodes of the plurality of third light-emitting elements spaced apart along the first direction.

[0036] According to some exemplary embodiments, the partition layer includes a plurality of partition portions spaced apart along the second direction, each of the partition portions is in the shape of a strip extending along the first direction, and the first portion, the second portion and the third portion are independently located between two adjacent partition portions.

[0037] According to some exemplary embodiments, the first portion includes a plurality of second electrodes spaced apart along the second direction, two adjacent second electrodes are electrically connected via a bridge portion, and the first portion serves as a plurality of second electrodes of a plurality of first light-emitting elements spaced apart along the second direction;

[0038] The second portion includes a plurality of second electrodes spaced apart along the second direction, two adjacent second electrodes are electrically connected via a bridge portion, and the second portion serves as a plurality of second electrodes of a plurality of second light-emitting elements spaced apart along the second direction; and

[0039] The third portion includes a plurality of second electrodes spaced apart along the second direction, two adjacent second electrodes are electrically connected via a bridge portion, and the third portion serves as a plurality of second electrodes of the plurality of third light-emitting elements spaced apart along the second direction.

[0040] According to some exemplary embodiments, the partition layer includes a plurality of partition portions spaced apart along a first direction, each partition portion is in the shape of a strip extending along the second direction, and the first portion, the second portion and the third portion are independently located between two adjacent partition portions.

[0041] According to some exemplary embodiments, the peripheral area includes a second side area and a third side area located on both sides of the display area along the first direction, and the display substrate further includes a first side signal input structure, a second side signal input structure, and a third side signal input structure;

[0042] The first side signal input structure is located in the second peripheral area and / or the third peripheral area, is electrically connected to the first portion, and is used to input the first signal to the first portion;

[0043] the second side signal input structure is located in the second peripheral area and / or the third peripheral area, the second side signal input structure is electrically connected to the second portion, and the second side signal input structure is used to input the second signal to the second portion; and

[0044] The third side signal input structure is located in the second peripheral area and / or the third peripheral area, the third side signal input structure is electrically connected to the third part, and the third side signal input structure is used to input the third signal to the third part.

[0045] According to some exemplary embodiments, the first side signal input structure includes a first-layer first side signal portion located in the first electrode layer, a second-layer first side signal portion located in the third source / drain metal layer, a third-layer first side signal portion located in the second source / drain metal layer, and a fourth-layer first side signal portion located in the first source / drain metal layer, the first portion extends to the peripheral area and overlaps with the first-layer first side signal portion, the first-layer first side signal portion overlaps with the second-layer first side signal portion, the second-layer first side signal portion overlaps with the third-layer first side signal portion, and the third-layer first side signal portion overlaps with the fourth-layer first side signal portion;

[0046] The second side signal input structure includes a first-layer second side signal portion located in the first electrode layer, a second-layer second side signal portion located in the third source / drain metal layer, a third-layer second side signal portion located in the second source / drain metal layer, and a fourth-layer second side signal portion located in the first source / drain metal layer, the second portion extends to the peripheral area and overlaps with the first-layer second side signal portion, the first-layer second side signal portion overlaps with the second-layer second side signal portion, the second-layer second side signal portion overlaps with the third-layer second side signal portion, and the third-layer second side signal portion overlaps with the fourth-layer second side signal portion;

[0047] The third side signal input structure includes a first-layer third side signal portion located in the first electrode layer, a second-layer third side signal portion located in the third source / drain metal layer, a third-layer third side signal portion located in the second source / drain metal layer, and a fourth-layer third side signal portion located in the first source / drain metal layer. The third portion extends to the peripheral area and overlaps with the first-layer third side signal portion, the first-layer third side signal portion overlaps with the second-layer third side signal portion, the second-layer third side signal portion overlaps with the third-layer third side signal portion, and the third-layer third side signal portion overlaps with the fourth-layer third side signal portion.

[0048] According to some exemplary embodiments, the peripheral area further includes a corner area, and the corner area includes a first corner area connecting the first side area and the second side area and a second corner area connecting the first side area and the third side area;

[0049] The first side signal portion of the third layer is directly connected to the first signal connection portion in the corner area, and / or the first side signal portion of the fourth layer is directly connected to the first signal input portion in the corner area;

[0050] The second side signal portion of the third layer is directly connected to the second signal connection portion in the corner area, and / or the second side signal portion of the fourth layer is directly connected to the second signal input portion in the corner area; and

[0051] The third-layer third-side signal portion is directly connected to the third signal connection portion in the corner area, and / or the fourth-layer third-side signal portion is directly connected to the third signal input portion in the corner area.

[0052] According to some exemplary embodiments, the display substrate includes m light-emitting units arranged at intervals along the first direction, and one light-emitting unit includes a first light-emitting group, a first second light-emitting group, a third light-emitting group, and a second second light-emitting group arranged along the first direction;

[0053] The first light-emitting group includes n first light-emitting elements and n third light-emitting elements, and the n first light-emitting elements and the n third light-emitting elements are alternately arranged along the second direction;

[0054] The second light-emitting group includes 2n second light-emitting elements arranged at intervals along the second direction;

[0055] The third light-emitting group includes n third light-emitting elements and n first light-emitting elements, and the n third light-emitting elements and the n first light-emitting elements are alternately arranged along the second direction, where n and m are positive integers;

[0056] Wherein, one of the first parts includes the second electrode of one of the first light-emitting elements, and one of the first parts is electrically connected to one of the first traces through one of the first connecting portions;

[0057] One second portion includes one second electrode of the second light-emitting element, and one second portion is electrically connected to one second trace through one second connecting portion; and

[0058] One of the third parts includes the second electrode of one of the third light-emitting elements, and one of the third parts is electrically connected to one of the third traces through one of the third connecting portions.

[0059] According to some exemplary embodiments, in one first light-emitting group, n first portions of n first light-emitting elements are electrically connected to one first trace through n first connecting portions, and n third portions of n third light-emitting elements are electrically connected to one third trace through n third connecting portions.

[0060] In one second light-emitting group, 2n second parts of 2n second light-emitting elements are electrically connected to one second wiring through 2n second connecting portions respectively; and

[0061] In a third light-emitting group, the n third parts of the n third light-emitting elements are electrically connected to one third routing line through n third connecting portions, and the n first parts of the n first light-emitting elements are electrically connected to one first routing line through n first connecting portions.

[0062] According to some exemplary embodiments, the second power signal line includes m routing groups arranged at intervals along the first direction, one routing group includes a first second routing line, a first routing line, a second second routing line, and a third routing line arranged at intervals along the first direction, and one routing group is electrically connected to one light-emitting unit;

[0063] In one of the electrically connected wiring groups and one of the light-emitting units, the first second wiring and the orthographic projection of the first wiring on the substrate overlap with the orthographic projection of the first second light-emitting group on the substrate, and the orthographic projection of the second second wiring and the third wiring on the substrate overlap with the orthographic projection of the second second light-emitting group on the substrate;

[0064] In the first light-emitting group, the n first portions of the n first light-emitting elements are electrically connected to the first trace in the trace group adjacent to the first-second trace on a side away from the first trace through the n first connecting portions, and the n third portions of the n third light-emitting elements are electrically connected to the third trace in the trace group adjacent to the first-second trace on a side away from the first trace through the n third connecting portions.

[0065] In the first second light-emitting group, 2n second parts of 2n second light-emitting elements are electrically connected to the first second trace through 2n second connecting portions respectively;

[0066] In the third light-emitting group, the n first portions of the n first light-emitting elements are electrically connected to the first wiring through the n first connecting portions, and the n third portions of the n third light-emitting elements are electrically connected to the third wiring through the n third connecting portions.

[0067] In the second second light-emitting group, the 2n second parts of the 2n second light-emitting elements are electrically connected to the second second trace through the 2n second connecting portions respectively.

[0068] According to some exemplary embodiments, the second power signal line includes m routing groups arranged at intervals along the first direction, one routing group includes a first second routing line, a first routing line, a second second routing line, and a third routing line arranged at intervals along the first direction, and one routing group is electrically connected to one light-emitting unit;

[0069] In one of the electrically connected wiring groups and one of the light-emitting units, the first second wiring and the orthographic projection of the first wiring on the substrate overlap with the orthographic projection of the first second light-emitting group on the substrate, and the orthographic projection of the second second wiring and the third wiring on the substrate overlap with the orthographic projection of the second second light-emitting group on the substrate;

[0070] In the first light-emitting group, the n first portions of the n first light-emitting elements are electrically connected to the first routing line through the n first connecting portions, and the n third portions of the n third light-emitting elements are electrically connected to the third routing line in the routing line group adjacent to the first second routing line on a side away from the first routing line through the n third connecting portions.

[0071] In the first second light-emitting group, 2n second parts of 2n second light-emitting elements are electrically connected to the first second trace through 2n second connecting portions respectively;

[0072] In the third light-emitting group, the n first portions of the n first light-emitting elements are electrically connected to the first wiring through the n first connecting portions, and the n third portions of the n third light-emitting elements are electrically connected to the third wiring through the n third connecting portions.

[0073] In the second second light-emitting group, the 2n second parts of the 2n second light-emitting elements are electrically connected to the second second trace through the 2n second connecting portions respectively.

[0074] According to some exemplary embodiments, the display substrate includes n light-emitting units arranged at intervals along the second direction, and one light-emitting unit includes a first light-emitting group, a second light-emitting group, a third light-emitting group, and a second light-emitting group arranged along the second direction;

[0075] The first light-emitting group includes m first light-emitting elements and m third light-emitting elements, and the m first light-emitting elements and the m third light-emitting elements are alternately arranged along the first direction;

[0076] The second light-emitting group includes 2m second light-emitting elements arranged at intervals along the first direction;

[0077] The third light-emitting group includes m third light-emitting elements and m first light-emitting elements, and the m third light-emitting elements and the m first light-emitting elements are alternately arranged along the first direction, where n and m are positive integers;

[0078] The first portion includes a first sub-portion and a second sub-portion, wherein one first sub-portion includes m second electrodes of m first light-emitting elements in the first light-emitting group, and one second sub-portion includes m second electrodes of m first light-emitting elements in the third light-emitting group;

[0079] One second portion includes 2m second electrodes of 2m second light-emitting elements in one second light-emitting group;

[0080] The third part includes a third sub-part and a fourth sub-part, wherein one third sub-part includes m second electrodes of m third light-emitting elements in the first light-emitting group, and one fourth sub-part includes m second electrodes of m third light-emitting elements in the third light-emitting group.

[0081] According to some exemplary embodiments, one of the first sub-sections is electrically connected to m1 of the first routing lines through m1 of the first connecting parts, one of the second sub-sections is electrically connected to m2 of the first routing lines through m2 of the first connecting parts, one of the second sub-sections is electrically connected to 2m3 of the second routing lines through 2m3 of the second connecting parts, one of the third sub-sections is electrically connected to m4 of the third routing lines through m4 of the third connecting parts, and one of the fourth sub-sections is electrically connected to m5 of the third routing lines through m5 of the third connecting parts, and m1, m2, m3, m4, and m5 are independently selected from positive integers less than or equal to m.

[0082] According to some exemplary embodiments, the second power signal line includes m routing groups arranged at intervals along the first direction, one routing group includes a second routing line, a first routing line, a second routing line, and a third routing line arranged at intervals along the first direction, and an orthographic projection of the routing group on the base substrate partially overlaps with an orthographic projection of the second light-emitting group on the base substrate;

[0083] Among them, one second part is electrically connected to 2m second routing lines through 2m second connecting parts, one end of a second connecting part overlaps with one second part and the other end extends away from the first side area and overlaps with the adjacent second routing line.

[0084] According to some exemplary embodiments, the second power signal line includes m routing groups arranged at intervals along the first direction, one routing group includes a second routing line, a first routing line, a second routing line, and a third routing line arranged at intervals along the first direction, and an orthographic projection of the routing group on the base substrate partially overlaps with an orthographic projection of the second light-emitting group on the base substrate;

[0085] Among them, one second part is electrically connected to 2m second routing lines through 2m second connecting parts, one end of a second connecting part overlaps with one second part and the other end extends toward the direction close to the first side area and overlaps with the adjacent second routing line.

[0086] According to some exemplary embodiments, the display substrate includes m light-emitting units arranged at intervals along the first direction, and one light-emitting unit includes a first light-emitting group, a second light-emitting group, a third light-emitting group, and a second light-emitting group arranged along the first direction;

[0087] The first light-emitting group includes n first light-emitting elements and n third light-emitting elements, and the n first light-emitting elements and the n third light-emitting elements are alternately arranged along the second direction;

[0088] The second light-emitting group includes 2n second light-emitting elements arranged at intervals along the second direction;

[0089] The third light-emitting group includes n third light-emitting elements and n first light-emitting elements, and the n third light-emitting elements and the n first light-emitting elements are alternately arranged along the second direction, where n and m are positive integers;

[0090] The first portion includes a first sub-portion and a second sub-portion, wherein one first sub-portion includes n second electrodes of n first light-emitting elements in the first light-emitting group, and one second sub-portion includes n second electrodes of n first light-emitting elements in the third light-emitting group;

[0091] One second portion includes 2n second electrodes of 2n second light-emitting elements in one second light-emitting group;

[0092] The third part includes a third sub-part and a fourth sub-part, wherein one third sub-part includes n second electrodes of n third light-emitting elements in the first light-emitting group, and one fourth sub-part includes n second electrodes of n third light-emitting elements in the third light-emitting group.

[0093] According to some exemplary embodiments, one of the first sub-sections is electrically connected to n1 of the first routing lines through n1 of the first connecting parts, one of the second sub-sections is electrically connected to n2 of the first routing lines through n2 of the first connecting parts, one of the second sub-sections is electrically connected to 2n3 of the second routing lines through 2n3 of the second connecting parts, one of the third sub-sections is electrically connected to n4 of the third routing lines through n4 of the third connecting parts, and one of the fourth sub-sections is electrically connected to n5 of the third routing lines through n5 of the third connecting parts, and n1, n2, n3, n4, and n5 are independently selected from positive integers less than or equal to n.

[0094] According to some exemplary embodiments, the light-emitting element layer further includes a first functional layer located between the first electrode layer and the light-emitting layer, and a second functional layer located between the second electrode layer and the light-emitting layer;

[0095] The first functional layer includes a plurality of first functional parts arranged at intervals, and at least one partition part is provided between two adjacent first functional parts; the second functional layer includes a plurality of second functional parts arranged at intervals, and at least one partition part is provided between two adjacent second functional parts.

[0096] According to some exemplary embodiments, the first light emitting element emits red light, the second light emitting element emits green light, the third light emitting element emits blue light, the absolute value of the third signal is greater than the absolute value of the first signal, and the absolute value of the first signal is greater than the absolute value of the second signal.

[0097] In another aspect, a display substrate is provided, comprising:

[0098] A base substrate, comprising a display area and a peripheral area located outside the display area;

[0099] a plurality of sub-pixels disposed in a display area of ​​the base substrate, the plurality of sub-pixels being arranged in an array along a first direction and / or a second direction, the plurality of sub-pixels comprising a first sub-pixel and a second sub-pixel, the first sub-pixel comprising a first light-emitting element, the second sub-pixel comprising a second light-emitting element, the first light-emitting element and the second light-emitting element respectively comprising a first electrode, a light-emitting portion, and a second electrode;

[0100] A first electrode layer is provided on the base substrate, wherein the first electrode is located in the first electrode layer;

[0101] a pixel defining layer disposed on a side of the first electrode layer away from the base substrate, the pixel defining layer defining a plurality of pixel openings, the plurality of pixel openings including a first pixel opening and a second pixel opening;

[0102] a partition layer disposed on a side of the pixel defining layer away from the base substrate, the partition layer comprising a plurality of partition portions, an orthographic projection of the partition layer on the base substrate at least partially overlapping with an orthographic projection of the pixel defining layer on the base substrate; and

[0103] A second electrode layer is provided on a side of the partition layer away from the base substrate, wherein the second electrode is located in the second electrode layer.

[0104] The width of the partition portion at a side away from the base substrate is greater than the width at a side close to the base substrate;

[0105] The second electrode layer includes a first portion, a second portion, and a fourth portion that are spaced apart from each other, an orthographic projection of the first portion on the base substrate at least partially overlaps with an orthographic projection of the first pixel opening on the base substrate, an orthographic projection of the second portion on the base substrate at least partially overlaps with an orthographic projection of the second pixel opening on the base substrate, and an orthographic projection of the fourth portion on the base substrate at least partially overlaps with an orthographic projection of the partition portion on the base substrate; and

[0106] The adjacent first portion and the fourth portion are disconnected at one side edge of the partition portion, and the adjacent second portion and the fourth portion are disconnected at the other side edge of the partition portion.

[0107] In another aspect, a display device is provided, comprising the above-mentioned display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0108] Other objects and advantages of the present disclosure will become apparent from the following description of the present disclosure with reference to the accompanying drawings, which will help to provide a comprehensive understanding of the present disclosure.

[0109] FIG1 schematically shows a plan view of a display panel according to an embodiment of the present disclosure.

[0110] FIG. 2 shows a partially enlarged schematic diagram of the area Z in FIG. 1 .

[0111] FIG3 shows a schematic cross-sectional view taken along line A1 - A2 of FIG2 .

[0112] FIG. 4 is an equivalent circuit diagram of one pixel driving circuit of a display substrate according to some exemplary embodiments of the present disclosure.

[0113] 5A to 5V are plan views of some film layers in a display substrate located in a display area according to some exemplary embodiments of the present disclosure;

[0114] 5A schematically illustrates a light-shielding layer, FIG5B schematically illustrates a combination of a light-shielding layer and a first active layer, FIG5C schematically illustrates a combination of a light-shielding layer, a first active layer and a first gate metal layer, FIG5D schematically illustrates a combination of a light-shielding layer, a first active layer, a first gate metal layer and a second gate metal layer, FIG5E schematically illustrates a combination of a light-shielding layer, a first active layer, a first gate metal layer, a second gate metal layer and a second active layer, FIG5F schematically illustrates a combination of a light-shielding layer, a first active layer, a first gate metal layer, a second gate metal layer, a second active layer and a third gate metal layer, and FIG5G schematically illustrates a light-shielding layer, FIG5H illustrates a combination of a light shielding layer, a first active layer, a first gate metal layer, a second gate metal layer, a second active layer, a third gate metal layer and an interlayer insulating layer, and illustrates some vias in the interlayer insulating layer. FIG5I illustrates a combination of a light shielding layer, a first active layer, a first gate metal layer, a second gate metal layer, a second active layer, a third gate metal layer and an interlayer insulating layer, and FIG5J illustrates a combination of a second active layer, a third gate metal layer and an interlayer insulating layer. FIG5K illustrates a combination of a first active layer, a first gate metal layer, a second gate metal layer, an interlayer insulating layer and a first source / drain metal layer, FIG5L illustrates a combination of a first source / drain metal layer and a passivation layer, FIG5M illustrates a combination of a first source / drain metal layer, a passivation layer and a first planarization layer, FIG5N illustrates a combination of a first source / drain metal layer and a second source / drain metal layer, FIG5O illustrates a combination of a first source / drain metal layer, a second source / drain metal layer and a second planarization layer, and FIG5P illustrates a combination of a first source / drain metal layer, a second source / drain metal layer and a second planarization layer. Figure 5Q illustrates the combination of the third source-drain metal layer and the third planarization layer, Figure 5R illustrates the combination of the third source-drain metal layer and the first electrode layer, Figure 5S illustrates the combination of the third source-drain metal layer, the first electrode layer and the pixel defining layer, Figure 5T illustrates the combination of the third source-drain metal layer, the first electrode layer, the pixel defining layer and the spacer layer, Figure 5U illustrates the combination of the first electrode layer, the pixel defining layer and the spacer layer, and Figure 5V illustrates the combination of the first electrode layer, the pixel defining layer and the second electrode layer.

[0115] 6A-6E are plan views of some film layers in a display substrate located in a display area according to some exemplary embodiments of the present disclosure;

[0116] Figure 6A illustrates a combination of a third source-drain metal layer and a third planarization layer, Figure 6B illustrates a combination of a third source-drain metal layer and a first electrode layer, Figure 6C illustrates a combination of a third source-drain metal layer, a first electrode layer and a pixel defining layer, Figure 6D illustrates a combination of a third source-drain metal layer, a first electrode layer, a pixel defining layer and a spacer layer, and Figure 6E illustrates a combination of a third source-drain metal layer, a first electrode layer, a pixel defining layer, a spacer layer and a second electrode layer.

[0117] 7A-7F are plan views showing some film layers in a display substrate located in a peripheral area according to some exemplary embodiments of the present disclosure;

[0118] Figure 7A illustrates a first source-drain metal layer, Figure 7B illustrates a combination of the first source-drain metal layer and a passivation layer, Figure 7C illustrates a combination of the first source-drain metal layer, the passivation layer and the first planarization layer, Figure 7D illustrates a combination of the first source-drain metal layer and the second source-drain metal layer, Figure 7E illustrates a combination of the first source-drain metal layer, the second source-drain metal layer and the second planarization layer, and Figure 7F illustrates the first source-drain metal layer, the second source-drain metal layer, the second planarization layer and the third source-drain metal layer.

[0119] 8A-8F are plan views of some film layers in a display substrate located in a display area according to some exemplary embodiments of the present disclosure;

[0120] Among them, Figure 8A illustrates a combination of a third source-drain metal layer and a third planarization layer, Figure 8B illustrates a combination of a third source-drain metal layer and a first electrode layer, Figure 8C illustrates a combination of a third source-drain metal layer, a first electrode layer and a pixel defining layer, Figure 8D illustrates a combination of a third source-drain metal layer, a first electrode layer, a pixel defining layer and a spacer layer, Figure 8E illustrates a combination of a first electrode layer, a pixel defining layer and a spacer layer, and Figure 8F illustrates a combination of a first electrode layer, a pixel defining layer and a second electrode layer.

[0121] 9A-9E are plan views of some film layers in a display substrate located in a display area according to some exemplary embodiments of the present disclosure;

[0122] Among them, Figure 9A illustrates a combination of a third source-drain metal layer and a third planarization layer, Figure 9B illustrates a combination of a third source-drain metal layer and a first electrode layer, Figure 9C illustrates a combination of a third source-drain metal layer, a first electrode layer and a pixel defining layer, Figure 9D illustrates a combination of a third source-drain metal layer, a first electrode layer, a pixel defining layer and a spacer layer, and Figure 9E illustrates a combination of a third source-drain metal layer, a first electrode layer, a pixel defining layer, a spacer layer and a second electrode layer.

[0123] 10A-10M are plan views of some film layers in a display substrate located in a peripheral area according to some exemplary embodiments of the present disclosure;

[0124] 10A illustrates a first source-drain metal layer, FIG10B illustrates a combination of a first source-drain metal layer and a passivation layer, FIG10C illustrates a combination of a first source-drain metal layer, a passivation layer and a first planarization layer, FIG10D illustrates a combination of a first source-drain metal layer and a second source-drain metal layer, FIG10E illustrates a combination of a first source-drain metal layer, a second source-drain metal layer and a second planarization layer, FIG10F illustrates a combination of a first source-drain metal layer, a second source-drain metal layer, a second planarization layer and a third source-drain metal layer, and FIG10G illustrates a first A combination of a source-drain metal layer, a second source-drain metal layer, a third source-drain metal layer and a third planarization layer, FIG10H illustrates a combination of the first source-drain metal layer, the second source-drain metal layer, the third source-drain metal layer and the first electrode layer, FIG10I illustrates a combination of the first electrode layer and the pixel defining layer, FIG10J illustrates a spacer layer, FIG10K illustrates a combination of the first electrode layer, the pixel defining layer and the spacer layer, FIG10L illustrates a second electrode layer, and FIG10M illustrates a combination of the first electrode layer, the pixel defining layer, the spacer layer and the second electrode layer.

[0125] 11A to 11F are plan views of some film layers in a display substrate located in a display area according to some exemplary embodiments of the present disclosure;

[0126] Among them, Figure 11A illustrates a combination of a third source-drain metal layer and a third planarization layer, Figure 11B illustrates a combination of a third source-drain metal layer and a first electrode layer, Figure 11C illustrates a combination of a third source-drain metal layer, a first electrode layer and a pixel defining layer, Figure 11D illustrates a combination of a third source-drain metal layer, a first electrode layer, a pixel defining layer and a spacer layer, Figure 11E illustrates a combination of a first electrode layer, a pixel defining layer and a spacer layer, and Figure 11F illustrates a combination of a first electrode layer, a pixel defining layer and a second electrode layer.

[0127] It should be noted that, for the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the sizes of layers, structures or regions may be enlarged or reduced, that is, these drawings are not drawn according to the actual scale. DETAILED DESCRIPTION

[0128] In the following description, for the purpose of explanation, many specific details are set forth to provide a comprehensive understanding of the various exemplary embodiments. However, it is apparent that the various exemplary embodiments can be implemented without these specific details or with one or more equivalent arrangements. In other cases, well-known structures and devices are shown in block diagram form to avoid unnecessarily obscuring the various exemplary embodiments. In addition, the various exemplary embodiments can be different, but not necessarily exclusive. For example, the specific shape, configuration, and characteristics of the exemplary embodiment can be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0129] In the accompanying drawings, the sizes and relative sizes of the elements may be exaggerated for clarity and / or descriptive purposes. Thus, the sizes and relative sizes of the individual elements are not necessarily limited to those shown in the drawings. When the exemplary embodiments can be implemented differently, the specific process sequence can be performed differently from the described sequence. For example, two processes described in succession can be performed substantially simultaneously or in an order opposite to the described sequence. In addition, the same reference numerals represent the same elements.

[0130] When an element is described as being "on" another element, "connected to" another element, or "coupled to" another element, the element may be directly on, directly connected to, or directly coupled to another element, or there may be an intermediate element. However, when an element is described as being "directly on" another element, "directly connected to," or "directly coupled to," another element, there is no intermediate element. Other terms and / or expressions used to describe the relationship between elements should be interpreted in a similar manner, for example, "between" versus "directly between," "adjacent" versus "directly adjacent," or "on" versus "directly on," etc. In addition, the term "connected" may refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. In addition, the X-axis, the Y-axis, and the Z-axis are not limited to the three axes of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the X-axis, the Y-axis, and the Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XY, YZ, and XZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0131] It should be understood that although the terms first, second, etc. may be used herein to describe different elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. For example, a first element may be named a second element, and similarly, a second element may be named a first element without departing from the scope of the exemplary embodiments.

[0132] An OLED display device includes red, blue, and green OLED devices. Research has found that the red, blue, and green OLED devices require different light-emitting currents. Therefore, the voltage difference between the first power supply voltage signal connected to the anode side and the second power supply voltage signal connected to the cathode side required by OLED devices of different colors is also different. Typically, the blue OLED device requires the largest voltage difference, followed by the red OLED device, and the green OLED device requires the smallest voltage difference. However, in related art, the OLED devices in an OLED display device share a common cathode, meaning that the cathodes of the various OLED devices are connected to the same second power supply voltage signal. This inevitably results in a surplus voltage difference between the red and green OLED devices in order to meet the voltage difference requirement of the blue OLED device, leading to wasted power consumption of the second power supply voltage signal.

[0133] FIG1 schematically shows a plan view of a display panel according to an embodiment of the present disclosure, FIG2 shows a partially enlarged schematic view of area Z in FIG1 , and FIG3 shows a cross-sectional schematic view along line A1 - A2 in FIG2 .

[0134] 1 , the display substrate includes a base substrate 100. The base substrate 100 may include a display area AA and a peripheral area NA located on at least one side of the display area. It should be noted that in the embodiment shown in FIG1 , the peripheral area NA surrounds the display area AA. However, the embodiments of the present disclosure are not limited thereto. In other embodiments, the peripheral area NA may be located on at least one side of the display area AA but may not surround the display area AA.

[0135] 2 and 3 , the display substrate may include a light-emitting element layer 200 on a base substrate 100. The light-emitting element layer 200 includes a plurality of light-emitting elements located in a display area AA. The plurality of light-emitting elements are arranged in an array along a first direction X and / or a second direction Y. The plurality of light-emitting elements include a plurality of first light-emitting elements E1, a plurality of second light-emitting elements E2, and a plurality of third light-emitting elements E3.

[0136] The light-emitting element layer 200 includes a first electrode layer ANE located on the base substrate 100, a light-emitting layer EL located on the side of the first electrode layer ANE away from the base substrate 100, and a second electrode layer Cath located on the side of the light-emitting layer EL away from the base substrate 100. The first electrode layer ANE includes a first electrode F1 of each light-emitting element, the light-emitting layer EL includes a light-emitting portion EL1 of each light-emitting element, and the second electrode layer Cath includes a second electrode F2 of each light-emitting element.

[0137] The display substrate further includes a pixel definition layer (PDL) disposed on a side of the first electrode layer ANE away from the base substrate 100. The pixel definition layer (PDL) defines a plurality of pixel openings, including a first pixel opening K1, a second pixel opening K2, and a third pixel opening K3. The first pixel opening K1 exposes a portion of the first electrode F1 of the first light-emitting element E1, the second pixel opening K2 exposes a portion of the first electrode F1 of the second light-emitting element E2, and the third pixel opening K3 exposes a portion of the first electrode F1 of the third light-emitting element E3. Each light-emitting portion EL1 is located within a corresponding pixel opening.

[0138] Continuing with FIG. 3 , the display substrate may further include an isolating layer 300 positioned between the first electrode layer ANE and the second electrode layer Cath. For example, the isolating layer 300 may be disposed on the side of the pixel defining layer PDL facing away from the base substrate 100. The orthographic projection of the isolating layer 300 on the base substrate 100 at least partially overlaps with the orthographic projection of the pixel defining layer on the base substrate 100. The isolating layer 300 includes a plurality of isolating portions 301, which divide the second electrode layer Cath into at least one first portion CA1, at least one second portion CA2, at least one third portion CA3, and at least one fourth portion CA4, which are spaced apart from each other. At least one isolating portion 301 is disposed between any two of the at least one first portion CA1, at least one second portion CA2, at least one third portion CA3, and at least one fourth portion CA4.

[0139] The orthographic projection of the first portion CA1 on the substrate 100 at least partially overlaps with the orthographic projection of the first pixel opening K1 on the substrate 100. The first portion CA1 includes the second electrode F2 of at least one first light-emitting element E1 and is configured to receive a first signal. The orthographic projection of the second portion CA2 on the substrate 100 at least partially overlaps with the orthographic projection of the second pixel opening K2 on the substrate 100. The second portion CA2 includes the second electrode F2 of at least one second light-emitting element E2 and is configured to receive a second signal. The orthographic projection of the third portion CA3 on the substrate 100 at least partially overlaps with the orthographic projection of the third pixel opening K3 on the substrate 100. The third portion CA3 includes the second electrode F2 of at least one third light-emitting element E3 and is configured to receive a third signal. At least two of the first, second, and third signals are different from each other. The orthographic projection of the fourth portion CA4 on the substrate 100 at least partially overlaps with the orthographic projection of the partition portion 301 on the substrate 100.

[0140] By providing a partition portion 301, the second electrode layer Cath is divided into a first portion CA1, a second portion CA2, and a third portion CA3. Thus, according to the different light-emitting current requirements of the first light-emitting element E1, the second light-emitting element E2, and the third light-emitting element E3, the second power supply signals required by each portion can be independently connected to the first portion CA1, the second portion CA2, and the third portion CA3, thereby avoiding power consumption waste of the second power supply voltage signal, and thus helping to reduce the power consumption of the display substrate.

[0141] For example, the substrate 101 may be a flexible substrate or a rigid substrate. The rigid substrate may be, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.

[0142] For example, the light emitting element may be an OLED device, the first electrode layer ANE may be an anode layer, and the second electrode layer Cath may be a cathode layer.

[0143] For example, the material of the first electrode layer ANE may include at least one transparent conductive oxide material, including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), etc. In addition, the first electrode layer ANE may include a metal with high reflectivity as a reflective layer, such as silver (Ag).

[0144] Exemplarily, the second electrode layer Cath may include various conductive materials, such as lithium (Li), aluminum (Al), magnesium (Mg), silver (Ag), or alloys thereof.

[0145] Exemplarily, the material of the light-emitting layer EL may include a small molecule organic material or a polymer molecule organic material, may be a fluorescent light-emitting material or a phosphorescent light-emitting material, and may emit red light, green light, blue light, or white light.

[0146] According to some exemplary embodiments, the first light-emitting element E1 emits red light, the second light-emitting element E2 emits green light, and the third light-emitting element E3 emits blue light. The absolute value of the third signal is greater than the absolute value of the first signal, and the absolute value of the first signal is greater than the absolute value of the second signal. Exemplarily, the voltage values ​​of the first signal, the second signal, and the third signal are all negative. Therefore, the third signal is smaller than the first signal, and the first signal is smaller than the second signal.

[0147] According to some exemplary embodiments, with continued reference to FIG. 3 , the light-emitting element layer 200 further includes a first functional layer 400 located between the first electrode layer ANE and the light-emitting layer EL, and a second functional layer 500 located between the second electrode layer Cath and the light-emitting layer EL. The first functional layer 400 includes a plurality of first functional portions 401 spaced apart from each other, with at least one partition 301 disposed between two adjacent first functional portions 401. The second functional layer 500 includes a plurality of second functional portions 501 spaced apart from each other, with at least one partition 301 disposed between two adjacent second functional portions 501. The distribution of the plurality of first functional portions 401 and the plurality of second functional portions 501 is similar to the distribution of the first portion CA1, the second portion CA2, and the third portion in the second electrode layer Cath. That is, in a direction perpendicular to the base substrate 100, a first functional portion 401 and a second functional portion 501 are respectively arranged on both sides of a first portion CA1, a first functional portion 401 and a second functional portion 501 are respectively arranged on both sides of a second portion CA2, and a first functional portion 401 and a second functional portion 501 are respectively arranged on both sides of a third portion CA3.

[0148] It should be noted that the partitioning portion 301 can be formed after the pixel definition layer (PDL) and before the first functional layer 400. Therefore, when forming the first functional layer 400 and the second functional layer 500, the partitioning portion 301 divides the first functional layer 400 and the second functional layer 500 into a plurality of first functional portions 401 and a plurality of second functional portions 501. In other words, the partitioning portion 301 further separates the conductive first functional layer 400 and the second functional layer 500 into a plurality of independent portions, thereby cutting off the leakage current transmission path between the first light-emitting element E1, the second light-emitting element E2, and the third light-emitting element E3 along the first functional layer 400 and the second functional layer 500, thereby effectively preventing color crosstalk between different light-emitting elements.

[0149] According to some exemplary embodiments, the width of the partition portion 301 on the side away from the base substrate 100 is greater than the width on the side closer to the base substrate 100. In this case, the cross-sectional shape of each partition portion 301 is, for example, an inverted trapezoid. Forming a cross-sectional shape such as an inverted trapezoid facilitates separating these layers into multiple independent portions during the fabrication of the second electrode layer Cath, the first functional layer 400, and the second functional layer 500. To facilitate forming the partition portion 301 into a cross-sectional shape such as an inverted trapezoid during the fabrication process, the material of the partition portion 301 can include, for example, a negative photoresist.

[0150] According to some exemplary embodiments, the display substrate includes a spacer layer BPS positioned between the first electrode layer ANE and the second electrode layer Cath. The spacer layer BPS includes spacers and a partition portion 301. The partition portion 301 is manufactured using the same manufacturing process as the conventional spacers in the display substrate, simplifying the display substrate manufacturing process. Typically, spacers are used to support the mask during the evaporation process to prevent deformation of the mask due to stress, which could cause the deposition position of the organic material to shift.

[0151] According to some exemplary embodiments, referring to FIG. 2 , the display substrate includes a second power signal line VSS at least partially located in the display area AA. The second power signal line VSS is used to input a second power signal to the second electrode layer Cath. The second power signal includes the aforementioned first, second, and third signals. The second power signal line VSS includes a first trace VSS1, a second trace VSS2, and a third trace VSS3.

[0152] Among them, the first routing VSS1 is electrically connected to the first part CA1, and the first routing VSS1 is used to input the first signal to the first part CA1; the second routing VSS2 is electrically connected to the second part CA2, and the second routing VSS2 is used to input the second signal to the second part CA2; the third routing VSS3 is electrically connected to the third part CA3, and the third routing VSS3 is used to input the third signal to the third part CA3.

[0153] According to some exemplary embodiments, the display substrate further includes a driving circuit layer located between the base substrate 100 and the first electrode layer ANE. The driving circuit layer includes a metal layer, and the second power signal line VSS is located in the metal layer. That is, the second power signal line VSS is located on a side of the first electrode layer ANE closer to the base substrate 100.

[0154] According to some exemplary embodiments, the first electrode layer ANE includes a first connection portion L1, a second connection portion L2 and a third connection portion L3, the first portion CA1 is electrically connected to the first trace VSS1 through the first connection portion L1, the second portion CA2 is electrically connected to the second trace VSS2 through the second connection portion L2, and the third portion CA3 is electrically connected to the third trace VSS3 through the third connection portion L3.

[0155] More specifically, one end of the first connection portion L1 is electrically connected to the first portion CA1 via via H1, and the other end is electrically connected to the first trace VSS1 via via H2. One end of the second connection portion L2 is electrically connected to the second portion CA1 via via H1, and the other end is electrically connected to the second trace VSS2 via via H2. One end of the third connection portion L3 is electrically connected to the third portion CA3 via via H1, and the other end is electrically connected to the third trace VSS3 via via H2. Via H1 is, for example, located in the pixel definition layer PDL between the first electrode layer ANE and the second electrode layer Cath, and via H2 is, for example, located in the planarization layer between the first electrode layer ANE and the metal layer.

[0156] According to some exemplary embodiments, referring to FIG1 and FIG2 , the display substrate includes a plurality of sub-pixels arranged in a display area AA of a base substrate 100, the plurality of sub-pixels are arranged in an array along a first direction X and / or a second direction Y, the plurality of sub-pixels include a first sub-pixel, a second sub-pixel, and a third sub-pixel, the first sub-pixel includes a first light-emitting element E1 and a pixel driving circuit electrically connected to the first light-emitting element E1, the second sub-pixel includes a second light-emitting element E2 and a pixel driving circuit electrically connected to the second light-emitting element E2, and the third sub-pixel includes a third light-emitting element E3 and a pixel driving circuit electrically connected to the third light-emitting element E3.

[0157] FIG. 4 is an equivalent circuit diagram of one pixel driving circuit of a display substrate according to some exemplary embodiments of the present disclosure.

[0158] 4 , the pixel driving circuit includes a storage capacitor C, a first transistor T1 , a second transistor T2 , a third transistor T3 , a fourth transistor T4 , a fifth transistor T5 , a sixth transistor T6 , a seventh transistor T7 and an eighth transistor T8 .

[0159] The storage capacitor C is electrically connected to the first power signal line VDD and the gate of the third transistor T3. Exemplarily, the gate of the third transistor T3 is reused as the first plate Cst1 of the storage capacitor C, and the second plate Cst2 of the storage capacitor C is electrically connected to the first power signal line VDD.

[0160] The gate of the first transistor T1 is electrically connected to the second scan line Scan2 , the first electrode S1 of the first transistor T1 is electrically connected to the second electrode D2 of the third transistor T2 , and the second electrode D1 of the first transistor T1 is electrically connected to the gate of the third transistor T3 .

[0161] The gate of the second transistor T2 is electrically connected to the first reset line R1 , the first electrode S2 of the second transistor T2 is electrically connected to the first initialization signal line Vinit1 , and the second electrode D2 of the second transistor T2 and the first electrode S1 of the first transistor T1 are electrically connected to the third node N3 .

[0162] The third transistor T3 is a driving transistor. The node connected to the gate of the third transistor T3 is the first node N1. The node connected to the first electrode S3 of the third transistor T3 is the second node N2. The node connected to the second electrode D3 of the third transistor T3 is the third node N3.

[0163] The gate of the fourth transistor T4 is electrically connected to the first scan line Scan1, the first electrode S4 of the fourth transistor T4 is electrically connected to the data signal line Data, and the second electrode D4 of the fourth transistor T4 is electrically connected to the first electrode S4 of the third transistor T3, that is, the second electrode D4 of the fourth transistor T4 is electrically connected to the second node N2.

[0164] The gate of the fifth transistor T5 is electrically connected to the light-emitting control line EM, the first electrode S5 of the fifth transistor T5 is electrically connected to the first power signal line VDD, and the second electrode D5 of the fifth transistor T5 is electrically connected to the first electrode S3 of the third transistor T3, that is, the second electrode D5 of the fifth transistor T5 is electrically connected to the second node N2.

[0165] The gate of the sixth transistor T6 is electrically connected to the light emitting control line EM, the first electrode S6 of the sixth transistor T6 is electrically connected to the second electrode D3 of the third transistor T3, that is, the first electrode S6 of the sixth transistor T6 is connected to the third node N3, and the second electrode D6 of the sixth transistor T6 is electrically connected to the light emitting element OLED.

[0166] The gate of the seventh transistor T7 is electrically connected to the third scan line S3, the first electrode S of the seventh transistor T7 is electrically connected to the second initialization signal line Vinit2, and the second electrode D of the seventh transistor T7 is electrically connected to the first electrode of the light-emitting element OLED. In addition, the second electrode of the light-emitting element OLED is electrically connected to the second power signal line VSS.

[0167] The gate of the eighth transistor T8 is electrically connected to the second reset line R2, the first electrode S8 of the eighth transistor T8 is electrically connected to the third initialization signal line Vinit3, and the second electrode D8 of the eighth transistor T8 is electrically connected to the second electrode D3 of the third transistor T3, that is, the second electrode D8 of the eighth transistor T8 is electrically connected to the third node N3.

[0168] In some embodiments, the first transistor T1 and the second transistor T2 are oxide-type thin-film transistors. The third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are low-temperature polysilicon thin-film transistors. That is, the pixel driving circuit may include both low-temperature polysilicon thin-film transistors and oxide-type thin-film transistors.

[0169] In some embodiments, the first transistor T1 and the second transistor T2 are N-channel field effect transistors, and the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are P-channel field effect transistors.

[0170] The driving method of the pixel driving circuit includes three stages: an initialization stage, a data writing stage and a light emitting stage.

[0171] During the initialization phase, the first and second transistors T1 and T2 are turned on and transmit a first initialization signal inputted from the first initialization signal line Vinit1 to the first node N1. The seventh transistor T7 is turned on and transmits a second initialization signal inputted from the second initialization signal line Vinit2 to the first electrode of the light-emitting element OLED. The eighth transistor T8 is turned on and transmits a third initialization signal inputted from the third initialization signal line Vinit3 to the third node N3.

[0172] In the data writing stage: the first transistor T1 and the fourth transistor T4 are turned on, and the data signal line Data writes the compensation voltage Vdata+Vth to the first node N1, where Vdata is the voltage value corresponding to the data signal and Vth is the threshold voltage of the driving transistor.

[0173] In the light emitting stage: the fifth transistor T5 and the sixth transistor T6 are turned on, and the third transistor T3 supplies a driving current Id to the light emitting element OLED under the action of the voltage Vdata+Vth stored in the storage capacitor C to drive the light emitting element OLED to emit light.

[0174] In an embodiment of the present disclosure, the first electrode of the transistor may be a source electrode, and the second electrode of the transistor may be a drain electrode; or, the first electrode of the transistor may be a drain electrode, and the second electrode of the transistor may be a source electrode.

[0175] In the above description, the circuit structure of the 8T1C pixel driving circuit is taken as an example to describe in detail the structure of the pixel driving circuit of each sub-pixel located in the display area AA. However, the embodiments of the present disclosure are not limited to the above-mentioned circuit structure. In the absence of conflict, other known circuit structures can be applied to the embodiments of the present disclosure.

[0176] According to some exemplary embodiments, the display substrate includes a base substrate, and a light-shielding layer LS, an isolation layer, a first active layer Poly, a first gate insulating layer GI1, a first gate metal layer Gate1, a second gate insulating layer GI2, a second gate metal layer Gate2, a third gate insulating layer GI3, a second active layer IGZO, a fourth gate insulating layer GI4, a third gate metal layer Gate3, an interlayer insulating layer ILD, a first source-drain metal layer SD1, a passivation layer PVX, a first flat layer PLN1, a second source-drain metal layer SD2, a second flat layer PLN2, a third source-drain metal layer SD3, a third flat layer PLN3, a first electrode layer ANE, a pixel defining layer PDL, a spacer layer BPS, a light-emitting layer EL, a second electrode layer Cath and an encapsulation layer.

[0177] It should be noted that the driving circuit layer mentioned above includes, for example, a light-shielding layer LS, an isolation layer, a first active layer Poly, a first gate insulating layer GI1, a first gate metal layer Gate1, a second gate insulating layer GI2, a second gate metal layer Gate2, a third gate insulating layer GI3, a second active layer IGZO, a fourth gate insulating layer GI4, a third gate metal layer Gate3, an interlayer insulating layer ILD, a first source-drain metal layer SD1, a passivation layer PVX, a first flat layer PLN1, a second source-drain metal layer SD2, a second flat layer PLN2 and a third source-drain metal layer SD3.

[0178] 5A to 5V are plan views of some film layers in a display substrate located in a display area according to some exemplary embodiments of the present disclosure;

[0179] 5A schematically illustrates a light-shielding layer, FIG5B schematically illustrates a combination of a light-shielding layer and a first active layer, FIG5C schematically illustrates a combination of a light-shielding layer, a first active layer and a first gate metal layer, FIG5D schematically illustrates a combination of a light-shielding layer, a first active layer, a first gate metal layer and a second gate metal layer, FIG5E schematically illustrates a combination of a light-shielding layer, a first active layer, a first gate metal layer, a second gate metal layer and a second active layer, FIG5F schematically illustrates a combination of a light-shielding layer, a first active layer, a first gate metal layer, a second gate metal layer, a second active layer and a third gate metal layer, and FIG5G schematically illustrates a light-shielding layer, FIG5H illustrates a combination of a light shielding layer, a first active layer, a first gate metal layer, a second gate metal layer, a second active layer, a third gate metal layer and an interlayer insulating layer, and illustrates some vias in the interlayer insulating layer. FIG5I illustrates a combination of a light shielding layer, a first active layer, a first gate metal layer, a second gate metal layer, a second active layer, a third gate metal layer and an interlayer insulating layer, and FIG5J illustrates a combination of a second active layer, a third gate metal layer and an interlayer insulating layer. FIG5K illustrates a combination of a first active layer, a first gate metal layer, a second gate metal layer, an interlayer insulating layer and a first source / drain metal layer, FIG5L illustrates a combination of a first source / drain metal layer and a passivation layer, FIG5M illustrates a combination of a first source / drain metal layer, a passivation layer and a first planarization layer, FIG5N illustrates a combination of a first source / drain metal layer and a second source / drain metal layer, FIG5O illustrates a combination of a first source / drain metal layer, a second source / drain metal layer and a second planarization layer, and FIG5P illustrates a combination of a first source / drain metal layer, a second source / drain metal layer and a second planarization layer. Figure 5Q illustrates the combination of the third source-drain metal layer and the third planarization layer, Figure 5R illustrates the combination of the third source-drain metal layer and the first electrode layer, Figure 5S illustrates the combination of the third source-drain metal layer, the first electrode layer and the pixel defining layer, Figure 5T illustrates the combination of the third source-drain metal layer, the first electrode layer, the pixel defining layer and the spacer layer, Figure 5U illustrates the combination of the first electrode layer, the pixel defining layer and the spacer layer, and Figure 5V illustrates the combination of the first electrode layer, the pixel defining layer and the second electrode layer.

[0180] 5A , the light-shielding layer LS may include a plurality of light-shielding portions LS1 distributed in a first direction X and a second direction Y. Adjacent light-shielding portions LS1 in the first direction X are connected to each other, and a connecting line connecting adjacent light-shielding portions LS1 is on the same straight line. The extending direction of the connecting line is parallel or substantially parallel to the first direction X. Two adjacent light-shielding portions LS1 in the second direction Y are also connected to each other. The light-shielding layer LS may be a conductive structure, for example, a light-shielding metal layer.

[0181] Referring to Figure 5B , the first active layer Poly is formed by patterning a semiconductor material. The first active layer Poly includes at least a portion of the active portions of the aforementioned transistors. For example, the first active layer Poly can be used to form the active portions of the aforementioned third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, seventh transistor T7, and eighth transistor T8. The active portion of each transistor includes a channel portion and doped portions located on either side of the channel portion. The channel portion and doped portions of the aforementioned transistors in the same pixel circuit are integrally formed.

[0182] The orthographic projection of the light shielding portion LS1 on the base substrate can cover the orthographic projection of the channel portion CH3 in the active portion of the third transistor T3 on the base substrate. The light shielding portion LS1 can reduce the influence of light on the characteristics of the third transistor T3.

[0183] For example, the material of the first active layer Poly includes low temperature polysilicon.

[0184] 5C , the first gate metal layer Gate1 includes a first scan line Scan1 extending along a first direction X, a light emitting control line EM, a first reset line R1 and a second reset line R2 , and a gate G3 of a third transistor T3 .

[0185] It should be noted that some of the lines described in the embodiments of the present disclosure extending along the first direction X or the second direction Y represent that the lines generally extend along the first direction X or the second direction Y, but due to factors such as space limitations, a portion of the line may be bent.

[0186] For example, the dashed rectangles in Figure 5C illustrate the overlapping portions of the first active layer Poly and the first gate metal layer Gate1, each serving as the channel portion of a transistor. Specifically, the portion of the first active layer Poly overlapping the first scan line Scan1 serves as the channel portion CH4 of the fourth transistor T4; the portion of the first active layer Poly overlapping the gate G3 serves as the channel portion CH3 of the third transistor T3; the first active layer Poly and the emission control line EM have two overlapping portions, one serving as the channel portion CH5 of the fifth transistor T5 and the other serving as the channel portion CH6 of the sixth transistor T6; the portion of the first active layer Poly overlapping the second reset line R2 serves as the channel portion CH7 of the seventh transistor T7; and the portion of the first active layer Poly overlapping the third reset line R3 serves as the channel portion CH8 of the eighth transistor T8. Portions of the first active layer Poly on either side of each channel portion are conductively formed through processes such as ion doping to serve as the doped portions of each transistor. The doped portions include a source and a drain located on either side of the channel portion, i.e., the first and second electrodes described above.

[0187] It should be noted that the source and drain of each of the above-mentioned transistors can be symmetrical in structure, so the source and drain can be physically identical. In the embodiments of the present disclosure, in order to distinguish transistors, except for the gate as the control electrode, one electrode is directly described as the first electrode and the other electrode is directly described as the second electrode. Therefore, the first electrode and the second electrode of all or part of the transistors in the embodiments of the present disclosure can be interchanged as needed.

[0188] For example, the gate of the seventh transistor T7 and the gate of the eighth transistor T8 can be connected to the same reset signal, that is, the gate of the seventh transistor T7 and the gate of the eighth transistor T8 can be electrically connected to the same signal line to receive the same signal, thereby reducing the number of signal lines. Specifically, referring to FIG. 5C , the first reset line R1 and the second reset line R2 are the same line.

[0189] For example, the gate of the seventh transistor T7 and the gate of the eighth transistor T8 may also be electrically connected to different reset lines, respectively. In this case, the signals transmitted by the different reset lines may be the same or different.

[0190] For example, the gate G3 of the third transistor T3 may reuse the first plate Cst1 of the storage capacitor C.

[0191] 5D , the second gate metal layer Gate2 includes a first reset line R1 and a first second scan line Scan2 . The first reset line R1 and the second scan line Scan2 may both extend along the first direction X.

[0192] The second gate metal layer Gate2 includes a second plate Cst2 of the storage capacitor C. Referring to FIG. 5D and FIG. 5C , the second plate Cst2 overlaps with the first plate Cst1 to form the storage capacitor. A via H11 is defined on the second plate Cst2. The orthographic projection of the via H11 on the substrate lies within the orthographic projection of the gate G3 of the third transistor T3 (the first plate Cst1) on the substrate. This via H11 electrically connects the gate G3 of the third transistor T3 to other structures above it, as described below.

[0193] The second gate metal layer Gate2 includes a connection structure C11. Among the multiple second plates Cst2 arranged at intervals along the first direction X, two adjacent second plates Cst2 are connected by the connection structure C11, and the remaining two adjacent second plates Cst2 are connected by wiring. The connection structure C11 is used to achieve electrical connection between the second plate Cst2 and other upper structures, which will be described in detail later.

[0194] 5E , the second active layer IGZO is formed by patterning a semiconductor material, and includes at least a portion of the active portion of the transistor. For example, the second active layer IGZO can be used to fabricate the active portions of the first transistor T1 and the second transistor T2.

[0195] The dashed rectangular boxes in Figure 5E illustrate the overlapping portions of the second active layer IGZO and the second gate metal layer Gate2, which serve as the channel portions of respective transistors. Specifically, the portion of the second active layer IGZO overlapping the first reset line R1 serves as the channel portion CH2 of the second transistor T2, and the portion of the second active layer IGZO overlapping the second scan line Scan2 serves as the channel portion CH1 of the first transistor T1.

[0196] The material of the second active layer IGZO is a metal oxide semiconductor, for example, indium gallium zinc oxide (IGZO).

[0197] 5F , the third gate metal layer Gate3 includes a second first reset line R1 and a second second scan line Scan2 . The first reset line R1 and the second scan line Scan2 may both extend along the first direction X.

[0198] Referring to Figures 5F and 5D , the second first reset line R1 located on the third gate metal layer Gate3 substantially overlaps the first first reset line R1 located on the second gate metal layer Gate2. The portion where the first first reset line R1 overlaps the second active layer IGZO serves as the first gate of the second transistor T2, also known as the bottom gate. The portion where the second first reset line R1 overlaps the second active layer IGZO serves as the second gate of the second transistor T2, also known as the top gate. The first and second first reset lines R1 transmit the same signal and can be electrically connected via vias in the peripheral area of ​​the display substrate.

[0199] The second second scan line Scan2 located on the third gate metal layer Gate3 substantially overlaps with the first second scan line Scan2 located on the second gate metal layer Gate2. The portion where the first second scan line Scan2 overlaps with the second active layer IGZO serves as the first gate of the first transistor T1, i.e., the bottom gate. The portion where the second second scan line Scan2 overlaps with the second active layer IGZO serves as the second gate of the first transistor T1, i.e., the top gate. The first second scan line Scan2 and the second second scan line Scan2 transmit the same signal. The first second scan line Scan2 and the second second scan line Scan2 can be electrically connected through vias in the peripheral area of ​​the display substrate.

[0200] The third gate metal layer Gate3 includes a first mesh segment M1 , which is used to connect with other structures in an upper layer to form a mesh-shaped routing, as will be described later.

[0201] 5G , the interlayer insulating layer ILD has a first via hole H201, a second via hole H202, a third via hole H203, a fourth via hole H204, a fifth via hole H205, a sixth via hole H206, a seventh via hole H207, and an eighth via hole H208. The first via hole H201, the second via hole H202, and the third via hole H203 penetrate the interlayer insulating layer ILD and the fourth gate insulating layer GI4 to expose a portion of the second active layer IGZO. The fourth via hole H204, the fifth via hole H205, the sixth via hole H206, the seventh via hole H207, and the eighth via hole H208 penetrate the interlayer insulating layer ILD to expose a portion of the first mesh segment M1.

[0202] It should be noted that the interlayer insulating layer ILD has multiple vias, and the etching processes for vias with different hole depths are different. In order to ensure that each via has a good morphology, one type of via with a shallower hole depth is formed by a single patterning process, and another type of via with a deeper hole depth is formed by another patterning process. For example, the first via H201 to the eighth via H208 shown in FIG5G are formed by a single patterning process, and the remaining vias are formed by another patterning process, as will be described later.

[0203] 5H , the interlayer insulating layer ILD further includes a ninth via hole H209 , a tenth via hole H210 , an eleventh via hole H211 , a twelfth via hole H212 , a thirteenth via hole H213 , a fourteenth via hole H214 , a fifteenth via hole H215 , a sixteenth via hole H216 , and a seventeenth via hole H217 .

[0204] Among them, the ninth via H209 penetrates the interlayer insulating layer ILD, the fourth gate insulating layer GI4, the third gate insulating layer GI3 and the second gate insulating layer GI2 to expose the gate G3 of the third transistor T3. Referring to Figures 5H and 5D, the orthographic projection of the ninth via H209 on the substrate is within the orthographic projection of the via H11 located on the second electrode plate Cst2 on the substrate.

[0205] The tenth via hole H210, the eleventh via hole H211, the twelfth via hole H212, the thirteenth via hole H213, the fourteenth via hole H214, the fifteenth via hole H215 and the sixteenth via hole H216 penetrate the interlayer insulating layer ILD, the fourth gate insulating layer GI4, the third gate insulating layer GI3, the second gate insulating layer GI2 and the first gate insulating layer GI1 to expose a portion of the first active layer Poly.

[0206] The seventeenth via hole H217 penetrates the interlayer insulating layer ILD, the fourth gate insulating layer GI4 and the third gate insulating layer GI3 to expose the connection structure C11 located in the second gate metal layer Gate2 .

[0207] 5I , the first source / drain metal layer SD1 has a first connection structure C21 , a second connection structure C22 , a third connection structure C23 , a fourth connection structure C24 , a fifth connection structure C25 , a first mesh segment M1 , a first initialization signal line Vinit1 , a second initialization signal line Vinit2 , and a third initialization signal line Vinit3 .

[0208] Referring to Figures 5J, 5I, and 5G, the first mesh segments M1 and the second mesh segments M2 are generally arranged alternately along the second direction. The ends of the second mesh segment M2 are electrically connected to two adjacent first mesh segments M1 via the fourth via H204 and the fifth via H205, respectively. This allows the plurality of first mesh segments M1 and the plurality of second mesh segments M2 arranged alternately along the second direction to be sequentially electrically connected, forming mesh lines extending along the second direction. Simultaneously, the first initialization signal line Vinit1 is electrically connected to the first mesh segment M1 via the eighth via H208, the second initialization signal line Vinit2 is electrically connected to the first mesh segment M1 via the sixth via H206, and the third initialization signal line Vinit3 is electrically connected to the first mesh segment M1 via the seventh via H207. Consequently, the plurality of first initialization signal lines Vinit1, the second initialization signal line Vinit2, and the third initialization signal line Vinit3 extending along the first direction X are electrically connected to the plurality of mesh lines extending along the second direction, forming a grid-like initialization signal structure. Compared to conventional initialization signal lines that only include horizontally arranged initialization signal lines, this grid-like initialization signal structure can reduce initialization signal loading, allowing the initialization signal to charge faster and providing a better reset effect for the corresponding nodes. This beneficial effect is particularly significant for large-screen, high-frequency display substrates.

[0209] 4 , the second connection structure C22 is electrically connected to the connection node between the first transistor T1 and the second transistor T2 via H202. That is, the second connection structure C22 is electrically connected to the first electrode S1 of the first transistor T1 and the second electrode D2 of the second transistor T2. The third connection structure C23 is electrically connected to the second electrode D1 of the first transistor T1 via a third via H203.

[0210] With reference to Figures 5K, 5I, and 5H in conjunction with Figure 4, the first connection structure C21 is electrically connected to the first electrode S4 of the fourth transistor T4 via the sixteenth via H216. The second connection structure C22 is electrically connected to the connection node (third node N3) between the first transistor T1 and the second transistor T2 via the tenth via H210. Specifically, the second connection structure C22 is electrically connected to the first electrode S6 of the sixth transistor T6 and the second electrode D3 of the third transistor T3. Simultaneously, the second connection structure C22 is electrically connected to the second electrode D8 of the eighth transistor T8 via the twelfth via H212. Through the connection of the second connection structure C22, the first electrode S1 of the first transistor T1, the second electrode D2 of the second transistor T2, the first electrode S6 of the sixth transistor T6, the second electrode D3 of the third transistor T3, and the second electrode D8 of the eighth transistor T8 are all electrically connected to the third node N3. The third connection structure C23 is electrically connected to the gate G3 of the third transistor T3 via the ninth via H209, thereby electrically connecting the gate G3 of the third transistor T3 to the second electrode D1 of the first transistor T1. The fourth connection structure C24 is electrically connected to the second electrode D6 of the sixth transistor T6 through the eleventh via H211. The fifth connection structure C25 is electrically connected to the connection structure C11 located on the second gate metal layer Gate2 through the seventeenth via H217, thereby achieving electrical connection to the second electrode plate Cst2. The fifth connection structure C25 is electrically connected to the first electrode S5 of the fifth transistor T1 through the fifteenth via H215.

[0211] 5L , the passivation layer PVX has a first via hole H31, a second via hole H32, and a third via hole H33. The first via hole H31 exposes a portion of the first connection structure C21, the second via hole H32 exposes a portion of the fourth connection structure C24, and the third via hole H33 exposes a portion of the fifth connection structure C25.

[0212] 5M , the first planarization layer PLN1 has a fourth via hole H34 , a fifth via hole H35 , and a sixth via hole H36 .

[0213] The orthographic projection of the fourth via H34 on the base substrate overlaps the orthographic projection of the first via H31 on the base substrate. The fourth via H34 and the first via H31 are connected, jointly exposing a portion of the first connection structure C21. The orthographic projection of the fifth via H35 on the base substrate overlaps the orthographic projection of the second via H32 on the base substrate. The fifth via H35 and the second via H32 are connected, jointly exposing a portion of the fourth connection structure C24. The orthographic projection of the sixth via H36 on the base substrate overlaps the orthographic projection of the third via H33 on the base substrate. The sixth via H36 and the third via H33 are connected, jointly exposing a portion of the fifth connection structure C25.

[0214] 5N , the second source / drain metal layer SD2 includes a first connection structure C31, a second connection structure C32, a third connection structure C33, a data signal transmission structure C1, and a data signal transmission structure C2. The data signal transmission structures C1 and C2 are used to facilitate transmission of data signals from the driver chip to corresponding data signal lines.

[0215] 5N , 5M , and 5L , the first connection structure C31 is electrically connected to the first connection structure C21 in the first source / drain metal layer SD1 via the interconnected fourth via H34 and the first via H31. The second connection structure C32 is electrically connected to the fourth connection structure C24 in the first source / drain metal layer SD1 via the interconnected fifth via H35 and the second via H32. The third connection structure C33 is electrically connected to the fifth connection structure C25 in the first source / drain metal layer SD1 via the interconnected sixth via H36 and the third via H33.

[0216] 5O , the second planarization layer PLN2 has a first via hole H41, a second via hole H42, and a third via hole H43. The first via hole H41 exposes a portion of the first connection structure C31, the second via hole H42 exposes a portion of the second connection structure C32, and the third via hole H43 exposes a portion of the third connection structure C33.

[0217] 5P , the third source / drain metal layer SD3 has a data signal line Data, a first power signal line VDD, a second power signal line VSS, and a first connection structure C41 . The data signal line Data, the first power signal line VDD, and the second power signal line VSS all extend along the second direction Y.

[0218] Referring to Figure 5P and Figure 5O, the data signal line Data is electrically connected to the first connection structure C31 through the first via H41. The data signal line is electrically connected to the first electrode S4 of the fourth transistor T4 through the first connection structure C31 located in the second source-drain metal layer and the first connection structure C21 located in the first source-drain metal layer SD1 in sequence. The data signal line Data is used to connect the data signal to the first electrode S4 of the fourth transistor T4.

[0219] The first power signal line VDD is electrically connected to a third connection structure C33 located in the second source / drain metal layer through a third via H43. Multiple third connection structures C33 arranged along the first direction X electrically connect the multiple first power signal lines VDD in sequence. The multiple third connection structures C33 and the multiple first power signal lines VDD are electrically connected to each other to form a grid of power signal lines. This helps reduce the voltage drop across the first power signal line VDD, thereby improving the uniformity of the display when the display substrate is used in a display panel. Simultaneously, the first power signal line VDD is electrically connected to the connection structure C11 located in the second gate metal layer Gate2 and the first electrode S5 of the fifth transistor T1, respectively, through the third connection structure C33 located in the second source / drain metal layer and the fifth connection structure C25 located in the first source / drain metal layer SD1. The first power signal line VDD is used to couple the first power signal to the second plate Cst2 of the storage capacitor C and the first electrode S5 of the fifth transistor T1.

[0220] The first connection structure C41 is electrically connected to the second connection structure C32 through the second via H42.

[0221] 5Q , the third planarization layer PLN3 has a first via hole H51 and a second via hole H52 , wherein the first via hole H51 exposes a portion of the first connection structure C41 and the second via hole H52 exposes a portion of the second power signal line VSS.

[0222] 5R , the first electrode layer ANE includes a first electrode F1 , an electrode connecting portion L4 , a first connecting portion L1 , a second connecting portion L2 , and a third connecting portion L3 .

[0223] 5R and 5Q , the electrode connection portion L4 is directly connected to the first electrode F1, and the electrode connection portion L4 is electrically connected to the first connection structure C41 through the second via H52 in the third planarization layer PLN3. That is, the first electrode F1 is electrically connected to the second electrode D6 of the sixth transistor T6 via the first connection structure C41, the second connection structure C32, and the fourth connection structure C24 in sequence.

[0224] The first connection part L1 is electrically connected to the first trace VSS 1 through the first via H51 of the third planarization layer PLN3, the second connection part L2 is electrically connected to the second trace VSS2 through the first via H51 of the third planarization layer PLN3, and the third connection part L3 is electrically connected to the third trace VSS3 through the first via H51 of the third planarization layer PLN3.

[0225] 5S , the pixel defining layer PDL has a pixel opening K, a first via hole H61 , a second via hole H62 , and a third via hole H63 .

[0226] 5S and 5R , the pixel opening K exposes a portion of the first electrode F1 , the first via hole H61 exposes a portion of the first connection portion L1 , the second via hole H62 exposes a portion of the second connection portion L2 , and the third via hole H63 exposes a portion of the third connection portion L3 .

[0227] 5T and 5U , the barrier layer 300 is in a grid-like configuration and includes a first opening 300a, a second opening 300b, and a third opening 300c. Continuing with FIG5V , the first portion CA1 is embedded within the first opening 300a, the second portion CA2 is embedded within the second opening 300b, and the third portion CA3 is embedded within the third opening 300c. Each first portion CA1 includes the second electrode F2 of a first light-emitting element E1, each second portion CA2 includes the second electrode F2 of a second light-emitting element E2, and each third portion CA3 includes the second electrode F2 of a third light-emitting element E3.

[0228] Exemplarily, referring back to FIG5T , the display substrate includes m light-emitting units W (one light-emitting unit W is exemplarily shown in the figure) arranged at intervals along the first direction X, and one light-emitting unit W includes a first light-emitting group W1, a first second light-emitting group W2, a third light-emitting group W3, and a second second light-emitting group W2 arranged in sequence along the first direction X.

[0229] The first light-emitting group W1 includes n first light-emitting elements E1 and n third light-emitting elements E3, and the n first light-emitting elements E1 and the n third light-emitting elements E3 are alternately arranged along the second direction Y; the second light-emitting group W2 includes 2n second light-emitting elements E2 arranged along the second direction Y; the third light-emitting group W3 includes n third light-emitting elements E3 and n first light-emitting elements E1, and the n third light-emitting elements E3 and the n first light-emitting elements E1 are alternately arranged along the second direction Y, where n and m are positive integers.

[0230] 5T , the light-emitting elements are arranged along the first direction X and the second direction Y to form multiple rows and columns of light-emitting elements. The first light-emitting group W1 comprises n first light-emitting elements E1 and n third light-emitting elements E3 arranged alternately in a column. The third light-emitting group W3 comprises n third light-emitting elements E3 and n first light-emitting elements E1 arranged alternately in a column. One first light-emitting element E1 in the first light-emitting group W1 and one third light-emitting element E3 in the third light-emitting group W3 are located in the same row, and one third light-emitting element E3 in the first light-emitting group W1 and one first light-emitting element E1 in the third light-emitting group W3 are located in the same row. The second light-emitting group W2 comprises 2n second light-emitting elements E2 in a column. For example, the 2n second light-emitting elements E2 are located in odd rows, and the n first light-emitting elements E1 and n third light-emitting elements E3 are located in even rows, or the 2n second light-emitting elements E2 are located in even rows, and the n first light-emitting elements E1 and n third light-emitting elements E3 are located in odd rows.

[0231] A first portion CA1 includes a second electrode F2 of a first light-emitting element E1, and a first portion CA1 is electrically connected to a first trace VSS1 through a first connection portion L1; a second portion CA2 includes a second electrode F2 of a second light-emitting element E2, and a second portion CA2 is electrically connected to a second trace VSS2 through a second connection portion L2; a third portion CA3 includes a second electrode F2 of a third light-emitting element E3, and a third portion CA3 is electrically connected to a third trace VSS3 through a third connection portion L3.

[0232] According to some exemplary embodiments, referring to FIG. 5T , in a first light-emitting group W1, the n first portions CA1 of the n first light-emitting elements E1 are electrically connected to the same first wiring VSS1 through the n first connection portions L1, and the n third portions CA3 of the n third light-emitting elements E3 are electrically connected to the same third wiring VSS3 through the n third connection portions L3; in a second light-emitting group W2, the 2n second portions CA2 of the 2n second light-emitting elements E2 are electrically connected to the same second wiring VSS2 through the 2n second connection portions L2; ​​in a third light-emitting group W3, the n third portions CA3 of the n third light-emitting elements E3 are electrically connected to the same third wiring VSS3 through the n third connection portions L3, and the n first portions CA1 of the n first light-emitting elements E1 are electrically connected to the same first wiring VSS1 through the n first connection portions L1.

[0233] 5T , the second power signal line VSS includes m routing groups V (one routing group V is exemplarily shown in the figure) arranged at intervals along the first direction X. One routing group V includes a first second routing line VSS2, a first routing line VSS1, a second second routing line VSS2, and a third routing line VSS3 arranged at intervals along the first direction X. One routing group V is electrically connected to one light-emitting unit W.

[0234] In an electrically connected wiring group V and a light-emitting unit W, the orthographic projections of the first second wiring VSS2 and the first wiring VSS1 on the substrate 100 partially overlap with the orthographic projections of the first second light-emitting group W2 on the substrate 100, and the orthographic projections of the second second wiring VSS2 and the third wiring VSS3 on the substrate 100 partially overlap with the orthographic projections of the second second light-emitting group W2 on the substrate 100. That is, the first wiring VSS1, the second wiring VSS2, the third wiring VSS3 and the data signal line Data are arranged corresponding to the column where the second light-emitting element E2 is located, and the first power signal line VDD is arranged corresponding to the column where the first light-emitting element E1 and the third light-emitting element E3 are located.

[0235] For example, the first wiring VSS1 , the second wiring VSS2 , and the third wiring VSS3 are each located between the corresponding adjacent data signal line Data and the first power signal line VDD.

[0236] In the first light-emitting group W1, the n first parts CA1 of the n first light-emitting elements E1 are respectively electrically connected to the first routing wire VSS1 in the adjacent routing wire group V located on the side of the first second routing wire VSS2 away from the first routing wire VSS1 through n first connection parts L1 (specifically, the first connection part L1 marked as L11 in the figure, wherein the corresponding first connection part L11 in the first light-emitting group W1 marked in the figure is not fully illustrated, and the L11 marked in the figure is the corresponding first connection part L11 in the first light-emitting group W1 of the adjacent light-emitting unit W), and the n third parts CA3 of the n third light-emitting elements E3 are respectively electrically connected to the third routing wire VSS3 in the adjacent routing wire group V located on the side of the first second routing wire VSS2 away from the first routing wire VSS1 through n third connection parts L3 (specifically, the third connection part L3 marked as L31 in the figure).

[0237] In the first second light-emitting group W2 , the 2n second portions CA2 of the 2n second light-emitting elements E2 are electrically connected to the first second wiring VSS2 through the 2n second connecting portions L2 .

[0238] In the third light-emitting group W3, the n first parts CA1 of the n first light-emitting elements E1 are respectively electrically connected to the first wiring VSS1 through n first connection parts L1 (specifically, the first connection part L1 marked as L12 in the figure), and the n third parts CA3 of the n third light-emitting elements E3 are respectively electrically connected to the third wiring VSS3 through n third connection parts L3 (specifically, the third connection part L3 marked as L32 in the figure).

[0239] In the second second light-emitting group W2 , the 2n second portions CA2 of the 2n second light-emitting elements E2 are electrically connected to the second second wiring VSS2 through the 2n second connecting portions L2 .

[0240] 6A-6E are plan views of some film layers in a display substrate located in a display area according to some exemplary embodiments of the present disclosure;

[0241] Among them, Figure 6A illustrates the combination of the third source-drain metal layer and the third planarization layer, Figure 6B illustrates the combination of the third source-drain metal layer and the first electrode layer, Figure 6C illustrates the combination of the third source-drain metal layer, the first electrode layer and the pixel defining layer, Figure 6D illustrates the combination of the third source-drain metal layer, the first electrode layer, the pixel defining layer and the spacer layer, and Figure 6E illustrates the combination of the third source-drain metal layer, the first electrode layer, the pixel defining layer, the spacer layer and the second electrode layer.

[0242] 6A , the third planarization layer PLN3 has a first via hole H51 and a second via hole H52 , wherein the first via hole H51 exposes a portion of the first connection structure C41 , and the second via hole H52 exposes a portion of the second power signal line VSS.

[0243] 6B , the first electrode layer ANE includes a first electrode F1 , an electrode connecting portion L4 , a first connecting portion L1 , a second connecting portion L2 , and a third connecting portion L3 .

[0244] 6B and 6A , the electrode connection portion L4 is directly connected to the first electrode F1, and the electrode connection portion L4 is electrically connected to the first connection structure C41 through the second via H52 in the third planarization layer PLN3. That is, the first electrode F1 is electrically connected to the second electrode D6 of the sixth transistor T6 via the first connection structure C41, the second connection structure C32, and the fourth connection structure C24 in sequence.

[0245] The first connection part L1 is electrically connected to the first trace VSS1 through the first via H51 of the third planarization layer PLN3, the second connection part L2 is electrically connected to the second trace VSS2 through the first via H51 of the third planarization layer PLN3, and the third connection part L3 is electrically connected to the third trace VSS3 through the first via H51 of the third planarization layer PLN3.

[0246] 6C , the pixel defining layer PDL has a pixel opening K, a first via hole H61 , a second via hole H62 , and a third via hole H63 .

[0247] 6C and 6B , the pixel opening K exposes a portion of the first electrode F1 , the first via hole H61 exposes a portion of the first connection portion L1 , the second via hole H62 exposes a portion of the second connection portion L2 , and the third via hole H63 exposes a portion of the third connection portion L3 .

[0248] 6D and 6E , the barrier layer 300 is in a grid configuration and includes a first opening 300a, a second opening 300b, and a third opening 300c. A first portion CA1 is embedded within the first opening 300a, a second portion CA2 is embedded within the second opening 300b, and a third portion CA3 is embedded within the third opening 300c. Each first portion CA1 includes the second electrode F2 of a first light-emitting element E1, each second portion CA2 includes the second electrode F2 of a second light-emitting element E2, and each third portion CA3 includes the second electrode F2 of a third light-emitting element E3.

[0249] For example, referring back to FIG6D , the display substrate includes m light-emitting units W (one light-emitting unit W is shown in the figure as an example) arranged at intervals along the first direction X, and one light-emitting unit W includes a first light-emitting group W1, a first second light-emitting group W2, a third light-emitting group W3, and a second second light-emitting group W2 arranged in sequence along the first direction X.

[0250] The first light-emitting group W1 includes n first light-emitting elements E1 and n third light-emitting elements E3, and the n first light-emitting elements E1 and the n third light-emitting elements E3 are alternately arranged along the second direction Y; the second light-emitting group W2 includes 2n second light-emitting elements E2 arranged along the second direction Y; the third light-emitting group W3 includes n third light-emitting elements E3 and n first light-emitting elements E1, and the n third light-emitting elements E3 and the n first light-emitting elements E1 are alternately arranged along the second direction Y, where n and m are positive integers.

[0251] 6D , the light-emitting elements are arranged along the first direction X and the second direction Y to form multiple rows and columns of light-emitting elements. The first light-emitting group W1 comprises n first light-emitting elements E1 and n third light-emitting elements E3 arranged alternately in a column. The third light-emitting group W3 comprises n third light-emitting elements E3 and n first light-emitting elements E1 arranged alternately in a column. One first light-emitting element E1 in the first light-emitting group W1 and one third light-emitting element E3 in the third light-emitting group W3 are located in the same row, and one third light-emitting element E3 in the first light-emitting group W1 and one first light-emitting element E1 in the third light-emitting group W3 are located in the same row. The second light-emitting group W2 comprises 2n second light-emitting elements E2 in a column. For example, the 2n second light-emitting elements E2 are located in odd rows, and the n first light-emitting elements E1 and n third light-emitting elements E3 are located in even rows, or the 2n second light-emitting elements E2 are located in even rows, and the n first light-emitting elements E1 and n third light-emitting elements E3 are located in odd rows.

[0252] A first portion CA1 includes a second electrode F2 of a first light-emitting element E1, and a first portion CA1 is electrically connected to a first trace VSS1 through a first connection portion L1; a second portion CA2 includes a second electrode F2 of a second light-emitting element E2, and a second portion CA2 is electrically connected to a second trace VSS2 through a second connection portion L2; a third portion CA3 includes a second electrode F2 of a third light-emitting element E3, and a third portion CA3 is electrically connected to a third trace VSS3 through a third connection portion L3.

[0253] According to some exemplary embodiments, referring to FIG6D , in a first light-emitting group W1, the n first portions CA1 of the n first light-emitting elements E1 are electrically connected to the same first wiring VSS1 through the n first connection portions L1, and the n third portions CA3 of the n third light-emitting elements E3 are electrically connected to the same third wiring VSS3 through the n third connection portions L3; in a second light-emitting group W2, the 2n second portions CA2 of the 2n second light-emitting elements E2 are electrically connected to the same second wiring VSS2 through the 2n second connection portions L2; ​​in a third light-emitting group W3, the n third portions CA3 of the n third light-emitting elements E3 are electrically connected to the same third wiring VSS3 through the n third connection portions L3, and the n first portions CA1 of the n first light-emitting elements E1 are electrically connected to the same first wiring VSS1 through the n first connection portions L1.

[0254] 6D , the second power signal line VSS includes m routing groups V (one routing group V is exemplarily shown in the figure) arranged at intervals along the first direction X. One routing group V includes a first second routing line VSS2, a first routing line VSS1, a second second routing line VSS2, and a third routing line VSS3 arranged at intervals along the first direction X. One routing group V is electrically connected to one light-emitting unit W.

[0255] In an electrically connected wiring group V and a light-emitting unit W, the orthographic projections of the first second wiring VSS2 and the first wiring VSS1 on the substrate 100 partially overlap with the orthographic projections of the first second light-emitting group W2 on the substrate 100, and the orthographic projections of the second second wiring VSS2 and the third wiring VSS3 on the substrate 100 partially overlap with the orthographic projections of the second second light-emitting group W2 on the substrate 100. That is, the first wiring VSS1, the second wiring VSS2, the third wiring VSS3 and the data signal line Data are arranged corresponding to the column where the second light-emitting element E2 is located, and the first power signal line VDD is arranged corresponding to the column where the first light-emitting element E1 and the third light-emitting element E3 are located.

[0256] For example, the first wiring VSS1 , the second wiring VSS2 , and the third wiring VSS3 are each located between the corresponding adjacent data signal line Data and the first power signal line VDD.

[0257] In the first light-emitting group W1, the n first portions CA1 of the n first light-emitting elements E1 are respectively electrically connected to the first routing line VSS1 through the n first connection portions L1 (specifically, the first connection portion L1 marked as L11 in the figure), and the n third portions CA3 of the n third light-emitting elements E3 are respectively electrically connected to the third routing line VSS3 in the adjacent routing line group V located on the side of the first second routing line VSS2 away from the first routing line VSS 1 through the n third connection portions L3 (specifically, the third connection portion L3 marked as L31 in the figure).

[0258] In the first second light-emitting group W2 , the 2n second portions CA2 of the 2n second light-emitting elements E2 are electrically connected to the first second wiring VSS2 through the 2n second connecting portions L2 .

[0259] In the third light-emitting group W3, the n first parts CA1 of the n first light-emitting elements E1 are respectively electrically connected to the first wiring VSS1 through n first connection parts L1 (specifically, the first connection part L1 marked as L12 in the figure), and the n third parts CA3 of the n third light-emitting elements E3 are respectively electrically connected to the third wiring VSS3 through n third connection parts L3 (specifically, the third connection part L3 marked as L32 in the figure).

[0260] In the second second light-emitting group W2 , the 2n second portions CA2 of the 2n second light-emitting elements E2 are electrically connected to the second second wiring VSS2 through the 2n second connecting portions L2 .

[0261] 7A-7E are plan views showing some film layers in a display substrate located in a peripheral area according to some exemplary embodiments of the present disclosure;

[0262] Figure 7A illustrates a first source-drain metal layer, Figure 7B illustrates a combination of the first source-drain metal layer and a passivation layer, Figure 7C illustrates a combination of the first source-drain metal layer, the passivation layer and the first planarization layer, Figure 7D illustrates a combination of the first source-drain metal layer and the second source-drain metal layer, Figure 7E illustrates a combination of the first source-drain metal layer, the second source-drain metal layer and the second planarization layer, and Figure 7F illustrates the first source-drain metal layer, the second source-drain metal layer, the second planarization layer and the third source-drain metal layer.

[0263] Referring back to FIG. 1 , the peripheral area NA includes a first side area NA1 located outside the display area AA along the second direction Y.

[0264] 1 and 7A , the first source / drain metal layer SD1 includes a first signal input portion QA1, a second signal input portion QA2, and a third signal input portion QA3 located in the first side area NA1. The first signal input portion QA1, the second signal input portion QA2, and the third signal input portion QA3 extend along the first direction X and are spaced apart along the second direction Y.

[0265] Referring to Figure 7D , the second source / drain metal layer SD2 includes a first signal connection portion QB1, a second signal connection portion QB2, and a third signal connection portion QB3 located in the first side area NA1. The first signal connection portion QB1, the second signal connection portion QB2, and the third signal connection portion QB3 all extend along the first direction X and are spaced apart along the second direction Y. The orthographic projection of the first signal connection portion QB1 on the substrate at least partially overlaps with the orthographic projection of the first signal input portion QA1 on the substrate, the orthographic projection of the second signal connection portion QB2 on the substrate at least partially overlaps with the orthographic projection of the second signal input portion QA2 on the substrate, and the orthographic projection of the third signal connection portion QB3 on the substrate at least partially overlaps with the orthographic projection of the third signal input portion QA3 on the substrate. The first signal connection portion QB1 is electrically connected to the first signal input portion QA1, the second signal connection portion QB2 is electrically connected to the second signal input portion QA2, and the third signal connection portion QB3 is electrically connected to the third signal input portion QA3.

[0266] 1 and 7F , one end of the first trace VSS1 extends to the first side area NA1 and is electrically connected to the first signal connection portion QB1 , that is, the first signal input portion QA1 is electrically connected to the first trace VSS1 through the first signal connection portion QB1 , and the first signal input portion QA1 is used to input the first signal to the first trace VSS1 .

[0267] One end of the second wiring VSS2 extends to the first side area NA1 and is electrically connected to the second signal connection part QB2, that is, the second signal input part QA2 is electrically connected to the second wiring VSS2 through the second signal connection part QB2, and the second signal input part QA2 is used to input the second signal to the second wiring VSS2.

[0268] One end of the third wiring VSS3 extends to the first side area NA1 and is electrically connected to the third signal connection part QB3, that is, the third signal input part QA3 is electrically connected to the third wiring VSS3 through the third signal connection part QB3, and the third signal input part QA3 is used to input the third signal to the third wiring VSS3.

[0269] According to some exemplary embodiments, a first insulating layer is provided between the first source-drain metal layer SD1 and the second source-drain metal layer SD2, and a second insulating layer is provided between the second source-drain metal layer SD2 and the third source-drain metal layer SD3; the first insulating layer has a plurality of first vias, the first signal connection part QB1 overlaps with the first signal input part QA1 through part of the first vias, the second signal connection part QB2 overlaps with the second signal input part QA2 through part of the first vias, and the third signal connection part QB3 overlaps with the third signal input part QA3 through part of the first vias; the second insulating layer has a plurality of second vias, the first routing VSS1 overlaps with the first signal connection part QB1 through part of the second vias, the second routing VSS2 overlaps with the second signal connection part QB2 through part of the second vias, and the third routing VSS3 overlaps with the third signal connection part QB3 through part of the second vias; the orthographic projection of each first via on the base substrate 100 is spaced apart from the orthographic projection of each second via on the base substrate 100.

[0270] For example, the first insulating layer between the first source-drain metal layer SD1 and the second source-drain metal layer SD2 includes a passivation layer PVX and a first planarization layer PLN1. Referring to FIG7B , the passivation layer PVX has a plurality of seventh vias H37, a portion of which exposes the first signal input portion QA1, a portion of which exposes the second signal input portion QA2, and a portion of which exposes the third signal input portion QA3. Referring to FIG7C , the first planarization layer PLN1 has a plurality of eighth vias H38, one eighth via H38 being connected to one seventh via H37, and the orthographic projection of the eighth via H38 on the base substrate overlaps the orthographic projection of the seventh via H37 on the base substrate.

[0271] The first signal connection part QB1 and the first signal input part QA1 are overlapped through part of the seventh via H37 and the eighth via H38, the second signal connection part QB2 and the second signal input part QA2 are overlapped through part of the seventh via H37 and the eighth via H38, and the third signal connection part QB3 and the third signal input part QA3 are overlapped through part of the seventh via H37 and the eighth via H38.

[0272] For example, the second insulating layer between the second source / drain metal layer SD2 and the third source / drain metal layer SD3 includes a second planarization layer PLN2. Referring to FIG. 7E and FIG. 7F , the second planarization layer PLN2 has a plurality of fourth vias H44. A portion of the fourth vias H44 exposes the first signal connection portion QB1, and one end of the first trace VSS1 overlaps the first signal connection portion QB1 through a portion of the fourth vias H44. A portion of the fourth vias H44 exposes the second signal connection portion, and one end of the second trace VSS2 overlaps the second signal connection portion QB2 through a portion of the fourth vias H44. A portion of the fourth vias H44 exposes QB2 and the third signal connection portion QB3, and one end of the third trace VSS3 overlaps the third signal connection portion QB3 through a portion of the fourth vias H44.

[0273] 7B , 7C and 7E , the orthographic projection of the fourth via hole H44 on the base substrate is spaced apart from the orthographic projections of the seventh via hole H37 and the eighth via hole H38 on the base substrate.

[0274] 8A-8F are plan views of some film layers in a display substrate located in a display area according to some exemplary embodiments of the present disclosure;

[0275] Among them, Figure 8A illustrates a combination of a third source-drain metal layer and a third planarization layer, Figure 8B illustrates a combination of a third source-drain metal layer and a first electrode layer, Figure 8C illustrates a combination of a third source-drain metal layer, a first electrode layer and a pixel defining layer, Figure 8D illustrates a combination of a third source-drain metal layer, a first electrode layer, a pixel defining layer and a spacer layer, Figure 8E illustrates a combination of a first electrode layer, a pixel defining layer and a spacer layer, and Figure 8F illustrates a combination of a first electrode layer, a pixel defining layer and a second electrode layer.

[0276] 8A , the third planarization layer PLN3 has a first via hole H51 and a second via hole H52 , wherein the first via hole H51 exposes a portion of the first connection structure C41 , and the second via hole H52 exposes a portion of the second power signal line VSS.

[0277] 8B , the first electrode layer ANE includes a first electrode F1 , an electrode connecting portion L4 , a first connecting portion L1 , a second connecting portion L2 , and a third connecting portion L3 .

[0278] 8B and 8A , the electrode connection portion L4 is directly connected to the first electrode F1, and the electrode connection portion L4 is electrically connected to the first connection structure C41 through the second via H52 in the third planarization layer PLN3. That is, the first electrode F1 is electrically connected to the second electrode D6 of the sixth transistor T6 via the first connection structure C41, the second connection structure C32, and the fourth connection structure C24, in sequence.

[0279] The first connection part L1 is electrically connected to the first trace VSS 1 through the first via H51 of the third planarization layer PLN3, the second connection part L2 is electrically connected to the second trace VSS2 through the first via H51 of the third planarization layer PLN3, and the third connection part L3 is electrically connected to the third trace VSS3 through the first via H51 of the third planarization layer PLN3.

[0280] 8C , the pixel defining layer PDL has a pixel opening K, a first via hole H61 , a second via hole H62 , and a third via hole H63 .

[0281] 8C and 8B , the pixel opening K exposes a portion of the first electrode F1 , the first via hole H61 exposes a portion of the first connection portion L1 , the second via hole H62 exposes a portion of the second connection portion L2 , and the third via hole H63 exposes a portion of the third connection portion L3 .

[0282] 8D and 8E , the partition layer 300 includes a plurality of partition portions 301 spaced apart along the second direction Y, each partition portion 301 being in the shape of a strip extending along the first direction X, and the partition portion 301 being arranged to bypass the pixel opening K, the first via H61, the second via H62, and the third via H63 in the pixel definition layer PDL. Exemplarily, the orthographic projection of the partition portion 301 on the substrate is spaced apart from the orthographic projection of the pixel opening K on the substrate, and the orthographic projection of the partition portion 301 on the substrate is spaced apart from the orthographic projections of the first via H61, the second via H62, and the third via H63 on the substrate, or the orthographic projection of the partition portion 301 on the substrate partially overlaps with the orthographic projections of the first via H61, the second via H62, and the third via H63 on the substrate.

[0283] 8F , the first portion CA1 , the second portion CA2 , and the third portion CA3 are each independently located between two adjacent partition portions 301 .

[0284] Exemplarily, referring back to FIG8D , the display substrate includes n light-emitting units W (one light unit W is exemplarily shown in the figure) arranged at intervals along the second direction Y, and one light-emitting unit W includes a first light-emitting group W1, a second light-emitting group W2, a third light-emitting group W3 and a second light-emitting group W2 arranged along the second direction Y.

[0285] The first light-emitting group W1 includes m first light-emitting elements E1 and m third light-emitting elements E3, and the m first light-emitting elements E1 and the m third light-emitting elements E3 are alternately arranged along the first direction X; the second light-emitting group W2 includes 2m second light-emitting elements E2 arranged along the first direction X; the third light-emitting group W3 includes m third light-emitting elements E3 and m first light-emitting elements E1, and the m third light-emitting elements E3 and the m first light-emitting elements E1 are alternately arranged along the first direction X, where n and m are positive integers.

[0286] 8D , the light-emitting elements are arranged along the first direction X and the second direction Y to form multiple rows and columns of light-emitting elements. The first light-emitting group W1 comprises m first light-emitting elements E1 and m third light-emitting elements E3 arranged alternately in a row. The third light-emitting group W3 comprises m third light-emitting elements E3 and m first light-emitting elements E1 arranged alternately in a row. One first light-emitting element E1 in the first light-emitting group W1 and one third light-emitting element E3 in the third light-emitting group W3 are located in the same column, and one third light-emitting element E3 in the first light-emitting group W1 and one first light-emitting element E1 in the third light-emitting group W3 are located in the same column. The second light-emitting group W2 comprises 2m second light-emitting elements E2 in a row. For example, the 2m second light-emitting elements E2 are located in odd columns, and the m first light-emitting elements E1 and the m third light-emitting elements E3 are located in even columns, or the 2m second light-emitting elements E2 are located in even columns, and the m first light-emitting elements E1 and the m third light-emitting elements E3 are located in odd columns.

[0287] 8F , the first portion CA1 includes a plurality of second electrodes F2 spaced apart along the first direction X, with two adjacent second electrodes F2 electrically connected by a bridge F2a. The first portion CA1 serves as a plurality of second electrodes F2 for a plurality of first light-emitting elements E1 spaced apart along the first direction X. The second portion CA2 includes a plurality of second electrodes F2 spaced apart along the first direction X, with two adjacent second electrodes F2 electrically connected by a bridge F2a. The second portion CA2 serves as a plurality of second electrodes F2 for a plurality of second light-emitting elements E2 spaced apart along the first direction X. The third portion CA3 includes a plurality of second electrodes F2 spaced apart along the first direction X, with two adjacent second electrodes F2 electrically connected by a bridge F2a. The third portion CA3 serves as a plurality of second electrodes F2 for a plurality of third light-emitting elements E3 spaced apart along the first direction X.

[0288] Further, in combination with Figure 8D and Figure 8F, the first part CA1 includes a first sub-part CA11 and a second sub-part CA12, a first sub-part CA11 includes m second electrodes F2 of m first light-emitting elements E1 in a first light-emitting group W1, and a second sub-part CA12 includes m second electrodes F2 of m first light-emitting elements E1 in a third light-emitting group W3; a second part CA2 includes 2m second electrodes F2 of 2m second light-emitting elements E2 in a second light-emitting group W2; the third part CA3 includes a third sub-part CA31 and a fourth sub-part CA32, a third sub-part CA31 includes m second electrodes F2 of m third light-emitting elements E3 in a first light-emitting group W1, and a fourth sub-part CA32 includes m second electrodes F2 of m third light-emitting elements E3 in a third light-emitting group W3.

[0289] A first sub-section CA11 is electrically connected to m1 first wires VSS1 through m1 first connection parts L1, a second sub-section CA12 is electrically connected to m2 first wires VSS1 through m2 first connection parts L1, a second sub-section CA2 is electrically connected to 2m3 second wires VSS2 through 2m3 second connection parts L2, a third sub-section CA31 is electrically connected to m4 third wires VSS3 through m4 third connection parts L3, a fourth sub-section CA32 is electrically connected to m5 third wires VSS3 through m5 third connection parts L3, and m1, m2, m3, m4, and m5 are independently selected from positive integers less than or equal to m. That is, multiple first sub-sections CA11 are electrically connected to multiple first routings VSS1 respectively to form a grid-like routing, multiple second sub-sections CA12 are electrically connected to multiple first routings VSS1 respectively to form a grid-like routing, multiple second sections CA2 are electrically connected to multiple second routings VSS2 respectively to form a grid-like routing, multiple third sub-sections CA31 are electrically connected to multiple third routings VSS3 respectively to form a grid-like routing, and multiple fourth sub-sections CA32 are electrically connected to multiple third routings VSS3 respectively to form a grid-like routing. By forming such a grid-like routing, it is beneficial to reduce the voltage drop generated by the first signal, the second signal and the third signal during the transmission process.

[0290] For example, referring to FIG8D , the second power signal line VSS includes m routing groups V (one routing group V is shown in the figure as an example) arranged at intervals along the first direction X. Each routing group V includes a second routing group VSS2, a first routing group VSS1, a second routing group VSS2, and a third routing group VSS3 arranged at intervals along the first direction X. The orthographic projection of the routing group V on the base substrate 100 partially overlaps with the orthographic projection of the second light-emitting group W2 on the base substrate 100. That is, the first routing group VSS1, the second routing group VSS2, the third routing group VSS3, and the data signal line Data are arranged in a column corresponding to the second light-emitting element E2, and the first power signal line VDD is arranged in a column corresponding to the first light-emitting element E1 and the third light-emitting element E3.

[0291] For example, referring to Figure 8D, the first second routing VSS2 is located between two adjacent data signal lines Data, the first routing VSS1 is located between the connected data signal line Data and the first power signal line VDD, the second second routing VSS2 is located between two adjacent data signal lines Data, and the third routing VSS3 is located between the connected data signal line Data and the first power signal line VDD.

[0292] For example, a first sub-section CA11 is electrically connected to m first wires VSS1 through m first connection parts L1, a second sub-section CA12 is electrically connected to m first wires VSS1 through m first connection parts L1, a second sub-section CA2 is electrically connected to 2m second wires VSS2 through 2m second connection parts L2, a third sub-section CA31 is electrically connected to m third wires VSS3 through m third connection parts L3, and a fourth sub-section CA32 is electrically connected to m third wires VSS3 through m third connection parts L3.

[0293] For example, as shown in FIG8D , one end of a second connection portion L2 overlaps a second portion CA2 and the other end extends in a direction away from the first side area NA1 and overlaps an adjacent second trace VSS2 .

[0294] 9A-9E are plan views of some film layers in a display substrate located in a display area according to some exemplary embodiments of the present disclosure;

[0295] Among them, Figure 9A illustrates a combination of a third source-drain metal layer and a third planarization layer, Figure 9B illustrates a combination of a third source-drain metal layer and a first electrode layer, Figure 9C illustrates a combination of a third source-drain metal layer, a first electrode layer and a pixel defining layer, Figure 9D illustrates a combination of a third source-drain metal layer, a first electrode layer, a pixel defining layer and a spacer layer, and Figure 9E illustrates a combination of a third source-drain metal layer, a first electrode layer, a pixel defining layer, a spacer layer and a second electrode layer.

[0296] 9A , the third planarization layer PLN3 has a first via hole H51 and a second via hole H52 , wherein the first via hole H51 exposes a portion of the first connection structure C41 and the second via hole H52 exposes a portion of the second power signal line VSS.

[0297] 9B , the first electrode layer ANE includes a first electrode F1 , an electrode connecting portion L4 , a first connecting portion L1 , a second connecting portion L2 , and a third connecting portion L3 .

[0298] 9B and 9A , the electrode connection portion L4 is directly connected to the first electrode F1, and the electrode connection portion L4 is electrically connected to the first connection structure C41 through the second via H52 in the third planarization layer PLN3. That is, the first electrode F1 is electrically connected to the second electrode D6 of the sixth transistor T6 via the first connection structure C41, the second connection structure C32, and the fourth connection structure C24, in sequence.

[0299] The first connection part L1 is electrically connected to the first trace VSS1 through the first via H51 of the third planarization layer PLN3, the second connection part L2 is electrically connected to the second trace VSS2 through the first via H51 of the third planarization layer PLN3, and the third connection part L3 is electrically connected to the third trace VSS3 through the first via H51 of the third planarization layer PLN3.

[0300] 9C , the pixel defining layer PDL has a pixel opening K, a first via hole H61 , a second via hole H62 , and a third via hole H63 .

[0301] 9C and 9B , the pixel opening K exposes a portion of the first electrode F1 , the first via hole H61 exposes a portion of the first connection portion L1 , the second via hole H62 exposes a portion of the second connection portion L2 , and the third via hole H63 exposes a portion of the third connection portion L3 .

[0302] 9D and 9E , the partition layer 300 includes a plurality of partition portions 301 spaced apart along the second direction Y. Each partition portion 301 is in the shape of a strip extending along the first direction X. The first portion CA1 , the second portion CA2 , and the third portion CA3 are independently located between two adjacent partition portions 301 .

[0303] Exemplarily, referring back to FIG9D , the display substrate includes n light-emitting units W (one light-emitting unit W is shown exemplarily in the figure) arranged at intervals along the second direction Y, and one light-emitting unit W includes a first light-emitting group W1, a second light-emitting group W2, a third light-emitting group W3 and a second light-emitting group W2 arranged along the second direction Y.

[0304] The first light-emitting group W1 includes m first light-emitting elements E1 and m third light-emitting elements E3, and the m first light-emitting elements E1 and the m third light-emitting elements E3 are alternately arranged along the first direction X; the second light-emitting group W2 includes 2m second light-emitting elements E2 arranged along the first direction X; the third light-emitting group W3 includes m third light-emitting elements E3 and m first light-emitting elements E1, and the m third light-emitting elements E3 and the m first light-emitting elements E1 are alternately arranged along the first direction X, where n and m are positive integers.

[0305] 9D , the light-emitting elements are arranged along the first direction X and the second direction Y to form multiple rows and columns of light-emitting elements. The first light-emitting group W1 comprises m first light-emitting elements E1 and m third light-emitting elements E3 arranged alternately in a row. The third light-emitting group W3 comprises m third light-emitting elements E3 and m first light-emitting elements E1 arranged alternately in a row. One first light-emitting element E1 in the first light-emitting group W1 and one third light-emitting element E3 in the third light-emitting group W3 are located in the same column, and one third light-emitting element E3 in the first light-emitting group W1 and one first light-emitting element E1 in the third light-emitting group W3 are located in the same column. The second light-emitting group W2 comprises 2m second light-emitting elements E2 in a row. For example, the 2m second light-emitting elements E2 are located in odd columns, and the m first light-emitting elements E1 and the m third light-emitting elements E3 are located in even columns, or the 2m second light-emitting elements E2 are located in even columns, and the m first light-emitting elements E1 and the m third light-emitting elements E3 are located in odd columns.

[0306] 9E , the first portion CA1 includes a plurality of second electrodes F2 spaced apart along the first direction X, two adjacent second electrodes F2 being electrically connected by a bridge F2a, and the first portion CA1 serving as a plurality of second electrodes F2 for a plurality of first light-emitting elements E1 spaced apart along the first direction X; the second portion CA2 includes a plurality of second electrodes F2 spaced apart along the first direction X, two adjacent second electrodes F2 being electrically connected by a bridge F2a, and the second portion CA2 serving as a plurality of second electrodes F2 for a plurality of second light-emitting elements E2 spaced apart along the first direction X; and the third portion CA3 includes a plurality of second electrodes F2 spaced apart along the first direction X, two adjacent second electrodes F2 being electrically connected by a bridge F2a, and the third portion CA3 serving as a plurality of second electrodes F2 for a plurality of third light-emitting elements E3 spaced apart along the first direction X.

[0307] Further, the first portion CA1 includes a first sub-portion CA11 and a second sub-portion CA12, a first sub-portion CA11 includes m second electrodes F2 of m first light-emitting elements E1 in a first light-emitting group W1, and a second sub-portion CA12 includes m second electrodes F2 of m first light-emitting elements E1 in a third light-emitting group W3; a second portion CA2 includes 2m second electrodes F2 of 2m second light-emitting elements E2 in a second light-emitting group W2; the third portion CA3 includes a third sub-portion CA31 and a fourth sub-portion CA32, a third sub-portion CA31 includes m second electrodes F2 of m third light-emitting elements E3 in a first light-emitting group W1, and a fourth sub-portion CA32 includes m second electrodes F2 of m third light-emitting elements E3 in a third light-emitting group W3.

[0308] A first sub-section CA11 is electrically connected to m1 first wires VSS1 through m1 first connection parts L1, a second sub-section CA12 is electrically connected to m2 first wires VSS1 through m2 first connection parts L1, a second sub-section CA2 is electrically connected to 2m3 second wires VSS2 through 2m3 second connection parts L2, a third sub-section CA31 is electrically connected to m4 third wires VSS3 through m4 third connection parts L3, a fourth sub-section CA32 is electrically connected to m5 third wires VSS3 through m5 third connection parts L3, and m1, m2, m3, m4, and m5 are independently selected from positive integers less than or equal to m. That is, multiple first sub-sections CA11 are electrically connected to multiple first routings VSS1 respectively to form a grid-like routing, multiple second sub-sections CA12 are electrically connected to multiple first routings VSS1 respectively to form a grid-like routing, multiple second sections CA2 are electrically connected to multiple second routings VSS2 respectively to form a grid-like routing, multiple third sub-sections CA31 are electrically connected to multiple third routings VSS3 respectively to form a grid-like routing, and multiple fourth sub-sections CA32 are electrically connected to multiple third routings VSS3 respectively to form a grid-like routing. By forming such a grid-like routing, it is beneficial to reduce the voltage drop generated by the first signal, the second signal and the third signal during the transmission process.

[0309] By way of example, referring to FIG. 9D , the second power signal line VSS includes m routing groups V (one routing group V is shown in the figure as an example) arranged at intervals along the first direction X. Each routing group V includes a second routing group VSS2, a first routing group VSS1, a second routing group VSS2, and a third routing group VSS3 arranged at intervals along the first direction X. The orthographic projection of the routing group V on the base substrate 100 partially overlaps with the orthographic projection of the second light-emitting group W2 on the base substrate 100. That is, the first routing group VSS1, the second routing group VSS2, the third routing group VSS3, and the data signal line Data are arranged in a column corresponding to the second light-emitting element E2, and the first power signal line VDD is arranged in a column corresponding to the first light-emitting element E1 and the third light-emitting element E3.

[0310] For example, referring to Figure 9D, the first second routing VSS2 is located between two adjacent data signal lines Data, the first routing VSS1 is located between the connected data signal line Data and the first power signal line VDD, the second second routing VSS2 is located between two adjacent data signal lines Data, and the third routing VSS3 is located between the connected data signal line Data and the first power signal line VDD.

[0311] For example, a first sub-section CA11 is electrically connected to m first wires VSS1 through m first connection parts L1, a second sub-section CA12 is electrically connected to m first wires VSS1 through m first connection parts L1, a second sub-section CA2 is electrically connected to 2m second wires VSS2 through 2m second connection parts L2, a third sub-section CA31 is electrically connected to m third wires VSS3 through m third connection parts L3, and a fourth sub-section CA32 is electrically connected to m5 third wires VSS3 through m third connection parts L3.

[0312] For example, one end of a second connection portion L2 overlaps with a second portion CA2 and the other end extends toward the first side area NA1 and overlaps with an adjacent second trace VSS2 .

[0313] 10A-10M are plan views of some film layers in a display substrate located in a peripheral area according to some exemplary embodiments of the present disclosure;

[0314] 10A illustrates a first source-drain metal layer, FIG10B illustrates a combination of a first source-drain metal layer and a passivation layer, FIG10C illustrates a combination of a first source-drain metal layer, a passivation layer and a first planarization layer, FIG10D illustrates a combination of a first source-drain metal layer and a second source-drain metal layer, FIG10E illustrates a combination of a first source-drain metal layer, a second source-drain metal layer and a second planarization layer, FIG10F illustrates a combination of a first source-drain metal layer, a second source-drain metal layer, a second planarization layer and a third source-drain metal layer, and FIG10G illustrates a first A combination of a source-drain metal layer, a second source-drain metal layer, a third source-drain metal layer and a third planarization layer, FIG10H illustrates a combination of the first source-drain metal layer, the second source-drain metal layer, the third source-drain metal layer and the first electrode layer, FIG10I illustrates a combination of the first electrode layer and the pixel defining layer, FIG10J illustrates a spacer layer, FIG10K illustrates a combination of the first electrode layer, the pixel defining layer and the spacer layer, FIG10L illustrates a second electrode layer, and FIG10M illustrates a combination of the first electrode layer, the pixel defining layer, the spacer layer and the second electrode layer.

[0315] Referring back to FIG. 1 , the peripheral area NA includes a second side area NA2 and a third side area NA3 located on both sides of the display area AA along the first direction X.

[0316] 10M , the display substrate further includes a first side signal input structure U1, a second side signal input structure U2, and a third side signal input structure U3. The first side signal input structure U1 is located in the second peripheral area NA, or the first side signal input structure U1 is located in the third peripheral area NA (the figure exemplarily shows the first side signal input structure U1 located in the second peripheral area NA), or the first side signal input structure U1 is located in both the second and third peripheral areas NA. The first side signal input structure U1 is electrically connected to the first portion CA1 and is used to input a first signal to the first portion CA1. The second side signal input structure U2 is located in the second peripheral area NA, or the second side signal input structure U2 is located in the third peripheral area NA (the figure exemplarily shows the second side signal input structure U2 located in the second peripheral area NA), or the second side signal input structure U2 is located in both the second and third peripheral areas NA. The second side signal input structure U2 is electrically connected to the second portion CA2 and is used to input a second signal to the second portion CA2. The third side signal input structure U3 is located in the second peripheral area NA, or the third side signal input structure U3 is located in the third peripheral area NA (the figure shows the third side signal input structure U3 located in the second peripheral area NA by way of example), or the third side signal input structure U3 is located in the second peripheral area NA and the third peripheral area NA, the third side signal input structure U3 is electrically connected to the third part CA3, and the third side signal input structure U3 is used to input the third signal to the third part CA3.

[0317] In addition to the first, second, and third signals input into the display area through the first, second, and third traces VSS1, VSS2, and VSS3, respectively, first, second, and third side signal input structures U1, U2, and U3 are further added to input the first, second, and third signals into the peripheral area. This helps improve the uniformity of the distribution of the first, second, and third signals within the display area. Of course, depending on actual process requirements, either of the two signal input methods can be used.

[0318] According to some exemplary embodiments, with reference to FIG10A , FIG10D , FIG10F , and FIG10H , the first side signal input structure U1 includes a first-layer first side signal portion U1a located on the first electrode layer ANE, a second-layer first side signal portion U1b located on the third source / drain metal layer SD3 , a third-layer first side signal portion U1c located on the second source / drain metal layer SD2 , and a fourth-layer first side signal portion U1d located on the first source / drain metal layer SD1 , the first portion CA1 extends to the peripheral area NA and overlaps with the first-layer first side signal portion U1a, the first-layer first side signal portion U1a overlaps with the second-layer first side signal portion U1b, the second-layer first side signal portion U1b overlaps with the third-layer first side signal portion U1c, and the third-layer first side signal portion U1c overlaps with the fourth-layer first side signal portion U1d;

[0319] 10A , 10D , 10F , and 10H , the second side signal input structure U2 includes a first-layer second side signal portion U2a located on the first electrode layer ANE, a second-layer second side signal portion U2b located on the third source / drain metal layer SD3, a third-layer second side signal portion U2c located on the second source / drain metal layer SD2, and a fourth-layer second side signal portion U2d located on the first source / drain metal layer SD1. The second portion CA2 extends to the peripheral area NA and overlaps with the first-layer second side signal portion U2a. The first-layer second side signal portion U2a overlaps with the second-layer second side signal portion U2b. The second-layer second side signal portion U2b overlaps with the third-layer second side signal portion U2c. The third-layer second side signal portion U2c overlaps with the fourth-layer second side signal portion U2d.

[0320] 10A , 10D , 10F and 10H , the third side signal input structure U3 includes a first-layer third side signal portion U3a located in the first electrode layer ANE, a second-layer third side signal portion U3b located in the third source / drain metal layer SD3, a third-layer third side signal portion U3c located in the second source / drain metal layer SD2, and a fourth-layer third side signal portion U3d located in the first source / drain metal layer SD1. The third portion CA3 extends to the peripheral area NA and overlaps with the first-layer third side signal portion U3a, the first-layer third side signal portion U3a overlaps with the second-layer third side signal portion U3b, the second-layer third side signal portion U3b overlaps with the third-layer third side signal portion U3c, and the third-layer third side signal portion U3c overlaps with the fourth-layer third side signal portion U3d.

[0321] Exemplarily, a passivation layer PVX and a first planarization layer PLN1 are provided between the first source-drain metal layer SD1 and the second source-drain metal layer SD2. Referring to FIG10B , the passivation layer PVX has a plurality of ninth vias H39, a portion of the ninth vias H39 exposing the first side signal portion U1d of the fourth layer, a portion of the ninth vias H39 exposing the second side signal portion U2d of the fourth layer, and a portion of the ninth vias H39 exposing the third side signal portion U3d of the fourth layer. Referring to FIG10C , the first planarization layer PLN1 has a plurality of tenth vias H310, the tenth vias H310 are connected to the ninth vias H39, and the orthographic projection of the tenth vias H310 on the base substrate covers the orthographic projection of the ninth vias H39 on the base substrate. The first side signal portion U1c of the third layer is overlapped with the first side signal portion U1d of the fourth layer through the tenth via hole H310 and the ninth via hole H39, the second side signal portion U2c of the third layer is overlapped with the second side signal portion U2d of the fourth layer through the tenth via hole H310 and the ninth via hole H39, and the third side signal portion U3c of the third layer is overlapped with the third side signal portion U3d of the fourth layer through the tenth via hole H310 and the ninth via hole H39.

[0322] Exemplarily, a second planarization layer PLN2 is disposed between the second source / drain metal layer SD2 and the third source / drain metal layer SD3. Referring to FIG10E , the second planarization layer PLN2 has a plurality of fifth vias H45. Some of the fifth vias H45 expose the third-layer first side signal portion U1c, some of the fifth vias H45 expose the third-layer second side signal portion U2c, and some of the fifth vias expose the third-layer third side signal portion U3c. The second-layer first side signal portion U1b overlaps the third-layer first side signal portion U1c through the fifth vias H45. The second-layer second side signal portion U2b overlaps the third-layer second side signal portion U2c through the fifth vias H45. The second-layer third side signal portion U3b overlaps the third-layer third side signal portion U3c through the fifth vias H45.

[0323] Exemplarily, a third planarization layer PLN3 is disposed between the third source / drain metal layer SD3 and the first electrode layer ANE. Referring to FIG10G , the third planarization layer PLN3 has G multiple third vias H53. Part of the third vias H53 expose the second-layer first side signal portion U1b, part of the third vias H53 expose the second-layer second side signal portion U2b, and part of the third vias H53 expose the second-layer third side signal portion U3b. The first-layer first side signal portion U1a overlaps the second-layer first side signal portion U1b through part of the third vias H53. The first-layer second side signal portion U2a overlaps the second-layer second side signal portion U2b through part of the third vias H53. The first-layer third side signal portion U3a overlaps the second-layer third side signal portion U3b through part of the third vias H53.

[0324] Exemplarily, a pixel-defining layer (PDL) is further disposed between the first electrode layer ANE and the second electrode layer Cath. Referring to FIG10I , the pixel-defining layer PDL includes a fourth via H64, a fifth via H65, and a sixth via H66. The fourth via H64 exposes a portion of the first-layer first side signal portion U1a, the fifth via H65 exposes a portion of the first-layer second side signal portion U2a, and the sixth via H66 exposes a portion of the first-layer third side signal portion U3a. Referring to FIG10I and FIG10M , the first sub-segment CA11 and the second sub-segment CA12 extend to the peripheral area and overlap with a portion of the first-layer first side signal portion U1a via the fourth via H64. The second sub-segment CA2 extends to the peripheral area and overlaps with the first-layer second side signal portion U2a via the fifth via H65. The third sub-segment CA31 and the fourth sub-segment CA32 extend to the peripheral area and overlap with the first-layer third side signal portion U3a via the sixth via H66.

[0325] 10K , the orthographic projection of the partition layer 300 on the base substrate does not cover the orthographic projections of the fourth via H64, the fifth via H65, and the sixth via H66 on the base substrate, or the orthographic projection of the partition layer 300 on the base substrate only partially covers the orthographic projections of the fourth via H64, the fifth via H65, and the sixth via H66 on the base substrate.

[0326] 10K , 10J and 10L , the partition layer 300 includes a first partition portion 3011 , a second partition portion 3012 , a third partition portion 3013 , a fourth partition portion 3014 , a fifth partition portion 3015 and a sixth partition portion 3016 , which are spaced apart along the second direction Y.

[0327] The second sub-section CA12 is located between the first partition section 3011 and the second partition section 3012, a portion of the second portion CA2 is located between the second partition section 3012 and the third partition section 3013, the third sub-section CA31 is located between the third partition section 3013 and the fourth partition section 3014, the first sub-section CA11 is located between the fourth partition section 3014 and the fifth partition section 3015, a portion of the second portion CA2 is located between the fifth partition section 3015 and the sixth partition section 3016, and the fourth sub-section CA32 is located between the sixth partition section 3016 and the first partition section 3011.

[0328] The first and second partition portions 3011 and 3012 extend to the second side area NA2 and / or the third side area and connect to the side of the fourth via H64 away from the display area AA, thereby jointly exposing a portion of the first-layer first side signal portion U1a with the fourth via H64. The second and third partition portions 3012 and 3013 extend to the second side area NA2 and / or the third side area and connect to the side of the fifth via H65 away from the display area AA, thereby jointly exposing a portion of the first-layer second side signal portion U1b with the fifth via H65. The third and fourth partition portions 3013 and 3014 extend to the second side area NA2 and / or the third side area but are not connected, thereby jointly exposing a portion of the first-layer third side signal portion U1c with the sixth via H66. The fourth and fifth partition portions 3014 and 3015 extend to the second side area NA2 and / or the third side area and connect to the side of the fourth via H64 away from the display area AA, thereby jointly exposing a portion of the first-layer first side signal portion U1a with the fourth via H64. The fifth and sixth partition portions 3015 and 3016 extend to the second and / or third side areas and connect to the side of the fifth via H65 away from the display area AA, thereby jointly exposing a portion of the first-layer second side signal portion U1b with the fifth via H65. The sixth and sixth partition portions 3016 extend to the second and / or third side areas but are not connected to the first partition portion 3011, thereby jointly exposing a portion of the first-layer third side signal portion U1c with the sixth via H66.

[0329] According to some exemplary embodiments, referring to FIG. 1 , the peripheral area NA further includes a corner area NA-C including a first corner area NA-C1 connecting the first side area NA1 and the second side area NA2 and a second corner area NA-C2 connecting the first side area NA1 and the third side area NA3.

[0330] Referring to Figures 7A, 7D, 10A, and 10D, the third-layer first side signal portion U1c and the first signal connection portion QB1 can be directly connected in the corner area NA-C, and / or the fourth-layer first side signal portion U1d and the first signal input portion QA1 can be directly connected in the corner area NA-C. In other words, the first signal can be transmitted from the driver chip sequentially to the first signal input portion QA1, the first signal input portion QA1, and the first side signal input structure U1.

[0331] Referring to Figures 7A, 7D, 10A, and 10D, the third-layer second side signal portion U2c and the second signal connection portion QB2 can be directly connected in the corner area NA-C, and / or the fourth-layer second side signal portion U2d and the second signal input portion QA2 can be directly connected in the corner area NA-C. In other words, the second signal can be transmitted from the driver chip sequentially to the second signal input portion QA2, the second signal input portion QA2, and the second side signal input structure U2.

[0332] Referring to Figures 7A, 7D, 10A, and 10D, the third-layer third-side signal portion U3c and the third signal connection portion QB3 can be directly connected in the corner area NA-C, and / or the fourth-layer third-side signal portion U3d and the third signal input portion QA3 can be directly connected in the corner area NA-C. In other words, the third signal can be sequentially transmitted from the driver chip to the third signal input portion QA3, the third signal input portion QA3, and the third side signal input structure U3.

[0333] 11A to 11F are plan views of some film layers in a display substrate located in a display area according to some exemplary embodiments of the present disclosure;

[0334] Among them, Figure 11A illustrates a combination of a third source-drain metal layer and a third planarization layer, Figure 11B illustrates a combination of a third source-drain metal layer and a first electrode layer, Figure 11C illustrates a combination of a third source-drain metal layer, a first electrode layer and a pixel defining layer, Figure 11D illustrates a combination of a third source-drain metal layer, a first electrode layer, a pixel defining layer and a spacer layer, Figure 11E illustrates a combination of a first electrode layer, a pixel defining layer and a spacer layer, and Figure 11F illustrates a combination of a first electrode layer, a pixel defining layer and a second electrode layer.

[0335] 11A , the third planarization layer PLN3 has a first via hole H51 and a second via hole H52 , wherein the first via hole H51 exposes a portion of the first connection structure C41 and the second via hole H52 exposes a portion of the second power signal line VSS.

[0336] 11B and 11A , the electrode connection portion L4 is directly connected to the first electrode F1, and the electrode connection portion L4 is electrically connected to the first connection structure C41 through the second via H52 in the third planarization layer PLN3. That is, the first electrode F1 is electrically connected to the second electrode D6 of the sixth transistor T6 via the first connection structure C41, the second connection structure C32, and the fourth connection structure C24, in sequence.

[0337] The first connection part L1 is electrically connected to the first trace VSS1 through the first via H51 of the third planarization layer PLN3, the second connection part L2 is electrically connected to the second trace VSS2 through the first via H51 of the third planarization layer PLN3, and the third connection part L3 is electrically connected to the third trace VSS3 through the first via H51 of the third planarization layer PLN3.

[0338] 11C , the pixel defining layer PDL has a pixel opening K, a first via hole H61 , a second via hole H62 , and a third via hole H63 .

[0339] 11C and 11B , the pixel opening K exposes a portion of the first electrode F1 , the first via hole H61 exposes a portion of the first connection portion L1 , the second via hole H62 exposes a portion of the second connection portion L2 , and the third via hole H63 exposes a portion of the third connection portion L3 .

[0340] 11D and 11E , the partition layer 300 includes a plurality of partition portions 301 arranged at intervals along the first direction X. Each partition portion 301 is in a strip shape extending along the second direction Y.

[0341] 11F , the first portion CA1 , the second portion CA2 , and the third portion CA3 are each independently located between two adjacent partition portions 301 .

[0342] For example, referring back to FIG11D , the display substrate includes m light-emitting units W (one light-emitting unit W is shown as an example in the figure) arranged at intervals along the first direction X, and one light-emitting unit W includes a first light-emitting group W1, a first second light-emitting group W2, a third light-emitting group W3 and a second second light-emitting group W2 arranged in sequence along the first direction X.

[0343] The first light-emitting group W1 includes n first light-emitting elements E1 and n third light-emitting elements E3, and the n first light-emitting elements E1 and the n third light-emitting elements E3 are alternately arranged along the second direction Y; the second light-emitting group W2 includes 2n second light-emitting elements E2 arranged along the second direction Y; the third light-emitting group W3 includes n third light-emitting elements E3 and n first light-emitting elements E1, and the n third light-emitting elements E3 and the n first light-emitting elements E1 are alternately arranged along the second direction Y, where n and m are positive integers.

[0344] 11D , the light-emitting elements are arranged along the first direction X and the second direction Y to form multiple rows and columns of light-emitting elements. The first light-emitting group W1 comprises n first light-emitting elements E1 and n third light-emitting elements E3 arranged alternately in a column. The third light-emitting group W3 comprises n third light-emitting elements E3 and n first light-emitting elements E1 arranged alternately in a column. One first light-emitting element E1 in the first light-emitting group W1 and one third light-emitting element E3 in the third light-emitting group W3 are located in the same row, and one third light-emitting element E3 in the first light-emitting group W1 and one first light-emitting element E1 in the third light-emitting group W3 are located in the same row. The second light-emitting group W2 comprises 2n second light-emitting elements E2 in a column. For example, the 2n second light-emitting elements E2 are located in odd rows, and the n first light-emitting elements E1 and n third light-emitting elements E3 are located in even rows, or the 2n second light-emitting elements E2 are located in even rows, and the n first light-emitting elements E1 and n third light-emitting elements E3 are located in odd rows.

[0345] Referring to Figure 11F, the first portion CA1 includes a plurality of second electrodes F2 spaced apart along the second direction Y, two adjacent second electrodes F2 are electrically connected by a bridge portion F2a, and the first portion CA1 serves as a plurality of second electrodes F2 for a plurality of first light-emitting elements E1 spaced apart along the second direction Y; the second portion CA2 includes a plurality of second electrodes F2 spaced apart along the second direction Y, two adjacent second electrodes F2 are electrically connected by a bridge portion F2a, and the second portion CA2 serves as a plurality of second electrodes F2 for a plurality of second light-emitting elements E2 spaced apart along the second direction Y; and the third portion CA3 includes a plurality of second electrodes F2 spaced apart along the second direction Y, two adjacent second electrodes F2 are electrically connected by a bridge portion F2a, and the third portion CA3 serves as a plurality of second electrodes F2 for a plurality of third light-emitting elements E3 spaced apart along the second direction Y.

[0346] Further, in combination with Figure 11D and Figure 11F, the first part CA1 includes a first sub-part CA11 and a second sub-part CA12, a first sub-part CA11 includes n second electrodes F2 of n first light-emitting elements E1 in a first light-emitting group W1, and a second sub-part CA12 includes n second electrodes F2 of n first light-emitting elements E1 in a third light-emitting group W3; a second part CA2 includes 2n second electrodes F2 of 2n second light-emitting elements E2 in a second light-emitting group W2; the third part CA3 includes a third sub-part CA31 and a fourth sub-part CA32, a third sub-part CA31 includes n second electrodes F2 of n third light-emitting elements E3 in a first light-emitting group W1, and a fourth sub-part CA32 includes n second electrodes F2 of n third light-emitting elements E3 in a third light-emitting group W3.

[0347] Further, a first sub-section CA11 is electrically connected to n1 first routing lines VSS1 through n1 first connection parts L1, a second sub-section CA12 is electrically connected to n2 first routing lines VSS1 through n2 first connection parts L1, a second sub-section CA2 is electrically connected to 2n3 second routing lines VSS2 through 2n3 second connection parts L2, a third sub-section CA31 is electrically connected to n4 third routing lines VSS3 through n4 third connection parts L3, and a fourth sub-section CA32 is electrically connected to n5 third routing lines VSS3 through n5 third connection parts L3, and n1, n2, n3, n4, and n5 are independently selected from positive integers less than or equal to n.

[0348] By way of example, referring to FIG. 11D , the second power signal line VSS includes m routing groups V (one routing group V is shown in the figure as an example) spaced apart along the first direction X. One routing group V includes a second routing group VSS2, a third routing group VSS3, a second routing group VSS2, and a first routing group VSS1 spaced apart along the first direction X. The orthographic projection of the routing group V on the base substrate 100 partially overlaps with the orthographic projections of the first light-emitting group W1 and the third light-emitting group W3 on the base substrate 100. That is, the first routing group VSS1, the second routing group VSS2, the third routing group VSS3, and the data signal line Data are arranged in the columns corresponding to the first light-emitting element E1 and the third light-emitting element E3, and the first power signal line VDD is arranged in the column corresponding to the second light-emitting element E2.

[0349] For example, referring to FIG. 11D , the first routing line VSS1 , the second routing line VSS2 , and the third routing line VSS3 are each located between the corresponding adjacent data signal line Data and the first power signal line VDD.

[0350] In another aspect, a display device is provided, comprising the display substrate described above. The display device may be a display device such as a liquid crystal display, electronic paper, or an OLED (Organic Light-Emitting Diode) display, as well as any product or component with touch and display functions, such as a television, digital camera, mobile phone, watch, tablet computer, laptop computer, or navigation system, that includes such a display device.

[0351] It should be understood that the display devices according to some exemplary embodiments of the present disclosure have all the features and advantages of the above-mentioned display substrate. These features and advantages can be referred to in the above description of the display substrate and will not be repeated here.

[0352] As used herein, the terms "substantially," "about," "approximately," and other similar terms are used as terms of approximation rather than as terms of degree, and are intended to account for the inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. To account for factors such as process fluctuations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), "about" or "approximately," as used herein, are inclusive of the stated value and mean within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within ±10% or ±5% of the stated value.

[0353] Although some embodiments according to the general inventive concept of the present disclosure have been illustrated and described, it will be appreciated by those skilled in the art that changes may be made to these embodiments without departing from the principles and spirit of the general inventive concept of the present disclosure, the scope of which is defined by the claims and their equivalents.

Claims

1. A display substrate, wherein, The display substrate includes: a substrate substrate, including a display area and a peripheral area located outside the display area; a light-emitting element layer located on the substrate substrate, the light-emitting element layer including a plurality of light-emitting elements located in the display area, the plurality of light-emitting elements being arranged in an array along a first direction and / or a second direction, the plurality of light-emitting elements including a plurality of first light-emitting elements, a plurality of second light-emitting elements, and a plurality of third light-emitting elements, the light-emitting element layer including a first electrode layer located on the substrate substrate, a light-emitting layer located on a side of the first electrode layer away from the substrate substrate, and a second electrode layer located on a side of the light-emitting layer away from the substrate substrate, the first electrode layer including a first electrode of each of the light-emitting elements, the light-emitting layer including a light-emitting portion of each of the light-emitting elements, and the second electrode layer including a second electrode of each of the light-emitting elements; and a partition layer located between the first electrode layer and the second electrode layer, the partition layer including a plurality of partition portions; wherein, the second electrode layer includes a first portion, a second portion, and a third portion that are spaced apart, at least one of the partition portions is provided between any two of the first portion, the second portion, and the third portion, the first portion includes a second electrode of at least one of the first light-emitting elements and is configured to access a first signal, the second portion includes a second electrode of at least one of the second light-emitting elements and is configured to access a second signal, the third portion includes a second electrode of at least one of the third light-emitting elements and is configured to access a third signal, and at least two of the first signal, the second signal, and the third signal are different from each other.

2. The display substrate according to claim 1, wherein, A width of a side of the partition portion away from the substrate substrate is greater than a width of a side of the partition portion close to the substrate substrate.

3. The display substrate according to claim 1 or 2, wherein The display substrate includes a spacer layer located between the first electrode layer and the second electrode layer, the spacer layer including spacers and the partition portions.

4. The display substrate according to any one of claims 1-3, wherein The display substrate includes a second power signal line at least partially located in the display area, the second power signal line including a first trace, a second trace, and a third trace; wherein, the first trace is electrically connected to the first portion, and the first trace is configured to input the first signal to the first portion; the second trace is electrically connected to the second portion, and the second trace is configured to input the second signal to the second portion; and the third trace is electrically connected to the third portion, and the third trace is configured to input the third signal to the third portion.

5. The display substrate according to claim 4, wherein, The display substrate further includes a driving circuit layer located between the substrate substrate and the first electrode layer, the driving circuit layer including a metal layer, and the second power signal line is located on the metal layer.

6. The display substrate according to claim 5, wherein, The first electrode layer includes a first connection portion, a second connection portion, and a third connection portion, the first portion is electrically connected to the first trace through the first connection portion, the second portion is electrically connected to the second trace through the second connection portion, and the third portion is electrically connected to the third trace through the third connection portion.

7. The display substrate according to claim 5 or 6, wherein, The driving circuit layer includes a third source-drain metal layer, and the second power supply signal line is located in the third source-drain metal layer. The third source-drain metal layer further includes a plurality of data signal lines and a plurality of first power supply signal lines extending along the second direction; Wherein, the second power supply signal line is located in the display area, at least part of the second power supply signal line is located between the adjacent data signal line and the first power supply signal line, and / or at least part of the second power supply signal line is located between two adjacent data signal lines.

8. The display substrate according to claim 7, wherein, The driving circuit layer further includes a second source-drain metal layer located on the side of the third source-drain metal layer close to the substrate, and a first source-drain metal layer located on the side of the second source-drain metal layer close to the substrate; The peripheral area includes a first side area located outside the display area along the second direction. The first source-drain metal layer includes a first signal input portion, a second signal input portion and a third signal input portion located in the first side area. The second source-drain metal layer includes a first signal connection portion, a second signal connection portion and a third signal connection portion located in the first side area; Wherein, the first signal input portion is electrically connected to the first trace through the first signal connection portion, and the first signal input portion is used to input the first signal to the first trace; The second signal input portion is electrically connected to the second trace through the second signal connection portion, and the second signal input portion is used to input the second signal to the second trace; and The third signal input portion is electrically connected to the third trace through the third signal connection portion, and the third signal input portion is used to input the third signal to the third trace.

9. The display substrate according to claim 8, wherein, The first signal connection portion, the second signal connection portion and the third signal connection portion are arranged to extend along the first direction and are spaced apart along the second direction. The second power supply signal line is arranged to extend along the second direction; Wherein, one end of the first trace is overlapped with the first signal connection portion, one end of the second trace is overlapped with the second signal connection portion, and one end of the third trace is overlapped with the third signal connection portion.

10. The display substrate according to claim 8 or 9, wherein There is a first insulating layer between the first source-drain metal layer and the second source-drain metal layer, and there is a second insulating layer between the second source-drain metal layer and the third source-drain metal layer; The first insulating layer has a plurality of first vias. The first signal connection portion is overlapped with the first signal input portion through some of the first vias. The second signal connection portion is overlapped with the second signal input portion through some of the first vias. The third signal connection portion is overlapped with the third signal input portion through some of the first vias; The second insulating layer has a plurality of second vias. The first trace is overlapped with the first signal connection portion through some of the second vias. The second trace is overlapped with the second signal connection portion through some of the second vias. The third trace is overlapped with the third signal connection portion through some of the second vias; Wherein, the orthographic projection of each of the first vias on the substrate is spaced apart from the orthographic projection of each of the second vias on the substrate.

11. The display substrate according to any one of claims 7-10, wherein, One of the first parts includes the second electrode of one of the first light-emitting elements, one of the second parts includes the second electrode of one of the second light-emitting elements, and one of the third parts includes the second electrode of one of the third light-emitting elements.

12. The display substrate according to claim 11, wherein, The partition layer is in a grid shape and includes a first opening, a second opening, and a third opening. The first part is embedded in the first opening, the second part is embedded in the second opening, and the third part is embedded in the third opening.

13. The display substrate according to any one of claims 8-10, wherein, The first part includes a plurality of the second electrodes spaced along the first direction, and two adjacent second electrodes are electrically connected by a bridging portion. The first part serves as the second electrodes of a plurality of the first light-emitting elements arranged at intervals along the first direction; The second part includes a plurality of the second electrodes spaced along the first direction, and two adjacent second electrodes are electrically connected by a bridging portion. The second part serves as the second electrodes of a plurality of the second light-emitting elements arranged at intervals along the first direction; and The third part includes a plurality of the second electrodes spaced along the first direction, and two adjacent second electrodes are electrically connected by a bridging portion. The third part serves as the second electrodes of a plurality of the third light-emitting elements arranged at intervals along the first direction.

14. The display substrate according to claim 13, wherein, The partition layer includes a plurality of partition portions spaced along the second direction, and each partition portion is in a strip shape extending along the first direction. The first part, the second part, and the third part are respectively and independently located between two adjacent partition portions.

15. The display substrate according to any one of claims 7-10, wherein, The first part includes a plurality of the second electrodes spaced along the second direction, and two adjacent second electrodes are electrically connected by a bridging portion. The first part serves as the second electrodes of a plurality of the first light-emitting elements arranged at intervals along the second direction; The second part includes a plurality of the second electrodes spaced along the second direction, and two adjacent second electrodes are electrically connected by a bridging portion. The second part serves as the second electrodes of a plurality of the second light-emitting elements arranged at intervals along the second direction; and The third part includes a plurality of the second electrodes spaced along the second direction, and two adjacent second electrodes are electrically connected by a bridging portion. The third part serves as the second electrodes of a plurality of the third light-emitting elements arranged at intervals along the second direction.

16. The display substrate according to claim 15, wherein, The partition layer includes a plurality of partition portions spaced along the first direction, and each partition portion is in a strip shape extending along the second direction. The first part, the second part, and the third part are respectively and independently located between two adjacent partition portions.

17. The display substrate according to claim 13 or 14, wherein, The peripheral region includes a second side region and a third side region located on both sides of the display region along the first direction. The display substrate further includes a first side portion signal input structure, a second side portion signal input structure, and a third side portion signal input structure; Among them, the first side signal input structure is located in the second peripheral region and / or the third peripheral region. The first side signal input structure is electrically connected to the first part, and the first side signal input structure is used to input the first signal to the first part; The second side signal input structure is located in the second peripheral region and / or the third peripheral region. The second side signal input structure is electrically connected to the second part, and the second side signal input structure is used to input the second signal to the second part; and The third side signal input structure is located in the second peripheral region and / or the third peripheral region. The third side signal input structure is electrically connected to the third part, and the third side signal input structure is used to input the third signal to the third part.

18. The display substrate according to claim 17, wherein, The first side signal input structure includes a first-layer first side signal part located in the first electrode layer, a second-layer first side signal part located in the third source-drain metal layer, a third-layer first side signal part located in the second source-drain metal layer, and a fourth-layer first side signal part located in the first source-drain metal layer. The first part extends to the peripheral region and overlaps with the first-layer first side signal part. The first-layer first side signal part overlaps with the second-layer first side signal part. The second-layer first side signal part overlaps with the third-layer first side signal part. The third-layer first side signal part overlaps with the fourth-layer first side signal part; The second side signal input structure includes a first-layer second side signal part located in the first electrode layer, a second-layer second side signal part located in the third source-drain metal layer, a third-layer second side signal part located in the second source-drain metal layer, and a fourth-layer second side signal part located in the first source-drain metal layer. The second part extends to the peripheral region and overlaps with the first-layer second side signal part. The first-layer second side signal part overlaps with the second-layer second side signal part. The second-layer second side signal part overlaps with the third-layer second side signal part. The third-layer second side signal part overlaps with the fourth-layer second side signal part; The third side signal input structure includes a first-layer third side signal part located in the first electrode layer, a second-layer third side signal part located in the third source-drain metal layer, a third-layer third side signal part located in the second source-drain metal layer and a fourth-layer third side signal part located in the first source-drain metal layer. The third part extends to the peripheral region and overlaps with the first-layer third side signal part. The first-layer third side signal part overlaps with the second-layer third side signal part. The second-layer third side signal part overlaps with the third-layer third side signal part. The third-layer third side signal part overlaps with the fourth-layer third side signal part.

19. The display substrate according to claim 17, wherein, The peripheral region further includes a corner region. The corner region includes a first corner region connecting the first side region and the second side region and a second corner region connecting the first side region and the third side region; The first side signal part of the third layer is directly connected to the first signal connection part in the corner area, and / or the first side signal part of the fourth layer is directly connected to the first signal input part in the corner area; The second side signal part of the third layer is directly connected to the second signal connection part in the corner area, and / or the second side signal part of the fourth layer is directly connected to the second signal input part in the corner area; and The third side signal part of the third layer is directly connected to the third signal connection part in the corner area, and / or the third side signal part of the fourth layer is directly connected to the third signal input part in the corner area.

20. The display substrate according to claim 11 or 12, wherein The display substrate includes m light-emitting units arranged at intervals along the first direction, and one light-emitting unit includes a first light-emitting group, a first second light-emitting group, a third light-emitting group, and a second second light-emitting group arranged along the first direction; The first light-emitting group includes n first light-emitting elements and n third light-emitting elements, and the n first light-emitting elements and the n third light-emitting elements are alternately arranged at intervals along the second direction; The second light-emitting group includes 2n second light-emitting elements arranged at intervals along the second direction; The third light-emitting group includes n third light-emitting elements and n first light-emitting elements, and the n third light-emitting elements and the n first light-emitting elements are alternately arranged at intervals along the second direction, where n and m are positive integers; Among them, one first part includes the second electrode of one first light-emitting element, and one first part is electrically connected to a first trace through a first connection part; One second part includes the second electrode of one second light-emitting element, and one second part is electrically connected to a second trace through a second connection part; and One third part includes the second electrode of one third light-emitting element, and one third part is electrically connected to a third trace through a third connection part.

21. The display substrate according to claim 20, wherein In one first light-emitting group, the n first parts of the n first light-emitting elements are respectively electrically connected to a first trace through n first connection parts, and the n third parts of the n third light-emitting elements are respectively electrically connected to a third trace through n third connection parts; In one second light-emitting group, the 2n second parts of the 2n second light-emitting elements are respectively electrically connected to a second trace through 2n second connection parts; And In one third light-emitting group, the n third parts of the n third light-emitting elements are respectively electrically connected to a third trace through n third connection parts, and the n first parts of the n first light-emitting elements are respectively electrically connected to a first trace through n first connection parts.

22. The display substrate according to claim 21, wherein, The second power signal line includes m wiring groups arranged at intervals along the first direction. One wiring group includes a first second trace, a first trace, a second second trace, and a third trace arranged at intervals along the first direction. One wiring group is electrically connected to one light-emitting unit; In one wiring group and one light-emitting unit that are electrically connected, the orthographic projections of the first second trace and the first trace on the substrate partially coincide with the orthographic projection of the first second light-emitting group on the substrate, and the orthographic projections of the second second trace and the third trace on the substrate partially coincide with the orthographic projection of the second second light-emitting group on the substrate; In the first light-emitting group, the n first parts of the n first light-emitting elements are respectively electrically connected to the first traces in the adjacent wiring group on the side of the first second trace away from the first trace through n first connection parts, and the n third parts of the n third light-emitting elements are respectively electrically connected to the third traces in the adjacent wiring group on the side of the first second trace away from the first trace through n third connection parts; In the first second light-emitting group, the 2n second parts of the 2n second light-emitting elements are respectively electrically connected to the first second trace through 2n second connection parts; In the third light-emitting group, the n first parts of the n first light-emitting elements are respectively electrically connected to the first traces through n first connection parts, and the n third parts of the n third light-emitting elements are respectively electrically connected to the third traces through n third connection parts; In the second second light-emitting group, the 2n second parts of the 2n second light-emitting elements are respectively electrically connected to the second second trace through 2n second connection parts.

23. The display substrate according to claim 21, wherein, The second power signal line includes m wiring groups arranged at intervals along the first direction. One wiring group includes a first second trace, a first trace, a second second trace, and a third trace arranged at intervals along the first direction. One wiring group is electrically connected to one light-emitting unit; In one wiring group and one light-emitting unit that are electrically connected, the orthographic projections of the first second trace and the first trace on the substrate partially coincide with the orthographic projection of the first second light-emitting group on the substrate, and the orthographic projections of the second second trace and the third trace on the substrate partially coincide with the orthographic projection of the second second light-emitting group on the substrate; In the first light-emitting group, the n first parts of the n first light-emitting elements are respectively electrically connected to the first traces through n first connection parts, and the n third parts of the n third light-emitting elements are respectively electrically connected to the third traces in the adjacent wiring group on the side of the first second trace away from the first trace through n third connection parts; In the first second light-emitting group, the 2n second portions of the 2n second light-emitting elements are electrically connected to the first second trace through the 2n second connection portions respectively; In the third light-emitting group, the n first portions of the n first light-emitting elements are electrically connected to the first trace through the n first connection portions respectively, and the n third portions of the n third light-emitting elements are electrically connected to the third trace through the n third connection portions respectively; In the second second light-emitting group, the 2n second portions of the 2n second light-emitting elements are electrically connected to the second second trace through the 2n second connection portions respectively.

24. The display substrate according to claim 13 or 14, wherein, The display substrate includes n light-emitting units arranged at intervals along the second direction, and one light-emitting unit includes a first light-emitting group, a second light-emitting group, a third light-emitting group and a second light-emitting group arranged along the second direction; The first light-emitting group includes m first light-emitting elements and m third light-emitting elements, and the m first light-emitting elements and the m third light-emitting elements are alternately arranged at intervals along the first direction; The second light-emitting group includes 2m second light-emitting elements arranged at intervals along the first direction; The third light-emitting group includes m third light-emitting elements and m first light-emitting elements, and the m third light-emitting elements and the m first light-emitting elements are alternately arranged at intervals along the first direction, where n and m are positive integers: The first portion includes a first sub-portion and a second sub-portion. One first sub-portion includes the m second electrodes of the m first light-emitting elements in one first light-emitting group, and one second sub-portion includes the m second electrodes of the m first light-emitting elements in one third light-emitting group; One second portion includes the 2m second electrodes of the 2m second light-emitting elements in one second light-emitting group; The third portion includes a third sub-portion and a fourth sub-portion. One third sub-portion includes the m second electrodes of the m third light-emitting elements in one first light-emitting group, and one fourth sub-portion includes the m second electrodes of the m third light-emitting elements in one third light-emitting group.

25. The display substrate according to claim 24, wherein, One first sub-portion is electrically connected to m1 first traces through m1 first connection portions respectively, one second sub-portion is electrically connected to m2 first traces through m2 first connection portions respectively, one second portion is electrically connected to 2m3 second traces through 2m3 second connection portions respectively, one third sub-portion is electrically connected to m4 third traces through m4 third connection portions respectively, and one fourth sub-portion is electrically connected to m5 third traces through m5 third connection portions respectively. m1, m2, m3, m4, m5 are independently selected from positive integers less than or equal to m.

26. The display substrate according to claim 24 or 25, wherein The second power supply signal line includes m wiring groups arranged at intervals along the first direction. One wiring group includes a second wiring, a first wiring, a second wiring, and a third wiring arranged at intervals along the first direction. The orthographic projection of the wiring group on the substrate partially coincides with the orthographic projection of the second light-emitting group on the substrate; Wherein, one second part is electrically connected to 2m second wirings respectively through 2m second connection parts. One end of one second connection part overlaps with one second part, and the other end extends in a direction away from the first side region and overlaps with the adjacent second wiring.

27. The display substrate according to claim 24 or 25, wherein The second power supply signal line includes m wiring groups arranged at intervals along the first direction. One wiring group includes a second wiring, a first wiring, a second wiring, and a third wiring arranged at intervals along the first direction. The orthographic projection of the wiring group on the substrate partially coincides with the orthographic projection of the second light-emitting group on the substrate; Wherein, one second part is electrically connected to 2m second wirings respectively through 2m second connection parts. One end of one second connection part overlaps with one second part, and the other end extends in a direction close to the first side region and overlaps with the adjacent second wiring.

28. The display substrate according to claim 15 or 16, wherein, The display substrate includes m light-emitting units arranged at intervals along the first direction. One light-emitting unit includes a first light-emitting group, a second light-emitting group, a third light-emitting group, and a second light-emitting group arranged along the first direction; The first light-emitting group includes n first light-emitting elements and n third light-emitting elements. The n first light-emitting elements and the n third light-emitting elements are alternately arranged at intervals along the second direction; The second light-emitting group includes 2n second light-emitting elements arranged at intervals along the second direction; The third light-emitting group includes n third light-emitting elements and n first light-emitting elements. The n third light-emitting elements and the n first light-emitting elements are alternately arranged at intervals along the second direction. n and m are positive integers; The first part includes a first sub-part and a second sub-part. One first sub-part includes n second electrodes of n first light-emitting elements in one first light-emitting group. One second sub-part includes n second electrodes of n first light-emitting elements in one third light-emitting group; One second part includes 2n second electrodes of 2n second light-emitting elements in one second light-emitting group; The third part includes a third sub-part and a fourth sub-part. One third sub-part includes n second electrodes of n third light-emitting elements in one first light-emitting group. One fourth sub-part includes n second electrodes of n third light-emitting elements in one third light-emitting group.

29. The display substrate according to claim 28, wherein, One of the first sub - parts is electrically connected to n1 first traces respectively through n1 first connection parts, one of the second sub - parts is electrically connected to n2 first traces respectively through n2 first connection parts, one of the second parts is electrically connected to 2n3 second traces respectively through 2n3 second connection parts, one of the third sub - parts is electrically connected to n4 third traces respectively through n4 third connection parts, one of the fourth sub - parts is electrically connected to n5 third traces respectively through n5 third connection parts, and n1, n2, n3, n4, n5 are independently selected from positive integers less than or equal to n.

30. The display substrate according to any one of claims 1-29, wherein, The light - emitting element layer further includes a first functional layer located between the first electrode layer and the light - emitting layer and a second functional layer located between the second electrode layer and the light - emitting layer; Wherein, the first functional layer includes a plurality of first functional parts arranged at intervals, and at least one partition part is arranged between two adjacent first functional parts; the second functional layer includes a plurality of second functional parts arranged at intervals, and at least one partition part is arranged between two adjacent second functional parts.

31. The display substrate according to any one of claims 1-29, wherein, The first light - emitting element emits red light, the second light - emitting element emits green light, the third light - emitting element emits blue light, the absolute value of the third signal is greater than the absolute value of the first signal, and the absolute value of the first signal is greater than the absolute value of the second signal.

32. A display substrate, wherein, The display substrate includes: A substrate, including a display area and a peripheral area located outside the display area; A plurality of sub - pixels disposed in the display area of the substrate, the plurality of sub - pixels are arranged in an array along a first direction and / or a second direction, the plurality of sub - pixels include a first sub - pixel and a second sub - pixel, the first sub - pixel includes a first light - emitting element, the second sub - pixel includes a second light - emitting element, and the first light - emitting element and the second light - emitting element respectively include a first electrode, a light - emitting part, and a second electrode; A first electrode layer disposed on the substrate, and the first electrode is located in the first electrode layer; A pixel - defining layer disposed on a side of the first electrode layer away from the substrate, the pixel - defining layer defines a plurality of pixel openings, and the plurality of pixel openings include a first pixel opening and a second pixel opening; A partition layer disposed on a side of the pixel - defining layer away from the substrate, the partition layer includes a plurality of partition parts, and a positive projection of the partition layer on the substrate at least partially overlaps a positive projection of the pixel - defining layer on the substrate; and A second electrode layer disposed on a side of the partition layer away from the substrate, and the second electrode is located in the second electrode layer, Wherein, a width of a side of the partition part away from the substrate is greater than a width of a side close to the substrate; The second electrode layer includes a first part, a second part, and a fourth part arranged at intervals, and a positive projection of the first part on the substrate at least partially Overlap, the orthographic projection of the second part on the substrate substrate at least partially overlaps with the orthographic projection of the second pixel opening on the substrate substrate, and the orthographic projection of the fourth part on the substrate substrate at least partially overlaps with the orthographic projection of the partition portion on the substrate substrate; and The adjacent first part and fourth part are disconnected at one side edge of the partition portion, and the adjacent second part and fourth part are disconnected at the other side edge of the partition portion.

33. A display device, wherein, The display device includes the display substrate according to any one of claims 1-32.

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