Novel silicon-on-insulator wafer and preparation method therefor

Abstract

The present invention provides a novel silicon-on-insulator wafer and a preparation method therefor. According to the present invention, the preparation method for a novel silicon-on-insulator wafer comprises the following steps: S1: preparing a TRL or porous silicon on and injecting hydrogen into a silicon wafer to form a hydrogen-injected silicon wafer; S2: growing SiO2 as BOX2 on a substrate, and flipping the hydrogen-injected silicon wafer over to undergo low-temperature bonding with BOX2; S3: after high-temperature stripping, growing SiO2 as BOX1 on the TRL or porous silicon; and S4: injecting hydrogen into the silicon wafer, then flipping the silicon wafer over to undergo low-temperature bonding with BOX1, and, after high-temperature stripping, forming SOI to obtain a novel silicon-on-insulator wafer. The novel silicon-on-insulator wafer of the present invention has lower back gate leakage.

Description

A novel silicon-on-insulator wafer and its preparation method Technical Field

[0001] The present invention relates to the technical field of silicon-on-insulator wafers, and in particular to a novel silicon-on-insulator wafer and a preparation method thereof. Background Art

[0002] The existing RF circuit structure is shown in Figure 1. When a bias voltage is applied to the back gate, a large back-gate leakage current occurs between the trap-rich layer (TRL) on the active area side of the RF circuit and the back-gate region formed by doping the TRL, seriously affecting the back-gate control capability.

[0003] In addition, SOI (Silicon-On-Insulator) used for the preparation of radio frequency circuits is a buried oxide layer (BOX) grown between the top silicon and the back substrate through a deposition process. However, the SiO2 grown by the deposition process has disadvantages such as poor step coverage, low surface flatness, and slow output rate.

[0004] In view of this, the present invention is proposed.

[0005] Summary of the Invention

[0006] The object of the present invention is to provide a novel silicon-on-insulator wafer and a preparation method thereof, wherein the novel silicon-on-insulator wafer has lower back-gate leakage capability.

[0007] The present invention provides a novel method for preparing a silicon-on-insulator wafer, comprising the following steps:

[0008] S1: Prepare TRL or porous silicon on a silicon wafer and implant hydrogen to form a hydrogen implanted silicon wafer;

[0009] S2: Grow SiO2 on the substrate as BOX2, flip the hydrogen-implanted silicon wafer over and bond it to BOX2 at low temperature;

[0010] S3: After high-temperature stripping, SiO2 is grown on TRL or porous silicon as BOX1;

[0011] S4: Hydrogen is injected into the silicon wafer, which is then flipped over and bonded to BOX1 at low temperature. After high-temperature peeling, SOI is formed to produce a new type of silicon-on-insulator wafer.

[0012] In one embodiment, step S1 includes: growing polysilicon as TRL on a silicon wafer by low pressure chemical vapor deposition (LPCVD), and then implanting hydrogen to form a hydrogen implanted silicon wafer.

[0013] Specifically, the temperature during LPCVD is 600-650° C., and the time is 20-60 minutes. The growth thickness of polysilicon is related to the growth time.

[0014] In another embodiment, step S1 includes: first injecting hydrogen into a silicon wafer, then growing single crystal silicon on the hydrogen-injected silicon wafer, and then electrolyzing the single crystal silicon into porous silicon using an electrolysis method to form a hydrogen-injected silicon wafer.

[0015] Specifically, a CVD epitaxial process is used to grow single crystal silicon; the CVD epitaxial process includes: first vaporizing the Si in the silicon wafer with H2 at 200-500°C to generate gaseous SiH4, then allowing the gaseous SiH4 to chemically react with oxygen at 550-650°C to generate single crystal silicon and H2, and the single crystal silicon is deposited on the surface of the silicon wafer.

[0016] The electrolyte used in the electrolysis is composed of 40% hydrofluoric acid and 40% dimethylformamide, with a volume ratio of hydrofluoric acid to dimethylformamide of 1:(1.5-2.5). The electrolysis includes applying a bias voltage at room temperature and without the aid of light to achieve a current density of 60-70 mA / cm 2 The longer the corrosion time, the larger the pore diameter and the greater the depth, which can be reasonably set according to actual needs.

[0017] In addition, in step S1, the hydrogen injection dosage is 6×10 16 -9×10 16 ions / cm 2 The hydrogen injection energy is 10-80kev, and the hydrogen injection depth is 0.2-0.8μm. The hydrogen injection energy and the hydrogen injection depth are approximately linearly related, and the relationship between the hydrogen injection energy and the hydrogen injection depth is shown in Figure 4.

[0018] In step S2, SiO2 can be grown in a conventional manner, such as a deposition process. The deposition process includes: first reacting Si in the substrate with H2 at 500-900°C to generate gaseous SiH4, and then reacting gaseous SiH4 with oxygen at 500-900°C to generate SiO2 and deposit it on the substrate surface.

[0019] Preferably, thermal oxidation is used to grow SiO2 in a vertical oxidation furnace at a temperature of 700-1000°C. Thermal oxidation involves exposing the substrate to the oxygen-rich environment of the vertical oxidation furnace, where the Si in the substrate is thermally oxidized at high temperatures to form SiO2. The relationship between thermal oxidation time and oxide layer thickness at a temperature of 700°C is shown in Figure 5.

[0020] In addition, in step S2, the silicon wafer and the substrate are hydrophilicized before low-temperature bonding. The hydrophilicization treatment involves immersing the silicon wafer and the substrate in water. The water adsorbed on the surface of the silicon wafer and the substrate destroys the Si-O-Si bonds on the surface of the silicon wafer and forms OH bonds with the water. After the hydrophilicization treatment, the silicon wafer and the substrate with the OH bonds undergo a polymerization reaction at a bonding temperature of 120-150°C to form a bond.

[0021] In step S3, the high-temperature stripping temperature is 500-600°C, and TRL or porous silicon is left after the high-temperature stripping; subsequently, SiO2 can be grown on the TRL or porous silicon using the above-mentioned deposition process or thermal oxidation method.

[0022] In step S4, the hydrogen injection dosage is 6×10 16 -9×10 16 ions / cm 2 The hydrogen injection energy is 10-80keV, and the hydrogen injection depth is 0.2-0.8μm.

[0023] Before low-temperature bonding, the silicon wafer and substrate are subjected to the above-mentioned hydrophilic treatment; after the hydrophilic treatment, low-temperature bonding is performed at 120-150°C; after low-temperature bonding, high-temperature stripping is performed at 500-600°C. After hydrogen injection, the hydrogen ion enrichment area in the upper hydrogen-injected silicon wafer after bonding is bubbled at high temperature, and the area above the bubble is peeled.

[0024] The present invention also provides a novel silicon-on-insulator wafer, which is prepared according to the above preparation method.

[0025] Specifically, the novel silicon-on-insulator wafer includes a substrate, a BOX2 is arranged on the substrate, a TRL or porous silicon is arranged on the BOX2, a BOX1 is arranged on the TRL or porous silicon, and an SOI is arranged on the BOX1.

[0026] The present invention provides a novel silicon-on-insulator wafer. This novel RFSOI wafer structure with low substrate leakage has even lower back-gate leakage capability. In addition, the preparation method of the present invention can also prepare BOX1 and BOX2 by thermal oxidation, thereby forming an interface with less interface trapped charge and less fixed charge, making the bonding surface smoother, flatter, and more uniform. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0028] FIG1 is a schematic diagram of the structure of an existing radio frequency circuit;

[0029] FIG2 is a flow chart of the preparation process of the novel silicon-on-insulator wafer of Example 1;

[0030] FIG3 is a diagram showing the relationship between hydrogen injection depth and hydrogen injection energy;

[0031] FIG4 is a graph showing the relationship between oxidation time and oxidation thickness during thermal oxidation;

[0032] FIG5 is a schematic structural diagram of the novel silicon-on-insulator wafer of Example 1;

[0033] FIG6 is a flow chart of the preparation process of the novel silicon-on-insulator wafer of Example 2;

[0034] FIG7 is a schematic diagram of preparing porous silicon by electrolysis;

[0035] FIG8 is a schematic structural diagram of a silicon-on-insulator wafer of Comparative Example 1. DETAILED DESCRIPTION

[0036] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the present application belongs.

[0037] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular also includes the plural. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or combinations thereof.

[0038] The following will clearly and completely describe the technical solutions of the present invention in conjunction with the embodiments. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0039] Example 1

[0040] 2 , the method for preparing the novel silicon-on-insulator wafer of this embodiment comprises the following steps:

[0041] S1: Preparation of TRL and hydrogen injection

[0042] First, polysilicon was grown on a silicon wafer as TRL by LPCVD. The LPCVD conditions included: temperature of 625° C. and time of 40 min.

[0043] Subsequently, hydrogen is injected into the silicon wafer on which the polysilicon is grown to form a hydrogen-injected silicon wafer; wherein the hydrogen injection dose is 6×10 16 ions / cm 2 The hydrogen injection energy is 10keV, the hydrogen injection depth is 0.2μm, and the relationship between the hydrogen injection depth and the hydrogen injection energy is shown in Figure 3.

[0044] S2: Make BOX2, low temperature bonding

[0045] The substrate (silicon wafer, referred to as SUB) was placed in an oxygen-rich environment of a vertical oxidation furnace, and the Si in the substrate was thermally oxidized at 700°C to generate SiO2 as BOX2; the thermal oxidation time and oxidation thickness were obtained according to Figure 4.

[0046] Subsequently, the hydrogen-implanted silicon wafer of step S1 and the substrate of step S2 are immersed in water for hydrophilic treatment, and then low-temperature bonding is performed at 120° C. after the hydrophilic treatment.

[0047] S3: High temperature peeling and making BOX1

[0048] The substrates bonded at low temperature in step S2 are subjected to high temperature peeling at 500° C., leaving the TRL after the high temperature peeling.

[0049] Subsequently, the substrate after high-temperature stripping was placed in an oxygen-rich environment of a vertical oxidation furnace, and the Si in the substrate was thermally oxidized at 700°C to generate SiO2 as BOX1; the thermal oxidation time and oxidation thickness were obtained according to Figure 4.

[0050] S4: Hydrogen injection, low temperature bonding, high temperature peeling

[0051] Hydrogen is injected into another silicon wafer to form a hydrogen-injected silicon wafer; wherein the hydrogen injection dose is 6×10 16 ions / cm 2 The hydrogen injection energy is 10keV, the hydrogen injection depth is 0.2μm, and the relationship between the hydrogen injection depth and the hydrogen injection energy is shown in Figure 3.

[0052] The substrate after BOX1 growth in step S3 and the hydrogen-implanted silicon wafer in step S4 are immersed in water for hydrophilic treatment, and then low-temperature bonding is performed at 120° C. after the hydrophilic treatment.

[0053] The substrate after low-temperature bonding is subjected to high-temperature stripping at 500° C., and SOI is formed after high-temperature stripping, that is, a new type of silicon-on-insulator wafer (i.e., a new type of RFSOI) is produced.

[0054] The novel RFSOI structure prepared in this embodiment is shown in FIG5 . The novel RFSOI includes a substrate, a BOX2 arranged on the substrate, a TRL arranged on BOX2, a BOX1 arranged on the TRL, and an SOI arranged on BOX1. The novel RFSOI has lower back gate leakage capability.

[0055] Example 2

[0056] 6 , the method for preparing the novel silicon-on-insulator wafer of this embodiment comprises the following steps:

[0057] S1: Hydrogen injection and preparation of porous silicon

[0058] Hydrogen is injected into the silicon wafer with a hydrogen injection dose of 9×10 16 ions / cm 2 The hydrogen injection energy is 80keV, the hydrogen injection depth is 0.8μm, and the relationship between the hydrogen injection depth and the hydrogen injection energy is shown in Figure 3.

[0059] Single crystal silicon is grown using a CVD epitaxial process. The CVD epitaxial process involves vaporizing the Si in the silicon wafer with H2 at 400°C to generate gaseous SiH4. The gaseous SiH4 then reacts with oxygen at 600°C to form single crystal silicon and H2, which is then deposited on the surface of the silicon wafer.

[0060] As shown in FIG7 , single crystal silicon is electrolyzed into porous silicon to form hydrogen-implanted silicon wafers using an electrolytic method. The electrolyte used in the electrolysis is composed of 40% hydrofluoric acid and 40% dimethylformamide, with a volume ratio of 1:2. A bias voltage is applied at room temperature without light to achieve a current density of 64 mA / cm 2 .

[0061] S2: Make BOX2, low temperature bonding

[0062] The substrate (silicon wafer, referred to as SUB) was placed in an oxygen-rich environment of a vertical oxidation furnace, and the Si in the substrate was thermally oxidized at 700°C to generate SiO2 as BOX2; the thermal oxidation time and oxidation thickness were obtained according to Figure 4.

[0063] Subsequently, the hydrogen-implanted silicon wafer of step S1 and the substrate of step S2 are immersed in water for hydrophilic treatment, and then low-temperature bonding is performed at 150° C. after the hydrophilic treatment.

[0064] S3: High temperature peeling and making BOX1

[0065] The substrate bonded at low temperature in step S2 is subjected to high temperature stripping at 600° C., leaving porous silicon after the high temperature stripping.

[0066] Subsequently, the substrate after high-temperature stripping was placed in an oxygen-rich environment of a vertical oxidation furnace, and the Si in the substrate was thermally oxidized at 700°C to generate SiO2 as BOX1; the thermal oxidation time and oxidation thickness were obtained according to Figure 4.

[0067] S4: Hydrogen injection, low temperature bonding, high temperature peeling

[0068] Hydrogen is injected into another silicon wafer to form a hydrogen-injected silicon wafer; wherein the hydrogen injection dose is 9×10 16 ions / cm 2The hydrogen injection energy is 80keV, the hydrogen injection depth is 0.8μm, and the relationship between the hydrogen injection depth and the hydrogen injection energy is shown in Figure 3.

[0069] The substrate after BOX1 growth in step S3 and the hydrogen-implanted silicon wafer in step S4 are immersed in water for hydrophilic treatment, and then low-temperature bonding is performed at 150° C. after the hydrophilic treatment.

[0070] The substrate after low-temperature bonding is subjected to high-temperature stripping at 600°C to form SOI, thereby obtaining a new type of silicon-on-insulator wafer (i.e., a new type of RFSOI).

[0071] The novel RFSOI fabricated in this embodiment includes a substrate, a BOX2 disposed on the substrate, porous silicon disposed on BOX2, a BOX1 disposed on the porous silicon, and an SOI disposed on BOX1; the novel RFSOI has lower back-gate leakage capability.

[0072] Comparative Example 1

[0073] The silicon-on-insulator wafer structure of this comparative example is shown in FIG8 , and the preparation steps are as follows:

[0074] S1: Hydrogen injection

[0075] The silicon wafer is injected with hydrogen to form a hydrogen-injected silicon wafer; wherein the hydrogen injection dose is 6×10 16 ions / cm 2 The hydrogen injection energy is 10keV and the hydrogen injection depth is 0.2μm.

[0076] S2: Make BOX2, low temperature bonding

[0077] The substrate (silicon wafer, referred to as SUB) was placed in an oxygen-rich environment of a vertical oxidation furnace, and the Si in the substrate was thermally oxidized at 700°C to generate SiO2 as BOX2; the thermal oxidation time and oxidation thickness were obtained according to Figure 4.

[0078] Subsequently, the hydrogen-implanted silicon wafer of step S1 and the substrate of step S2 are immersed in water for hydrophilic treatment, and then low-temperature bonding is performed at 120° C. after the hydrophilic treatment.

[0079] S3: High temperature peeling and making BOX1

[0080] The substrate bonded at low temperature in step S2 is subjected to high temperature peeling at 500° C. to form SOI2.

[0081] Subsequently, the substrate after high-temperature stripping was placed in an oxygen-rich environment of a vertical oxidation furnace, and the Si in the substrate was thermally oxidized at 700°C to generate SiO2 as BOX1; the thermal oxidation time and oxidation thickness were obtained according to Figure 4.

[0082] S4: Hydrogen injection, low temperature bonding, high temperature peeling

[0083] Hydrogen is injected into another silicon wafer to form a hydrogen-injected silicon wafer; wherein the hydrogen injection dose is 6×10 16 ions / cm 2 The hydrogen injection energy is 10keV, the hydrogen injection depth is 0.2μm, and the relationship between the hydrogen injection depth and the hydrogen injection energy is shown in Figure 3.

[0084] The substrate after BOX1 growth in step S3 and the hydrogen-implanted silicon wafer in step S4 are immersed in water for hydrophilic treatment, and then low-temperature bonding is performed at 120° C. after the hydrophilic treatment.

[0085] The substrate after low-temperature bonding is subjected to high-temperature stripping at 500° C., and SOI1 is formed after high-temperature stripping, that is, a silicon-on-insulator wafer is obtained.

[0086] The silicon-on-insulator wafer prepared in this comparative example includes a substrate, BOX2 is arranged on the substrate, SOI2 is arranged on BOX2, BOX1 is arranged on SOI2, and SOI1 is arranged on BOX1; the silicon-on-insulator wafer in this comparative example has a large back gate leakage current, which seriously affects the back gate control capability.

[0087] Comparative Example 2

[0088] Except for using a deposition process to make BOX2 and BOX1, the rest is basically the same as the control example 1; the deposition process steps are as follows: first, the Si in the substrate reacts with H2 at 700°C to generate gaseous SiH4, and then the gaseous SiH4 reacts with oxygen at 700°C to generate SiO2 and deposit it on the substrate surface.

[0089] The results show that BOX2 and BOX1 fabricated by deposition process have poor step coverage and low surface flatness; while BOX2 and BOX1 fabricated by thermal oxidation method can form interfaces with less interface trapped charges and less fixed charges, making the bonding surface smoother, flatter and more uniform.

[0090] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A preparation method of a novel silicon-on-insulator wafer, characterized in that, It includes the following steps: S1: Prepare TRL or porous silicon on a silicon wafer and inject hydrogen to form a hydrogen-injected silicon wafer; S2: Grow SiO2 as BOX2 on a substrate, flip the hydrogen-injected silicon wafer and bond it to BOX2 at a low temperature; S3: After high-temperature stripping, grow SiO2 as BOX1 on the TRL or porous silicon; S4: Inject hydrogen into the silicon wafer, then flip and bond it to BOX1 at a low temperature. After high-temperature stripping, form SOI to obtain a new silicon-on-insulator wafer.

2. The preparation method according to claim 1, characterized in that, Step S1 includes: Growing polysilicon as TRL on a silicon wafer by LPCVD, and then injecting hydrogen to form a hydrogen-injected silicon wafer.

3. The preparation method according to claim 2, wherein The temperature during LPCVD is 600 - 650 °C, and the time is 20 - 60 min.

4. The preparation method according to claim 1, characterized in that, Step S1 includes: First inject hydrogen into the silicon wafer, then grow single-crystalline silicon on the hydrogen-injected silicon wafer, and then electrolyze the single-crystalline silicon into porous silicon by electrolysis to form a hydrogen-injected silicon wafer.

5. The preparation method according to claim 4, characterized in that, Grow single-crystalline silicon by CVD epitaxy process; The CVD epitaxy process includes: First, make Si in the silicon wafer vaporize with H2 at 200 - 500 °C to generate gaseous SiH4, and then make the gaseous SiH4 react chemically with oxygen at 550 - 650 °C to generate single-crystalline silicon and H2, and the single-crystalline silicon is deposited on the surface of the silicon wafer.

6. The preparation method according to claim 4, characterized in that, The electrolyte used for electrolysis is composed of hydrofluoric acid with a mass concentration of 40% and dimethylformamide with a mass concentration of 40%, and the volume ratio of hydrofluoric acid to dimethylformamide is 1:(1.5 - 2.5); Electrolysis includes: applying a bias voltage at room temperature without the aid of light such that the current density reaches 60 - 70 mA / cm 2 .

7. The preparation method according to claim 1, characterized in that, The hydrogen injection dose during hydrogen injection is 6×10 16 -9×10 16 ions / cm 2 , the hydrogen injection energy is 10 - 80 keV, and the hydrogen injection depth is 0.2 - 0.8 μm.

8. The preparation method according to claim 1, characterized in that, Grow SiO2 by thermal oxidation method, and carry out thermal oxidation in a vertical oxidation furnace. The thermal oxidation temperature is 700 - 1000 °C.

9. The preparation method according to claim 1, characterized in that, Before low-temperature bonding, first perform hydrophilic treatment on the silicon wafer and the substrate. The low-temperature bonding temperature is 120 - 150 °C; The high-temperature stripping temperature is 500 - 600 °C.

10. A novel silicon-on-insulator wafer, characterized in that, Obtained by the preparation method according to any one of claims 1 - 9, the new silicon-on-insulator wafer includes a substrate, BOX2 is provided on the substrate, TRL or porous silicon is provided on BOX2, BOX1 is provided on the TRL or porous silicon, and SOI is provided on BOX1.

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