Planar-gate silicon carbide mosfet power device and manufacturing method therefor

Abstract

A planar-gate silicon carbide MOSFET power device and a manufacturing method therefor. The device comprises: a characteristic trench (4), which is located between adjacent second conductivity type well regions (6) and located in a first epitaxial layer (3); a first characteristic dielectric layer (5-1), which is located at the bottom of the characteristic trench (4); a second characteristic dielectric layer (5-2), which is located on a side wall of the characteristic trench (4); and a characteristic conductive layer (8), which is located in the characteristic trench (4) and is enclosed by the first characteristic dielectric layer (5-1) and the second characteristic dielectric layer (5-2), wherein the characteristic conductive layer (8), the second characteristic dielectric layer (5-2) and the first epitaxial layer (3) form a field plate structure.

Description

Planar gate silicon carbide MOSFET power device and manufacturing method thereof

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on December 28, 2023, with application number 202311836344.1. The entire contents of the above application are incorporated by reference into this application. Technical Field

[0002] The present application belongs to the technical field of semiconductor devices, and for example relates to a planar gate silicon carbide metal oxide semiconductor field-effect transistor (MOSFET) power device and a manufacturing method thereof. Background Art

[0003] The development of power electronics systems has placed higher demands on the performance of power semiconductor devices in terms of high temperature, high frequency, radiation, and high voltage resistance. Compared to silicon, silicon carbide (SiC) has become one of the most important semiconductor materials for manufacturing high-power devices capable of adapting to extreme environments due to its higher thermal conductivity, wider bandgap, and higher critical breakdown electric field strength.

[0004] Among SiC power devices, SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) are widely used due to their advantages, such as simple gate drive and unipolar conduction. However, the dielectric constant of SiC material is nearly three times that of SiO2, which means that the gate dielectric must withstand a high electric field strength in the off state, causing premature device breakdown.

[0005] Summary of the Invention

[0006] In response to the above-mentioned shortcomings of SiC MOSFET power devices, the present application provides a planar gate silicon carbide MOSFET power device and a manufacturing method thereof.

[0007] The present application provides a planar gate silicon carbide MOSFET power device, comprising:

[0008] a first substrate;

[0009] a drain electrode and a first epitaxial layer located on opposite sides of the first substrate;

[0010] a second conductivity type well region located in the first epitaxial layer on a side away from the first substrate;

[0011] a first conductivity type source region located in the second conductivity type well region;

[0012] A characteristic trench located between adjacent second conductivity type well regions and in the first epitaxial layer, a first characteristic dielectric layer located at the bottom of the characteristic trench, and a second characteristic dielectric layer located at the sidewalls of the characteristic trench;

[0013] A characteristic conductive layer located in the characteristic trench and wrapped by the first characteristic dielectric layer and the second characteristic dielectric layer, wherein the characteristic conductive layer, the second characteristic dielectric layer and the first epitaxial layer form a field plate structure;

[0014] A gate dielectric layer located on the surface of the first epitaxial layer away from the first substrate; a gate electrode located on the surface of the gate dielectric layer away from the first epitaxial layer; an isolation dielectric layer located on both sides of the gate electrode and on the surface away from the gate dielectric layer and completely surrounding the gate electrode; and a source electrode located on both sides of the isolation dielectric layer and on the surface away from the gate electrode.

[0015] The present application provides a method for manufacturing a planar gate silicon carbide MOSFET power device, comprising:

[0016] forming a first epitaxial layer on the first side surface of the first substrate by epitaxial growth;

[0017] forming a second conductivity type well region and a first conductivity type source region located in the second conductivity type well region in sequence in a portion of the first epitaxial layer away from the first substrate by an epitaxial process or an ion implantation process;

[0018] Etching the first epitaxial layer to form a characteristic trench, wherein the characteristic trench is located between adjacent second conductivity type well regions;

[0019] A first characteristic dielectric layer, a second characteristic dielectric layer, and a characteristic conductive layer are formed in the characteristic trench by a chemical vapor deposition process or a thermal oxidation process combined with photolithography and etching processes; wherein the first characteristic dielectric layer is located at the bottom of the characteristic trench, the second characteristic dielectric layer is located on the sidewall opposite to the characteristic trench, and the characteristic conductive layer is surrounded by the first characteristic dielectric layer and the second characteristic dielectric layer;

[0020] forming a gate dielectric layer material and a gate electrode material on a surface of the first epitaxial layer away from the first substrate by a chemical vapor deposition process;

[0021] A gate dielectric layer and a gate electrode are formed respectively by photolithography and etching processes on the gate dielectric layer material and the gate electrode material, and an isolation dielectric layer that completely surrounds the gate electrode is formed on the surface of the gate electrode away from the gate dielectric layer and on both side walls of the gate electrode; a source metal is deposited on both side walls of the isolation dielectric layer and on the surface of the side away from the gate electrode to form a source ohmic contact, so as to form a source electrode on the surface of the source ohmic contact; a drain metal is deposited on the second side of the first substrate opposite to the first side to form a drain ohmic contact, so as to form a drain electrode on the surface of the drain ohmic contact.

[0022] This application also provides another planar gate silicon carbide MOSFET power device, including:

[0023] a first substrate;

[0024] a drain electrode and a first epitaxial layer located on opposite sides of the first substrate;

[0025] a second conductivity type well region located in the first epitaxial layer on a side away from the first substrate;

[0026] a first conductivity type source region located in the second conductivity type well region;

[0027] A characteristic trench located between adjacent second conductivity type well regions and in the first epitaxial layer, a first characteristic dielectric layer located at the bottom of the characteristic trench, and a second characteristic dielectric layer located at the sidewalls of the characteristic trench;

[0028] A source metal located in the characteristic trench and wrapped by the first characteristic dielectric layer and the second characteristic dielectric layer, wherein the source metal, the second characteristic dielectric layer and the first epitaxial layer form a field plate structure;

[0029] a gate dielectric layer located on a surface of the first epitaxial layer away from the first substrate;

[0030] a first gate electrode and a second gate electrode located on a surface of the gate dielectric layer away from the first epitaxial layer; the first gate electrode and the second gate electrode are respectively located on the first epitaxial layer, the second conductivity type well region and a portion of the first conductivity type source region corresponding thereto;

[0031] a first isolation dielectric layer located on both sides of the first gate electrode and on a surface of the first gate electrode away from the gate dielectric layer and completely surrounding the first gate electrode, and a second isolation dielectric layer located on both sides of the second gate electrode and on a surface of the second gate electrode away from the gate dielectric layer and completely surrounding the second gate electrode;

[0032] The source electrode is located on both sides of the first isolation dielectric layer and the second isolation dielectric layer and on the surface of the side away from the gate electrode.

[0033] This application also provides another method for manufacturing a planar gate silicon carbide MOSFET power device, comprising:

[0034] forming a first epitaxial layer on a first side surface of the first substrate by epitaxial growth;

[0035] forming a second conductivity type well region and a first conductivity type source region located in the second conductivity type well region in sequence in a portion of the first epitaxial layer away from the first substrate by an epitaxial process or an ion implantation process;

[0036] forming a gate dielectric layer material and a gate electrode material on a surface of the first epitaxial layer away from the first substrate by a chemical vapor deposition process;

[0037] A gate dielectric layer and a gate electrode located on the gate dielectric layer are formed by photolithography and etching processes on the gate dielectric layer material and the gate electrode material; the gate electrode comprises at least a first gate electrode and a second gate electrode that are not connected; wherein the first gate electrode and the second gate electrode are respectively located on the first epitaxial layer, the second conductivity type well region and a portion of the first conductivity type source region corresponding to each other;

[0038] forming a first isolation dielectric layer that completely surrounds the first gate electrode on both sides of the first gate electrode and on a surface of the first gate electrode away from the gate dielectric layer, and forming a second isolation dielectric layer that completely surrounds the second gate electrode on both sides of the second gate electrode and on a surface of the second gate electrode away from the gate dielectric layer;

[0039] Etching the first epitaxial layer to form a characteristic trench, wherein the characteristic trench is located between adjacent second conductivity type well regions;

[0040] A first characteristic dielectric layer and a second characteristic dielectric layer are formed in the characteristic trench by a chemical vapor deposition process or a thermal oxidation process combined with a photolithography and etching process; wherein the first characteristic dielectric layer is located at the bottom of the characteristic trench, and the second characteristic dielectric layer is located on the sidewalls on the opposite side of the characteristic trench;

[0041] Depositing source metal on the inside of a characteristic trench surrounded by the side walls of the first isolation dielectric layer and the second isolation dielectric layer, on both sides of the first isolation dielectric layer and the second isolation dielectric layer, and on the surface of the first isolation dielectric layer and the second isolation dielectric layer away from the gate electrode to form a source ohmic contact, thereby forming a source electrode on the surface of the source ohmic contact and serving as a characteristic conductive layer in the characteristic trench, wherein the characteristic conductive layer, the second characteristic dielectric layer, and the first epitaxial layer form a field plate structure;

[0042] A drain metal is deposited on a second side of the first substrate opposite to the first side to form a drain ohmic contact, so as to form a drain electrode on a surface of the drain ohmic contact. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] FIG1 is a schematic diagram of a planar gate silicon carbide MOSFET power device with an integrated field plate structure shown in Example 1;

[0044] FIG2 is a schematic diagram of a planar gate silicon carbide MOSFET power device with an integrated field plate structure shown in Example 2;

[0045] FIG3 is a schematic diagram of a planar gate silicon carbide MOSFET power device with an integrated field plate structure shown in Example 3;

[0046] FIG4A is a flow chart of a method for manufacturing the device of Example 1;

[0047] FIG4B is a flow chart of a method for manufacturing the device of Example 2;

[0048] FIG5 is a schematic diagram of the structure formed in step 1 of the method for manufacturing the device of Example 1;

[0049] FIG6 is a schematic diagram of the structure formed in step 2 of the method for manufacturing the device of Example 1;

[0050] FIG7 is a schematic diagram of the structure formed in step 3 of the method for manufacturing the device of Example 1;

[0051] FIG8 is a schematic diagram of the structure formed in step 4 of the method for manufacturing the device of Example 1;

[0052] FIG9 is a schematic diagram of the structure formed in step 5 of the method for manufacturing the device of Example 1;

[0053] FIG10 is a schematic diagram of the structure formed in step 6 of the method for manufacturing the device of Example 1. FIG.

[0054] Explanation of the accompanying drawings: 1. drain electrode; 2. first substrate; 3. first epitaxial layer; 4. characteristic trench; 5-1. first characteristic dielectric layer; 5-2. second characteristic dielectric layer; 6. second conductive type well region; 7. first conductive type source region; 8. characteristic conductive layer; 9. gate electrode; 9-1. first gate electrode; 9-2. second gate electrode; 10. isolation dielectric layer; 10-1. first isolation dielectric layer; 10-2. second isolation dielectric layer; 11. source electrode; 12. gate dielectric layer; 13. source metal; 14. second conductive type heavily doped region. DETAILED DESCRIPTION

[0055] The present application is described below with reference to the following examples. The examples are only used to illustrate the present application and do not constitute a limitation on the scope of the claims. Other alternative means that can be thought of by those skilled in the art are all within the scope of the claims of the present application.

[0056] Furthermore, in the description of this application, terms such as "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer" indicate positions or locations based on those shown in the accompanying drawings. These terms are used solely to facilitate the description of this application and simplify the description. They are not intended to indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0057] Example 1

[0058] As shown in FIG1 , a planar gate silicon carbide MOSFET power device with an integrated field plate structure according to this embodiment includes:

[0059] drain electrode 1;

[0060] A first substrate 2 is provided on the drain electrode 1, and the first substrate 2 is a first conductive type SiC substrate;

[0061] A first epitaxial layer 3 is provided on the first substrate 2, and the first epitaxial layer 3 is a first conductivity type SiC epitaxial layer;

[0062] a second conductivity type well region 6 located in the first epitaxial layer 3; a first conductivity type source region 7 located in the second conductivity type well region 6;

[0063] A characteristic trench 4 located between adjacent second conductivity type well regions 6 and in the first epitaxial layer 3, a first characteristic dielectric layer 5-1 located at the bottom of the characteristic trench 4, and a second characteristic dielectric layer 5-2 located on the sidewalls of the characteristic trench 4;

[0064] A characteristic conductive layer 8 located in the characteristic trench 4 and wrapped by the first characteristic dielectric layer 5-1 and the second characteristic dielectric layer 5-2, wherein the characteristic conductive layer 8, the second characteristic dielectric layer 5-2 and the first epitaxial layer 3 form a field plate structure;

[0065] A gate dielectric layer 12 located on the first epitaxial layer 3; a gate electrode 9 located on the gate dielectric layer 12; an isolation dielectric layer 10 located on both sides and above the gate electrode 9 and completely surrounding the gate electrode 9; and a source electrode 11 located on both sides and above the isolation dielectric layer 10.

[0066] In the present application, the first conductivity type is N-type, and the second conductivity type is P-type; or the first conductivity type is P-type, and the second conductivity type is N-type.

[0067] This application integrates a field plate structure inside the semiconductor of the junction field-effect transistor (JFET) region of a planar-gate silicon carbide MOSFET power device, achieving effective modulation of the electric field distribution on the semiconductor surface, significantly reducing the electric field strength borne by the gate dielectric, and improving device reliability.

[0068] In addition, the present application effectively reduces the gate-drain overlap area by setting a field plate structure, significantly reduces the gate-drain capacitance, and thus greatly reduces the switching loss of the device and improves the switching characteristics.

[0069] The method for manufacturing the above-mentioned planar gate silicon carbide MOSFET power device with an integrated field plate structure comprises the following steps:

[0070] Step 1. Form a first epitaxial layer 3 on a first substrate 2 by epitaxial growth. As shown in FIG5 , the first epitaxial layer 3 is formed on the first substrate 2 by epitaxial growth. The doping concentration of the first epitaxial layer 3 ranges from 1e15 cm⁻³ to 1e17 cm⁻³. The semiconductor material used for the first substrate 2 and the first epitaxial layer 3 is 3C-SiC, 4H-SiC or 6H-SiC.

[0071] Step 2: Form a second conductivity type well region 6 and a first conductivity type source region 7 located within the second conductivity type well region 6 in sequence through an epitaxial process or an ion implantation process. As shown in FIG6 , a patterned ion implantation mask layer is formed on the surface of the first epitaxial layer 3. Ions are implanted using the patterned ion implantation mask layer to form the second conductivity type well region 6. The ion implantation mask layer is then removed. The depth of the second conductivity type well region 6 ranges from 0.5 μm to 1.5 μm, and the doping concentration ranges from 5e16 cm⁻³ to 5e18 cm⁻³. A patterned ion implantation mask layer is then formed on the surface of the first epitaxial layer 3. Ions are implanted using the patterned ion implantation mask layer to form the first conductivity type source region 7. The ion implantation mask layer is then removed. The depth of the first conductivity type source region 7 ranges from 0.2 μm to 0.5 μm, and the doping concentration ranges from 5e18 cm⁻³ to 5e20 cm⁻³. The first conductivity type source region 7 is located within the second conductivity type well region 6. In the present application, the depth of the first conductive type source region 7 is smaller than the depth of the second conductive type well region 6 .

[0072] Step 3: Etch the first epitaxial layer 3 to form a characteristic groove 4, which is located between adjacent second conductive type well regions 6; as shown in Figure 7, a patterned etching mask layer is formed on the surface of the first epitaxial layer 3, and the first epitaxial layer 3 is etched by inductively coupled plasma (ICP) using the patterned etching mask layer to form a characteristic groove 4 between the second conductive type well regions 6. The etching gas used can be one or more combinations of gases such as SF6, HBr, Cl2, O2, Ar, etc. The depth range of the characteristic groove 4 is 0.5μm~1.0μm, the width range is 0.5μm~1.2μm, and the distance between the characteristic groove 4 and the second conductive type well region 6 in the x direction ranges from 0.2μm to 1.0μm; in this application, the x direction refers to the width direction of the device, and the y direction refers to the height / depth direction of the device.

[0073] Step 4: Form a first characteristic dielectric layer 5-1, a second characteristic dielectric layer 5-2, and a characteristic conductive layer 8 in the characteristic trench 4 through a chemical vapor deposition process or a thermal oxidation process in combination with a photolithography and etching process. The first characteristic dielectric layer 5-1 and the second characteristic dielectric layer 5-2 can be formed by performing heavy-dose ion implantation and thermal oxidation on the bottom of the characteristic trench 4, or by depositing polycrystalline silicon or amorphous silicon at the bottom of the characteristic trench 4 and then performing thermal oxidation. The material of the characteristic conductive layer 8 is polycrystalline silicon or amorphous silicon.

[0074] In this embodiment, as shown in FIG8 , the etch mask layer formed in step 3 is used to perform Si ion implantation into the bottom of the feature trench 4, converting the SiC material at the bottom of the feature trench 4 into an amorphous state. The etch mask layer is then removed and a thermal oxidation process is performed to form a first feature dielectric layer 5-1 and a second feature dielectric layer 5-2. The first feature dielectric layer 5-1 is located at the bottom of the feature trench 4, while the second feature dielectric layer 5-2 is located on the sidewalls of the feature trench 4. The thickness of the first feature dielectric layer 5-1 ranges from 200 nm to 500 nm, while the thickness of the second feature dielectric layer 5-2 ranges from 50 nm to 100 nm. Subsequently, a feature conductive layer material is deposited by chemical vapor deposition, subjected to large-area etching, and flattened by chemical-mechanical polishing (CMP) to form a feature conductive layer 8 located within the feature trench 4. The material of the feature conductive layer 8 can be polysilicon or one or more combinations of metals such as Ti, Al, Ni, and Pt. The characteristic conductive layer 8, the second characteristic dielectric layer 5-2 and the first epitaxial layer 3 form a field plate structure; the field plate refers to changing the curvature of the depletion layer boundary near the gate edge, that is, the field plate structure is integrated inside the semiconductor in the JFET region in this application, which realizes the effective modulation of the electric field distribution on the semiconductor surface, significantly reduces the electric field strength borne by the gate dielectric, and improves the device reliability.

[0075] Step 5: Form a gate dielectric layer material and a gate electrode material on the surface of the first epitaxial layer 3 by chemical vapor deposition. As shown in FIG9 , a gate dielectric layer material and a gate electrode material are deposited on the surface of the device obtained in Step 4 by chemical vapor deposition. The gate dielectric layer material has a thickness ranging from 30 nm to 70 nm, and the gate electrode material has a thickness ranging from 0.4 μm to 1.0 μm. The gate dielectric layer material can be silicon oxide, silicon nitride, borophosphosilicate glass, aluminum oxide, sapphire, or hafnium oxide. The gate electrode material can be metal or doped polysilicon.

[0076] Step 6: Form a gate electrode 9 and a gate dielectric layer 12 by photolithography and etching processes, form an isolation dielectric layer 10 on and on both sides of the gate electrode 9 to completely surround the gate electrode 9, deposit a source metal 13 on both sides and on the isolation dielectric layer 10 to form a source ohmic contact, deposit a drain metal on the bottom of the first substrate 2 to form a drain ohmic contact, form a source electrode 11 on the surface of the source ohmic contact, and form a drain electrode 1 on the surface of the drain ohmic contact; as shown in FIG10, in STEP A patterned etch mask layer is deposited on the surface of the device formed by the process. The gate electrode material and the gate dielectric layer material are etched using the patterned etch mask layer to form a gate electrode 9 and a gate dielectric layer 12. The gate electrode 9 is located on the gate dielectric layer 12. The gate electrode 9 is located on the characteristic conductive layer 8, the second characteristic dielectric layer 5-2, the first epitaxial layer 3, the second conductivity type well region 6, and a portion of the first conductivity type source region 7. The etch mask layer is then removed, and the gate electrode 9 is implanted and activated by annealing. A dielectric material is then deposited on the device surface and patterned to form an isolation dielectric layer 10. The isolation dielectric layer 10 completely surrounds the gate electrode 9. Source metal 13 is deposited on both sides of and above the isolation dielectric layer 10 to form a source ohmic contact. A drain metal is deposited on the bottom layer of the first substrate 2 to form a drain ohmic contact. A source electrode 11 is formed on the surface of the source ohmic contact, and a drain electrode 1 is formed on the surface of the drain ohmic contact.

[0077] The material of the isolation dielectric layer 10 is silicon dioxide, or nitride, or a composite of silicon dioxide and nitride. The material of the source electrode 11 can be one or a combination of metals such as Ti, Al, Ni, and Pt.

[0078] In summary, as shown in FIG4A , the method for manufacturing a planar gate silicon carbide MOSFET power device includes:

[0079] S11 . Form a first epitaxial layer on a first side surface of a first substrate by epitaxial growth.

[0080] S12. Forming a second conductive type well region and a first conductive type source region located in the second conductive type well region in sequence in a portion of the first epitaxial layer away from the first substrate through an epitaxial process or an ion implantation process.

[0081] S13. Etch the first epitaxial layer to form a characteristic trench, where the characteristic trench is located between adjacent second conductivity type well regions.

[0082] S14. Form a first characteristic dielectric layer, a second characteristic dielectric layer and a characteristic conductive layer in the characteristic groove through a chemical vapor deposition process or a thermal oxidation process combined with a photolithography and etching process; wherein the first characteristic dielectric layer is located at the bottom of the characteristic groove, the second characteristic dielectric layer is located on the sidewall on the opposite side of the characteristic groove, and the characteristic conductive layer is wrapped by the first characteristic dielectric layer and the second characteristic dielectric layer.

[0083] S15. Form a gate dielectric layer material and a gate electrode material on the surface of the first epitaxial layer away from the first substrate through a chemical vapor deposition process.

[0084] S16. Form a gate dielectric layer and a gate electrode respectively by using photolithography and etching processes on the gate dielectric layer material and the gate electrode material; form an isolation dielectric layer that completely surrounds the gate electrode on the surface of the gate electrode away from the gate dielectric layer and on both side walls of the gate electrode; deposit source metal on both side walls of the isolation dielectric layer and on the surface of the side away from the gate electrode to form a source ohmic contact, so as to form a source electrode on the surface of the source ohmic contact; deposit drain metal on the second side of the first substrate opposite to the first side to form a drain ohmic contact, so as to form a drain electrode on the surface of the drain ohmic contact.

[0085] The planar gate silicon carbide MOSFET power device manufactured using the above-mentioned planar gate silicon carbide MOSFET power device manufacturing method includes:

[0086] a first substrate;

[0087] a drain electrode and a first epitaxial layer located on opposite sides of the first substrate;

[0088] a second conductivity type well region located in a side of the first epitaxial layer away from the first substrate;

[0089] a first conductivity type source region located in the second conductivity type well region;

[0090] A characteristic trench located between adjacent second conductivity type well regions and in the first epitaxial layer, a first characteristic dielectric layer located at the bottom of the characteristic trench, and a second characteristic dielectric layer located at the sidewalls of the characteristic trench;

[0091] A characteristic conductive layer located in the characteristic trench and wrapped by the first characteristic dielectric layer and the second characteristic dielectric layer, wherein the characteristic conductive layer, the second characteristic dielectric layer and the first epitaxial layer form a field plate structure;

[0092] A gate dielectric layer located on a surface of the first epitaxial layer away from the first substrate; a gate electrode located on a surface of the gate dielectric layer away from the first epitaxial layer; an isolation dielectric layer located on both sides of the gate electrode and on a surface away from the gate dielectric layer and completely surrounding the gate electrode; and a source electrode located on both sides of the isolation dielectric layer and on a surface away from the gate electrode.

[0093] Example 2

[0094] As shown in FIG2 , a planar gate silicon carbide MOSFET power device with an integrated field plate structure in this embodiment is basically the same as that in Example 1, except that a split-gate structure is adopted in this embodiment, i.e., the gate electrode 9 includes at least two disconnected parts: a first gate electrode 9-1 and a second gate electrode 9-2, and the isolation dielectric layer 10 also includes two disconnected parts: a first isolation dielectric layer 10-1 and a second isolation dielectric layer 10-2; the first gate electrode 9-1 is wrapped by the first isolation dielectric layer 10-1 and the gate dielectric layer 12; the second gate electrode 9-2 is wrapped by the second isolation dielectric layer 10-2 and the gate dielectric layer 1 ... -1, the second gate electrode 9-2 is located on the first epitaxial layer 3, the second conductivity type well region 6 and a portion of the first conductivity type source region 7; at the same time, the electrode material of the source electrode 11, namely the source metal 13, extends into the characteristic trench 4 and is surrounded by the first characteristic dielectric layer 5-1 and the second characteristic dielectric layer 5-2 in the characteristic trench 4. In other words, the source metal 13 replaces the characteristic conductive layer 8 in Example 1; the electrode material of the source electrode 11 in the characteristic trench 4, namely the source metal 13, the second characteristic dielectric layer 5-2 and the first epitaxial layer 3 form a field plate structure, which can also play a role in modulating the electric field distribution on the surface of the semiconductor material, thereby effectively protecting the gate dielectric. In addition, the split-gate structure can further reduce the gate-drain capacitance and improve the switching characteristics.

[0095] A method for manufacturing a planar gate silicon carbide MOSFET power device with an integrated field plate structure in this embodiment includes the following steps:

[0096] Step 1: forming a first epitaxial layer 3 on a first substrate 2 by epitaxial growth.

[0097] Step 2: Form a second conductive type well region 6 and a first conductive type source region 7 located in the second conductive type well region 6 in sequence through an epitaxial process or an ion implantation process; STEP 1 and STEP 2 in this embodiment are the same as STEP 1 and STEP 2 in embodiment 1.

[0098] Step 3: forming a gate dielectric layer material and a gate electrode material on the surface of the first epitaxial layer 3 by a chemical vapor deposition process.

[0099] Step 4: Form a gate dielectric layer 12 and a gate electrode located on the gate dielectric layer 12 through photolithography and etching processes. The gate electrode includes at least two unconnected parts: a first gate electrode 9-1 and a second gate electrode 9-2. An isolation dielectric layer is formed above and on both sides of the gate electrode to completely surround the gate electrode. The isolation dielectric layer also includes two unconnected parts: a first isolation dielectric layer 10-1 and a second isolation dielectric layer 10-2. The first gate electrode 9-1 is wrapped by the first isolation dielectric layer 10-1 and the gate dielectric layer 12. The second gate electrode 9-2 is wrapped by the second isolation dielectric layer 10-2 and the gate dielectric layer 12.

[0100] Step 5: Etch the first epitaxial layer 3 to form a characteristic trench 4 , where the characteristic trench 4 is located between adjacent second conductivity type well regions 6 ; STEP 5 in this embodiment is the same as STEP 3 in the first embodiment.

[0101] Step 6: Form a first characteristic dielectric layer 5-1 and a second characteristic dielectric layer 5-2 in the characteristic groove 4 through a chemical vapor deposition process or a thermal oxidation process in combination with a photolithography and etching process. The first characteristic dielectric layer 5-1 and the second characteristic dielectric layer 5-2 can be formed by performing heavy-dose ion implantation and thermal oxidation on the bottom of the characteristic groove 4, or by depositing polycrystalline silicon or amorphous silicon at the bottom of the characteristic groove 4 and then performing thermal oxidation to form the first characteristic dielectric layer 5-1 and the second characteristic dielectric layer 5-2.

[0102] Step 7: Deposit source metal 13 on both sides and on top of the first isolation dielectric layer 10-1 and the second isolation dielectric layer 10-2 to form a source ohmic contact. The source metal 13 extends into the characteristic groove 4 and is surrounded by the first characteristic dielectric layer 5-1 and the second characteristic dielectric layer 5-2. That is, the source metal 13 replaces the characteristic conductive layer 8 in Example 1; the electrode material of the source electrode 11 in the characteristic groove 4, namely the source metal 13, the second characteristic dielectric layer 5-2 and the first epitaxial layer 3 form a field plate structure.

[0103] Step 8: Deposit drain metal on the bottom of the first substrate 2 to form a drain ohmic contact, form a source electrode 11 on the surface of the source ohmic contact, and form a drain electrode 1 on the surface of the drain ohmic contact.

[0104] In summary, as shown in FIG4B , the method for manufacturing a planar gate silicon carbide MOSFET power device includes:

[0105] S21, forming a first epitaxial layer on a first side surface of a first substrate by epitaxial growth;

[0106] S22, sequentially forming a second conductivity type well region and a first conductivity type source region located in the second conductivity type well region in a portion of the first epitaxial layer away from the first substrate by an epitaxial process or an ion implantation process;

[0107] S23, forming a gate dielectric layer material and a gate electrode material on a surface of the first epitaxial layer away from the first substrate by a chemical vapor deposition process;

[0108] S24. Forming a gate dielectric layer and a gate electrode located on the gate dielectric layer by photolithography and etching processes on the gate dielectric layer material and the gate electrode material, respectively; the gate electrodes at least include a first gate electrode and a second gate electrode that are not connected; wherein the first gate electrode and the second gate electrode are respectively located on the first epitaxial layer, the second conductive type well region, and a portion of the first conductive type source region corresponding to each other; forming a first isolation dielectric layer that completely surrounds the first gate electrode on both sides of the first gate electrode and on a surface of the first gate electrode away from the gate dielectric layer, and forming a second isolation dielectric layer that completely surrounds the second gate electrode on both sides of the second gate electrode and on a surface of the second gate electrode away from the gate dielectric layer;

[0109] S25, etching the first epitaxial layer to form a characteristic trench, wherein the characteristic trench is located between adjacent second conductivity type well regions;

[0110] S26, forming a first characteristic dielectric layer and a second characteristic dielectric layer in the characteristic trench by a chemical vapor deposition process or a thermal oxidation process combined with a photolithography and etching process; wherein the first characteristic dielectric layer is located at the bottom of the characteristic trench, and the second characteristic dielectric layer is located on the sidewalls on opposite sides of the characteristic trench;

[0111] S27, depositing source metal on a portion within a characteristic trench enclosed by two side walls of the first isolation dielectric layer and the second isolation dielectric layer, on both sides of the first isolation dielectric layer and the second isolation dielectric layer, and on a surface of the first isolation dielectric layer and the second isolation dielectric layer away from the gate electrode, to form a source ohmic contact, thereby forming a source electrode on the surface of the source ohmic contact and serving as a characteristic conductive layer in the characteristic trench, wherein the characteristic conductive layer, the second characteristic dielectric layer, and the first epitaxial layer form a field plate structure;

[0112] S28. Deposit a drain metal on a second side of the first substrate opposite to the first side to form a drain ohmic contact, so as to form a drain electrode on a surface of the drain ohmic contact.

[0113] The planar gate silicon carbide MOSFET power device manufactured using the above-mentioned planar gate silicon carbide MOSFET power device manufacturing method includes:

[0114] a first substrate;

[0115] a drain electrode and a first epitaxial layer located on opposite sides of the first substrate;

[0116] a second conductivity type well region located in a side of the first epitaxial layer away from the first substrate;

[0117] a first conductivity type source region located in the second conductivity type well region;

[0118] A characteristic trench located between adjacent second conductivity type well regions and in the first epitaxial layer, a first characteristic dielectric layer located at the bottom of the characteristic trench, and a second characteristic dielectric layer located at the sidewalls of the characteristic trench;

[0119] A source metal located in the characteristic trench and wrapped by the first characteristic dielectric layer and the second characteristic dielectric layer, wherein the source metal, the second characteristic dielectric layer and the first epitaxial layer form a field plate structure;

[0120] a gate dielectric layer located on a surface of the first epitaxial layer away from the first substrate;

[0121] a first gate electrode and a second gate electrode located on a surface of the gate dielectric layer away from the first epitaxial layer; the first gate electrode and the second gate electrode are respectively located on the first epitaxial layer, the second conductivity type well region, and a portion of the first conductivity type source region corresponding to each of the first and second gate electrodes;

[0122] a first isolation dielectric layer located on both sides of the first gate electrode and on a surface of the first gate electrode away from the gate dielectric layer and completely surrounding the first gate electrode, and a second isolation dielectric layer located on both sides of the second gate electrode and on a surface of the second gate electrode away from the gate dielectric layer and completely surrounding the second gate electrode;

[0123] A source electrode is located on both sides of the first isolation dielectric layer and the second isolation dielectric layer and on a surface away from the gate electrode.

[0124] Example 3

[0125] As shown in Figure 3, a planar gate silicon carbide MOSFET power device with an integrated field plate structure in this embodiment is basically the same as the structure of Example 1 or the structure of Example 2, except that a second conductive type heavily doped region 14 is formed in the second conductive type well region 6, and the depth of the second conductive type heavily doped region 14 ranges from 0.2μm to 0.7μm, and the doping concentration ranges from 1e19cm-3 to 5e20cm-3. The second conductive type heavily doped region 14 can be adjacent to the first conductive type source region 7, and the two can be in contact or not in contact; the second conductive type heavily doped region 14 can further improve the body diode characteristics of the device.

Claims

1. A planar-gate silicon carbide metal-oxide-semiconductor field-effect transistor (MOSFET) power device, comprising: A first substrate; A drain electrode and a first epitaxial layer located on opposite sides of the first substrate; A second-conductivity-type well region located in the first epitaxial layer on the side away from the first substrate; A first-conductivity-type source region located in the second-conductivity-type well region; A feature trench located between adjacent second-conductivity-type well regions and in the first epitaxial layer, a first feature dielectric layer located at the bottom of the feature trench, and a second feature dielectric layer located on the sidewalls of the feature trench; A feature conductive layer located in the feature trench and wrapped by the first feature dielectric layer and the second feature dielectric layer, and the feature conductive layer, the second feature dielectric layer, and the first epitaxial layer form a field plate structure; A gate dielectric layer located on the surface of the first epitaxial layer on the side away from the first substrate; a gate electrode located on the surface of the gate dielectric layer on the side away from the first epitaxial layer; an isolation dielectric layer located on the two sides of the gate electrode and on the surface on the side away from the gate dielectric layer and completely surrounding the gate electrode; A source electrode located on the two sides of the isolation dielectric layer and on the surface on the side away from the gate electrode.

2. The device according to claim 1, wherein The depth range of the feature trench is 0.5 μm to 1.0 μm, the width range is 0.5 μm to 1.2 μm, and the distance range in the x direction between the feature trench and the second-conductivity-type well region is 0.2 μm to 1.0 μm; the x direction refers to the width direction of the planar-gate silicon carbide MOSFET power device.

3. The device according to claim 1, wherein The thickness range of the first feature dielectric layer is 200 nm to 500 nm, and the thickness range of the second feature dielectric layer is 50 nm to 100 nm.

4. The device according to claim 1, wherein The gate electrode adopts a split-gate structure and includes a first gate electrode and a second gate electrode that are not connected to each other. The first gate electrode and the second gate electrode are respectively located on the corresponding first epitaxial layer, the second-conductivity-type well region, and a part of the first-conductivity-type source region on both sides of the feature trench; The source metal forming the source electrode extends into the feature trench to serve as the feature conductive layer, and the source metal in the feature trench, the second feature dielectric layer, and the first epitaxial layer outside the feature trench form a field plate structure.

5. The device according to claim 1, wherein A second-conductivity-type heavily doped region is provided in the second-conductivity-type well region, where the depth range of the second-conductivity-type heavily doped region is 0.2 μm to 0.7 μm, and the doping concentration range is 1e19 cm -3 ~5e20 cm -3 .

6. The device according to claim 1, wherein The depth range of the second conductivity type well region is 0.5 μm to 1.5 μm, and the doping concentration range is 5e16 cm -3 ~5e18 cm -3 ; the depth range of the first conductivity type source region is 0.2 μm to 0.5 μm, and the doping concentration range is 5e18 cm -3 ~5e20 cm -3 .

7. A manufacturing method of a planar-gate silicon carbide metal-oxide-semiconductor field-effect transistor (MOSFET) power device, comprising: Forming a first epitaxial layer on the first side surface of the first substrate by epitaxial growth; Sequentially forming a second-conductivity-type well region and a first-conductivity-type source region located in the second-conductivity-type well region in the part of the first epitaxial layer away from the first substrate by an epitaxial process or an ion implantation process; Etching the first epitaxial layer to form a feature trench, and the feature trench is located between adjacent second-conductivity-type well regions; Form a first characteristic dielectric layer, a second characteristic dielectric layer, and a characteristic conductive layer in the characteristic trench through a chemical vapor deposition process or a thermal oxidation process, in combination with a photolithography process and an etching process; wherein, the first characteristic dielectric layer is located at the bottom of the characteristic trench, the second characteristic dielectric layer is located on the sidewalls of the opposite sides of the characteristic trench, and the characteristic conductive layer is wrapped by the first characteristic dielectric layer and the second characteristic dielectric layer; Form a gate dielectric layer material and a gate electrode material on the surface of the first epitaxial layer away from the first substrate through a chemical vapor deposition process; Respectively form a gate dielectric layer and a gate electrode by using a photolithography process and an etching process on the gate dielectric layer material and the gate electrode material; Form an isolation dielectric layer that completely surrounds the gate electrode on the surface of the gate electrode away from the gate dielectric layer and on both sidewalls of the gate electrode; Deposit source metal on both sidewalls of the isolation dielectric layer and on the surface of the isolation dielectric layer away from the gate electrode to form a source ohmic contact, so as to form a source electrode on the surface of the source ohmic contact; Deposit drain metal on the second side of the first substrate opposite to the first side to form a drain ohmic contact, so as to form a drain electrode on the surface of the drain ohmic contact.

8. A planar-gate silicon carbide metal-oxide-semiconductor field-effect transistor (MOSFET) power device, comprising: A first substrate; A drain electrode and a first epitaxial layer located on opposite sides of the first substrate; A second-conductivity-type well region located in the first epitaxial layer away from the first substrate; A first-conductivity-type source region located in the second-conductivity-type well region; A characteristic trench located between adjacent second-conductivity-type well regions and in the first epitaxial layer, a first characteristic dielectric layer located at the bottom of the characteristic trench, and a second characteristic dielectric layer located on the sidewalls of the characteristic trench; Source metal located in the characteristic trench and wrapped by the first characteristic dielectric layer and the second characteristic dielectric layer, and the source metal, the second characteristic dielectric layer, and the first epitaxial layer form a field plate structure; A gate dielectric layer located on the surface of the first epitaxial layer away from the first substrate; A first gate electrode and a second gate electrode located on the surface of the gate dielectric layer away from the first epitaxial layer; the first gate electrode and the second gate electrode are respectively located on their corresponding first epitaxial layer, second-conductivity-type well region, and part of the first-conductivity-type source region; A first isolation dielectric layer located on both sides of the first gate electrode and on the surface of the first gate electrode away from the gate dielectric layer and completely surrounding the first gate electrode, and a second isolation dielectric layer located on both sides of the second gate electrode and on the surface of the second gate electrode away from the gate dielectric layer and completely surrounding the second gate electrode; A source electrode located on both sides of the first isolation dielectric layer and the second isolation dielectric layer and on the surface of the isolation dielectric layer away from the gate electrode.

9. The device according to claim 8, wherein A second-conductivity-type heavily doped region is provided in the second-conductivity-type well region, and the depth range of the second-conductivity-type heavily doped region is 0.2 μm to 0.7 μm, and the doping concentration range is 1e19 cm -3 ~5e20 cm -3 .

10. A manufacturing method of a planar-gate silicon carbide MOSFET power device, comprising: A first epitaxial layer is formed on the first side surface of the first substrate by epitaxial growth; A second conductivity type well region and a first conductivity type source region located in the second conductivity type well region are sequentially formed in a portion of the first epitaxial layer far from the first substrate by an epitaxial process or an ion implantation process; A gate dielectric layer material and a gate electrode material are formed on the surface of the first epitaxial layer far from the first substrate by a chemical vapor deposition process; A gate dielectric layer and a gate electrode located on the gate dielectric layer are respectively formed by performing photolithography and etching processes on the gate dielectric layer material and the gate electrode material; the gate electrode at least includes a first gate electrode and a second gate electrode that are not connected; wherein, the first gate electrode and the second gate electrode are respectively located on the corresponding first epitaxial layer, the second conductivity type well region, and a part of the first conductivity type source region; A first isolation dielectric layer that completely surrounds the first gate electrode is formed on both sides of the first gate electrode and on the surface of the first gate electrode far from the gate dielectric layer, and a second isolation dielectric layer that completely surrounds the second gate electrode is formed on both sides of the second gate electrode and on the surface of the second gate electrode far from the gate dielectric layer; The first epitaxial layer is etched to form characteristic trenches, and the characteristic trenches are located between adjacent second conductivity type well regions; A first characteristic dielectric layer and a second characteristic dielectric layer are formed in the characteristic trenches by a chemical vapor deposition process or a thermal oxidation process in combination with photolithography and etching processes; wherein, the first characteristic dielectric layer is located at the bottom of the characteristic trenches, and the second characteristic dielectric layer is located on the sidewalls of the opposite sides of the characteristic trenches; Source metal is deposited in the characteristic trenches surrounded by the sidewalls of the first isolation dielectric layer and the second isolation dielectric layer, on both sides of the first isolation dielectric layer and the second isolation dielectric layer, and on the surface of the first isolation dielectric layer and the second isolation dielectric layer far from the gate electrode to form a source ohmic contact, so as to form a source electrode on the surface of the source ohmic contact and serve as a characteristic conductive layer in the characteristic trenches, wherein the characteristic conductive layer, the second characteristic dielectric layer, and the first epitaxial layer form a field plate structure; Drain metal is deposited on the second side of the first substrate opposite to the first side to form a drain ohmic contact, so as to form a drain electrode on the surface of the drain ohmic contact.

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