Planar-gate silicon carbide mosfet power device and manufacturing method therefor

Abstract

A planar-gate silicon carbide MOSFET power device and a manufacturing method therefor. The device comprises a feature trench (6), a first conductive type silicon carbide substrate (2), a first conductive type silicon carbide epitaxial layer (3), first conductive type source regions (5), a first conductive type channel diode source region (7), second conductive type well regions (4), and a second conductive type channel diode well region (8). A channel diode control gate (10-2) is formed in the feature trench (6), and a gate electrode (10-1) is formed on the surface of the first conductive type silicon carbide epitaxial layer (3).

Description

Planar gate silicon carbide MOSFET power device and manufacturing method thereof

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on December 28, 2023, with application number 202311836348.X. The entire contents of the above application are incorporated by reference into this application. Technical Field

[0002] The present application belongs to the field of semiconductor device technology, and for example relates to a planar gate silicon carbide MOSFET power device and a manufacturing method thereof. Background Art

[0003] As power electronics technology continues to advance toward higher power density, lower switching losses, and miniaturization, the performance of power semiconductor devices urgently needs to be improved. The superior performance of SiC power devices in high-power, high-temperature applications has brought new hope to the power electronics field, attracting significant attention from companies and research institutions both domestically and internationally.

[0004] Among SiC power devices, the SiC Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) has been widely used due to its advantages such as simple gate drive and unipolar conduction. However, as a core component in power systems, SiC power MOSFET devices require not only good forward conduction characteristics but also excellent reverse conduction performance. Although SiC power MOSFET devices have an internal body diode that can continue current in third-quadrant operating conditions, the body diode's turn-on voltage is as high as 2V to 3V, inevitably resulting in significant conduction losses. Furthermore, in the reverse conduction state, the energy generated by the recombination of electrons and holes causes stacking dislocations to propagate at basal plane dislocations in the SiC epitaxial layer, resulting in a bipolar degeneration effect that degrades the device's electrical performance.

[0005] A common solution in the industry is to use SiC MOSFET devices in anti-parallel with external diodes, but this solution adds additional parasitic capacitance and inductance, and the metal connections also reduce device reliability.

[0006] Summary of the Invention

[0007] In response to the above-mentioned shortcomings of SiC MOSFET power devices, the present application provides a planar gate silicon carbide MOSFET power device and a manufacturing method thereof, integrating a trench diode in the planar gate SiC MOSFET power device to achieve optimization of the third quadrant characteristics.

[0008] The present application provides a planar gate silicon carbide MOSFET power device, comprising:

[0009] A first conductive type silicon carbide substrate, and a drain electrode and a first conductive type silicon carbide epitaxial layer respectively located on two opposite surfaces of the first conductive type silicon carbide substrate;

[0010] a second conductivity type well region and a second conductivity type channel diode well region located in a portion of the first conductivity type silicon carbide epitaxial layer away from the first conductivity type silicon carbide substrate, wherein along the length direction of the planar gate silicon carbide MOSFET power device, the second conductivity type well region is located on both sides of the second conductivity type channel diode well region;

[0011] a first conductivity type source region located in the second conductivity type well region, and a first conductivity type channel diode source region located in the second conductivity type channel diode well region;

[0012] A characteristic trench sequentially penetrating the first conductive type trench diode source region and the second conductive type trench diode well region along the depth direction of the planar gate silicon carbide MOSFET power device and ending in the first conductive type silicon carbide epitaxial layer;

[0013] a first dielectric layer located on a surface of the first conductive type silicon carbide epitaxial layer on a side away from the first conductive type silicon carbide substrate;

[0014] a second dielectric layer located on both sidewalls of the characteristic trench;

[0015] and a third dielectric layer located at the bottom of the characteristic trench;

[0016] a gate electrode located on a surface of the first dielectric layer on a side away from the first conductive type silicon carbide substrate;

[0017] a channel diode control gate located in the characteristic trench and surrounded by the second dielectric layer and the third dielectric layer;

[0018] a fourth dielectric layer surrounding the gate electrode;

[0019] Source electrodes are located on both sides of the fourth dielectric layer and on a surface of the fourth dielectric layer on a side away from the first conductive type silicon carbide substrate.

[0020] The present application provides a method for preparing a planar gate silicon carbide MOSFET power device, comprising:

[0021] forming a first conductive type silicon carbide epitaxial layer by epitaxial growth on the first side surface of the first conductive type silicon carbide substrate;

[0022] forming a second conductivity type well region and a second conductivity type channel diode well region in a portion of the first conductivity type silicon carbide epitaxial layer away from the first conductivity type silicon carbide substrate by an epitaxial process or an ion implantation process;

[0023] forming a first conductivity type source region in the second conductivity type well region by an epitaxial process or an ion implantation process, and forming a first conductivity type channel diode source region in the second conductivity type channel diode well region;

[0024] Etching the first conductive type silicon carbide epitaxial layer to form a characteristic trench penetrating the first conductive type channel diode source region and the second conductive type channel diode well region and ending in the first conductive type silicon carbide epitaxial layer;

[0025] forming a dielectric layer on the first conductive type silicon carbide epitaxial layer, on the bottom of the characteristic trench and on both sidewalls of the characteristic trench;

[0026] A gate electrode material is deposited on a surface of the dielectric layer away from the first conductive type silicon carbide substrate, and a first dielectric layer, a second dielectric layer, a third dielectric layer, a gate electrode, and a trench diode control gate are formed by photolithography and etching processes; wherein the first dielectric layer is located above the first conductive type silicon carbide epitaxial layer, the second dielectric layer is located on both sidewalls of the characteristic trench, and the third dielectric layer is located at the bottom of the characteristic trench; and the gate electrode is located above the first dielectric layer, and the trench diode control gate is located in a space enclosed by the second dielectric layer and the third dielectric layer;

[0027] forming a fourth dielectric layer completely surrounding the gate electrode on and on both sides of a surface of the gate electrode on a side away from the first conductive type silicon carbide substrate;

[0028] A source metal is formed on both sides of the fourth dielectric layer and on a surface of the fourth dielectric layer away from the first conductive type silicon carbide substrate to form a source electrode, and a metal layer is deposited on a second side of the first conductive type silicon carbide substrate opposite to the first side to form a drain electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] FIG1 is a schematic diagram of a low-power planar gate silicon carbide MOSFET power device according to Example 1.

[0030] FIG2 is a schematic diagram of a low-power planar gate silicon carbide MOSFET power device according to Example 2.

[0031] FIG3 is a flow chart of a method for manufacturing the device of Example 1.

[0032] FIG4 is a schematic diagram of the structure formed in step 1 of the method for manufacturing the device of Example 1. FIG.

[0033] FIG5 is a schematic diagram of the structure formed in step 2 of the method for manufacturing the device of Example 1. FIG.

[0034] FIG6 is a schematic diagram of the structure formed in step 3 of the method for manufacturing the device of Example 1.

[0035] FIG. 7 is a schematic diagram of the structure formed in step 4 of the method for manufacturing the device of Example 1. FIG.

[0036] FIG8 is a schematic diagram of the structure formed in step 5 of the method for manufacturing the device of Example 1.

[0037] FIG9 is a schematic diagram of the structure formed in step 6 of the method for manufacturing the device of Example 1. FIG.

[0038] FIG10 is a schematic diagram of the structure formed in step 7 of the method for manufacturing the device of Example 1. FIG.

[0039] Explanation of the accompanying symbols: 1. drain electrode; 2. first conductive type silicon carbide substrate; 3. first conductive type silicon carbide epitaxial layer; 4. second conductive type well region; 5. first conductive type source region; 6. characteristic trench; 7. first conductive type channel diode source region; 8. second conductive type channel diode well region; 9-1. first dielectric layer; 9-2. second dielectric layer; 9-3. third dielectric layer; 9-4. fourth dielectric layer; 10-1. gate electrode; 10-2. channel diode control gate; 11. source electrode; 12. first conductive type current extension region. DETAILED DESCRIPTION

[0040] The present application is described below with reference to the following examples. The examples are only used to illustrate the present application and do not constitute a limitation on the scope of the claims. Other alternative means that can be thought of by those skilled in the art are all within the scope of the claims of the present application.

[0041] Furthermore, in the description of this application, terms such as "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer" indicate positions or locations based on those shown in the accompanying drawings. These terms are intended solely to facilitate the description of this application and simplify the description. They are not intended to indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0042] Example 1

[0043] As shown in Figure 1, the low-power planar gate silicon carbide MOSFET power device has an x-direction that is the length direction of the device and a y-direction that is the depth direction of the device; it includes a drain electrode 1; a first-conductivity-type silicon carbide substrate 2 located on the drain electrode 1; and a first-conductivity-type silicon carbide epitaxial layer 3 located on the first-conductivity-type silicon carbide substrate 2.

[0044] A second conductivity type well region 4 located in the first conductivity type silicon carbide epitaxial layer 3 ; and a first conductivity type source region 5 located in the second conductivity type well region 4 .

[0045] A second conductive type channel diode well region 8 is located in the first conductive type silicon carbide epitaxial layer 3; a first conductive type channel diode source region 7 is located in the second conductive type channel diode well region 8; a second conductive type channel diode well region 8 is provided between adjacent second conductive type well regions 4; the distance between the second conductive type channel diode well region 8 and the second conductive type well region 4 in the x direction is not less than 0.3 μm.

[0046] A characteristic trench 6 is located in the first conductive type silicon carbide epitaxial layer 3 and penetrates the second conductive type channel diode well region 8 and the first conductive type channel diode source region 7; the characteristic trench 6 has a depth range of 0.5μm to 3.0μm and a width range of 0.5μm to 3.0μm.

[0047] A first dielectric layer 9-1 is located on the surface of the first conductive type silicon carbide epitaxial layer 3; a second dielectric layer 9-2 is located on both sidewalls of the characteristic groove 6; and a third dielectric layer 9-3 is located at the bottom of the characteristic groove 6. The thickness of the first dielectric layer ranges from 30nm to 70nm, the thickness of the second dielectric layer ranges from 5nm to 35nm, and the thickness of the third dielectric layer ranges from 15nm to 140nm. The thickness of the third dielectric layer is 3 to 4 times the thickness of the second dielectric layer.

[0048] Exemplarily, there are multiple first dielectric layers 9-1; the first dielectric layer 9-1 close to the characteristic groove 6 is located above a portion of the second conductive type channel diode well region 8, above a portion of the first conductive type source region 5, and above the second conductive type well region 4 and the first conductive type silicon carbide epitaxial layer 3 between the second conductive type channel diode well region 8 and the first conductive type source region 5; the first dielectric layer 9-1 away from the characteristic groove 6 is located above a portion of the first conductive type source region 5, the second conductive type well region 4 and the first conductive type silicon carbide epitaxial layer 3 away from the characteristic groove 6.

[0049] The gate electrode 10-1 is located on the first dielectric layer 9-1. As shown in Figure 1, the edges of the two gate electrodes 10-1 on the same side of the characteristic trench 6 are located on the first conductive type source region 5. The trench diode control gate 10-2 is located between the second dielectric layers 9-2. The fourth dielectric layer 9-4 is located on the first conductive type silicon carbide epitaxial layer 3 and completely surrounds the gate electrode 10-1. The source electrode 11 is located on both sides of and on the fourth dielectric layer 9-4.

[0050] The depth of the characteristic trench 6 is greater than the depth of the channel diode control gate 10-2, and the difference between the two is not less than 0.05μm. The depth of the channel diode control gate 10-2 is greater than the depth of the second conductive type channel diode well region 8, and the difference between the two is not less than 0.1μm.

[0051] The method for preparing the above-mentioned low-power planar gate silicon carbide MOSFET power device comprises the following steps:

[0052] Step 1: As shown in FIG4 , a first conductivity type silicon carbide epitaxial layer 3 is formed on a first conductivity type silicon carbide substrate 2 by epitaxial growth. The doping concentration of the first conductivity type silicon carbide epitaxial layer 3 is 1e15 cm −3 to 1e17 cm −3 .

[0053] Step 2. As shown in Figure 5, a patterned ion implantation mask layer is formed on the surface of the first conductive type silicon carbide epitaxial layer 3 prepared in step 1, and ion implantation is performed using the patterned ion implantation mask layer. A second conductive type well region 4 and a second conductive type channel diode well region 8 are formed by the ion implantation process. The second conductive type well region 4 and the second conductive type channel diode well region 8 have the same depth and no width, which are set according to actual conditions. The depth range of the two is 0.5μm to 3.5μm, and the doping concentration range is 1e17cm-3 to 5e18cm-3. The ion implantation mask layer is then removed; the second conductive type well region 4 is located on both sides of the second conductive type channel diode well region 8.

[0054] Step 3. As shown in Figure 6, a patterned ion implantation mask layer is formed on the surface of the first conductive type silicon carbide epitaxial layer 3 prepared in step 2, and ion implantation is performed using the patterned ion implantation mask layer. A first conductive type source region 5 and a first conductive type channel diode source region 7 are formed by the ion implantation process. The depths of the first conductive type source region 5 and the first conductive type channel diode source region 7 are the same, and the depth range of the two is 0.1μm to 0.4μm. The width of the first conductive type source region 5 is smaller than the width of the first conductive type channel diode source region 7, and the difference between the two is not less than 0.5μm. The doping concentration range is 5e18cm-3 to 2e20cm-3, and then the ion implantation mask layer is removed; the first conductive type source region 5 is located in the second conductive type well region 4, and the first conductive type channel diode source region 7 is located in the second conductive type channel diode well region 8. The width of the first conductive type channel diode source region 7 is smaller than the width of the second conductive type channel diode well region 8, and the difference between the two is not less than 0.3μm.

[0055] Step 4: As shown in FIG7 , a patterned etch mask layer is formed on the surface of the SiC MOSFET device prepared in step 3. The first conductivity type silicon carbide epitaxial layer 3 is etched using the patterned etch mask layer using inductively coupled plasma (ICP) to form a characteristic trench 6 that penetrates the second conductivity type trench diode well region 8 and the first conductivity type trench diode source region 7. The etch mask layer is then removed. The characteristic trench 6 has a depth ranging from 0.5 μm to 3.0 μm and a width ranging from 0.5 μm to 3.0 μm.

[0056] Step 5, as shown in Figure 8, a dielectric layer is formed on the surface of the first conductive type silicon carbide epitaxial layer 3 through a thermal oxidation process, a second dielectric layer 9-2 is formed on both sidewalls of the characteristic trench 6, and a third dielectric layer 9-3 is formed at the bottom of the characteristic trench 6. The thickness of the second dielectric layer 9-2 is in the range of 5nm to 35nm, and the thickness of the third dielectric layer 9-3 and the dielectric on the surface of the first conductive type silicon carbide epitaxial layer 3 is in the range of 15nm to 140nm. The thickness of the third dielectric layer and the dielectric layer on the surface of the first conductive type silicon carbide epitaxial layer 3 is 3 to 4 times the thickness of the second dielectric layer 9-2. After high-temperature annealing, polycrystalline silicon is grown on the surface of the dielectric layer through a low-pressure chemical vapor deposition (LPCVD) process.

[0057] Step 6, as shown in Figure 9, a patterned etching mask layer is deposited on the surface of the device formed in step 5, and the patterned etching mask layer is used to etch the gate material and the dielectric layer on the surface of the first conductive type silicon carbide epitaxial layer 3 to form a gate electrode 10-1, a trench diode control gate 10-2 and a first dielectric layer 9-1. The etching mask layer is then removed, and the gate electrode 10-1 is implanted and activated by annealing; the gate electrode 10-1 is located on the first dielectric layer 9-1. The number of first dielectric layers 9-1 is several, and they are located on part of the second conductive type trench diode well region 8, part of the first conductive type source region 5, the second conductive type well region 4 and the first conductive type silicon carbide epitaxial layer 3, that is, the first dielectric layer 9-1 is located between the gate electrode 10-1 and the forward conductive channel of the MOSFET, that is, located on the surface area of ​​the second conductive type well region 4 outside the first conductive type source region 5; the trench diode control gate 10-2 is located in the characteristic trench 6 and is wrapped by the second dielectric layer 9-2 and the third dielectric layer 9-3.

[0058] Step 7. As shown in Figure 10, a dielectric layer is deposited on the surface of the device prepared in Step 6 and patterned to form a fourth dielectric layer 9-4. The fourth dielectric layer 9-4 completely surrounds the gate electrode 10-1. Source metal is deposited on both sides and above the fourth dielectric layer 9-4 to form a source ohmic contact. Drain metal is deposited on the bottom layer of the first conductivity type silicon carbide substrate 2 to form a drain ohmic contact. A source electrode 11 is formed on the surface of the source ohmic contact, and a drain electrode 1 is formed on the surface of the drain ohmic contact.

[0059] The gate material can be metal or doped polysilicon.

[0060] The gate dielectric layer can be made of silicon oxide, silicon nitride, borophosphosilicate glass, aluminum oxide, sapphire, or hafnium oxide. The semiconductor material used in the device can be 3C-SiC, 4H-SiC, or 6H-SiC. The source electrode material can be one or more metals such as Ti, Al, Ni, and Pt. The isolation dielectric layer can be silicon dioxide, nitride, or a combination of silicon dioxide and nitride.

[0061] In summary, as shown in FIG3 , a method for preparing a low-power planar gate silicon carbide MOSFET power device includes:

[0062] S1. epitaxially growing a first conductive type silicon carbide epitaxial layer on a first side surface of a first conductive type silicon carbide substrate;

[0063] S2. forming a second conductivity type well region and a second conductivity type channel diode well region in a portion of the first conductivity type silicon carbide epitaxial layer away from the first conductivity type silicon carbide substrate by an epitaxial process or an ion implantation process;

[0064] S3, forming a first conductivity type source region in the second conductivity type well region by an epitaxial process or an ion implantation process, and forming a first conductivity type channel diode source region in the second conductivity type channel diode well region;

[0065] S4, etching the first conductive type silicon carbide epitaxial layer to form a characteristic trench penetrating the first conductive type channel diode source region and the second conductive type channel diode well region and ending in the first conductive type silicon carbide epitaxial layer;

[0066] S5, forming a dielectric layer on the first conductive type silicon carbide epitaxial layer, at the bottom of the characteristic trench and on both sidewalls of the characteristic trench;

[0067] S6. Depositing a gate electrode material on a surface of the dielectric layer away from the first conductive type silicon carbide substrate, and forming a first dielectric layer, a second dielectric layer, a third dielectric layer, a gate electrode, and a trench diode control gate through photolithography and etching processes; wherein the first dielectric layer is located above the first conductive type silicon carbide epitaxial layer, the second dielectric layer is located on both sidewalls of the characteristic trench, and the third dielectric layer is located at the bottom of the characteristic trench; and the gate electrode is located above the first dielectric layer, and the trench diode control gate is located in a space enclosed by the second dielectric layer and the third dielectric layer;

[0068] S7, forming a fourth dielectric layer completely surrounding the gate electrode on and on both sides of the surface of the gate electrode on a side away from the first conductive type silicon carbide substrate;

[0069] S8. Form source metal on both sides of the fourth dielectric layer and on the surface of the fourth dielectric layer away from the first conductive type silicon carbide substrate to form a source electrode, and deposit a metal layer on the second side of the first conductive type silicon carbide substrate opposite to the first side to form a drain electrode.

[0070] The low-power planar gate silicon carbide MOSFET power device manufactured using the above manufacturing method includes:

[0071] A first conductive type silicon carbide substrate, and a drain electrode and a first conductive type silicon carbide epitaxial layer respectively located on two opposite surfaces of the first conductive type silicon carbide substrate;

[0072] a second conductivity type well region and a second conductivity type channel diode well region located in a portion of the first conductivity type silicon carbide epitaxial layer away from the first conductivity type silicon carbide substrate, wherein along the length direction of the planar gate silicon carbide MOSFET power device, the second conductivity type well region is located on both sides of the second conductivity type channel diode well region;

[0073] a first conductivity type source region located in the second conductivity type well region, and a first conductivity type channel diode source region located in the second conductivity type channel diode well region;

[0074] A characteristic trench sequentially penetrating the first conductive type trench diode source region and the second conductive type trench diode well region along the depth direction of the planar gate silicon carbide MOSFET power device and ending in the first conductive type silicon carbide epitaxial layer;

[0075] a first dielectric layer located on a surface of the first conductive type silicon carbide epitaxial layer on a side away from the first conductive type silicon carbide substrate;

[0076] a second dielectric layer located on both sidewalls of the characteristic trench, and a third dielectric layer located at the bottom of the characteristic trench;

[0077] a gate electrode located on a surface of the first dielectric layer on a side away from the first conductive type silicon carbide substrate;

[0078] a channel diode control gate located in the characteristic trench and surrounded by the second dielectric layer and the third dielectric layer;

[0079] a fourth dielectric layer surrounding the gate electrode;

[0080] Source electrodes are located on both sides of the fourth dielectric layer and on a surface of the fourth dielectric layer on a side away from the first conductive type silicon carbide substrate.

[0081] Example 2

[0082] A low-power planar gate silicon carbide MOSFET power device, as shown in Figure 2, is basically the same as Example 1, except that a first conductive type current extension region 12 is formed on the surface of the first conductive type silicon carbide epitaxial layer 3 by ion implantation or epitaxial growth; a second conductive type well region 4 and a second conductive type channel diode well region 8 are formed in the first conductive type current extension region 12; a first conductive type source region 5 is formed in the second conductive type well region 4, a first conductive type channel diode source region 7 is formed in the second conductive type channel diode well region 8, and a characteristic groove 6 is formed that passes through the first conductive type channel diode source region 7, the second conductive type channel diode well region 8, and the first conductive type current extension region 12.

[0083] The depth of the first conductive type current extension region 12 is in the range of 0.5 μm to 3.0 μm, and the doping concentration is in the range of 5e16 cm-3 to 5e18 cm-3, which can further increase the current density of the device and improve the forward conduction characteristics of the device.

[0084] The low-power planar gate silicon carbide MOSFET power device proposed in this application integrates a trench diode in the planar gate silicon carbide MOSFET power device. In the reverse conduction state, unipolar conduction is achieved through the freewheeling path of the trench diode, preventing the body diode from turning on, avoiding the bipolar degradation effect, and effectively improving the reverse recovery characteristics and reliability of the device.

[0085] The low-power planar gate silicon carbide MOSFET power device proposed in this application effectively reduces the gate-drain overlap area by setting a channel diode, significantly reduces the gate-drain capacitance, and thus greatly reduces the switching loss of the device and improves the switching characteristics.

Claims

1. A planar-gate silicon carbide metal-oxide-semiconductor field-effect transistor (MOSFET) power device, comprising: A silicon carbide substrate of a first conductivity type, and a drain electrode and a silicon carbide epitaxial layer of the first conductivity type respectively located on opposite surfaces of the silicon carbide substrate of the first conductivity type; A second conductivity type well region and a second conductivity type channel diode well region located in a portion of the silicon carbide epitaxial layer of the first conductivity type away from the silicon carbide substrate of the first conductivity type. Along the length direction of the planar-gate silicon carbide MOSFET power device, the second conductivity type well region is located on both sides of the second conductivity type channel diode well region; A first conductivity type source region located in the second conductivity type well region, and a first conductivity type channel diode source region located in the second conductivity type channel diode well region; A characteristic trench sequentially penetrating through the first conductivity type channel diode source region and the second conductivity type channel diode well region along the depth direction of the planar-gate silicon carbide MOSFET power device and ending in the silicon carbide epitaxial layer of the first conductivity type; A first dielectric layer located on a surface of the silicon carbide epitaxial layer of the first conductivity type away from the silicon carbide substrate of the first conductivity type; A second dielectric layer located on both sidewalls of the characteristic trench, and a third dielectric layer located at the bottom of the characteristic trench; A gate electrode located on a surface of the first dielectric layer away from the silicon carbide substrate of the first conductivity type; A channel diode control gate located in the characteristic trench and surrounded by the second dielectric layer and the third dielectric layer; A fourth dielectric layer surrounding the gate electrode; Source electrodes located on both sides of the fourth dielectric layer and on a surface of the fourth dielectric layer away from the silicon carbide substrate of the first conductivity type.

2. The device according to claim 1, wherein The channel diode control gate is in full contact with the source electrodes. The thickness range of the first dielectric layer is 30 nm to 100 nm, the thickness range of the second dielectric layer is 5 nm to 35 nm, and the thickness range of the third dielectric layer is 20 nm to 150 nm.

3. The device according to claim 1, wherein, The difference in depth between the second conductivity type channel diode well region and the first conductivity type channel diode source region is equal to the channel length of the channel diode, and the difference in depth between the second conductivity type channel diode well region and the first conductivity type channel diode source region is not less than 0.3 μm.

4. The device according to claim 1, wherein The width of the first conductivity type channel diode source region is less than the width of the second conductivity type channel diode well region, and the difference in width between the first conductivity type channel diode source region and the second conductivity type channel diode well region is not less than 0.3 μm.

5. The device according to claim 1, wherein, The distance between the second conductivity type channel diode well region and the second conductivity type well region in the x direction is not less than 0.3 μm. The second conductivity type channel diode well region and the second conductivity type well region have the same depth. The depth of the characteristic trench is greater than the depth of the channel diode control gate, and the depth of the channel diode control gate is greater than the depth of the second conductivity type channel diode well region.

6. The device according to claim 1, wherein, The number of the first dielectric layers is multiple; The first dielectric layer near the feature trench is located above a part of the second-conductivity-type channel diode well region, above a part of the first-conductivity-type source region, and above the second-conductivity-type well region and the first-conductivity-type silicon carbide epitaxial layer between the second-conductivity-type channel diode well region and the first-conductivity-type source region; The first dielectric layer far from the feature trench is located above a part of the first-conductivity-type source region, above the second-conductivity-type well region far from the feature trench, and above the first-conductivity-type silicon carbide epitaxial layer.

7. The device according to claim 1, wherein The width of the first-conductivity-type source region is smaller than the width of the first-conductivity-type channel diode source region, and the difference between the width of the first-conductivity-type source region and the width of the first-conductivity-type channel diode source region is not less than 0.5 μm.

8. A method for manufacturing a planar-gate silicon carbide metal-oxide-semiconductor field-effect transistor (MOSFET) power device, comprising: Epitaxially growing a first-conductivity-type silicon carbide epitaxial layer on a first side of a first-conductivity-type silicon carbide substrate; Forming a second-conductivity-type well region and a second-conductivity-type channel diode well region in a part of the side of the first-conductivity-type silicon carbide epitaxial layer away from the first-conductivity-type silicon carbide substrate by an epitaxial process or an ion implantation process; Forming a first-conductivity-type source region in the second-conductivity-type well region and a first-conductivity-type channel diode source region in the second-conductivity-type channel diode well region by an epitaxial process or an ion implantation process; Etching the first-conductivity-type silicon carbide epitaxial layer to form a feature trench that penetrates through the first-conductivity-type channel diode source region and the second-conductivity-type channel diode well region and terminates in the first-conductivity-type silicon carbide epitaxial layer; Forming a dielectric layer on the first-conductivity-type silicon carbide epitaxial layer, at the bottom of the feature trench, and on both sidewalls of the feature trench; Depositing a gate electrode material on the surface of the dielectric layer away from the first-conductivity-type silicon carbide substrate, and forming a first dielectric layer, a second dielectric layer, a third dielectric layer, a gate electrode, and a channel diode control gate through photolithography and etching processes; wherein, the one located above the first-conductivity-type silicon carbide epitaxial layer is the first dielectric layer, the ones located on both sidewalls of the feature trench are the second dielectric layers, and the one located at the bottom of the feature trench is the third dielectric layer; and, the gate electrode is located above the first dielectric layer, and the channel diode control gate is located in the space surrounded by the second dielectric layer and the third dielectric layer; Forming a fourth dielectric layer that completely surrounds the gate electrode on the surface of the gate electrode away from the first-conductivity-type silicon carbide substrate and on both sides; Forming a source metal on both sides of the fourth dielectric layer and on the surface of the fourth dielectric layer away from the first-conductivity-type silicon carbide substrate to form a source electrode, and depositing a metal layer on a second side of the first-conductivity-type silicon carbide substrate opposite to the first side to form a drain electrode.

9. According to the method of claim 8, wherein, The etching process is an inductively coupled plasma (ICP) etching process, and the etching gas used is at least one of SF6, HBr, Cl2, O2, and Ar gases.

10. According to the method of claim 8, wherein, The process of forming the first dielectric layer, the second dielectric layer, and the third dielectric layer is a thermal oxidation process. The thickness range of the formed second dielectric layer is 5 nm to 35 nm, and the thickness range of the third dielectric layer is 15 nm to 200 nm.

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