Manufacturing method for gallium nitride high-electron-mobility transistor device

Abstract

A manufacturing method for a GaN HEMT device, comprising: providing a substrate (1), wherein a GaN channel layer (3) and an AlGaN barrier layer (4) which are stacked are formed on the substrate (1), a PGaN cap layer (5) is formed on the AlGaN barrier layer (4), and a gate metal layer (6) is formed on the PGaN cap layer (5); forming a source metal layer (8) and a drain metal layer (9) on the AlGaN barrier layer (4), wherein in the horizontal direction, the source metal layer (8) and the drain metal layer (9) are respectively arranged on two sides of the PGaN cap layer (5); performing local annealing, wherein during local annealing, the source metal layer (8) and the drain metal layer (9) are in an annealing temperature range, the source metal layer (8) and the drain metal layer (9) respectively form ohmic contact with the AlGaN barrier layer (4), and the gate metal layer (6) is not in the annealing temperature range.

Description

Method for manufacturing gallium nitride high electron mobility transistor device

[0001] Related applications

[0002] This application claims priority to Chinese patent application number 202311831540.X, filed on December 27, 2023, entitled “Method for manufacturing GaN HEMT device,” the entire text of which is hereby incorporated by reference. Technical Field

[0003] The present invention belongs to the field of semiconductor technology and relates to a method for manufacturing a gallium nitride high electron mobility transistor (GaN HEMT) device. Background Art

[0004] Gallium nitride high electron mobility transistors (GaN HEMTs) have great application prospects in radio frequency, microwave, and power conversion circuits due to their high breakdown electric field and low on-resistance. Among them, P-type gate technology is the main method for realizing enhancement-mode GaN HEMT devices. It has the advantages of strong process controllability and large-scale reproducible production, and is the mainstream technology used in commercial products. Figure 1 shows a schematic structural diagram of a P-type gate GaN HEMT device. As shown in Figure 1, a high concentration of two-dimensional electron gas (2DEG) naturally exists at the interface between the GaN channel layer 3 and the AlGaN barrier layer 4. A PGaN cap layer 5 is formed on the AlGaN barrier layer 4 to deplete the 2DEG in the gate region, realizing a normally-off (enhancement-mode) device. In this case, the gate metal layer 6 is located on the PGaN cap layer 5, and the source metal layer 8 and the drain metal layer 9 are located on the AlGaN barrier layer 4 and are respectively arranged on both sides of the PGaN cap layer 5.

[0005] During the manufacturing process, a gate-first process is usually used to produce low-voltage GaN HEMT devices. That is, the gate contact structure is completed first, and then the source and drain ohmic contacts are patterned and annealed. As shown in Figure 2, through the annealing process, the source metal layer 8 is thermally diffused into the AlGaN barrier layer 4, reducing the interface contact resistance to form an ohmic structure. The drain metal layer 9 is thermally diffused into the AlGaN barrier layer 4 to reduce the interface contact resistance to form an ohmic structure. However, during annealing, the gate metal layer 6 is exposed to a high temperature environment, causing the gate metal layer 6 to diffuse into the PGaN cap layer 5, resulting in increased gate forward leakage and limited device performance.

[0006] Therefore, how to provide a method for manufacturing a GaN HEMT device to reduce gate forward leakage and improve device performance has become a technical problem that needs to be urgently solved by those skilled in the art.

[0007] Summary of the Invention

[0008] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for manufacturing a gallium nitride high electron mobility transistor (GaN HEMT) device, so as to solve the problems of increased gate forward leakage and low device performance in the prior art.

[0009] To achieve the above-mentioned and other related objectives, the present invention provides a method for manufacturing a GaN HEMT device, comprising the following steps.

[0010] A substrate is provided, on which a GaN channel layer and an AlGaN barrier layer are stacked from bottom to top, wherein a PGaN cap layer is formed on the AlGaN barrier layer, and a gate metal layer is formed on the PGaN cap layer.

[0011] A source metal layer and a drain metal layer are formed on the AlGaN barrier layer. In a horizontal direction, the source metal layer and the drain metal layer are respectively arranged on two sides of the PGaN cap layer.

[0012] Local annealing is performed, wherein during the local annealing process, the source metal layer and the drain metal layer are in an annealing temperature range, the source metal layer and the AlGaN barrier layer form an ohmic contact, the drain metal layer and the AlGaN barrier layer form an ohmic contact, and the gate metal layer is not in the annealing temperature range.

[0013] In some embodiments, before performing the local annealing, the method further includes forming a high thermal resistance layer, wherein the high thermal resistance layer covers the gate metal layer, but does not cover the source metal layer and the drain metal layer.

[0014] In some embodiments, the thermal conductivity of the high thermal resistance layer is no more than 30 W / (m·K).

[0015] In some embodiments, the material of the high thermal resistance layer includes SiO 2 .

[0016] In some embodiments, the step of forming the high thermal resistance layer includes: forming a high thermal resistance material layer on the AlGaN barrier layer by a deposition method, wherein the high thermal resistance material layer covers the gate metal layer, the source metal layer and the drain metal layer; and patterning the high thermal resistance material layer by an etching method to form the high thermal resistance layer.

[0017] In some embodiments, the local annealing is performed by laser annealing; a patterned mask is arranged between the laser light source and the electrode metal layer, wherein the electrode metal layer includes the gate metal layer, the source metal layer, and the drain metal layer; the mask includes an absorption area and a penetrable area; the projection of the absorption area in the direction toward the substrate covers the gate metal layer, and the projection of the penetrable area in the direction toward the substrate covers the source metal layer and the drain metal layer.

[0018] In some embodiments, the material of the absorption region includes Cr, and the material of the transparent region includes SiO 2 .

[0019] In some embodiments, before forming the source metal layer and the drain metal layer on the AlGaN barrier layer, the method further includes forming a passivation layer; the passivation layer covers the exposed surface of the AlGaN barrier layer, wherein the source metal layer penetrates the passivation layer and is electrically connected to the AlGaN barrier layer, and the drain metal layer penetrates the passivation layer and is electrically connected to the AlGaN barrier layer.

[0020] In some embodiments, the passivation layer is made of SiN.

[0021] In some embodiments, the local annealing temperature ranges from 500 to 900 degrees Celsius.

[0022] In some embodiments, a buffer layer is formed between the substrate and the GaN channel layer.

[0023] In some embodiments, the substrate includes a silicon substrate, a silicon carbide substrate, or a sapphire substrate.

[0024] In some embodiments, the buffer layer 2 is a GaN buffer layer.

[0025] In some embodiments, the thermal conductivity of the high thermal resistance layer is no more than 10 W / (m·K).

[0026] As described above, in the method for manufacturing a GaN HEMT device of the present invention, local annealing is performed during annealing. The source metal layer and the drain metal layer regions are annealed to achieve ohmic contact between the source metal layer and the AlGaN barrier layer, and ohmic contact between the drain metal layer and the AlGaN barrier layer. The gate metal layer is not within the annealing temperature range, and the gate metal layer region is not annealed. This can effectively reduce thermal diffusion from the gate metal layer to the PGaN cap layer, thereby reducing the forward leakage level of the gate and improving the performance and reliability of the GaN HEMT device. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] FIG1 is a schematic structural diagram of a P-type gate GaN HEMT device in the related art.

[0028] FIG. 2 is a schematic diagram showing a P-type gate GaN HEMT device in the related art after high temperature annealing.

[0029] FIG3 is a process flow chart showing a method for manufacturing a GaN HEMT device according to the present invention.

[0030] FIG. 4 is a schematic diagram showing a process of forming a gate metal layer on a PGaN cap layer of a GaN HEMT device according to an embodiment of the present invention.

[0031] FIG. 5 is a schematic diagram showing a GaN HEMT device in which a source metal layer and a drain metal layer are formed according to an embodiment of the present invention.

[0032] FIG. 6 is a schematic diagram showing a GaN HEMT device having a high thermal resistance layer formed thereon according to an embodiment of the present invention.

[0033] FIG. 7 is a schematic diagram showing a GaN HEMT device after high temperature annealing according to an embodiment of the present invention.

[0034] FIG. 8 is a schematic diagram showing a GaN HEMT device after high temperature annealing according to an embodiment of the present invention.

[0035] Component Reference Numerals 1 Substrate 2 Buffer layer 3 GaN channel layer 4 AlGaN barrier layer 5 PGaN cap layer 6 Gate metal layer 7 Passivation layer 8 Source metal layer 9 Drain metal layer 10 High thermal resistance layer 11 Laser light source 12 Mask 1200 Absorption region 1201 Transmissive region S1-S3 Steps DETAILED DESCRIPTION

[0036] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0037] Please refer to Figures 1 to 8. It should be noted that the figures provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Therefore, the figures only show components relevant to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, number, and proportion of each component may be varied arbitrarily, and the component layout may also be more complex.

[0038] The present application provides a method for manufacturing a GaN HEMT device. In one embodiment, FIG3 shows a process flow chart of the method for manufacturing the GaN HEMT device. As shown in FIG3 , the method includes the following steps S1-S3.

[0039] S1: providing a substrate 1 on which a GaN channel layer 3 and an AlGaN barrier layer 4 are stacked from bottom to top, wherein a PGaN cap layer 5 is formed on the AlGaN barrier layer 4, and a gate metal layer 6 is formed on the PGaN cap layer 5.

[0040] S2: forming a source metal layer 8 and a drain metal layer 9 on the AlGaN barrier layer 4 . In a horizontal direction, the source metal layer 8 and the drain metal layer 9 are respectively arranged on two sides of the PGaN cap layer 5 .

[0041] S3: Perform local annealing, wherein during the local annealing process, the source metal layer 8 and the drain metal layer 9 are in an annealing temperature range, the source metal layer 8 and the AlGaN barrier layer 4 form an ohmic contact, the drain metal layer 9 and the AlGaN barrier layer 4 form an ohmic contact, and the gate metal layer 6 is not in the annealing temperature range.

[0042] First, referring to FIG4 , in step S1 : providing a substrate 1 , on which a GaN channel layer 3 and an AlGaN barrier layer 4 stacked from bottom to top are formed, wherein a PGaN cap layer 5 is formed on the AlGaN barrier layer 4 , and a gate metal layer 6 is formed on the PGaN cap layer 5 .

[0043] As an example, the substrate 1 may be a silicon substrate, a silicon carbide substrate, a sapphire substrate, or any other suitable substrate. Specifically, in one embodiment, the substrate 1 is a silicon substrate.

[0044] As an example, a buffer layer 2 is provided between the substrate 1 and the GaN channel layer 3 to reduce the possibility of crystal mismatch between the GaN channel layer 3 and the substrate 1 and improve the quality of the GaN channel layer 3. Specifically, in one embodiment, the buffer layer 2 is a GaN buffer layer.

[0045] As an example, a high concentration of 2DEG naturally exists at the interface between the GaN channel layer 3 and the AlGaN barrier layer 4 , and the PGaN cap layer 5 depletes the 2DEG in the gate region.

[0046] Please refer to FIG. 5 , in step S2 : a source metal layer 8 and a drain metal layer 9 are formed on the AlGaN barrier layer 4 . In the horizontal direction, the source metal layer 8 and the drain metal layer 9 are respectively disposed on both sides of the PGaN cap layer 5 .

[0047] As an example, before forming the source metal layer 8 and the drain metal layer 9 on the AlGaN barrier layer, a step of forming a passivation layer 7 is also included. The passivation layer 7 covers the exposed surface of the AlGaN barrier layer 4. Of course, the passivation layer 7 can also cover the exposed surfaces of the gate metal layer 6 and the PGaN cap layer 5. The material of the passivation layer 7 includes SiN. The passivation layer 7 can passivate the surface defects of the AlGaN barrier layer 4 and reduce interface leakage current.

[0048] As an example, the passivation layer 7 is etched to form a first opening and a second opening, wherein the first opening is used for the source metal layer 8 to pass through the passivation layer 7 and electrically connect to the AlGaN barrier layer 4, and the second opening is used for the drain metal layer 9 to pass through the passivation layer 7 and electrically connect to the AlGaN barrier layer 4.

[0049] Please refer to Figures 6 and 7. In step S3, local annealing is performed. During the annealing process, the source metal layer 8 and the drain metal layer 9 are in an annealing temperature range so that the source metal layer 8 and the AlGaN barrier layer 4 form an ohmic contact, and the drain metal layer 9 and the AlGaN barrier layer 4 form an ohmic contact. The gate metal layer 6 is not in the annealing temperature range.

[0050] As an example, in one embodiment, annealing is performed using a rapid thermal annealing method, and the annealing temperature range is 500-900°C. In one embodiment, as shown in FIG6 , before performing the local annealing, a step of forming a high thermal resistance layer 10 is also included, wherein the high thermal resistance layer 10 covers the gate metal layer 6, but does not cover the source metal layer 8 and the drain metal layer 9. Specifically, the steps of forming the high thermal resistance layer 10 include:

[0051] (1) A high thermal resistance material layer is formed on the AlGaN barrier layer 4 by a deposition method, wherein the high thermal resistance material layer covers the gate metal layer 6 , the source metal layer 8 and the drain metal layer 9 .

[0052] (2) Patterning the high thermal resistance material layer by etching to form the high thermal resistance layer 10 , that is, etching away the high thermal resistance material layer covering the source metal layer 8 and the drain metal layer 9 .

[0053] As an example, the thermal conductivity of the high thermal resistance layer 10 does not exceed 30 W / (m·K) to prevent the gate metal layer 6 from overheating and causing thermal diffusion during subsequent high-temperature annealing. In one embodiment, the thermal conductivity of the high thermal resistance layer 10 does not exceed 10 W / (m·K). The lower the thermal conductivity of the high thermal resistance layer 10, the better the thermal insulation effect on the gate metal layer 6 during the annealing process. Specifically, in one embodiment, the material of the high thermal resistance layer 10 includes SiO2. Since the passivation layer 7 is formed on the gate metal layer 6, the high thermal resistance layer 10 covers the passivation layer 7 on the periphery of the gate metal layer 6.

[0054] As an example, please refer to Figure 7, which is a schematic diagram of local annealing. Since the source metal layer 8 and the drain metal layer 9 are directly exposed to a high-temperature environment, they will diffuse into the AlGaN barrier layer 4, reducing the contact resistance of the contact surface, that is, the source metal layer 8 and the AlGaN barrier layer 4 are annealed at high temperature to form an ohmic contact, and the drain metal layer 9 and the AlGaN barrier layer 4 are annealed at high temperature to form an ohmic contact.

[0055] As an example, since the high thermal resistance layer 10 is formed in the region of the gate metal layer 6, the high thermal resistance layer 10 blocks heat from being transferred to the gate metal layer 6, and the gate metal layer 6 does not generate heat diffusion toward the PGaN cap layer 5, thereby reducing the gate forward leakage and improving the performance of the GaN HEMT device.

[0056] As described above, in the method for manufacturing a GaN HEMT device of the present invention, local annealing is performed during annealing. Annealing is performed in the source metal layer 8 and the drain metal layer 9 regions to achieve ohmic contact between the source metal layer 8 and the AlGaN barrier layer 4, and ohmic contact between the drain metal layer 9 and the AlGaN barrier layer 4. The gate metal layer 6 is not within the annealing temperature range, and the gate metal layer 6 region is not annealed. This can effectively reduce thermal diffusion from the gate metal layer 6 to the PGaN cap layer 5, thereby reducing the forward leakage level of the gate and improving the performance and reliability of the GaN HEMT device.

[0057] One embodiment of the present application further provides a method for fabricating a GaN HEMT device. Please refer to FIG8 , which is a schematic diagram of local annealing performed in this embodiment. This embodiment differs from the above-described embodiments in that laser annealing is employed, and a patterned mask 12 is disposed between the laser light source 11 and the electrode metal layer (including the gate metal layer 6 , the source metal layer 8 , and the drain metal layer 9 ). The mask 12 includes an absorption region 1200 and a transmissive region 1201 . The absorption region 1200 projects toward the substrate 1 covering the gate metal layer 6 , while the transmissive region 1201 projects toward the substrate 1 covering the source metal layer 8 and the drain metal layer 9 .

[0058] As an example, the material of the absorption region 1200 includes Cr, and the material of the penetrable region 1201 includes SiO2. When the laser emitted by the laser light source 11 passes through the penetrable region 1201, it can penetrate the penetrable region 1201 to reach the source metal layer 8 and the source metal layer 9, and perform high-temperature annealing on the source metal layer 8 and the drain metal layer 9, so that the source metal layer 8 thermally diffuses toward the AlGaN barrier layer 4, reducing the interface contact resistance to form an ohmic structure, and the drain metal layer 9 thermally diffuses toward the AlGaN barrier layer 4, reducing the interface contact resistance to form an ohmic structure.

[0059] As an example, the laser emitted by the laser light source 11 is absorbed when passing through the absorption region 1200, and the laser cannot reach the gate metal layer 6. The gate metal layer 6 will not generate heat diffusion toward the PGaN cap layer 5, thereby reducing the gate forward leakage and improving the performance of the GaN HEMT device.

[0060] In summary, in the method for fabricating a GaN HEMT device of the present invention, local annealing is performed during annealing. The source metal layer 8 and the drain metal layer 9 regions are annealed to achieve source and drain ohmic contacts, while the gate metal layer 6 region is not annealed. This effectively reduces thermal diffusion from the gate metal layer 6 to the PGaN cap layer 4. Thus, the present invention effectively overcomes the shortcomings of the prior art, reduces the forward leakage level of the gate, and improves the performance and reliability of the GaN HEMT device.

[0061] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A manufacturing method of a GaN HEMT device, comprising: Providing a substrate, on which a GaN channel layer and an AlGaN barrier layer are stacked from bottom to top. Among them, a p-GaN cap layer is formed on the AlGaN barrier layer, and a gate metal layer is formed on the p-GaN cap layer; Forming a source metal layer and a drain metal layer on the AlGaN barrier layer. In the horizontal direction, the source metal layer and the drain metal layer are respectively disposed on both sides of the p-GaN cap layer; Performing local annealing. During the local annealing process, the source metal layer and the drain metal layer are within the annealing temperature range, an ohmic contact is formed between the source metal layer and the AlGaN barrier layer, an ohmic contact is formed between the drain metal layer and the AlGaN barrier layer, and the gate metal layer is not within the annealing temperature range.

2. The manufacturing method of the GaN HEMT device according to claim 1, wherein: Before performing local annealing, it further includes forming a high thermal resistance layer, wherein the high thermal resistance layer covers the gate metal layer, and the high thermal resistance layer does not cover the source metal layer and the drain metal layer.

3. The manufacturing method of the GaN HEMT device according to claim 2, characterized in that: The thermal conductivity coefficient of the high thermal resistance layer does not exceed 30 W / (m·K).

4. The manufacturing method of the GaN HEMT device according to claim 2 or 3, characterized in that, The material of the high thermal resistance layer includes SiO2.

5. The manufacturing method of the GaN HEMT device according to any one of claims 2-4, characterized in that: The step of forming the high thermal resistance layer includes: Forming a high thermal resistance material layer on the AlGaN barrier layer by a deposition method, and the high thermal resistance material layer covers the gate metal layer, the source metal layer and the drain metal layer; Patternizing the high thermal resistance material layer by an etching method to form the high thermal resistance layer.

6. The manufacturing method of the GaN HEMT device according to any one of claims 1-5, characterized in that: The local annealing is performed by a laser annealing method; a patterned mask is provided between the laser light source and the electrode metal layer, wherein the electrode metal layer includes the gate metal layer, the source metal layer, and the drain metal layer; the mask includes an absorption region and a transmissive region; the projection of the absorption region in the direction towards the substrate covers the gate metal layer, and the projection of the transmissive region in the direction towards the substrate covers the source metal layer and the drain metal layer.

7. The manufacturing method of the GaN HEMT device according to claim 6, characterized in that: The material of the absorption region includes Cr, and the material of the transmissive region includes SiO2.

8. The manufacturing method of the GaN HEMT device according to any one of claims 1-7, characterized in that: Before forming the source metal layer and the drain metal layer on the AlGaN barrier layer, the method further includes forming a passivation layer; the passivation layer covers the exposed surface of the AlGaN barrier layer, wherein the source metal layer penetrates through the passivation layer and is electrically connected to the AlGaN barrier layer, and the drain metal layer penetrates through the passivation layer and is electrically connected to the AlGaN barrier layer.

9. The manufacturing method of the GaN HEMT device according to claim 8, characterized in that: The material of the passivation layer includes SiN.

10. The manufacturing method of the GaN HEMT device according to any one of claims 1-9, characterized in that: The temperature range of the local annealing is 500 to 900 degrees Celsius.

11. The manufacturing method of the GaN HEMT device according to any one of claims 1-10, characterized in that: A buffer layer is formed between the substrate and the GaN channel layer.

12. The manufacturing method of the GaN HEMT device according to any one of claims 1-11, characterized in that: The substrate includes a silicon substrate, a silicon carbide substrate or a sapphire substrate.

13. The manufacturing method of the GaN HEMT device according to claim 11, characterized in that: The buffer layer 2 is a GaN buffer layer.

14. The manufacturing method of the GaN HEMT device according to claim 2, characterized in that: The thermal conductivity coefficient of the high thermal resistance layer does not exceed 10 W / (m·K).

Images