Display panel

Abstract

The present application provides a display panel, comprising a selection control circuit. The selection control circuit is configured to output a start signal during an N-th frame by means of one of a first start signal output end and a second start signal output end on the basis of a frame inversion signal transmitted by a frame inversion signal input end and a stage transmission signal transmitted by a stage transmission signal input end, and output a start signal during an (N+1)-th frame by means of the other of the first start signal output end and the second start signal output end on the basis of the frame inversion signal and the stage transmission signal.

Description

Display panel

[0001] This application claims priority to Chinese patent application No. 202311869857.2 filed on December 29, 2023. The contents of the above-mentioned Chinese patent application disclosure are hereby incorporated by reference in their entirety as part of this application. Technical Field

[0002] The present application relates to, but is not limited to, the field of display technology, and specifically to a display panel. Background Art

[0003] Existing display panels generally output multiple clock signals to the gate drive circuit through a level converter electrically connected to the control chip. The gate drive circuit generates voltages to control the on and off of transistors in multiple rows of pixels on the display panel based on the multiple clock signals, thereby controlling the pixels to be turned on row by row, and multiple data lines transmit data signals to each pixel in the pixel row whose gate is turned on.

[0004] Since the gate driving circuit of a traditional display panel needs to turn on the pixels row by row from the first row of pixels to the last row of pixels during one frame until all the pixels of the display panel are charged to display one frame of picture, for a high-resolution display panel with a large number of rows of pixels, the display panel needs to transmit a large amount of data signals during one frame, resulting in higher power consumption of the display panel.

[0005] Therefore, it is necessary to propose a new technical solution to solve the above technical problems. SUMMARY OF THE INVENTION

[0006] The purpose of this application is to provide a display panel to reduce the power consumption of the display panel.

[0007] The present application proposes a display panel, comprising:

[0008] a first display area, a second display area, and a third display area, wherein the first display area, the second display area, and the third display area are arranged in sequence along a first direction;

[0009] The display panel further includes:

[0010] a plurality of rows of pixels arranged sequentially along the first direction;

[0011] a gate driving circuit comprising a multi-stage shift register unit, wherein an output end of each stage of the shift register unit is electrically connected to a row of pixels; and

[0012] The selection control circuit includes a frame inversion signal input terminal, a level transmission signal input terminal, a first start signal output terminal, and a second start signal output terminal. The level transmission signal input terminal is electrically connected to the level transmission signal output terminal of the shift register unit electrically connected to the last row of pixels in the second display area, the first start signal output terminal is electrically connected to the input terminal of the shift register unit electrically connected to the first row of pixels in the first display area, and the second start signal output terminal is electrically connected to the input terminal of the shift register unit electrically connected to the first row of pixels in the third display area. The selection control circuit is configured to select one of the first start signal output terminal and the second start signal output terminal to output a start signal during an Nth frame based on the frame inversion signal transmitted by the frame inversion signal input terminal and the level transmission signal transmitted by the level transmission signal input terminal, and to select the other of the first start signal output terminal and the second start signal output terminal to output a start signal during an N+1th frame based on the frame inversion signal input by the frame inversion signal input terminal and the level transmission signal transmitted by the level transmission signal input terminal, wherein N is a non-zero positive integer. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] FIG1 is a schematic diagram of a selection control circuit provided in Example 1 of the present application;

[0014] FIG2 is a circuit diagram of the selection control circuit shown in FIG1 ;

[0015] FIG3 is a schematic diagram of a display panel provided in Example 1 of the present application;

[0016] FIG4 is a schematic diagram of the connection relationship between the gate drive circuit and the selection control circuit shown in FIG3;

[0017] FIG5 is a timing diagram of the gate drive circuit and the selection control circuit shown in FIG4 ;

[0018] FIG6 is a schematic diagram of a display panel provided in Example 2 of the present application;

[0019] FIG7 is a schematic diagram showing the connection relationship between the gate drive circuit and the selection control circuit of the present application. Modes for Carrying Out the Invention

[0020] To make the purpose, technical solutions and effects of this application clearer and more specific, the following further describes this application in detail with reference to the accompanying drawings and examples. It should be understood that the specific examples described herein are only used to explain this application and are not intended to limit this application.

[0021] Optionally, in some embodiments of the present application, the selection control circuit further includes:

[0022] a first control unit, wherein a control end of the first control unit is electrically connected to the frame inversion signal input end, an input end of the first control unit is electrically connected to the level transmission signal input end, and an output end of the first control unit is electrically connected to the first start signal output end, the first control unit being configured to conduct the level transmission signal input end and the first start signal output end when the frame inversion signal transmitted by the frame inversion signal input end is at one of a high level and a low level, and to disconnect the level transmission signal input end and the first start signal output end when the frame inversion signal transmitted by the frame inversion signal input end is at the other of a high level and a low level;

[0023] A second control unit, wherein the control end of the second control unit is electrically connected to the frame inversion signal input end, the input end of the second control unit is electrically connected to the level transmission signal input end, the output end of the second control unit is electrically connected to the second start signal output end, and the second control unit is configured to turn on the level transmission signal input end and the second start signal output end when the frame inversion signal inputted from the frame inversion signal input end is the other of a high level and a low level, and to disconnect the level transmission signal input end and the second start signal output end when the frame inversion signal inputted from the frame inversion signal input end is the other of a high level and a low level.

[0024] Optionally, in some embodiments of the present application, during the Nth frame, the frame inversion signal input terminal transmits one of a continuous high-level signal and a low-level signal, and during the N+1th frame, the frame inversion signal input terminal transmits the other of a continuous high-level signal and a low-level signal.

[0025] Optionally, in some embodiments of the present application, the first control unit includes:

[0026] a first input control module, wherein an input end of the first input control module is electrically connected to the frame inversion signal input end, an output end of the first input control module is electrically connected to a first control node, and the first input control module is configured to control a level of the first control node according to a signal at the frame inversion signal input end;

[0027] a first output module, wherein an input end of the first output module is electrically connected to the first control node and the level transmission signal input end, an output end of the first output module is electrically connected to a first output node, the first output node is electrically connected to the first start signal output end, and the first output module is configured to control the connection and disconnection between the level transmission signal input end and the first start signal output end according to the level of the first control node;

[0028] a first pull-down module, wherein an input end of the first pull-down module is electrically connected to the frame inversion signal input end, the first high-level signal input end, and the first low-level signal input end; an output end of the first pull-down module is electrically connected to the first output node and the first control node; the first pull-down module is configured to pull down the levels of the first output node and the first control node according to a signal at the frame inversion signal input end, a signal at the first high-level signal input end, and a signal at the first low-level signal input end;

[0029] The second control unit includes:

[0030] a second input control module, wherein an input end of the second input control module is electrically connected to the frame inversion signal input end, the second high-level signal input end, and the second low-level signal input end, an output end of the second input control module is electrically connected to a second control node, and the second input control module is configured to control the level of the second control node according to the signal of the frame inversion signal input end, the signal of the second high-level signal input end, and the signal of the second low-level signal input end;

[0031] a third input control module, wherein an input end of the third input control module is electrically connected to the second control node, an output end of the third input control module is electrically connected to a third control node, and the third input control module is configured to control a level of the third control node according to a level of the second control node;

[0032] a second output module, wherein an input terminal of the second output module is electrically connected to the third control node and the stage transmission signal input terminal, an output terminal of the second output module is electrically connected to a second output node, and the second output node is electrically connected to the second start signal output terminal, and the second output module is configured to control the connection and disconnection between the stage transmission signal input terminal and the second start signal output terminal according to the level of the third control node;

[0033] A second pull-down module, wherein the input end of the second pull-down module is electrically connected to the second control node, the third high-level signal input end, and the second low-level signal input end, the output end of the second pull-down module is electrically connected to the third control node and the second output node, and the second pull-down module is configured to pull down the levels of the third control node and the second output node according to the level of the second control node, the signal of the third high-level signal input end, and the signal of the second low-level signal input end.

[0034] Optionally, in some embodiments of the present application, the first input control module includes a first switch element, wherein the control end and the input end of the first switch element are both electrically connected to the frame inversion signal input end, and the output end of the first switch element is electrically connected to the first control node;

[0035] The first output module includes a second switching element and a first capacitor, the control end of the second switching element is electrically connected to the first control node, the input end of the second switching element is electrically connected to the stage transfer signal input end, the output end of the second switching element is electrically connected to the first output node, the first output node is electrically connected to the first start signal output end, and the first capacitor is electrically connected to the first control node and the first output node.

[0036] Optionally, in some embodiments of the present application, the first pull-down module includes:

[0037] a third switch element, wherein a control terminal of the third switch element is electrically connected to the frame inversion signal input terminal, an input terminal of the third switch element is electrically connected to the first low-level signal input terminal, and an output terminal of the third switch element is connected to a fourth control node;

[0038] a fourth switch element, wherein the control terminal and the input terminal of the fourth switch element are both electrically connected to the first high-level signal input terminal, and the output terminal of the fourth switch element is electrically connected to the fourth control node;

[0039] a fifth switching element, wherein a control terminal of the fifth switching element is electrically connected to the fourth control node, an input terminal of the fifth switching element is electrically connected to the first low-level signal input terminal, and an output terminal of the fifth switching element is connected to the first control node;

[0040] A sixth switching element, wherein the control end of the sixth switching element is electrically connected to the fourth control node, the input end of the sixth switching element is electrically connected to the first low-level signal input end, and the output end of the sixth switching element is electrically connected to the first output node.

[0041] Optionally, in some embodiments of the present application, the second input control module includes:

[0042] a seventh switching element, wherein a control terminal of the seventh switching element is electrically connected to the frame inversion signal input terminal, an input terminal of the seventh switching element is electrically connected to the second low-level signal input terminal, and an output terminal of the seventh switching element is connected to the second control node;

[0043] An eighth switch element, wherein the control terminal and the input terminal of the eighth switch element are both connected to the second high-level signal input terminal, and the output terminal of the eighth switch element is connected to the second control node.

[0044] Optionally, in some embodiments of the present application, the third input control module includes a ninth switch element, wherein the control terminal and the input terminal of the ninth switch element are both electrically connected to the second control node, and the output terminal of the ninth switch element is electrically connected to the third control node;

[0045] The second output module includes a tenth switching element and a second capacitor, the control terminal of the tenth switching element is electrically connected to the third control node, the input terminal of the tenth switching element is electrically connected to the stage transmission signal input terminal, the output terminal of the tenth switching element is electrically connected to the second output node, and the second capacitor is electrically connected to the third control node and the second output node;

[0046] The second pull-down module includes:

[0047] an eleventh switching element, wherein a control terminal of the eleventh switching element is electrically connected to the second control node, an input terminal of the eleventh switching element is electrically connected to the second low-level signal input terminal, and an output terminal of the eleventh switching element is electrically connected to the fifth control node;

[0048] a twelfth switching element, wherein the control terminal and the input terminal of the twelfth switching element are electrically connected to the third high-level signal input terminal, and the output terminal of the twelfth switching element is electrically connected to the fifth control node;

[0049] a thirteenth switching element, wherein a control terminal of the thirteenth switching element is electrically connected to the fifth control node, an input terminal of the thirteenth switching element is electrically connected to the second low-level signal input terminal, and an output terminal of the thirteenth switching element is electrically connected to the third control node;

[0050] A fourteenth switching element, wherein the control end of the fourteenth switching element is electrically connected to the fifth control node, the input end of the fourteenth switching element is electrically connected to the second low-level signal input end, and the output end of the fourteenth switching element is electrically connected to the second output node.

[0051] Optionally, in some embodiments of the present application, the selection control circuit includes a first selection control circuit and a second selection control circuit, and the first selection control circuit and the second selection control circuit each include a frame inversion signal input terminal, a level transfer signal input terminal, a first start signal output terminal and a second start signal output terminal;

[0052] The level transmission signal input terminal of the first selection control circuit is electrically connected to the level transmission signal output terminal of the shift register unit electrically connected to the pixels in the row above the last row in the second display area, the first start signal output terminal of the first selection control circuit is electrically connected to the input terminal of the shift register unit electrically connected to the pixels in the first row in the first display area, and the second start signal output terminal of the first selection control circuit is electrically connected to the input terminal of the shift register unit electrically connected to the pixels in the first row in the third display area;

[0053] Therefore, the level transfer signal input terminal of the second selection control circuit is electrically connected to the level transfer signal output terminal of the shift register unit electrically connected to the last row of pixels located in the second display area, the first start signal output terminal of the second selection control circuit is electrically connected to the input terminal of the shift register unit electrically connected to the second row of pixels located in the first display area, and the second start signal output terminal of the second selection control circuit is electrically connected to the input terminal of the shift register unit electrically connected to the second row of pixels located in the third display area.

[0054] Optionally, in some embodiments of the present application, the number of rows of pixels located in the second display area is greater than or equal to the number of rows of pixels located in the first display area, and greater than or equal to the number of rows of pixels located in the third display area.

[0055] In the present application, the display panel is divided into a first display area, a second display area, and a third display area in sequence in the arrangement direction of multiple rows of pixels, and a selection control circuit is set in the gate drive circuit. The selection control circuit selects, according to the frame inversion signal, to output a start signal from the first start signal output end to the shift register unit electrically connected to the first row of pixels in the first display area after the stage transfer signal of the shift register unit electrically connected to the last row of pixels in the second display area is output, so that the gates of the pixels in the first display area are opened and start charging, or selects to output a start signal from the second start signal output end to the shift register unit electrically connected to the first row of pixels in the third display area, so that the gates of the pixels in the third display area are opened and start charging, that is, during one frame, after the gates of the pixel rows in the second display area are opened row by row, the gates of the pixels in the first display area are opened. The gate of only one of the pixels located in the first display area and the pixels located in the third display area is then opened row by row and charged, so that during each frame, only the pixels in two of the three display areas are charged, thereby reducing the power consumption of the display panel during each frame, and, during the next frame, the selection control circuit selects the other of the first start signal output terminal and the second start signal output terminal to output the start signal, that is, during two adjacent frames, the charging of the pixels located in the first display area and the charging of the pixels located in the third display area are alternately performed, thereby ensuring that the pixels in all display areas of the display panel can be charged at least once during two adjacent frames, ensuring that the display panel can display at high resolution, and during two adjacent frames, the pixels in the second display area between the first display area and the third display area can maintain a higher refresh frequency, which is conducive to ensuring a high refresh frequency of the display panel.

[0056] 1 to 7 , the present application provides a display panel, comprising a first display area 101 , a second display area 102 , and a third display area 103 , wherein the first display area 101 , the second display area 102 , and the third display area 103 are sequentially arranged along a first direction Y. The present application divides the display panel into at least three display areas along the first direction Y, so that the three display areas can be controlled separately.

[0057] In the present application, the display panel further includes a plurality of rows of pixels sequentially arranged along the first direction Y, a gate driving circuit and a selection control circuit 200 .

[0058] The gate driving circuit includes a multi-stage shift register unit, and the output end of a stage of the shift register unit is electrically connected to a row of pixels.

[0059] The selection control circuit 200 includes a frame inversion signal input terminal FHL, a level transmission signal input terminal Gm1_IN, a first start signal output terminal STV2, and a second start signal output terminal STV3. The level transmission signal input terminal Gm1_IN is electrically connected to the level transmission signal output terminal of the shift register unit Gm1 electrically connected to the last row of pixels in the second display area 102. The first start signal output terminal STV2 is electrically connected to the input terminal of the shift register unit Gm1+1 electrically connected to the first row of pixels in the first display area 101. The second start signal output terminal STV3 is electrically connected to the input terminal of the shift register unit Gm1+1 electrically connected to the first row of pixels in the third display area 103. The input terminals of m1+m2+1 are electrically connected, and the selection control circuit 200 is configured to select one of the first start signal output terminal STV2 and the second start signal output terminal STV3 to output the start signal according to the frame inversion signal transmitted by the frame inversion signal input terminal FHL and the level transmission signal transmitted by the level transmission signal input terminal Gm1_IN during the Nth frame, and to select the other of the first start signal output terminal STV2 and the second start signal output terminal STV3 to output the start signal according to the frame inversion signal input by the frame inversion signal input terminal FHL and the level transmission signal transmitted by the level transmission signal input terminal Gm1_IN during the N+1th frame, where N is a non-zero positive integer.

[0060] In the present application, the first-stage shift register unit G1 electrically connected to the first row of pixels in the second display area 102 is the first-stage shift register unit of the display panel. The start signal input terminal of the first-stage shift register unit G1 electrically connected to the first row of pixels in the second display area 102 is electrically connected to the control chip to receive the frame start signal STV from the control chip.

[0061] In the present application, the display panel is divided into a first display area 101, a second display area 102 and a third display area 103 in sequence in the arrangement direction of multiple rows of pixels, and a selection control circuit 200 is set in the gate drive circuit. The selection control circuit 200 selects, according to the frame inversion signal FHL, after the level transfer signal of the shift register unit Gm1 electrically connected to the last row of pixels in the second display area 102 is output, to output a start signal from the first start signal output terminal STV2 to the shift register unit electrically connected to the first row of pixels in the first display area 101, so that the gates of the pixels in the first display area 101 are opened and start charging, or selects to output a start signal STV3 from the second start signal output terminal STV3 to the shift register unit Gm1+m2+1 electrically connected to the first row of pixels in the third display area 103, so that the gates of the pixels in the third display area 103 are opened and start charging, that is, during one frame, the gates of the pixel rows in the second display area 102 are opened row by row. After being turned on in sequence, the gate of only one of the pixels located in the first display area 101 and the pixels located in the third display area 103 are then turned on row by row and charged, so that during each frame, only the pixels in two of the three display areas are charged, thereby reducing the power consumption of the display panel during each frame. In addition, during the next frame, the selection control circuit 200 selects the other of the first start signal output terminal STV2 and the second start signal output terminal STV3 to output the start signal, that is, during two adjacent frames, the charging of the pixels located in the first display area 101 and the charging of the pixels located in the third display area 103 are alternately performed, thereby ensuring that the pixels in all display areas of the display panel can be charged at least once during two adjacent frames, ensuring that the display panel can display at high resolution, and during two adjacent frames, the pixels in the second display area 102 located between the first display area 101 and the third display area 103 can maintain a high refresh rate, which is conducive to ensuring a high refresh rate of the display panel.

[0062] The present application controls the order of partition display by selecting the control circuit 200 and realizes different refresh frequencies for different displays. The display panel of the present application has lower power consumption and transmission bandwidth requirements.

[0063] As shown in Figures 1 to 5, in Example 1 of the present application, as shown in Figure 5, during the Nth frame, the frame inversion signal input terminal FHL transmits a continuous high-level signal. When the last-stage shift register unit Gm electrically connected to the pixels of the second display area 102 outputs a level transfer signal to the level transfer signal input terminal Gm1_IN of the selection control circuit 200, the selection control circuit 200 selects the first start signal output terminal STV2 to output the start signal based on the high-level signal transmitted by the frame inversion signal input terminal FHL and the level transfer signal of the level transfer signal input terminal Gm1_IN. The first-stage shift register unit Gm+1 electrically connected to the pixels in the first display area 101 opens the gate of the first row of pixels in the first display area 101 based on the start signal output from the first start signal output terminal STV2, and opens multiple rows of pixels in the first display area 101 row by row in sequence until all pixels in the first display area 101 complete one scan, thereby completing the scan of the display panel in the Nth frame. During the (N+1)th frame, the frame inversion signal input terminal FHL transmits a continuous low-level signal. When the last-stage shift register unit Gm1 electrically connected to the pixels of the second display area 102 outputs a level transfer signal to the level transfer signal input terminal Gm1_IN of the selection control circuit 200, the selection control circuit 200 selects the second start signal output terminal STV3 to output a start signal based on the low-level signal transmitted by the frame inversion signal input terminal FHL and the level transfer signal at the level transfer signal input terminal Gm1_IN. The first-stage shift register unit Gm1+m2+1 electrically connected to the pixels in the third display area 103 turns on the gates of the first row of pixels in the third display area 103 based on the start signal output from the second start signal output terminal STV3, and then turns on multiple rows of pixels in the third display area 103 row by row, until all pixels in the third display area 103 have completed one scan, thereby completing the scan of the display panel in the (N+1)th frame.

[0064] Alternatively, during the Nth frame, the frame inversion signal input terminal FHL transmits a continuous low-level signal, and the selection control circuit 200 outputs a start signal from the first start signal output terminal STV2 based on the low-level signal transmitted by the frame inversion signal input terminal FHL and the level transmission signal of the level transmission signal input terminal Gm1_IN. During the N+1th frame, the frame inversion signal input terminal FHL transmits a continuous high-level signal, and the selection control circuit 200 outputs a start signal from the second start signal output terminal STV3 based on the high-level signal transmitted by the frame inversion signal input terminal FHL and the level transmission signal of the level transmission signal input terminal Gm1_IN.

[0065] In this embodiment, the frame inversion signal input terminal FHL is electrically connected to the control chip.

[0066] As shown in Figures 1 to 3, in this embodiment, the selection control circuit 200 further includes a first control unit 210 and a second control unit 220. The control terminal of the first control unit 210 is electrically connected to the frame inversion signal input terminal FHL, the input terminal of the first control unit 210 is electrically connected to the level transfer signal input terminal Gm1_IN, and the output terminal of the first control unit 210 is electrically connected to the first start signal output terminal STV2. The first control unit 210 is configured to connect the level transfer signal input terminal Gm1_IN and the first start signal output terminal STV2 when the frame inversion signal transmitted by the frame inversion signal input terminal FHL is at one of a high level and a low level, and disconnect the level transfer signal input terminal Gm1_IN and the first start signal output terminal STV2 when the frame inversion signal transmitted by the frame inversion signal input terminal FHL is at the other of a high level and a low level.

[0067] The control end of the second control unit 220 is electrically connected to the frame inversion signal input end FHL, the input end of the second control unit 220 is electrically connected to the level transmission signal input end Gm1_IN, and the output end of the second controlled unit is electrically connected to the second start signal output end STV3. The second control unit 220 is configured to control the level transmission signal input end Gm1_IN and the second start signal output end STV3 to be turned on when the frame inversion signal input end FHL is the other of a high level and a low level, and to control the level transmission signal input end Gm1_IN and the second start signal output end STV3 to be disconnected when the frame inversion signal input end FHL is one of a high level and a low level.

[0068] As shown in FIG. 2 , in this embodiment, the first control unit 210 includes a first input control module 211 , a first output module 212 and a first pull-down module 213 .

[0069] The input end of the first input control module 211 is electrically connected to the frame inversion signal input end FHL, and the output end of the first input control module 211 is electrically connected to the first control node Q1. The first input control module 211 is configured to control the level of the first control node Q1 according to the signal of the frame inversion signal input end FHL.

[0070] The input end of the first output module 212 is electrically connected to the first control node Q1 and the stage transmission signal input end Gm1_IN, the output end of the first output module 212 is electrically connected to the first output node K1, the first output node K1 is electrically connected to the first start signal output end STV2, and the first output module 212 is configured to control the on and off of the stage transmission signal input end Gm1_IN and the first start signal output end STV2 according to the level of the first control node Q1.

[0071] The input end of the first pull-down module 213 is electrically connected to the frame inversion signal input end FHL, the first high-level signal input end VGH1 and the first low-level signal input end VGL1. The output end of the first pull-down module 213 is electrically connected to the first output node K1 and the first control node Q1. The first pull-down module 213 is configured to pull down the levels of the first output node K1 and the first control node Q1 according to the signal of the frame inversion signal input end FHL, the signal of the first high-level signal input end VGH1 and the signal of the first low-level signal input end VGL1, so that when the first start signal output end STV2 is disconnected from the stage transfer signal input end Gm1_IN, the first start signal output end STV2 continues to output a low level.

[0072] The second control unit 220 includes a second input control module 221 , a third input control module 222 , a second output module 223 and a second pull-down module 224 .

[0073] The input end of the second input control module 221 is electrically connected to the frame inversion signal input end FHL, the second high level signal input end VGH2 and the second low level signal input end VGL2, and the output end of the second input control module 221 is electrically connected to the second control node Q2. The second input control module 221 is configured to control the level of the second control node Q2 according to the signal of the frame inversion signal input end FHL, the signal of the second high level signal input end VGH2 and the signal of the second low level signal input end VGL2.

[0074] The input end of the third input control module 222 is electrically connected to the second control node Q2, the output end of the third input control module 222 is electrically connected to the third control node Q3, and the third input control module 222 is configured to control the level of the third control node Q3 according to the level of the second control node Q2.

[0075] The input end of the second output module 223 is electrically connected to the third control node Q3 and the level transmission signal input end Gm1_IN, the output end of the second output module 223 is electrically connected to the second output node K2, the second output node K2 is electrically connected to the second start signal output end STV3, and the second output module 223 is configured to control the on and off of the level transmission signal input end Gm1_IN and the second start signal output end STV3 according to the level of the third control node Q3.

[0076] The input end of the second pull-down module 224 is electrically connected to the second control node Q2, the third high-level signal input end VGH3, and the second low-level signal input end VGL2. The output end of the second pull-down module 224 is electrically connected to the third control node Q3 and the second output node K2. The second pull-down module 224 is configured to pull down the level of the third control node Q3 and the second output node K2 according to the level of the second control node Q2, the signal of the third high-level signal input end VGH3, and the signal of the second low-level signal input end VGL2.

[0077] In this embodiment, the first input control module 211 includes a first switching element T1. The control terminal and input terminal of the first switching element T1 are both electrically connected to the frame inversion signal input terminal FHL, and the output terminal of the first switching element T1 is electrically connected to the first control node Q1. The first switching element T1 is a first transistor. One of the source and drain of the first transistor and the gate of the first transistor are electrically connected to the frame inversion signal input terminal FHL, and the other of the source and drain of the first transistor is electrically connected to the first control node Q1. When the frame inversion signal input terminal FHL transmits a high-level signal, the gate of the first transistor is in a high-level position, and the first transistor transmits a high-level signal to the first control node Q1, maintaining the first control node Q1 at a high potential.

[0078] The first output module 212 includes a second switch element T2 and a first capacitor C1. The control terminal of the second switch element T2 is electrically connected to the first control node Q1, the input terminal of the second switch element T2 is electrically connected to the stage transfer signal input terminal Gm1_IN, the output terminal of the second switch element T2 is electrically connected to the first output node K1, and the first output node K1 is electrically connected to the first start signal output terminal STV2. The first capacitor C1 is electrically connected to the first control node Q1 and the first output node K1. The second switch element T2 is a second transistor. When the first control node Q1 is at a high potential, the gate of the second transistor is at a high potential, the first capacitor C1 is charged, and the stage transfer signal input terminal Gm1_IN is electrically connected to the first start signal output terminal STV2.

[0079] In this embodiment, the first pull-down module 213 includes a third switch element T3 , a fourth switch element T4 , a fifth switch element T5 and a sixth switch element T6 .

[0080] The control terminal of the third switch element T3 is electrically connected to the frame inversion signal input terminal FHL, the input terminal of the third switch element T3 is electrically connected to the first low-level signal input terminal VGL1, and the output terminal of the third switch element T3 is connected to the fourth control node P1. The third switch element T3 is a third transistor, the gate of the third transistor is electrically connected to the frame inversion signal input terminal FHL, one of the source and drain of the third transistor is electrically connected to the fourth control node P1, and the other of the source and drain of the third transistor is electrically connected to the first low-level signal input terminal VGL1. The first low-level signal input terminal VGL1 is electrically connected to a first voltage source, which is configured to output a low-level signal.

[0081] The control terminal and input terminal of the fourth switch element T4 are both electrically connected to the first high-level signal input terminal VGH1, and the output terminal of the fourth switch element T4 is electrically connected to the fourth control node P1. The fourth switch element T4 is a fourth transistor. One of the source and drain of the fourth transistor and the gate of the fourth transistor are electrically connected to the first high-level signal input terminal VGH1, and the other of the source and drain of the fourth transistor is electrically connected to the fourth control node P1. The first high-level signal input terminal VGH1 is electrically connected to the second voltage source.

[0082] The control terminal of the fifth switch element T5 is electrically connected to the fourth control node P1, the input terminal of the fifth switch element T5 is electrically connected to the first low-level signal input terminal VGL1, and the output terminal of the fifth switch element T5 is connected to the first control node Q1. The fifth switch element T5 is a fifth transistor, the gate of the fifth transistor is electrically connected to the fourth control node P1, one of the source and drain of the fifth transistor is electrically connected to the first low-level signal input terminal VGL1, and the other of the source and drain of the fifth transistor is electrically connected to the first control node Q1.

[0083] The control terminal of the sixth switch element T6 is electrically connected to the fourth control node P1, the input terminal of the sixth switch element T6 is electrically connected to the first low-level signal input terminal VGL1, and the output terminal of the sixth switch element T6 is electrically connected to the first output node K1. The sixth switch element T6 is a sixth transistor, the gate of the sixth transistor is electrically connected to the fourth control node P1, one of the source and drain of the sixth transistor is electrically connected to the first low-level signal input terminal VGL1, and the other of the source and drain of the sixth transistor is electrically connected to the first output node K1.

[0084] When the frame inversion signal output terminal transmits a low-level signal, the potential of the fourth control node P1 increases, the fifth transistor and the sixth transistor are turned on, and after the fifth transistor is turned on, the potential of the first control node Q1 is pulled low, the second transistor is turned off, and the stage transfer signal input terminal Gm1_IN is disconnected from the first start signal output terminal STV2. After the sixth transistor is turned on, the potential of the first output node K1 is pulled low, and the first start signal output terminal STV2 outputs a low-level signal, so that the shift register electrically connected to the pixel row located in the first display area does not perform stage transfer, and the pixel row located in the first display area is not charged.

[0085] When the frame inversion signal input terminal FHL transmits a high-level signal, the source and drain of the third transistor are turned on, thereby pulling down the potential of the fourth control node P1, and the fifth transistor and the sixth transistor are in the off state, so that the levels of the first control node Q1 and the first output node K1 are not affected by the signal of the first low-level signal input terminal VGL1.

[0086] In this embodiment, the second input control module 221 includes a seventh switch element T7 and an eighth switch element T8.

[0087] The control terminal of the seventh switch element T7 is electrically connected to the frame inversion signal input terminal FHL, the input terminal of the seventh switch element T7 is electrically connected to the second low-level signal input terminal VGL2, and the output terminal of the seventh switch element T7 is connected to the second control node Q2. The seventh switch element T7 is a seventh transistor. The gate of the seventh transistor is electrically connected to the frame inversion signal input terminal FHL, one of the source and drain of the seventh transistor is electrically connected to the second low-level signal input terminal VGL2, and the other of the source and drain of the seventh transistor is electrically connected to the second control node Q2. The second low-level signal input terminal VGL2 is electrically connected to the first voltage source.

[0088] The control terminal and input terminal of the eighth switch element T8 are both connected to the second high-level signal input terminal VGH2, and the output terminal of the eighth switch element T8 is connected to the second control node Q2. The eighth switch element T8 is an eighth transistor. The gate and one of the source and drain of the eighth transistor are electrically connected to the second high-level signal input terminal VGH2, and the other of the source and drain of the eighth transistor is electrically connected to the second control node Q2.

[0089] When the frame inversion signal input terminal FHL transmits a high level signal, the seventh transistor is turned on, causing the level of the second control node Q2 to be pulled low. When the frame inversion signal input terminal FHL transmits a low level signal, the seventh transistor is turned off, and the second control node Q2 maintains a high potential.

[0090] In this embodiment, the third input control module 222 includes a ninth switch element T9. The control terminal and input terminal of the ninth switch element T9 are both electrically connected to the second control node Q2, and the output terminal of the ninth switch element T9 is electrically connected to the third control node Q3. Specifically, the ninth switch element T9 is a ninth transistor. The gate and one of the source and drain of the ninth transistor are electrically connected to the second control node Q2, and the other of the source and drain of the ninth transistor is electrically connected to the third control node Q3. When the second control node Q2 is at a high potential, the ninth transistor turns on, thereby raising the potential of the third control node Q3.

[0091] The second output module 223 includes a tenth switching element T10 and a second capacitor C2. The control terminal of the tenth switching element T10 is electrically connected to the third control node Q3, the input terminal of the tenth switching element T10 is electrically connected to the stage-transmitting signal input terminal Gm1_IN, and the output terminal of the tenth switching element T10 is electrically connected to the second output node K2. The second capacitor C2 is electrically connected to the third control node Q3 and the second output node K2. The tenth switching element T10 is a tenth transistor. The gate of the tenth transistor is electrically connected to the third control node Q3, one of the source and drain of the tenth transistor is electrically connected to the stage-transmitting signal input terminal Gm1_IN, and the other of the source and drain of the tenth transistor is electrically connected to the second output node K2. When the third control node Q3 is at a high voltage, the tenth transistor turns on, connecting the stage-transmitting signal input terminal Gm1_IN and the second start signal output terminal STV3.

[0092] The second pull-down module 224 includes an eleventh switching element T11 , a twelfth switching element T12 , a thirteenth switching element T13 , and a fourteenth switching element T14 .

[0093] The control terminal of the eleventh switching element T11 is electrically connected to the second control node Q2, the input terminal of the eleventh switching element T11 is electrically connected to the second low-level signal input terminal VGL2, and the output terminal of the eleventh switching element T11 is electrically connected to the fifth control node P2. The eleventh switching element T11 is an eleventh transistor, the gate of the eleventh transistor is electrically connected to the second control node Q2, one of the source and drain of the eleventh transistor is electrically connected to the second low-level signal input terminal VGL2, and the other of the source and drain of the eleventh transistor is electrically connected to the fifth control node P2.

[0094] The control terminal and the input terminal of the twelfth switch element T12 are electrically connected to the third high-level signal input terminal VGH3, and the output terminal of the twelfth switch element T12 is electrically connected to the fifth control node P2. The gate and one of the source and the drain of the twelfth switch element T12 are electrically connected to the third high-level signal input terminal VGH3, and the other of the source and the drain of the twelfth switch element T12 is electrically connected to the fifth control node P2.

[0095] The control terminal of the thirteenth switch element T13 is electrically connected to the fifth control node P2, the input terminal of the thirteenth switch element T13 is electrically connected to the second low-level signal input terminal VGL2, and the output terminal of the thirteenth switch element T13 is electrically connected to the third control node Q3. The thirteenth switch element T13 is a thirteenth transistor, the gate of the thirteenth transistor is electrically connected to the fifth control node P2, one of the source and drain of the thirteenth transistor is electrically connected to the second low-level signal input terminal VGL2, and the other of the source and drain of the thirteenth transistor is electrically connected to the third control node Q3.

[0096] The control terminal of the fourteenth switch element T14 is electrically connected to the fifth control node P2, the input terminal of the fourteenth switch element T14 is electrically connected to the second low-level signal input terminal VGL2, and the output terminal of the fourteenth switch element T14 is electrically connected to the second output node K2. The fourteenth switch element T14 is a fourteenth transistor, the gate of the fourteenth transistor is electrically connected to the fifth control node P2, one of the source and drain of the fourteenth transistor is electrically connected to the second low-level signal input terminal VGL2, and the other of the source and drain of the thirteenth transistor is electrically connected to the second output node K2.

[0097] The second low-level signal input terminal VGL2 is electrically connected to a first voltage source, and the second high-level signal input terminal VGH2 and the third high-level signal input terminal VGH3 are electrically connected to a second voltage source.

[0098] When the frame inversion signal input terminal FHL transmits a low level, the seventh transistor is turned off and the eighth transistor is turned on, causing the level of the second control node Q2 to be pulled high. The ninth transistor is turned on, causing the level of the third control node Q3 to be pulled high. The tenth transistor is turned on, connecting the stage transfer signal input terminal Gm1_IN to the second initial signal output terminal. The eleventh transistor is turned on, causing the level of the fifth control node P2 to be pulled low. The thirteenth and fourteenth transistors are turned off.

[0099] When the frame inversion signal input terminal FHL transmits a high level, the seventh transistor is turned on, so that the level of the second control node Q2 is pulled low, the ninth transistor is turned off, the tenth transistor is turned off, the level transfer signal input terminal Gm1_IN is disconnected from the second start signal output terminal STV3, the eleventh transistor is turned off, so that the potential of the fifth control node P2 is pulled high, the thirteenth transistor is turned on, so that the potential of the third control node Q3 is pulled low, the fourteenth transistor is turned on, so that the potential of the second output node K2 is pulled low, and the second start signal output terminal STV3 outputs a low-level signal, so that the shift register electrically connected to the pixel row located in the third display area does not perform level transfer, and the pixel row located in the third display area is not charged.

[0100] In this embodiment, the number of rows of pixels in the second display area 102 is greater than or equal to the number of rows of pixels in the first display area 101, and greater than or equal to the number of rows of pixels in the third display area 103. Because the refresh rates of the first display area 101 and the second display area 102 are different from the refresh rate of the second display area 102, the number of rows of pixels in the second display area 102 is greater than or equal to the number of rows of pixels in the first display area 101, and greater than or equal to the number of rows of pixels in the third display area 103. This ensures that the majority of pixels in the middle of two adjacent frames of the display panel have a higher refresh rate, thereby ensuring a high-resolution display panel with a high refresh rate and optimizing the display effect.

[0101] In this embodiment, since only pixels in two of the three display areas are charged during one frame, the number of pixel rows whose gates need to be opened during one frame is reduced, thereby enabling the display panel to be provided with more pixels and improving the high resolution of the display panel.

[0102] In this embodiment, the second display area 102 includes a first sub-display area 102 a and a second sub-display area 102 b . The first sub-display area 102 a is adjacent to the first display area 101 , and the second sub-display area 102 b is adjacent to the third display area 103 .

[0103] As shown in FIG6 and FIG7 , in the second embodiment of the present application, the second embodiment is similar to the first embodiment and can be combined with the first embodiment. The difference between the second embodiment and the first embodiment is that:

[0104] In this embodiment, the level transmission signal output terminal of the n-stage shift register electrically connected to the n-3th row of pixels is electrically connected to the n-1th stage shift register, and the level transmission signal output terminal of the n-2th stage shift register electrically connected to the n-2th row of pixels is electrically connected to the n-stage shift register. The n-3th stage shift register and the n-1th stage shift register are both located on one side of the display area, and the n-2th stage shift register and the n-stage shift register are both located on the other side of the display area, where n is a non-zero positive integer greater than 3.

[0105] In this embodiment, the selection control circuit 200 includes a first selection control circuit 200 and a second selection control circuit 200. The first selection control circuit 200 and the second selection control circuit 200 both include a frame inversion signal input terminal FHL, a stage transfer signal input terminal Gm1_IN, a first start signal output terminal STV2 and a second start signal output terminal STV3.

[0106] In this embodiment, the first display area 101 contains m1 rows of pixels, and the second display area 102 contains m2 rows of pixels, where m1 and m2 are both greater than or equal to n.

[0107] The level transfer signal input terminal Gm1_IN of the first selection control circuit 200 is electrically connected to the level transfer signal output terminal of the shift register unit electrically connected to the row of pixels above the last row in the second display area 102, that is, the level transfer signal input terminal Gm1_IN of the first selection control circuit 200 is electrically connected to the level transfer signal output terminal of the m1-1th stage shift register.

[0108] The first start signal output terminal STV2 of the first selection control circuit 200 is electrically connected to the input terminal of the shift register unit electrically connected to the first row of pixels located in the first display area 101, that is, the first start signal output terminal STV2 of the first selection control circuit 200 is electrically connected to the input terminal of the m1+1th level shift register, and the pixel row electrically connected to the M+1th level shift register is located in the first display area 101.

[0109] The second start signal output terminal STV3 of the first selection control circuit 200 is electrically connected to the input terminal of the shift register unit electrically connected to the first row of pixels located in the third display area 103, that is, the second start signal output terminal STV3 of the first selection control circuit 200 is electrically connected to the input terminal of the m1+m2+1th level shift register unit, and the pixel row electrically connected to the m1+m2+1th level shift register unit is located in the third display area 103.

[0110] The first selection control circuit 200 is configured to output a start signal through one of the first start signal output terminal STV2 of the first selection control circuit 200 and the second start signal output terminal STV3 of the first selection control circuit 200 according to the frame inversion signal transmitted from the frame inversion signal input terminal FHL of the first selection control circuit 200 during the Nth frame, and to output a start signal through the other of the first start signal output terminal STV2 of the first selection control circuit 200 and the second start signal output terminal STV3 of the first selection control circuit 200 according to the frame inversion signal input from the frame inversion signal input terminal FHL of the first selection control circuit 200 during the N+1th frame.

[0111] The level transfer signal input terminal Gm1_IN of the second selection control circuit 200 is electrically connected to the level transfer signal output terminal of the shift register unit electrically connected to the last row of pixels located in the second display area 102, that is, the level transfer signal input terminal Gm1_IN of the second selection control circuit 200 is electrically connected to the output terminal of the m1-th level shift register, wherein the pixel row electrically connected to the M-th level shift register is located in the second display area 102.

[0112] The first start signal output terminal STV2 of the second selection control circuit 200 is electrically connected to the input terminal of the shift register unit electrically connected to the second row of pixels located in the first display area 101, that is, the first start signal output terminal STV2 of the second selection control circuit 200 is electrically connected to the input terminal of the m1+2th level shift register unit, wherein the pixel row electrically connected to the m1+2th level shift register unit is located in the first display area 101.

[0113] The second start signal output terminal STV3 of the second selection control circuit 200 is electrically connected to the input terminal of the shift register unit electrically connected to the second row of pixels located in the third display area 103, that is, the second start signal output terminal STV3 of the second selection control circuit 200 is electrically connected to the m1+m2+2th level shift register unit, wherein the pixel row electrically connected to the m1+m2+2th level shift register unit is located in the third display area 103.

[0114] The second selection control circuit 200 is configured to output a start signal through one of the first start signal output terminal STV2 of the second selection control circuit 200 and the second start signal output terminal STV3 of the second selection control circuit 200 according to the frame inversion signal transmitted from the frame inversion signal input terminal FHL of the second selection control circuit 200 during the Nth frame, and to output a start signal through the other of the first start signal output terminal STV2 of the second selection control circuit 200 and the second start signal output terminal STV3 of the second selection control circuit 200 according to the frame inversion signal input from the frame inversion signal input terminal FHL of the second selection control circuit 200 during the N+1th frame.

[0115] The first selection control circuit 200 and the second selection control circuit 200 are respectively arranged on the left and right sides of the display area, wherein the shift register unit that controls the odd-numbered rows of pixels in the first display area 101 and the second display area 102 is activated by the first selection control circuit 200, and the shift register unit that controls the even-numbered rows of pixels in the first display area 101 and the second display area 102 is activated by the second selection control circuit 200, which is conducive to thinning the frame of the display panel.

[0116] Those skilled in the art will appreciate that modifications or equivalent substitutions may be made to the embodiments of the present application without departing from the spirit and scope of the present application, and such modifications or equivalent substitutions shall be encompassed within the scope of the present application. The various embodiments may be combined with each other but will not be described in detail here.

[0117] This document uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. At the same time, for technical personnel in this field, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. A display panel, wherein, Including: A first display area, a second display area, and a third display area, which are arranged in sequence along a first direction; The display panel further includes: Multiple rows of pixels arranged in sequence along the first direction; A gate driving circuit including multiple stages of shift register units, and the output end of one stage of the shift register unit is electrically connected to one row of the pixels; and A selection control circuit, the selection control circuit includes a frame inversion signal input end, a stage transmission signal input end, a first start signal output end, and a second start signal output end. The stage transmission signal input end is electrically connected to the stage transmission signal output end of the shift register unit electrically connected to the last row of pixels in the second display area. The first start signal output end is electrically connected to the input end of the shift register unit electrically connected to the first row of pixels in the first display area. The second start signal output end is electrically connected to the input end of the shift register unit electrically connected to the first row of pixels in the third display area. The selection control circuit is configured to select one of the first start signal output end and the second start signal output end to output a start signal according to the frame inversion signal transmitted by the frame inversion signal input end and the stage transmission signal transmitted by the stage transmission signal input end during the Nth frame, and select the other of the first start signal output end and the second start signal output end to output a start signal according to the frame inversion signal input by the frame inversion signal input end and the stage transmission signal transmitted by the stage transmission signal input end during the (N + 1)th frame, where N is a non-zero positive integer.

2. The display panel according to claim 1, wherein, The selection control circuit further includes: A first control unit, the control end of the first control unit is electrically connected to the frame inversion signal input end, the input end of the first control unit is electrically connected to the stage transmission signal input end, and the output end of the first control unit is electrically connected to the first start signal output end. The first control unit is configured to conduct the stage transmission signal input end and the first start signal output end when the frame inversion signal transmitted by the frame inversion signal input end is one of a high level and a low level, and disconnect the stage transmission signal input end and the first start signal output end when the frame inversion signal transmitted by the frame inversion signal input end is the other of a high level and a low level; A second control unit, the control end of the second control unit is electrically connected to the frame inversion signal input end, the input end of the second control unit is electrically connected to the stage transmission signal input end, and the output end of the second control unit is electrically connected to the second start signal output end. The second control unit is configured to conduct the stage transmission signal input end and the second start signal output end when the frame inversion signal input by the frame inversion signal input end is the other of a high level and a low level, and disconnect the stage transmission signal input end and the second start signal output end when the frame inversion signal input by the frame inversion signal input end is one of a high level and a low level.

3. The display panel according to claim 2, wherein, During the Nth frame, the frame inversion signal input terminal transmits one of a continuous high-level signal and a low-level signal, and during the (N + 1)th frame, the frame inversion signal input terminal transmits the other of the continuous high-level signal and the low-level signal.

4. The display panel according to claim 2, wherein, The first control unit includes: A first input control module, the input end of the first input control module is electrically connected to the frame inversion signal input terminal, the output end of the first input control module is electrically connected to a first control node, and the first input control module is configured to control the level of the first control node according to the signal of the frame inversion signal input terminal; A first output module, the input end of the first output module is electrically connected to the first control node and the stage transmission signal input terminal, the output end of the first output module is electrically connected to a first output node, the first output node is electrically connected to the first start signal output terminal, and the first output module is configured to control the on / off between the stage transmission signal input terminal and the first start signal output terminal according to the level of the first control node; A first pull-down module, the input end of the first pull-down module is electrically connected to the frame inversion signal input terminal, a first high-level signal input terminal, and a first low-level signal input terminal, the output end of the first pull-down module is electrically connected to the first output node and the first control node, and the first pull-down module is configured to pull down the levels of the first output node and the first control node according to the signal of the frame inversion signal input terminal, the signal of the first high-level signal input terminal, and the signal of the first low-level signal input terminal; The second control unit includes: A second input control module, the input end of the second input control module is electrically connected to the frame inversion signal input terminal, a second high-level signal input terminal, and a second low-level signal input terminal, the output end of the second input control module is electrically connected to a second control node, and the second input control module is configured to control the level of the second control node according to the signal of the frame inversion signal input terminal, the signal of the second high-level signal input terminal, and the signal of the second low-level signal input terminal; A third input control module, the input end of the third input control module is electrically connected to the second control node, the output end of the third input control module is electrically connected to a third control node, and the third input control module is configured to control the level of the third control node according to the level of the second control node; A second output module, the input end of the second output module is electrically connected to the third control node and the stage transmission signal input terminal, the output end of the second output module is electrically connected to a second output node, the second output node is electrically connected to the second start signal output terminal, and the second output module is configured to control the on / off between the stage transmission signal input terminal and the second start signal output terminal according to the level of the third control node; A second pull-down module, the input end of the second pull-down module is electrically connected to the second control node, the third high-level signal input end, and the second low-level signal input end, the output end of the second pull-down module is electrically connected to the third control node and the second output node, and the second pull-down module is configured to pull down the levels of the third control node and the second output node according to the level of the second control node, the signal of the third high-level signal input end, and the signal of the second low-level signal input end.

5. The display panel according to claim 4, wherein, The first input control module includes a first switching element, the control end and the input end of the first switching element are both electrically connected to the frame inversion signal input end, and the output end of the first switching element is electrically connected to the first control node; The first output module includes a second switching element and a first capacitor, the control end of the second switching element is electrically connected to the first control node, the input end of the second switching element is electrically connected to the stage transmission signal input end, the output end of the second switching element is electrically connected to the first output node, the first output node is electrically connected to the first start signal output end, and the first capacitor is electrically connected to the first control node and the first output node.

6. The display panel according to claim 4, wherein, The first pull-down module includes: A third switching element, the control end of the third switching element is electrically connected to the frame inversion signal input end, the input end of the third switching element is electrically connected to the first low-level signal input end, and the output end of the third switching element is connected to the fourth control node; A fourth switching element, the control end and the input end of the fourth switching element are both connected to the first high-level signal input end, and the output end of the fourth switching element is electrically connected to the fourth control node; A fifth switching element, the control end of the fifth switching element is electrically connected to the fourth control node, the input end of the fifth switching element is electrically connected to the first low-level signal input end, and the output end of the fifth switching element is connected to the first control node; A sixth switching element, the control end of the sixth switching element is electrically connected to the fourth control node, the input end of the sixth switching element is electrically connected to the first low-level signal input end, and the output end of the sixth switching element is electrically connected to the first output node.

7. The display panel according to claim 4, wherein, The second input control module includes: A seventh switching element, the control end of the seventh switching element is electrically connected to the frame inversion signal input end, the input end of the seventh switching element is electrically connected to the second low-level signal input end, and the output end of the seventh switching element is connected to the second control node; An eighth switching element, the control end and the input end of the eighth switching element are both connected to the second high-level signal input end, and the output end of the eighth switching element is connected to the second control node.

8. The display panel according to claim 4, wherein, The third input control module includes a ninth switching element, the control end and the input end of the ninth switching element are both electrically connected to the second control node, and the output end of the ninth switching element is electrically connected to the third control node; The second output module includes a tenth switching element and a second capacitor. The control terminal of the tenth switching element is electrically connected to the third control node. The input terminal of the tenth switching element is electrically connected to the stage transmission signal input terminal. The output terminal of the tenth switching element is electrically connected to the second output node. The second capacitor is electrically connected to the third control node and the second output node; The second pull-down module includes: an eleventh switching element, the control terminal of the eleventh switching element is electrically connected to the second control node, the input terminal of the eleventh switching element is electrically connected to the second low-level signal input terminal, and the output terminal of the eleventh switching element is electrically connected to the fifth control node; a twelfth switching element, the control terminal and the input terminal of the twelfth switching element are electrically connected to the third high-level signal input terminal, and the output terminal of the twelfth switching element is electrically connected to the fifth control node; a thirteenth switching element, the control terminal of the thirteenth switching element is electrically connected to the fifth control node, the input terminal of the thirteenth switching element is electrically connected to the second low-level signal input terminal, and the output terminal of the thirteenth switching element is electrically connected to the third control node; a fourteenth switching element, the control terminal of the fourteenth switching element is electrically connected to the fifth control node, the input terminal of the fourteenth switching element is electrically connected to the second low-level signal input terminal, and the output terminal of the fourteenth switching element is electrically connected to the second output node.

9. The display panel according to any one of claims 1 to 8, wherein, The selection control circuit includes a first selection control circuit and a second selection control circuit. Both the first selection control circuit and the second selection control circuit include a frame inversion signal input terminal, a stage transmission signal input terminal, a first start signal output terminal, and a second start signal output terminal; The stage transmission signal input terminal of the first selection control circuit is electrically connected to the stage transmission signal output terminal of the shift register unit of the pixel in the row immediately above the last row in the second display area. The first start signal output terminal of the first selection control circuit is electrically connected to the input terminal of the shift register unit of the pixel in the first row of the first display area. The second start signal output terminal of the first selection control circuit is electrically connected to the input terminal of the shift register unit of the pixel in the first row of the third display area; Therefore, the stage transmission signal input terminal of the second selection control circuit is electrically connected to the stage transmission signal output terminal of the shift register unit of the pixel in the last row of the second display area. The first start signal output terminal of the second selection control circuit is electrically connected to the input terminal of the shift register unit of the pixel in the second row of the first display area. The second start signal output terminal of the second selection control circuit is electrically connected to the input terminal of the shift register unit of the pixel in the second row of the third display area.

10. The display panel according to any one of claims 1 to 8, wherein, The number of rows of the pixels in the second display area is greater than or equal to the number of rows of the pixels in the first display area and greater than or equal to the number of rows of the pixels in the third display area.

11. The display panel according to claim 9, wherein, The stage transmission signal output terminal of the nth-stage shift register unit electrically connected to the pixel described in the (n - 3)th row is electrically connected to the (n - 1)th-stage shift register unit, and the stage transmission signal output terminal of the (n - 2)th-stage shift register unit electrically connected to the pixel described in the (n - 2)th row is electrically connected to the nth-stage shift register unit; where n is a non-zero positive integer greater than 3.

12. The display panel according to claim 11, wherein, Both the (n - 3)th-stage shift register unit and the (n - 1)th-stage shift register unit are located on one side of the display area, and both the (n - 2)th-stage shift register unit and the nth-stage shift register unit are located on the other side of the display area.

13. The display panel according to claim 11, wherein, The first display area contains m1 rows of the pixels, and the second display area contains m2 rows of pixels; where both m1 and m2 are greater than or equal to n.

14. The display panel according to claim 9, wherein, The first selection control circuit and the second selection control circuit are respectively arranged on the left and right sides of the display area.

15. The display panel according to claim 13, wherein, The shift register units controlling the odd rows of the pixels in the first display area and the second display area are started by the first selection control circuit; the shift register units controlling the even rows of the pixels in the first display area and the second display area are started by the second selection control circuit.

Images