Voltage detection circuit and electronic device

Abstract

Embodiments of the present application provide a voltage detection circuit and an electronic device. The voltage detection circuit comprises: a comparison module, configured to compare a voltage signal to be compared with a reference voltage signal, and output a low-level initial detection signal if the comparison result indicates that the voltage of the voltage signal to be compared is less than the voltage of the reference voltage signal, and output a high-level initial detection signal if the comparison result indicates that the voltage of the voltage signal to be compared is greater than the voltage of the reference voltage signal, wherein the voltage signal to be compared is obtained from a power supply voltage; and an adjustment module, configured to detect the reference voltage signal and the power supply voltage, and adjust a first detection signal to a zero potential in response to the detection result failing to satisfy a predetermined condition, wherein the first detection signal is obtained from the initial detection signal, and the predetermined condition is that: the voltage of the reference voltage signal is greater than a detection voltage of the reference voltage signal, the power supply voltage is greater than or equal to an operating voltage of the reference voltage signal, and the operating voltage is greater than the detection voltage.

Description

Voltage detection circuits and electronic devices

[0001] This patent application claims priority to Chinese patent application No. 202311845291X filed on December 28, 2023 and entitled “Voltage Detection Circuit and Electronic Device” and Chinese patent application No. 202311847368.7 filed on December 28, 2023 and entitled “Reference Voltage Detection Circuit and Electronic Device”, and the entire contents of the Chinese patent applications are hereby incorporated by reference.

Technical field

[0002] The present application relates to the field of electronic circuits, more specifically to the field of chip power supplies, and in particular to a voltage detection circuit and electronic equipment. [Background Technology]

[0003] During chip power-up (or power-down), the timing of each module's on / off must be precisely controlled. Furthermore, the voltage input to each module must ensure it operates properly, ensuring the proper functioning of the entire chip. This improves chip reliability and safety, thereby extending the chip's lifespan. Therefore, chips often incorporate a power-on reset (POR) and a brown-out reset (BOR) module.

[0004] The POR and BOR serve as the first and last barriers during chip power-up and power-down, respectively. Their accuracy determines the timing and sequence of powering on and off other modules within the chip. To ensure that each module within the chip operates at the appropriate voltage, the industry is increasingly demanding POR and BOR accuracy.

[0005] [Summary of the invention]

[0006] The purpose of the embodiments of the present application is to provide a voltage detection circuit and an electronic device for performing high-precision detection of the power supply voltage during chip power-on (or power-off) to provide POR and BOR functions.

[0007] A first aspect of an embodiment of the present application provides a voltage detection circuit, including:

[0008] a comparison module, configured to compare a voltage signal to be compared with a reference voltage signal, and output a low-level initial detection signal if the comparison result shows that the voltage of the voltage signal to be compared is less than the voltage of the reference voltage signal, and output a high-level initial detection signal if the comparison result shows that the voltage of the voltage signal to be compared is greater than the voltage of the reference voltage signal, wherein the voltage signal to be compared is derived from a power supply voltage;

[0009] An adjustment module is used to detect the reference voltage signal and the power supply voltage, and adjust the first detection signal to zero potential in response to the detection result not satisfying a predetermined condition; the first detection signal is obtained from the initial detection signal; the preset condition is: the voltage of the reference voltage signal is greater than the detection voltage of the reference voltage signal and the power supply voltage is greater than or equal to the operating voltage of the reference voltage signal, and the operating voltage is greater than the detection voltage.

[0010] A second aspect of the embodiments of the present application provides an electronic device, which includes the voltage detection circuit described in the first aspect.

[0011] In an embodiment of the present application, during the power-on process, the comparison module compares the voltage signal to be compared (obtained from the power supply voltage) with the reference voltage signal. When the voltage signal to be compared is less than the voltage of the reference voltage signal, the initial detection signal output by the comparison module is a low level "0". When the voltage signal to be compared is greater than the voltage of the reference voltage signal, the initial detection signal output by the comparison module is a low level "1". The adjustment module detects the reference voltage signal and the power supply voltage. When the detection result does not meet the predetermined conditions (the voltage of the reference voltage signal is greater than the detection voltage of the reference voltage signal and the power supply voltage is greater than or equal to the operating voltage of the reference voltage signal, and the operating voltage is greater than the detection voltage), the first detection signal (obtained from the initial detection signal) is always clamped to zero potential. When the detection result meets the predetermined conditions, the clamping of the first detection signal is stopped so that the first detection signal is output. In an embodiment of the present application, the regulation module detects the reference voltage signal and the power supply voltage, and releases the first detection signal obtained by the initial detection signal (output by the comparison module) when both the reference voltage signal and the power supply voltage meet the chip power supply requirements; and the comparison module will output a high-level initial detection signal only when the voltage of the voltage signal to be compared (obtained from the power supply voltage) is greater than the voltage of the reference voltage signal, thereby realizing high-precision detection of the power supply voltage during the chip power-on process to provide a POR function (please refer to the following for more specific description of the power-off process).

Brief Description of the Drawings

[0012] FIG1 is a schematic diagram of a voltage detection circuit provided in an embodiment of the present application;

[0013] FIG2 is a schematic diagram of a voltage detection circuit provided in an embodiment of the present application;

[0014] FIG3 is a schematic diagram of a voltage detection circuit provided in an embodiment of the present application;

[0015] FIG4 is a schematic diagram of a voltage detection circuit provided in an embodiment of the present application;

[0016] FIG5 is a schematic diagram of a voltage detection circuit provided in an embodiment of the present application;

[0017] FIG6 is a schematic diagram of a voltage detection circuit provided in an embodiment of the present application;

[0018] FIG7 is a schematic diagram of a voltage detection circuit provided in an embodiment of the present application;

[0019] FIG8 is a schematic diagram of a voltage detection circuit provided in an embodiment of the present application;

[0020] FIG9 is a schematic diagram of a voltage detection circuit provided in an embodiment of the present application;

[0021] FIG10 is a schematic diagram of a voltage detection circuit provided in an embodiment of the present application;

[0022] FIG11 is a schematic diagram of a voltage detection circuit provided in an embodiment of the present application;

[0023] FIG12 is a schematic diagram of a voltage detection circuit provided in an embodiment of the present application;

[0024] FIG13 is a schematic diagram of a power-on voltage timing sequence provided in an embodiment of the present application;

[0025] FIG14 is a schematic diagram of a voltage detection circuit provided in an embodiment of the present application;

[0026] FIG15 is a schematic diagram of a voltage detection circuit provided in an embodiment of the present application. [Specific implementation method]

[0027] The following will be combined with the accompanying drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of this application.

[0028] The terms "first", "second", etc. in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of the same type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0029] To ensure safe and reliable chip operation, power-on and power-off sequencing requires layered control, requiring corresponding modules to be enabled or disabled at the appropriate voltage and time. The power-on reset (POR) and brown-out reset (BOR) modules are widely used in power-on and power-off detection modules. As modules that are always on at power-on, low power consumption is a key requirement. As the first and last barriers to timing control, the accuracy of the POR and BOR determines the timing for enabling and disabling all other modules. To ensure that these modules operate at the optimal operating voltage, the accuracy requirements for POR and BOR are becoming increasingly stringent. As chip applications expand and the variety of power supply types increases, the power-on and power-off speeds required by chips are widening, ranging from 100V / ms to 10s. POR and BOR detection directly determine the chip's power-on and power-off sequencing. These two modules must function correctly under different power supply modes, ensuring no glitches or errors. This places higher demands on the reliability and robustness of the POR and BOR modules.

[0030] As chip applications expand, the number of chip power supply types is also increasing. Chips must support a wider range of power-on and power-off speeds, from 100V / ms to 10s. POR and BOR detection directly determine the chip's power-on and power-off timing. These two modules must function properly in different power supply modes, placing higher demands on the reliability and robustness of POR and BOR. POR and BOR are always on after the chip is powered on, so they generally need to meet low power consumption requirements to reduce chip heat generation.

[0031] An embodiment of the present application provides a voltage detection circuit for performing high-precision detection of the power supply voltage during chip power-on (or power-off) to provide POR and BOR functions.

[0032] As shown in Figures 1 and 2, both of which are schematic diagrams of the structure of a voltage detection circuit provided by an embodiment of the present application, as shown in Figure 1, a voltage detection circuit 10 includes: a comparison module 11 and a regulation module 12.

[0033] Among them, the comparison module 11 is used to compare the voltage of the voltage signal V1 to be compared determined by the power supply voltage VDD (exemplarily, V1 is the voltage at point h in Figure 1) with the voltage of the reference voltage signal LPBG (Low Power Bandgap, ultra-low power bandgap reference voltage), and output an initial detection signal V2 (exemplarily, V2 is the voltage at point d in Figure 1). When the voltage of V1 is less than the voltage of LPBG, the V2 output by the comparison module 11 is a low level "0"; when the voltage of V1 is greater than the voltage of LPBG, the V2 output by the comparison module 11 is a high level "1".

[0034] In addition, the regulating module 12 is used to detect whether LPBG and VDD meet the predetermined conditions. In response to the detection result that LPBG and VDD do not meet the preset conditions, the regulating module 12 adjusts the first detection signal PORB (obtained from V2) to zero potential. That is, when LPBG and VDD do not meet the predetermined conditions, regardless of whether V1 output by the comparison module 11 is "0" or "1", the voltage detection circuit 10 will not input the start signal (i.e., PORB of high level "1") to other modules in the chip; on the contrary, in response to the detection result that LPBG and VDD meet the preset conditions, the regulating module 12 When a condition is set, PORB is stopped from being adjusted to zero potential. That is, when LPBG and VDD meet the predetermined conditions, PORB output by the voltage detection circuit 10 follows V2 output by the comparison module. That is, when LPBG and VDD meet the predetermined conditions and V1 is greater than the voltage of LPBG, the voltage detection circuit 10 inputs a start signal "1" to other modules in the chip. When LPBG and VDD meet the predetermined conditions but V1 is less than the voltage of LPBG, the voltage detection circuit 10 inputs a shutdown signal "0" (i.e., PORB at a low level "0") to other modules in the chip. The predetermined condition is: the voltage of LPBG is greater than the detection voltage U of LPBG. 检 And VDD is greater than or equal to the operating voltage U of LPBG 工 , U 工 Greater than U 检 .

[0035] In the embodiment of the present application, during the power-on process, the regulation module 12 detects LPBG and VDD. When both LPBG and VDD meet the chip power supply requirements (i.e., the aforementioned preset conditions), the regulation module 12 releases the PORB obtained by V2 (output by the comparison module 11). The comparison module 11 will only output the initial detection signal V2 of a high level "1" when the voltage of V1 determined by VDD is greater than the voltage of LPBG, thereby achieving high-precision detection of VDD during the chip power-on process to provide a POR function. During power-off, if the adjustment module 12 detects that either LPBG or VDD does not meet the preset conditions, it adjusts V2 output by the comparison module 11 to zero potential, thereby also causing PORB to become zero potential. That is, the PORB obtained by other modules in the chip is a shutdown signal. Alternatively, if the adjustment module 12 detects that both LPBG and VDD meet the preset conditions but the voltage of V1 is lower than the voltage of LPBG, V2 output by the comparison module 11 is "0", that is, the PORB obtained by other modules in the chip is still a shutdown signal. This achieves high-precision detection of VDD during the chip power-off process, providing a BOR function.

[0036] When powering a chip, the power supply typically needs to output a precise voltage. To ensure this output, a precise reference point is required for the output voltage. This reference point is known as the reference voltage. Among commonly used reference voltage circuits, a bandgap reference is a common and precise reference source that can output a relatively stable reference voltage, also known as a bandgap reference voltage. Bandgap references, also known as energy gap references, are often used for high-precision voltage references due to their excellent temperature stability. The bandgap refers to the energy difference between the lowest point in the conduction band and the highest point in the valence band of a semiconductor or insulator. As a precise reference voltage, bandgap references are widely used in chips across various fields.

[0037] During the chip mode switching (for example, some automotive-grade H-bridge driver chips have three modes: power-on mode, operation mode, and stop mode. Among them, the power-on mode can be regarded as the standby mode when the chip is powered on. The chip enters when it is powered on, a fault is detected, or it is forced to shut down, so that the chip is in self-protection and basic standby state. In this mode, the motor drive function cannot be realized; when in operation mode, the user can truly realize the chip function, which means that under certain command and control conditions, the motor can be driven to run, feedback is collected, and diagnostic information is transmitted. It is the only operation mode; stop mode means that this mode can be entered when motor drive is not required, waiting for the next function to start.) or during power on and off, the reference voltage output by the bandgap reference source may not meet the standard. It is necessary to wait until the reference voltage reaches the operating voltage before inputting a signal indicating that the reference voltage has reached the operating voltage to other modules in the chip to control the start of other modules. This is conducive to improving the reliability and safety of chip startup to ensure the service life of the chip.

[0038] The regulating module 12 is used to determine whether the reference voltage LPBG meets the standard. In the embodiment of the present application, the regulating module 12 can not only be used to determine whether the LPBG meets the standard but also to simultaneously determine whether the power supply voltage VDD meets the standard.

[0039] [Corrected 22.11.2024 in accordance with Rule 91] Continuing with Figure 1 , in some optional implementations, comparison module 11 includes the comparator CMP shown in Figure 1 , with V1 input at its non-inverting input and LPBG input at its inverting input. Of course, in other embodiments, comparison module 11 can also be implemented using multiple comparators and is not limited to the specific implementation shown in Figure 1 . Those skilled in the art can flexibly configure the implementation as needed.

[0040] Continuing to refer to FIG. 1 , in some optional implementations, the regulating module 12 includes: a third switching device S1 and a switching sub-module 121 .

[0041] The first terminal of the third switch device S1 is connected to input voltage V2 (i.e., the voltage at point e in Figure 1). The second terminal of the third switch device S1 is coupled to ground, and the control terminal of the third switch device S1 is connected to input voltage V3 (i.e., the voltage at point c in the figure). The third switch device S1 turns on in response to V3 being high. Obviously, when the third switch device S1 is turned on, V2 is clamped to ground, reaching zero potential. When the third switch device S1 is turned off, V2 is not clamped, and V2 maintains its original value. PORB is always equal to V2. When V2 is clamped to ground, PORB reaches zero potential.

[0042] The first terminal of the switch submodule 121 is connected to the control terminal of the third switch device S1, and the second terminal of the switch submodule 121 is coupled to ground. The first control terminal of the switch submodule 121 is input to the LPBG, and the second control terminal of the switch submodule 121 is input to the fourth voltage signal V4 (i.e., the voltage at point g in FIG1 ). The first terminal of the switch submodule 121 is also input to the fifth voltage signal V5 (i.e., the voltage at point b in FIG1 ). The switch submodule 121 responds to the voltage of the LPBG being greater than the detection voltage U of the LPBG. 检 And VDD is greater than or equal to the operating voltage U of LPBG 工 , to clamp V3 to ground and turn off the third switch device S1, U 工 Greater than U 检 .

[0043] The fourth voltage signal V4 is obtained from VDD.

[0044] In some optional embodiments, as shown in FIG1 , the voltage detection circuit 10 further includes: a first resistor R1, a second resistor R2, and a third resistor R3. The first end of the first resistor R1 is used to input VDD, the second end of the first resistor R1 is connected to the first end of the second resistor R2, the second end of the second resistor R2 is connected to the first end of the third resistor R3, and the second end of the third resistor R3 is coupled to ground. Therefore, in this optional embodiment,

[0045] In some optional embodiments, as shown in FIG1 , the voltage detection circuit 10 further includes: a fourth resistor R5. The first end of the fourth resistor R5 is used to input VDD, and the second end of the fourth resistor R5 is connected to the first end of the switch submodule 121. Therefore, in this optional embodiment, when the switch submodule 121 is turned on, V5 = VDD-I R5 ×R5, where I R5 is the current flowing through the resistor R5; when the switch sub-module 121 is turned off, V5 = VDD.

[0046] It should be noted that the first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R5 are not limited to the form of a single resistor as shown in Figure 1. Obviously, they can all be a resistor group composed of multiple resistors connected in at least one of series and parallel modes.

[0047] It should also be noted that V1, V4, and V5 can also be determined by the power supply voltage VDD output by the power supply through other methods, and are not limited to the embodiment shown in Figure 1. For example, at least one of the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R5 can be replaced by other devices such as diodes, thereby changing the specific method of determining V1, V4, and V5 based on the power supply voltage VDD.

[0048] Continuing with Figure 1 , in this embodiment, the switch submodule 121 includes a fourth switch device N2 and a fifth switch device N1. A first terminal of the fourth switch device N2 is connected to the control terminal of the third switch device S1 and the second terminal of the fourth resistor R5 . A second terminal of the fourth switch device N2 is connected to the first terminal of the fifth switch device N1 . The first control terminal of the fourth switch device N2 is used to input LPBG . A first terminal of the fifth switch device N1 is connected to the second terminal of the fourth switch device N2 . A second terminal of the fifth switch device N1 is coupled to ground . The second control terminal of the fifth switch device N1 is used to input V4 . Exemplarily, the fourth switch device N2 is the NMOS transistor N2 in Figure 1 , and the fifth switch device N1 is the NMOS transistor N1 in Figure 1 . A first terminal (i.e., drain) of the NMOS transistor N2 is connected to a first terminal of the third switching device S1 and a second terminal of the fourth resistor R5. A first control terminal (i.e., gate) of the NMOS transistor N2 is used to input LPBG. A second terminal (i.e., source) of the NMOS transistor N2 is connected to a first terminal (i.e., drain) of the NMOS transistor N1. A second terminal (i.e., source) of the NMOS transistor N1 is coupled to ground. A second control terminal (i.e., gate) of the NMOS transistor N1 is used to input V4.

[0049] The fourth switching device N2 responds to the voltage of LPBG being greater than the U 检 The fifth switching device N1 is turned on in response to VDD being greater than or equal to U of LPBG. 工 While conducting, U 工 Greater than U 检 .

[0050] In some optional embodiments, as shown in FIG1 , the fourth switch device (eg, the NMOS transistor N2 in FIG1 ) responds to the voltage U BG Greater than LPBG's U 检 While conducting, the detection voltage U 检 That is, the on-state voltage of the fourth switch device (eg, the NMOS transistor N2 in FIG. 1 ) (eg, the threshold voltage U of the NMOS transistor N1 when it is on) N2 ); For example, taking the embodiment shown in FIG. 1 as an example, U 检 =U N1 The fifth switch device (eg, NMOS transistor N1 in FIG. 1 ) responds to VDD being greater than or equal to U of LPBG. 工作 The fifth switch device (eg, the NMOS transistor N1 in FIG. 1 ) is turned on in response to V4 being greater than or equal to the turn-on voltage of the fifth switch device (eg, the NMOS transistor N1 in FIG. 1 ) (ie, the threshold voltage U when the NMOS transistor N1 is turned on). N1 ) and conduction; illustratively, taking the embodiment shown in FIG. 1 as an example, that is, is greater than or equal to the threshold voltage U of the fifth switch device NMOS tube N1 N1 When the NMOS tube N1 is turned on, that is, the power supply voltage VDD is greater than or equal to When NMOS tube N2 is turned on; obviously, therefore Among them, the working voltage U 工 Greater than the detection voltage U 检 ; For example, taking the embodiment shown in FIG1 as an example,

[0051] The following describes the working principle of the voltage detection circuit shown in FIG1 by taking the chip power-on process as an example.

[0052] Please continue to refer to Figure 1 (and refer to the voltage timing diagram in Figure 13). When the power supply (not shown in Figure 1) and the bandgap reference source (not shown in Figure 1) are turned on, the power supply provides VDD, the bandgap reference source provides LPBG, point b is pulled high, making S1 conductive, point e is fixedly pulled to ground, and the PORB output is fixed to 0; VDD continues to rise, and the LPBG startup circuit injects a current. Since LPBG is ultra-low power, the loop bandwidth will be very small. LPBG will first rush to VDD and then slowly drop to the normal output voltage. At this time, the N2 tube is turned on; when VDD rises to the appropriate voltage (this voltage is the operating voltage U for the normal operation of LPBG), the LPBG will start to work normally. 工 ), that is, when the voltage at point g exceeds the threshold voltage of N1, N1 also turns on, pulling point b to ground, turning point c low, and turning off S1. At this point, the voltage at point e follows the voltage V2 output by the CMP. When V1 exceeds the voltage of LPBG, the CMP output V2 becomes 1, signaling to the backend that VDD has reached the required level and can support chip operation. The principles of power-down are similar and will be readily understood by those skilled in the art, so I will not elaborate on them here.

[0053] In an embodiment of the present application, the reference voltage and power supply voltage are detected by the conduction condition of the switch module. During the power-on process, if the reference voltage signal does not meet the standard, the switch module is turned off, and the first voltage signal determined by the power supply voltage is inverted to 0 by the inversion module. That is, the output detection signal is 0, which indicates that the reference voltage signal does not meet the standard. When the reference voltage signal meets the standard and the power supply voltage reaches the minimum operating voltage of the reference voltage signal, the switch module is turned on, clamping the first voltage signal to ground, that is, the input voltage signal obtained by the inversion module becomes 0, and the output detection signal after inversion is 1, which indicates that the reference voltage signal meets the standard and the power supply voltage reaches the minimum operating voltage of the reference voltage signal. Compared with the same-source detection in the related art, in the embodiment of the present application, the fixed conduction condition of the switch module is used as a reference for the reference voltage signal. It is not affected by the reference voltage signal itself. Only when the reference voltage signal and the power supply voltage meet the conduction conditions of the corresponding switch module will the signal indicating that the reference voltage has reached the operating voltage be output, which is more reliable.

[0054] It should be noted that the signal "0" or "1" mentioned in this application does not mean that its actual voltage value is 0 or 1V, but rather indicates whether the level or potential corresponding to the signal "0" or "1" reaches the expected value.

[0055] The main difference between the voltage detection circuit 20 shown in FIG2 and the voltage detection circuit 10 shown in FIG1 lies in the switch submodule 121. In the voltage detection circuit shown in FIG2 , the switch submodule 121 also includes a fourth switch device N2 and a fifth switch device N1. However, the first terminal of the fourth switch device N2 is connected to the control terminal of the third switch device S1, the second terminal of the fourth switch device N2 is connected to the first terminal of the fifth switch device N1, and the first control terminal of the fourth switch device N2 is used to input V4. The first terminal of the fifth switch device N1 is connected to the second terminal of the fourth switch device N2, the second terminal of the fifth switch device N1 is coupled to ground, and the second control terminal of the fifth switch device N1 is used to input LPBG. The fourth switch device N2 turns on in response to VDD being greater than or equal to the operating voltage of the LPBG, and the fifth switch device N1 turns on in response to the voltage of the LPBG being greater than the detection voltage of the LPBG.

[0056] Comparing the voltage detection circuit 10 shown in FIG1 and the voltage detection circuit 20 shown in FIG2, the fourth switch device N2 and the fifth switch device N1 in the switch submodule 121 have a bias effect, resulting in a threshold voltage U N2 is always greater than the threshold voltage U of the fifth switching device N1 N1Therefore, the threshold voltage of the fourth switch device N2 in the voltage detection circuit 10 shown in FIG1 when it is turned on is always greater than the threshold voltage of the fourth switch device N2 in the voltage detection circuit 20 shown in FIG2 when it is turned on. In other words, the LPBG shown in FIG1 needs to reach a higher voltage to enable the switch submodule 121 to be turned on, compared to the LPBG shown in FIG2. In other words, the voltage detection circuit 10 shown in FIG1 is suitable for scenarios where the LPBG operating voltage is higher, while the voltage detection circuit 20 shown in FIG2 is suitable for scenarios where the LPBG operating voltage is lower.

[0057] As shown in Figures 3 and 4, Figures 3 and 4 are both structural schematic diagrams of a voltage detection circuit provided in an embodiment of the present application. Referring to Figure 3 (or Figure 4), the voltage detection circuit 30 (or voltage detection circuit 40) also includes: a first inverting module 13. The first inverting module 13 is used to invert the initial detection signal N times to obtain a first detection signal, N is an even number and N≥2; wherein, in response to the detection result not meeting the preset condition, the adjustment module 12 clamps the signal obtained after n inversions in the first inverting module 13 to the ground, so as to adjust the first detection signal output by the first inverting module 13 to zero potential, n is an even number, and N≥n≥0.

[0058] In some optional embodiments, the first inverter module 13 includes: an even number of first inverters. For example, the inverters INVR inverter1-INVR inverter 6 shown in Figure 3 (or Figure 4). These even number of first inverters are connected in series to form a first inverter chain, and the voltage signal input terminal of the first inverter at the head of the first inverter chain is used to input the initial detection signal (i.e., the voltage at point d in the figure), and the voltage signal output terminal of the inverter at the tail of the first inverter chain is used to output the first detection signal PORB; wherein, in response to the detection result not meeting the preset condition, the regulation module 12 clamps the signal output by the nth inverter from the head to the tail of the first inverter chain to ground.

[0059] The driving capability of the entire voltage detection circuit can be increased by multiple inversions of multiple inverters.

[0060] In some optional embodiments, at least one of the even-numbered first inverters is a Schmitt trigger. For example, INVR inverter 1 in the figure is a Schmitt trigger. A Schmitt trigger can filter out glitches in a signal.

[0061] As shown in Figures 5 and 6, each of which is a schematic diagram of the structure of a voltage detection circuit provided in an embodiment of the present application. Referring to Figure 5 (or Figure 6), the voltage detection circuit 50 (or voltage detection circuit 60) also includes a filtering module 14. Filtering module 14 is configured to filter the signal obtained after at least one inversion in the first inversion module 13.

[0062] In some optional implementations, the filtering module 14 is an RC filter.

[0063] The filtering module 14 can further filter out burrs in the signal.

[0064] As shown in Figures 7 and 8, Figures 7 and 8 are both structural schematic diagrams of a voltage detection circuit provided in an embodiment of the present application. Referring to Figure 7 (or Figure 8), the voltage detection circuit 70 (or voltage detection circuit 80) also includes: a transformer module 15. The transformer module 15 is used to convert the power supply voltage VDD into a first voltage signal or a second voltage signal for output, the voltage of the first voltage signal is always less than the voltage of the second voltage signal, and the voltage of the first voltage signal is always less than the power supply voltage; wherein, the transformer module 15 selects one of the first voltage signal and the second voltage signal according to the state of at least one of the first signal and the second signal, and inputs it into the comparison module 11, so that the comparison module 11 obtains the voltage signal to be compared; the first signal is the signal obtained after n inversions in the first inversion module 13, and the second signal is the signal obtained after m inversions in the first inversion module 13, m is an odd number, and N>m>0.

[0065] In some optional embodiments, the voltage transformation module 15 includes: a first resistor R1, a second resistor R2, a third resistor R3, a first switch device S2, and a second switch device S3.

[0066] In which, the first end of the first resistor R1 is used to input VDD; the first end of the second resistor R2 is connected to the second end of the first resistor R1; the first end of the third resistor R3 is connected to the second end of the second resistor R2, and the second end of the third resistor R3 is coupled to the ground; the first end of the first switch device S2 is connected to the first end of the second resistor R2, the second end of the first switch device S2 is connected to the first end of the comparison module 11, and the control end of the first switch device S2 is used to input the initial detection signal, the first detection signal or the first signal; the first end of the second switch device S3 is connected to the second end of the second resistor R2, the second end of the second switch device S3 is connected to the first end of the comparison module 11, and the control end of the second switch device S3 is used to input the second signal; wherein, the first switch device S2 is turned on in response to the signal input to the control end being a high potential, and the second switch device S3 is turned on in response to the signal input to the control end being a high potential.

[0067] Please continue to refer to Figure 1 (and refer to the voltage timing diagram in Figure 13). When the power supply (not shown in Figure 1) and the bandgap reference source (not shown in Figure 1) are turned on, the power supply provides VDD, the bandgap reference source provides LPBG, point b is pulled high, making S1 conductive, point e is fixedly pulled to ground, and the PORB output is fixed to 0; VDD continues to rise, and the LPBG startup circuit injects a current. Since LPBG is ultra-low power, the loop bandwidth will be very small. LPBG will first rush to VDD and then slowly drop to the normal output voltage. At this time, the N2 tube is turned on; when VDD rises to the appropriate voltage (this voltage is the operating voltage U for the normal operation of LPBG), the LPBG will start to work normally. 工 ), that is, when the voltage at point g is greater than the threshold voltage of N1, N1 also opens, pulling point b to ground, point c is low, S1 is cut off, and the voltage at point e follows V2 output by CMP. Point f is high at this time, S3 is on, S2 is cut off, and point h is a lower resistor divider point. When VDD continues to rise and point h is greater than the LPBG voltage, CMP outputs V2, point d is pulled high, and a Schmitt trigger is added to the back stage of CMP to avoid small glitches in the CMP output or glitches in PORB caused by the slew rate of CMP being too slow. At the same time, RC filtering is added to enhance robustness. At this time, PORB is pulled high, S2 is on, S3 is cut off, and point h is a higher resistor divider. By using output feedback and proportional resistors, different detection voltages for POR and BOR can be achieved, that is, precise hysteresis is generated. Robustness is increased to ensure that the POR voltage is higher and the BOR voltage is lower. The principle of power-off is similar, and those skilled in the art can refer to it for understanding, so it will not be repeated here.

[0068] As shown in Figures 9 and 10, Figures 9 and 10 are both structural schematic diagrams of a voltage detection circuit provided in an embodiment of the present application. Referring to Figure 9 (or Figure 10), the regulation module 12 in the voltage detection circuit 90 (or voltage detection circuit 100) shown in Figure 9 (or Figure 10) also includes: a second inverting module 16. The first end of the second inverting module 16 is used to input a third voltage signal and is connected to the first end of the switch submodule 121, and the second end of the second inverting module 16 is connected to the control end of the third switch device S1. The second inverting module 16 is used to invert the third voltage signal an even number of times. The driving capability of the regulation module 12 can be increased by multiple inversions of multiple inverters.

[0069] As shown in Figures 11 and 12, both of which are schematic diagrams of the structure of a voltage detection circuit provided in an embodiment of the present application. Referring to Figure 11 (or Figure 12), the regulation module 12 in the voltage detection circuit 110 (or voltage detection circuit 120) shown in Figure 11 (or Figure 12) further includes a capacitor C, a first end of which is used to input VDD, and a second end of which is connected to the first end of the third switch device S1.

[0070] When power is on, due to the presence of the capacitor, point b is pulled high and point c is pulled high. The response speed of the adjustment module 12 is increased to ensure that no false triggering occurs during fast power-on.

[0071] An embodiment of the present application further provides a structural diagram of a voltage detection circuit, as shown in FIG14 and FIG15 . FIG14 and FIG15 are both structural diagrams of a voltage detection circuit provided in an embodiment of the present application.

[0072] Comparing the voltage detection circuit 140 shown in FIG14 with the detection circuit 110 shown in FIG11 , it can be seen that the main difference in the embodiment shown in FIG14 lies in the second inverting module 16, that is, any odd number of inverters (for example, one inverter INVR inverter 8) in the second inverting module 16 of the detection circuit 110 is replaced by an odd number of inverters (i.e., inverters INVR inverter 9-INVR inverter 10) in the second inverting module 16 in the detection circuit 140, and a delay module is also included in the second inverting module 16 in the detection circuit 140. Multiple inversions of multiple inverters can increase the driving capability of the regulation module 12.

[0073] In some optional embodiments, the second inverter module 16 includes an even number of inverters. For example, as shown in FIG14 , the second inverter module 16 includes four inverters: INVR inverter 7, INVR inverter 9, INVR inverter 10, and INVR inverter 11; of course, it can also be 6 or 8. These even number of inverters are connected in series to form an inverter chain, and the voltage signal input end of the inverter at the head of the inverter chain (for example, INVR inverter 1 in FIG1 ) is the first end of the second inverter module 16, and the voltage signal output end of the inverter at the tail of the inverter chain (for example, INVR inverter 3 in FIG1 ) is the second end of the second inverter module 16.

[0074] In some optional embodiments, the second inverting module 16 further includes a delay module. The delay module is connected in series in the inverter chain constituting the inverting module. Referring to FIG14 , the delay module is connected in series between the INVR inverter 10 and the INVR inverter 11. The delay module is used to filter glitches, and the delay of the delay module can provide sufficient time for the reference voltage signal BG to continue to rise until it reaches an acceptable range; the delay is smaller on the rising edge and larger on the falling edge. The smaller rise allows BG to be established in a better range, while the larger fall can filter glitches.

[0075] The delay module can be implemented in various ways, such as an inverter chain, an RC filter, etc. Those skilled in the art can flexibly choose according to actual needs, and is not specifically limited in the embodiments of the present application.

[0076] The third switch device S1, switch submodule 121 and capacitor C2 in the voltage detection circuit 140 and the detection circuit 110 shown in Figure 11 are the same, so the switch submodule 121 in the voltage detection circuit 140 is not repeated here. For details, please refer to the relevant description in the previous text.

[0077] The reference voltage LPBG and the power supply voltage VDD are detected by the conduction condition of the switch submodule 121. During the power-up process, if the reference voltage signal LPBG does not meet the standard, the switch submodule 121 is turned off, and the fifth voltage signal V5 determined by the power supply voltage VDD is inverted to 1 by the second inversion module 16. That is, the signal at point c is 1, indicating that the reference voltage signal LPBG does not meet the standard. When the reference voltage signal LPBG meets the standard and the power supply voltage VDD reaches the minimum operating voltage of the reference voltage signal LPBG, the switch submodule 121 clamps the fifth voltage signal V5 to ground, causing the input voltage signal received by the second inversion module 16 to become 0. The detection signal output after inversion is 1, indicating that the reference voltage signal LPBG meets the standard and the power supply voltage VDD reaches the minimum operating voltage of the reference voltage signal LPBG.

[0078] The main difference between the voltage detection circuit 149 shown in FIG14 and the voltage detection circuit 150 shown in FIG15 lies in the switch submodule 121. The switch submodule 121 in the voltage detection circuit 150 shown in FIG15 has already been described in the detection circuit 20 shown in FIG2 , and therefore will not be repeated here. Please refer to the relevant description above.

[0079] The switching devices in the embodiments of the present application, such as the first switching device and the second switching device, are all transistors, such as triodes, thyristors, MOS tubes, TFT tubes, etc. Those skilled in the art can flexibly choose according to actual needs, and no specific limitation is made in this application.

[0080] An embodiment of the present application further provides an electronic device, comprising at least one of the reference voltage detection circuits shown in the aforementioned Figures 1 to 12 .

[0081] In the embodiments provided in the embodiments of the present application, it should be understood that the disclosed reference voltage detection circuit can be implemented in other ways. For example, the reference voltage detection circuit implementation described above is only schematic. For example, the division of the modules or units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the reference voltage detection circuit or unit can be electrical, mechanical or other forms.

[0082] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of this embodiment.

[0083] In addition, each functional unit in each implementation of the embodiment of the present application may be integrated into a processing unit, each unit may exist physically separately, or two or more units may be integrated into a single unit. The above-mentioned integrated units may be implemented in the form of hardware or software functional units.

[0084] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor (processor) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0085] The above description is only an implementation method of the embodiment of the present application, and does not limit the patent scope of the embodiment of the present application. The above specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can make equivalent structural or equivalent process changes using the description and drawings of the embodiment of the present application, or directly or indirectly apply them in other related technical fields. Without departing from the scope of protection of the purpose of this application and the claims, many forms can be made, which are also included in the patent protection scope of the embodiment of the present application.

Claims

1. A voltage detection circuit, wherein, Comprising: A comparison module for comparing a voltage signal to be compared with a reference voltage signal, outputting an initial detection signal with a low level when the comparison result is that the voltage of the voltage signal to be compared is less than the voltage of the reference voltage signal, and outputting an initial detection signal with a high level when the comparison result is that the voltage of the voltage signal to be compared is greater than the voltage of the reference voltage signal, wherein the voltage signal to be compared is obtained from a power supply voltage; An adjustment module for detecting the reference voltage signal and the power supply voltage, and adjusting the first detection signal to zero potential in response to the detection result not meeting a predetermined condition; The first detection signal is obtained from the initial detection signal; The preset condition is that the voltage of the reference voltage signal is greater than the detection voltage of the reference voltage signal and the power supply voltage is greater than or equal to the operating voltage of the reference voltage signal, and the operating voltage is greater than the detection voltage.

2. The voltage detection circuit according to claim 1, wherein, Further comprising: A first inverting module for inverting the initial detection signal N times to obtain the first detection signal, where N is an even number and N≥2; Wherein, the adjustment module clamps the signal obtained after being inverted n times in the first inverting module to ground in response to the detection result not meeting the preset condition, so as to adjust the first detection signal output by the first inverting module to zero potential, n is an even number, and N≥n≥0.

3. The voltage detection circuit according to claim 2, wherein, The first inverting module includes: An even number of first inverters, which are sequentially connected in series to form a first inverter chain. The voltage signal input terminal of the first inverter at the head of the first inverter chain is used to input the initial detection signal, and the voltage signal output terminal of the inverter at the tail of the first inverter chain is used to output the first detection signal; Wherein, the adjustment module clamps the signal output by the nth inverter counted from the head to the tail in the first inverter chain to ground in response to the detection result not meeting the preset condition.

4. The voltage detection circuit according to claim 3, wherein, At least one of the even number of first inverters is a Schmitt trigger.

5. The voltage detection circuit according to claim 2, wherein, Further comprising: A filtering module for filtering the signal obtained after being inverted at least once in the first inverting module.

6. The voltage detection circuit according to claim 5, wherein, The filtering module is an RC filter.

7. The voltage detection circuit according to claim 2, wherein, Further comprising: A voltage transformation module for transforming the power supply voltage into a first voltage signal or a second voltage signal for output, wherein the voltage of the first voltage signal is always less than the voltage of the second voltage signal, and the voltage of the first voltage signal is always less than the power supply voltage; Wherein, the voltage transformation module selects one of the first voltage signal and the second voltage signal to input to the comparison module according to the state of at least one of the first signal and the second signal, so that the comparison module obtains the voltage signal to be compared; the first signal is the signal obtained after being inverted n times in the first inverting module, and the second signal is the signal obtained after being inverted m times in the first inverting module, m is an odd number, and N>m>0.

8. The voltage detection circuit according to claim 7, wherein, The voltage transformation module includes: A first resistor, whose first end is used to input the power supply voltage; A second resistor, whose first end is connected to the second end of the first resistor; A third resistor, having a first end connected to the second end of the second resistor and a second end coupled to ground; A first switching device, having a first end connected to the first end of the second resistor, a second end connected to the first end of the comparison module, and a control end for inputting the initial detection signal, the first detection signal, or the first signal; A second switching device, having a first end connected to the second end of the second resistor, a second end connected to the first end of the comparison module, and a control end for inputting the second signal; Wherein, the first switching device is turned on in response to a high potential signal input at the control end, and the second switching device is turned on in response to a high potential signal input at the control end.

9. The voltage detection circuit according to claim 2, wherein, The adjustment module includes: A third switching device, having a first end for inputting the initial detection signal, the first detection signal, or the first signal, a second end coupled to ground, and a control end for inputting a third voltage signal obtained from the power supply voltage; the third switching device is turned on in response to a high potential signal input at the control end; the first signal is the signal obtained after n inversions in the first inverting module; A switch sub-module, having a first end connected to the control end of the third switching device, a second end coupled to ground, a first control end for inputting the reference voltage signal, and a second control end for inputting a fourth voltage signal obtained from the power supply voltage; Wherein, the switch sub-module is turned on in response to the voltage of the reference voltage signal being greater than the detection voltage of the reference voltage signal and the power supply voltage being greater than or equal to the operating voltage of the reference voltage signal, so as to clamp the third voltage signal to ground and turn off the third switching device, and the operating voltage is greater than the detection voltage.

10. The voltage detection circuit according to claim 9, wherein, The switch sub-module includes: A fourth switching device, having a first end connected to the control end of the third switching device and a first control end for inputting the reference voltage signal; A fifth switching device, having a first end connected to the second end of the fourth switching device, a second end coupled to ground, and a second control end for inputting the fourth voltage signal; Wherein, the fourth switching device is turned on in response to the voltage of the reference voltage signal being greater than the detection voltage of the reference voltage signal, and the fifth switching device is turned on in response to the power supply voltage being greater than or equal to the operating voltage of the reference voltage signal.

11. The voltage detection circuit according to claim 9, wherein, The switch sub-module includes: A fourth switching device, having a first end connected to the control end of the third switching device and a first control end for inputting the fourth voltage signal; A fifth switching device, having a first end connected to the second end of the fourth switching device, a second end coupled to ground, and a second control end for inputting the reference voltage signal; Wherein, the fourth switching device is turned on in response to the power supply voltage being greater than or equal to the operating voltage of the reference voltage signal, and the fifth switching device is turned on in response to the voltage of the reference voltage signal being greater than the detection voltage of the reference voltage signal.

12. The voltage detection circuit according to claim 9, wherein, The adjustment module further includes: A second inverting module, whose first end is used to input the third voltage signal and is connected to the first end of the switching sub-module, whose second end is connected to the control end of the third switching device, and which is used to invert the third voltage signal an even number of times.

13. The voltage detection circuit according to claim 12, wherein, wherein, The second inverting module includes: An even number of inverters, which are sequentially connected in series to form an inverter chain. The voltage signal input end of the inverter at the head of the inverter chain is the first end of the second inverting module, and the voltage signal output end of the inverter at the tail of the inverter chain is the second end of the second inverting module.

14. The voltage detection circuit according to claim 13, wherein, At least one of the even number of inverters is a Schmitt trigger.

15. The voltage detection circuit according to claim 13 or 14, wherein The adjustment module further includes: A delay module, which is connected in series in the inverter chain.

16. The voltage detection circuit according to claim 9, wherein, The adjustment module further includes: A capacitor, whose first end is used to input the power supply voltage, and whose second end is connected to the first end of the third switching device.

17. An electronic device, wherein, It includes the voltage detection circuit according to any one of claims 1 to 16.

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