Imaging device

Abstract

This imaging device comprises a photoelectric conversion unit that converts light into electric charges, a semiconductor substrate that includes a first impurity region and a second impurity region, and a first plug that is connected to the first impurity region and includes a silicide region, one of the first impurity region and the second impurity region being a charge accumulation region electrically connected to the photoelectric conversion unit, and the semiconductor substrate including, at a position facing the silicide region with the first impurity region interposed therebetween, a third impurity region that contains a group 14 element other than silicon.

Description

Imaging device

[0001] The present disclosure relates to an imaging device.

[0002] Charge-coupled device (CCD) image sensors and complementary metal oxide semiconductor (CMOS) image sensors are widely used in digital cameras, etc. These image sensors have, for example, a photodiode formed on a semiconductor substrate or a photoelectric conversion layer formed above the semiconductor substrate.

[0003] For example, Patent Document 1 discloses a solid-state imaging device including a photoelectric conversion unit formed on a semiconductor substrate, a transistor formed on the semiconductor substrate, and a gettering region in the semiconductor substrate, and further discloses that the source and drain of the transistor formed on the semiconductor substrate contain silicide.

[0004] JP 2019-102494 A International Publication No. 2012 / 147302 International Publication No. 2020 / 189169

[0005] In imaging devices, it is necessary to reduce leakage current in a semiconductor substrate in order to reduce noise.

[0006] Therefore, the present disclosure provides an imaging device that can reduce leakage current.

[0007] An imaging device according to one aspect of the present disclosure includes a photoelectric conversion unit that converts light into electric charges, a semiconductor substrate including a first impurity region and a second impurity region, and a first plug connected to the first impurity region and including a silicide region, wherein one of the first impurity region and the second impurity region is a charge accumulation region electrically connected to the photoelectric conversion unit, and the semiconductor substrate includes a third impurity region containing a Group 14 element other than silicon at a position facing the silicide region with the first impurity region interposed therebetween.

[0008] An imaging device according to one aspect of the present disclosure includes a semiconductor substrate including a photoelectric conversion unit that converts light into electric charges, a first impurity region electrically connected to the photoelectric conversion unit, and a second impurity region that is located at a position different from the first impurity region in a planar view and includes a silicide region, and a plug connected to the silicide region of the second impurity region, wherein the semiconductor substrate includes a third impurity region that contains a Group 14 element other than silicon at a position facing the plug with the second impurity region interposed therebetween, the second impurity region and the third impurity region being spaced apart, and the distance between the silicide region and the third impurity region being shorter than the distance between the silicide region and the first impurity region.

[0009] According to the present disclosure, an imaging device capable of reducing leakage current can be provided.

[0010] FIG. 1 is a diagram showing a configuration of an imaging device according to a first embodiment. FIG. 2 is a diagram showing a circuit configuration of the imaging device according to the first embodiment. FIG. 3 is a plan view showing a layout within a pixel according to the first embodiment. FIG. 4 is a schematic cross-sectional view of a device structure of a pixel according to the first embodiment. FIG. 5A is a diagram showing a distribution of nickel concentration in a contact plug and a contact plug. FIG. 5B is a diagram showing a distribution of impurity concentration near a gettering layer in a semiconductor substrate. FIG. 6 is a diagram showing a relationship between a concentration ratio of nickel to carbon and dark current. FIG. 7 is a diagram showing a relationship between a concentration ratio of nickel to oxygen and dark current. FIG. 8 is a schematic cross-sectional view of a device structure of an imaging device according to a modification of the first embodiment. FIG. 9 is a schematic cross-sectional view showing a device structure of a pixel of an imaging device according to a second embodiment. FIG. 10 is a schematic cross-sectional view showing a device structure of an imaging device according to a third embodiment. FIG. 11 is a schematic cross-sectional view showing a device structure of an imaging device according to a fourth embodiment. FIG. 12 is a diagram showing a configuration of an imaging device according to a fifth embodiment. FIG. 13 is a schematic cross-sectional view showing a device structure of an imaging device according to the fifth embodiment. FIG. 14 is a plan view of a silicide region in a substrate potential supply region. FIG. 15 is a block diagram showing an example of the configuration of a camera system according to the fifth embodiment.

[0011] (Foundation of the Present Disclosure) Before describing the embodiments of the present disclosure in detail, the foundation of the present inventors that forms the basis of the present disclosure will be described.

[0012] A technique for forming a silicide region at a contact point between a metal and a semiconductor is known to reduce contact resistance. In an imaging device, for example, forming a silicide region at the electrical connection portion of a transistor for driving the device is effective in improving the driving capability of the transistor. However, when a silicide region is formed, the metal used to form the silicide region diffuses into the semiconductor substrate as metal impurities, making it more likely that a leakage current will occur at the pn junction in the semiconductor substrate. For example, in an imaging device, the leakage current at the pn junction in an impurity region that functions as a charge storage region in the semiconductor substrate becomes a dark current that flows even in the dark, leading to increased noise. In this specification, unless otherwise specified, the leakage current in a semiconductor substrate refers to the leakage current at the pn junction in the semiconductor substrate.

[0013] The present inventors have noted that forming a gettering layer containing impurity elements within a semiconductor substrate is effective in reducing metal impurities when a silicide region is formed. A gettering layer is an impurity region formed within a semiconductor substrate for gettering metal impurities. The present inventors have also found that the diffusion of impurity elements in the gettering layer for gettering metal impurities can increase leakage current. Therefore, controlling the influence of impurity elements diffusing from the gettering layer is effective in effectively reducing leakage current within a semiconductor substrate.

[0014] The present disclosure has been made based on the inventor's findings and knowledge, and provides an imaging device that can reduce leakage current even when a silicide region is provided in the imaging device.

[0015] (Summary of the Present Disclosure) As an overview of one aspect of the present disclosure, an example of an imaging device according to the present disclosure will be described below.

[0016] For example, an imaging device according to a first aspect of the present disclosure includes a photoelectric conversion unit that converts light into electric charges, a semiconductor substrate including a first impurity region and a second impurity region, and a first plug that is connected to the first impurity region and includes a silicide region, wherein one of the first impurity region and the second impurity region is a charge accumulation region that is electrically connected to the photoelectric conversion unit, and the semiconductor substrate includes a third impurity region that contains a Group 14 element other than silicon, at a position facing the silicide region with the first impurity region interposed therebetween.

[0017] As a result, the first plug connected to the first impurity region includes a silicide region, which reduces contact resistance with the metal and improves conductance in electrical connection via the first impurity region. Furthermore, since the silicide region is present in the first plug, even if the first impurity region is not directly silicided, the conductance in electrical connection via the first impurity region can be improved. Therefore, the concentration of metal impurities in the first impurity region can be reduced. Furthermore, metal impurities diffusing from the silicide region of the first plug are gettered by Group 14 elements other than silicon in the third impurity region. Therefore, leakage current in the semiconductor substrate due to metal impurities can be reduced.

[0018] Also, for example, an imaging device according to a second aspect of the present disclosure is the imaging device according to the first aspect, wherein the first impurity region is the charge accumulation region.

[0019] This makes it possible to improve the conductance in the electrical connection to the charge accumulation region, while reducing the leakage current in the charge accumulation region that becomes a dark current.

[0020] Also, for example, an imaging device according to a third aspect of the present disclosure is the imaging device according to the first aspect, which includes a second plug connected to the second impurity region and not including a silicide region, and the second impurity region is a charge storage region.

[0021] As a result, the second plug not including a silicide region is connected to the charge storage region, so that diffusion of metal impurities into the charge storage region can be suppressed and leakage current in the charge storage region that becomes dark current can be reduced.

[0022] Also, for example, an imaging device according to a fourth aspect of the present disclosure is an imaging device according to any one of the first to third aspects, in which the distance between the first impurity region and the third impurity region is longer than the distance between the silicide region and the first impurity region.

[0023] This reduces the influence of Group 14 elements other than silicon in the third impurity region diffusing into the first impurity region, thereby reducing leakage current in the first impurity region due to Group 14 elements other than silicon. Furthermore, even if the distance between the first impurity region and the third impurity region is long, metal impurities in the silicide region have a diffusion coefficient significantly larger than that of Group 14 elements other than silicon, making them more likely to diffuse, and therefore reach the third impurity region and be gettered.

[0024] Furthermore, for example, an imaging device according to a fifth aspect of the present disclosure is the imaging device according to any one of the first to fourth aspects, wherein the third impurity region contains carbon, and the concentration of the metal element of the metal silicide in the silicide region is set to A [atoms / cm ３ ], and the carbon concentration in the third impurity region is B [atoms / cm ３ ], the relationship 1<A / B<400,000 is satisfied.

[0025] Also, for example, an imaging device according to a sixth aspect of the present disclosure is the imaging device according to the fifth aspect, and satisfies 10<A / B<7000.

[0026] These concentration ratios A / B enhance the effect of gettering metal elements in the silicide region by carbon in the third impurity region, while suppressing the diffusion of excess carbon for gettering metal elements, thereby further reducing leakage current in the semiconductor substrate.

[0027] Furthermore, for example, an imaging device according to a seventh aspect of the present disclosure is the imaging device according to any one of the first to sixth aspects, wherein the third impurity region contains the Group 14 element and oxygen, and the concentration of the metal element of the metal silicide in the silicide region is set to A [atoms / cm ３ ] and the concentration of oxygen in the third impurity region is C, the relationship 2<A / C<10000 is satisfied.

[0028] Also, for example, an imaging device according to an eighth aspect of the present disclosure is the imaging device according to the seventh aspect, and satisfies 40<A / C<200.

[0029] These A / C concentration ratios enhance the effect of gettering metal elements in the silicide region by oxygen in the third impurity region, while suppressing the diffusion of excess oxygen to getter the metal elements, thereby further reducing the leakage current in the semiconductor substrate.

[0030] Also, for example, an imaging device according to a ninth aspect of the present disclosure is an imaging device according to any one of the first to eighth aspects, wherein the semiconductor substrate includes a base substrate and an epitaxial layer on the base substrate, the first impurity region and the second impurity region are located in the epitaxial layer, and the third impurity region is located in the base substrate.

[0031] Since the third impurity region is located within the base substrate, the influence of Group 14 elements other than silicon in the third impurity region diffusing into the first impurity region and the second impurity region located within the epitaxial layer can be reduced, and leakage current in the first impurity region and the second impurity region can be reduced. Furthermore, since the first impurity region and the second impurity region are provided in the epitaxial layer, which has high crystallinity, rather than in the base substrate, where the provision of the third impurity region is likely to disrupt crystallinity, leakage current in the first impurity region and the second impurity region can be reduced.

[0032] Also, for example, an imaging device according to a tenth aspect of the present disclosure is an imaging device according to any one of the first to fourth aspects, wherein the semiconductor substrate includes an imaging region in which a plurality of pixels are arranged, each of which includes the photoelectric conversion unit, the first impurity region, the second impurity region, and a first plug, and the third impurity region is arranged continuously across the entire imaging region.

[0033] Also, for example, an imaging device according to an eleventh aspect of the present disclosure is an imaging device according to any one of the first to fourth aspects, in which the third impurity region is arranged continuously across the entire semiconductor substrate.

[0034] Furthermore, for example, an imaging device according to a twelfth aspect of the present disclosure includes a semiconductor substrate including a photoelectric conversion unit that converts light into electric charges, a first impurity region electrically connected to the photoelectric conversion unit, and a second impurity region that is located at a position different from the first impurity region in a planar view and includes a silicide region, and a plug connected to the silicide region of the second impurity region, wherein the semiconductor substrate includes a third impurity region that contains a Group 14 element other than silicon at a position facing the plug with the second impurity region interposed therebetween, the second impurity region and the third impurity region are spaced apart, and the distance between the silicide region and the third impurity region is shorter than the distance between the silicide region and the first impurity region.

[0035] As a result, the second impurity region is connected to the plug via the silicide region, which reduces the contact resistance between the second impurity region and the plug and improves the conductance of the electrical connection via the second impurity region. Furthermore, since the third impurity region is located closer to the silicide region than the first impurity region, metal impurities diffusing from the silicide region are more likely to be gettered by the Group 14 elements other than silicon in the third impurity region before reaching the first impurity region. This reduces the leakage current in the first impurity region.

[0036] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. Note that the embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component arrangements and connection forms, steps, and step orders shown in the following embodiments are merely examples and are not intended to limit the present disclosure. The various aspects described in this specification can be combined with each other as long as no contradiction occurs. Furthermore, among the components in the following embodiments, components not recited in independent claims are described as optional components. In each drawing, components having substantially the same functions are designated by common reference symbols, and redundant descriptions may be omitted or simplified.

[0037] Furthermore, the various elements shown in the drawings are merely shown schematically to facilitate understanding of the present disclosure, and the dimensional ratios and appearances may differ from the actual objects. In other words, each drawing is a schematic diagram and is not necessarily an accurate depiction. Therefore, for example, the scales of the drawings do not necessarily match.

[0038] Furthermore, in this specification, terms indicating the relationship between elements, such as parallel or coincident, terms indicating the shape of elements, such as circular or rectangular, and numerical ranges are not expressions that only express a strict meaning, but are expressions that also include a substantially equivalent range, for example, a difference of about a few percent.

[0039] Furthermore, in this specification, the terms "upper" and "lower" do not refer to the upward (vertically upward) and downward (vertically downward) directions in absolute spatial recognition, but are used as terms defined by a relative positional relationship based on the stacking order in the stacked structure. Specifically, the light-receiving side of the imaging device is referred to as "upper," and the side opposite the light-receiving side is referred to as "lower." Similarly, the "upper surface" and "lower surface" of each component refer to the surface facing the light-receiving side of the imaging device as the "upper surface," and the surface facing the side opposite the light-receiving side as the "lower surface." Note that the terms "upper," "lower," "upper surface," and "lower surface" are used solely to specify the relative arrangement of components and are not intended to limit the orientation of the imaging device during use. Furthermore, the terms "upper" and "lower" apply not only to cases where two components are arranged with a gap between them and another component is present between them, but also to cases where two components are arranged closely together and in contact with each other. In this specification, the term "plan view" refers to a view from a direction perpendicular to the semiconductor substrate (in other words, the thickness direction of the semiconductor substrate).

[0040] In this specification, when a transistor is disposed on a certain surface of a semiconductor substrate, it means that the gate, source, and drain of the transistor are disposed with the certain surface sandwiched therebetween.

[0041] In this specification, not only visible light but also invisible light such as ultraviolet light and near-infrared light will be referred to as "light" for convenience.

[0042] First Embodiment An imaging device according to a first embodiment will be described below.

[0043] [Configuration] First, the configuration of the imaging device according to this embodiment will be described.

[0044] Fig. 1 is a diagram showing the configuration of an image pickup device 100A according to the present embodiment. As shown in Fig. 1, the image pickup device 100A according to the present embodiment includes a plurality of pixels 10A and a peripheral circuit 40 formed on a semiconductor substrate 60. Each pixel 10A includes a photoelectric conversion unit 12 arranged above the semiconductor substrate 60. Such an image pickup device 100A including a photoelectric conversion unit 12 arranged above the semiconductor substrate 60 is also called a stacked image pickup device.

[0045] In the example shown in FIG. 1 , pixels 10A are arranged in a matrix of m rows and n columns. Here, m and n are integers greater than or equal to 2. The pixels 10A are arranged, for example, two-dimensionally on the semiconductor substrate 60 to form an imaging region R1. As described above, each pixel 10A includes a photoelectric conversion unit 12 arranged above the semiconductor substrate 60. Therefore, the imaging region R1 is defined as the region of the semiconductor substrate 60 that is covered by the photoelectric conversion unit 12. Note that, in FIG. 1 , the photoelectric conversion units 12 of each pixel 10A are shown spatially separated from one another for ease of explanation; however, the photoelectric conversion units 12 of multiple pixels 10A may be arranged on the semiconductor substrate 60 without any spacing between them.

[0046] The number and arrangement of the pixels 10A are not limited to the example shown in the figure. For example, the number of pixels 10A included in the imaging device 100A may be one. Also, in this example, the center of each pixel 10A is located on a lattice point of a square lattice, but the pixels 10A do not have to be arranged in this manner. For example, multiple pixels 10A may be arranged so that each center is located on a lattice point of a triangular lattice, hexagonal lattice, or the like. Furthermore, if the pixels 10A are arranged one-dimensionally, the imaging device 100A can be used as a line sensor.

[0047] In the configuration illustrated in FIG. 1 , the peripheral circuit 40 includes a vertical scanning circuit 46 and a horizontal signal readout circuit 48. The vertical scanning circuit 46, also called a row scanning circuit, is connected to address signal lines 34 provided corresponding to each row of the multiple pixels 10A. The horizontal signal readout circuit 48, also called a column scanning circuit, is connected to vertical signal lines 35 provided corresponding to each column of the multiple pixels 10A. As schematically illustrated in FIG. 1 , these circuits are arranged in a peripheral region R2 outside the imaging region R1. The peripheral circuit 40 is connected to the multiple pixels 10A to acquire signals from each pixel 10A, and may further include a load circuit, a signal processing circuit, an output circuit, a control circuit, a power supply that supplies a predetermined voltage to each pixel 10A, and the like.

[0048] Fig. 2 is a diagram showing the circuit configuration of the imaging device 100A according to the present embodiment. In order to avoid complicating the drawing, Fig. 2 shows four pixels 10A arranged in two rows and two columns out of the plurality of pixels 10A shown in Fig. 1.

[0049] The photoelectric conversion unit 12 of each pixel 10A generates positive and negative charges in response to incident light. That is, the photoelectric conversion unit 12 converts light into electric charges. The positive and negative charges are typically hole-electron pairs. The photoelectric conversion unit 12 of each pixel 10A is connected to an accumulation control line 39, and a predetermined voltage is applied to the accumulation control line 39 during operation of the imaging device 100A. By applying a predetermined voltage to the accumulation control line 39, one of the positive and negative charges generated by photoelectric conversion can be selectively accumulated in the charge accumulation region as a signal charge. In the following description, unless otherwise specified, a case will be exemplified in which, of the positive and negative charges generated by photoelectric conversion, the positive charge, i.e., the hole, is used as the signal charge.

[0050] Each pixel 10A includes a signal detection circuit 14 electrically connected to the photoelectric conversion unit 12. In the configuration illustrated in FIG. 2 , the signal detection circuit 14 includes an amplification transistor 22 and a reset transistor 26. The amplification transistor 22 is also referred to as a readout transistor. In the example illustrated in FIG. 2 , the signal detection circuit 14 further includes an address transistor 24. The address transistor 24 is also referred to as a row selection transistor. As will be described in detail later with reference to the drawings, the amplification transistor 22, reset transistor 26, and address transistor 24 of the signal detection circuit 14 are, for example, field effect transistors (FETs) formed on a semiconductor substrate 60 that supports the photoelectric conversion unit 12. In the example illustrated in FIG. 2 , each of the amplification transistor 22, reset transistor 26, and address transistor 24 is an N-channel MOSFET (Metal Oxide Semiconductor FET). Which of the two impurity diffusion regions of a FET corresponds to the source and drain is determined by the polarity of the FET and the level of the potential at that time. Therefore, which is the source and which is the drain may vary depending on the operating state of the FET. In other words, the source and drain of each transistor described below may have the opposite configuration depending on the operating state of the FET.

[0051] 2 , the gate of the amplification transistor 22 is electrically connected to the photoelectric conversion unit 12. Charges generated by the photoelectric conversion unit 12 are accumulated as signal charges in a charge accumulation node FD between the photoelectric conversion unit 12 and the amplification transistor 22. In other words, the charge accumulation node FD functions as at least a part of a charge accumulation region that accumulates signal charges, and the potential of the charge accumulation node FD corresponds to the amount of signal charge accumulated in the charge accumulation region. The charge accumulation node FD includes wiring that connects the photoelectric conversion unit 12, the amplification transistor 22, and the reset transistor 26.

[0052] One of the source and drain of the amplification transistor 22 is connected to a power supply wiring 32 that supplies a predetermined power supply voltage VDD to each pixel 10A when the imaging device 100A is in operation. The power supply voltage VDD is, for example, about 3.3 V, but is not limited to this. The amplification transistor 22 outputs a signal voltage that corresponds to the amount of signal charge generated by the photoelectric conversion unit 12. The other of the source and drain of the amplification transistor 22 is connected to one of the source and drain of the address transistor 24.

[0053] A vertical signal line 35 is connected to the other of the source and drain of the address transistor 24. As shown in FIGS. 1 and 2 , a vertical signal line 35 is provided for each column of pixels 10A, and a load circuit 42 and a column signal processing circuit 44 are connected to each vertical signal line 35. The column signal processing circuit 44 is also called a row signal accumulation circuit. The load circuit 42 forms a source follower circuit together with the amplification transistor 22, for example.

[0054] An address signal line 34 is connected to the gate of the address transistor 24. One address signal line 34 is provided for each row of pixels 10A. The address signal line 34 is connected to a vertical scanning circuit 46, which applies a row selection signal to the address signal line 34 to control the on / off of the address transistor 24. This causes the row to be readout to be scanned in the vertical direction (i.e., the column direction), thereby selecting the row to be readout. By controlling the on / off of the address transistor 24 via the address signal line 34, the vertical scanning circuit 46 can read out the output of the amplifier transistor 22 of the selected pixel 10A to the corresponding vertical signal line 35. The location of the address transistor 24 is not limited to the example shown in FIG. 2 , and may be between one of the source and drain of the amplifier transistor 22 and the power supply wiring 32.

[0055] The signal voltage from the pixel 10A output to the vertical signal line 35 via the address transistor 24 is input to a corresponding one of a plurality of column signal processing circuits 44 provided for each column of a plurality of pixels 10A corresponding to the vertical signal line 35. The column signal processing circuit 44 and the load circuit 42 may be part of the peripheral circuit 40 described above.

[0056] The column signal processing circuits 44 perform noise suppression signal processing, such as correlated double sampling, and analog-to-digital conversion (AD conversion). The column signal processing circuits 44 are connected to a horizontal signal readout circuit 48. The horizontal signal readout circuit 48 sequentially reads out signals from the multiple column signal processing circuits 44 to a horizontal common signal line 49.

[0057] In the configuration illustrated in FIG. 2 , the signal detection circuit 14 includes a reset transistor 26, one of whose source and drain is connected to the charge storage node FD. A reset signal line 36, which is connected to the vertical scanning circuit 46, is connected to the gate of the reset transistor 26. Like the address signal lines 34, the reset signal lines 36 are provided for each row of pixels 10A. The vertical scanning circuit 46 can select the pixels 10A to be reset row by row by applying a row selection signal to the address signal line 34. The vertical scanning circuit 46 can also turn on the reset transistor 26 of the selected row by applying a reset signal that controls the on / off of the reset transistor 26 to the gate of the reset transistor 26 via the reset signal line 36. Turning on the reset transistor 26 resets the potential of the charge storage node FD.

[0058] 2, the other of the source and drain of the reset transistor 26 is connected to one of the feedback lines 53 provided for each column of multiple pixels 10A. That is, in this example, the voltage of the feedback line 53 is supplied to the charge storage node FD as a reset voltage for initializing the charge generated in the photoelectric conversion unit 12. Here, the above-mentioned feedback line 53 is connected to the output terminal of a corresponding one of the inverting amplifiers 50 provided for each column of multiple pixels 10A. The inverting amplifier 50 may be part of the above-mentioned peripheral circuit 40.

[0059] Now, let us focus on one of the columns of pixels 10A. As shown in FIG. 2 , the inverting input terminal of the inverting amplifier 50 is connected to the vertical signal line 35 of that column. The output terminal of the inverting amplifier 50 is also connected to one or more pixels 10A belonging to that column via a feedback line 53. During operation of the imaging device 100A, a predetermined input voltage Vref is supplied to the non-inverting input terminal of the inverting amplifier 50. The vertical scanning circuit 46 selects one of the pixels 10A belonging to that column and turns on the address transistor 24 and the reset transistor 26, thereby forming a feedback path that negatively feeds back the output of that pixel 10A. The formation of the feedback path causes the voltage of the vertical signal line 35 to converge to the input voltage Vref to the non-inverting input terminal of the inverting amplifier 50. In other words, the formation of the feedback path resets the voltage of the charge storage node FD to a voltage that makes the voltage of the vertical signal line 35 equal to the input voltage Vref. The input voltage Vref may be any voltage within the range of the power supply voltage and the ground voltage. For example, the input voltage Vref is a voltage within the range of 0 V to 3.3 V. As an example, the input voltage Vref is a positive voltage of 1 V or close to 1 V. The inverting amplifier 50 is also called a feedback amplifier. Thus, the imaging device 100A includes a feedback circuit 16 that includes the inverting amplifier 50 as part of its feedback path.

[0060] As is well known, thermal noise called kTC noise occurs when a transistor is turned on or off. The noise generated when the reset transistor 26 is turned on or off is called reset noise. After resetting the potential of the charge storage region, reset noise generated by turning off the reset transistor 26 remains in the charge storage region before signal charge is accumulated. However, reset noise generated when the reset transistor 26 is turned off can be reduced by using feedback. Details of suppressing reset noise using feedback are described in Patent Document 2. The entire disclosure of Patent Document 2 is incorporated herein by reference.

[0061] 2, the formation of a feedback path causes the AC component of the thermal noise to be fed back to the other of the source and drain of the reset transistor 26. In the configuration illustrated in FIG. 2, the feedback path is formed until just before the reset transistor 26 is turned off, so it is possible to reduce the reset noise that occurs when the reset transistor 26 is turned off.

[0062] FIG. 3 is a plan view showing the layout within a pixel 10A according to the present embodiment. FIG. 4 is a schematic cross-sectional view of the device structure of the pixel 10A according to the present embodiment. FIG. 4 is a cross-sectional view of the pixel 10A cut along line IV-IV in FIG. 3 and expanded in the direction of the arrows. FIG. 3 schematically shows the arrangement of each element formed on the semiconductor substrate 60 when the pixel 10A shown in FIG. 4 is viewed from a direction perpendicular to the semiconductor substrate 60. Specifically, FIG. 3 shows the arrangement of the amplifier transistor 22, address transistor 24, and reset transistor 26 included in the pixel 10A. Here, the amplifier transistor 22 and the address transistor 24 are linearly arranged in the vertical direction on the paper. FIG. 3 also schematically shows the electrical connections of each element formed on the semiconductor substrate 60. Note that, for ease of viewing, each component shown in the plan view is shaded in the same manner as the shaded components shown in the cross section of FIG. 4. In addition, in FIG. 4, for ease of viewing, the hatching showing the cross section of the insulating layers 70 and 72 and the interlayer insulating layer 90 is omitted.

[0063] As shown in FIG. 4 , each pixel 10A generally includes a semiconductor substrate 60, a photoelectric conversion unit 12 disposed above the semiconductor substrate 60, and a wiring structure 80. Each pixel 10A has, for example, substantially the same device structure. The wiring structure 80 is disposed within an interlayer insulating layer 90 formed between the photoelectric conversion unit 12 and the semiconductor substrate 60, and includes a structure that electrically connects the photoelectric conversion unit 12 to an amplification transistor 22 formed on the semiconductor substrate 60. Here, the interlayer insulating layer 90 has a stacked structure including four insulating layers, 90a, 90b, 90c, and 90d. The wiring structure 80 includes four wiring layers, 80a, 80b, 80c, and 80d, and plugs pa1, pa2, pb, pc, and pd, disposed between these wiring layers. The number of insulating layers in the interlayer insulating layer 90 and the number of wiring layers in the wiring structure 80 are not limited to this example and can be set arbitrarily. The semiconductor substrate 60 and the interlayer insulating layer 90 are, for example, formed continuously over at least the entire imaging region R1 and are shared by multiple pixels 10 A. Alternatively, the semiconductor substrate 60 and the interlayer insulating layer 90 may be formed continuously from the imaging region R1 to the peripheral region R2.

[0064] The photoelectric conversion unit 12 is disposed on the interlayer insulating layer 90. The photoelectric conversion unit 12 includes a pixel electrode 12a formed on the interlayer insulating layer 90, a transparent electrode 12c facing the pixel electrode 12a, and a photoelectric conversion layer 12b located between the pixel electrode 12a and the transparent electrode 12c. The photoelectric conversion layer 12b of the photoelectric conversion unit 12 is formed from an organic material or an inorganic material such as amorphous silicon. It receives incident light through the transparent electrode 12c and generates positive and negative charges through photoelectric conversion. The photoelectric conversion layer 12b is formed continuously across, for example, multiple pixels 10A. In other words, the photoelectric conversion layer 12b is shared by multiple pixels 10A. The photoelectric conversion layer 12b may also include a layer made of an organic material and a layer made of an inorganic material. The photoelectric conversion layer 12b may also be provided separately for each pixel 10A.

[0065] The transparent electrode 12c is formed from a transparent conductive material such as ITO (Indium Tin Oxide) and is disposed on the light-receiving surface side of the photoelectric conversion layer 12b. The term "transparent" in this specification means that the photoelectric conversion layer 12b transmits at least a portion of light having a wavelength that can be absorbed, but does not necessarily transmit light over the entire wavelength range of visible light. The transparent electrode 12c, like the photoelectric conversion layer 12b, is formed continuously across multiple pixels 10A. That is, the transparent electrode 12c is shared by multiple pixels 10A. In other words, the photoelectric conversion unit 12 provided for each pixel 10A has a different portion of the transparent electrode 12c for each pixel 10A. The transparent electrode 12c may be provided separately for each pixel 10A.

[0066] Although not shown in FIG. 4 , the transparent electrode 12c is connected to the aforementioned accumulation control line 39. During operation of the imaging device 100A, the potential of the accumulation control line 39 is controlled to make the potential of the transparent electrode 12c different from the potential of the pixel electrode 12a, thereby allowing the pixel electrode 12a to collect signal charges generated by photoelectric conversion. For example, the potential of the accumulation control line 39 is controlled so that the potential of the transparent electrode 12c is higher than the potential of the pixel electrode 12a. Specifically, a positive voltage of, for example, about 10 V is applied to the accumulation control line 39. This allows the pixel electrode 12a to collect the holes, of the hole-electron pairs generated in the photoelectric conversion layer 12b, as signal charges. The signal charges collected by the pixel electrode 12a are accumulated in the n-type impurity region 67n (described below) electrically connected to the pixel electrode 12a via the wiring structure 80. When electrons are used as signal charges, a voltage is applied to the transparent electrode 12c so that the potential of the transparent electrode 12c is lower than the potential of the pixel electrode 12a.

[0067] The pixel electrode 12a is an electrode formed from a metal such as aluminum or copper, a metal nitride, or polysilicon doped with impurities to make it conductive. The pixel electrode 12a is spatially separated from the pixel electrodes 12a of other adjacent pixels 10A, and is thereby electrically isolated from the pixel electrodes 12a of other pixels 10A.

[0068] The semiconductor substrate 60 includes a base substrate 60 a and an epitaxial layer 60 b including one or more semiconductor layers formed on the base substrate 60 a. Here, the base substrate 60 a is exemplified by a p-type silicon (Si) substrate doped with p-type impurities such as boron (B).

[0069] 4, the epitaxial layer 60b includes a p-type semiconductor layer 61p on the base substrate 60a, an n-type semiconductor layer 62n on the p-type semiconductor layer 61p, a p-type semiconductor layer 63p on the n-type semiconductor layer 62n, and a p-type semiconductor layer 65p on the p-type semiconductor layer 63p. The p-type semiconductor layer 65p is located at the top of the semiconductor layers included in the semiconductor substrate 60, that is, it is the semiconductor layer closest to the photoelectric conversion unit 12. The p-type semiconductor layer 61p, the p-type semiconductor layer 63p, and the p-type semiconductor layer 65p are semiconductor layers containing p-type impurities. The configuration of one or more semiconductor layers included in the epitaxial layer 60b is not particularly limited and can be designed according to the purpose.

[0070] The semiconductor substrate 60 further includes a gettering layer 60g located within the base substrate 60a. The gettering layer 60g is an example of a third impurity region. The gettering layer 60g faces the silicide region SR via n-type impurity regions 67n, 68an, 68bn, and 68dn, which will be described later. The gettering layer 60g overlaps the n-type impurity regions 67n, 68an, 68bn, and 68dn in a planar view. In the example shown in FIG. 4, the gettering layer 60g is provided slightly away from the upper surface of the base substrate 60a, but it may also be provided in a portion including the upper surface of the base substrate 60a. The gettering layer 60g is, for example, continuously formed over at least the entire imaging region R1 and shared by multiple pixels 10A. The gettering layer 60g may be formed separately for each pixel 10A or for each pixel block consisting of two or more pixels 10A. Furthermore, as long as the gettering layer 60g is provided facing the silicide region SR, there may be a portion in the pixel 10A where the gettering layer 60g is not provided in plan view.

[0071] The gettering layer 60g contains a Group 14 element other than silicon as an impurity element and is formed by ion implantation of the impurity element into the base substrate 60a. The gettering layer 60g getters metal impurities in the semiconductor substrate 60 using the Group 14 element other than silicon. This reduces the leakage current of the pn junction in the semiconductor substrate 60. For example, it reduces the dark current flowing in the n-type impurity region 67n where signal charge is accumulated. The gettering layer 60g is formed, for example, before the formation of the epitaxial layer 60b. Furthermore, after the gettering layer 60g is formed on the base substrate 60a, a heat treatment may be performed before the formation of the epitaxial layer 60b to improve the crystallinity of the base substrate 60a.

[0072] The Group 14 element other than silicon is, for example, carbon. The Group 14 element other than silicon may be germanium. When the Group 14 element other than silicon is carbon, the gettering layer 60g may be formed by irradiating the base wafer 60a with cluster ions containing carbon. In this case, the gettering layer 60g further contains hydrogen derived from the cluster ions containing carbon. The gettering layer 60g may also contain oxygen. Oxygen in the semiconductor substrate 60 may collect in the gettering layer 60g during ion implantation of a Group 14 element other than silicon into the base wafer 60a. The oxygen in the gettering layer 60g also getter metal impurities in the semiconductor substrate 60.

[0073] The concentration of the Group 14 element other than silicon in the gettering layer 60g is, for example, 1×10 １６ atoms / cm ３ The concentration of the Group 14 elements other than silicon in the gettering layer 60g is 1×10 １７ atoms / cm ３ or more, and may be 1×10 １８ atoms / cm ３ The concentration of the Group 14 element other than silicon in the gettering layer 60g may be 1×10 ２１ atoms / cm ３ It may be the following:

[0074] In addition, when the gettering layer 60g contains oxygen, the concentration of oxygen in the gettering layer 60g is 1×10 １６ atoms / cm ３ or more, and may be 1×10 １８ atoms / cm ３ The oxygen concentration in the gettering layer 60g may be 1×10 ２０ atoms / cm ３ It may be the following:

[0075] In this specification, the element concentration in the gettering layer 60g is the peak concentration at a position corresponding to the gettering layer 60g when the element concentration distribution is measured in the depth direction (thickness direction of the semiconductor substrate 60).

[0076] The semiconductor substrate 60 further includes n-type impurity regions 67n, 68an, 68bn, 68cn, and 68dn, and an element isolation region 69. The n-type impurity regions 67n, 68an, 68bn, 68cn, and 68dn and the element isolation region 69 are located within the p-type semiconductor layer 65p, and a portion thereof is located on the upper surface of the p-type semiconductor layer 65p. The n-type impurity regions 67n, 68an, 68bn, 68cn, and 68dn are each an impurity diffusion region in which n-type impurities are diffused. The n-type impurity regions 67n, 68an, 68bn, 68cn, and 68dn are provided at different positions in the semiconductor substrate 60 in a plan view. In the present embodiment, the n-type impurity region 67n is an example of a first impurity region, and one of the n-type impurity regions 68an, 68bn, and 68dn is an example of a second impurity region.

[0077] As shown in FIGS. 3 and 4, an amplifier transistor 22, an address transistor 24, and a reset transistor 26 are formed on a semiconductor substrate 60.

[0078] 3 and 4, the n-type impurity region 67n is one of the source and drain of the reset transistor 26. The n-type impurity region 67n is also electrically connected to the photoelectric conversion unit 12 and is a charge accumulation region that temporarily accumulates signal charges generated by the photoelectric conversion unit 12. When the reset transistor 26 is turned on, it initializes the charges in the n-type impurity region 67n.

[0079] The reset transistor 26 includes an n-type impurity region 67n and an n-type impurity region 68an, an insulating layer 70 formed on the semiconductor substrate 60, and a gate electrode 26e on the insulating layer 70. The reset transistor 26 includes the n-type impurity region 67n as one of the source and drain, and the n-type impurity region 68an as the other of the source and drain, and stores photocharges converted by the photoelectric conversion unit 12. The reset transistor 26 also includes the gate electrode 26e on the insulating layer 70 as its gate.

[0080] The concentration of n-type impurities in the n-type impurity region 67n is lower than the concentration of n-type impurities in the n-type impurity region 68an, for example.

[0081] The amplifier transistor 22 includes n-type impurity regions 68bn and 68cn, a portion of the insulating layer 70, and a gate electrode 22e on the insulating layer 70. The amplifier transistor 22 includes the n-type impurity region 68bn as one of the source and drain, and the n-type impurity region 68cn as the other of the source and drain. The amplifier transistor 22 also includes the gate electrode 22e on the insulating layer 70 as its gate.

[0082] The address transistor 24 includes n-type impurity regions 68cn and 68dn, a portion of the insulating layer 70, and a gate electrode 24e on the insulating layer 70. In the example shown in Figures 3 and 4, the address transistor 24 shares the n-type impurity region 68cn with the amplifier transistor 22, thereby being electrically connected to the amplifier transistor 22. The address transistor 24 includes the n-type impurity region 68cn as one of the source and drain, and the n-type impurity region 68dn as the other of the source and drain. The address transistor 24 also includes the gate electrode 24e on the insulating layer 70 as its gate.

[0083] The n-type impurity concentration of n-type impurity region 67n may be lower than the n-type impurity concentration of n-type impurity regions 68bn, 68dn, and 68cn. This reduces the junction concentration at the junction between n-type impurity region 67n and p-type semiconductor layer 65p, thereby reducing the electric field strength at the junction. This reduces leakage current from or to n-type impurity region 67n, which is a charge accumulation region.

[0084] The concentration of the n-type impurity contained in the n-type impurity region 67n and the concentration of the p-type impurity contained in the p-type semiconductor layer 65p are 1×10 １６ atoms / cm ３ 5x10 or more １６ atoms / cm ３ This reduces the junction concentration between the n-type impurity region 67n and the p-type semiconductor layer 65p, thereby suppressing an increase in the electric field strength at the junction, thereby reducing the leakage current at the junction.

[0085] Each of the p-type semiconductor layer 61p, the n-type semiconductor layer 62n, the p-type semiconductor layer 63p, and the p-type semiconductor layer 65p is formed, for example, by ion implantation of impurities into a semiconductor layer formed by epitaxial growth. The impurity concentrations of the p-type semiconductor layer 63p and the p-type semiconductor layer 65p are, for example, approximately the same as each other and higher than the impurity concentration of the p-type semiconductor layer 61p. The n-type semiconductor layer 62n disposed between the p-type semiconductor layer 61p and the p-type semiconductor layer 63p suppresses the inflow of minority carriers from the base substrate 60a or the peripheral circuitry 40 into the n-type impurity region 67n, which is a charge accumulation region that accumulates signal charge. During operation of the imaging device 100A, the potential of the n-type semiconductor layer 62n is controlled via a contact (not shown) provided outside the imaging region R1 shown in FIG. 1.

[0086] In this example, the semiconductor substrate 60 also includes a p-type region 64p provided between the p-type semiconductor layer 65p and the base substrate 60a, penetrating the p-type semiconductor layer 61p, the n-type semiconductor layer 62n, and the p-type semiconductor layer 63p. The p-type region 64p does not have to penetrate the p-type semiconductor layer 63p or reach the p-type semiconductor layer 65p, as long as it reaches the p-type semiconductor layer 63p. The p-type region 64p has a higher impurity concentration than the p-type semiconductor layers 63p and 65p, and electrically connects the p-type semiconductor layers 63p and 65p to the base substrate 60a. In the example shown in FIG. 4, the p-type region 64p is in contact with the upper surface of the gettering layer 60g, but it may penetrate the gettering layer 60g or may not be in contact with the gettering layer 60g.

[0087] During operation of the imaging device 100A, the potentials of the p-type semiconductor layers 63p and 65p and the base substrate 60a are controlled via contacts (not shown) provided outside the imaging region R1. Furthermore, by arranging the p-type semiconductor layer 65p so as to be in contact with the p-type semiconductor layer 63p, the potential of the p-type semiconductor layer 65p can also be controlled via the p-type semiconductor layer 63p during operation of the imaging device 100A. Note that a contact may be provided on the p-type semiconductor layer 65p on the side opposite to the base substrate 60a, and the potential may be controlled via this contact.

[0088] The concentration of the p-type impurity contained in the base substrate 60a is higher than the concentration of the p-type impurity contained in the p-type semiconductor layers 61p, 63p, and 65p, for example. Specifically, the concentration of the p-type impurity contained in the base substrate 60a is, for example, 1×10 １８ atoms / cm ３ 1x10 or more １９ atoms / cm ３ or less. This allows a gettering effect of metal impurities in the semiconductor substrate 60 to be obtained by the relatively high concentration of p-type impurities, and the leakage current of the pn junction in the semiconductor substrate 60 to be reduced. For example, the dark current flowing in the n-type impurity region 67n where signal charges are accumulated is reduced. Furthermore, the resistance of the base substrate 60a is also reduced, so the potential of the well in the semiconductor substrate 60 can be stabilized. The concentration of the p-type impurities contained in the base substrate 60a is 2×10１８ atoms / cm ３ 6 x 10 or more １８ atoms / cm ３ It may be the following:

[0089] An element isolation region 69 is disposed between the n-type impurity region 68bn and the n-type impurity region 67n. The element isolation region 69 is, for example, a p-type impurity diffusion region. The element isolation region 69 electrically isolates the amplifier transistor 22 from the reset transistor 26.

[0090] As shown in FIG. 4 , the n-type impurity region 67 n and the isolation region 69 may be arranged so as not to contact each other. For example, when a p-type impurity layer is used as the isolation region 69, if the n-type impurity region 67 n and the isolation region 69 are in contact with each other, both the n-type impurity concentration and the p-type impurity concentration at the junction become high. Therefore, a leakage current due to this high junction concentration is likely to occur around the junction between the n-type impurity region 67 n and the isolation region 69. In other words, by arranging the n-type impurity region 67 n and the isolation region 69 so as not to contact each other, an increase in the pn junction concentration can be suppressed, thereby suppressing leakage current, even if a high-concentration p-type impurity layer is used for the isolation region 69. Another method is to use shallow trench isolation (STI) as the isolation region 69. In this case, the n-type impurity region 67 n and the STI may also be arranged so as not to contact each other in order to reduce leakage current due to crystal defects on the sidewalls of the STI.

[0091] The element isolation regions 69 are also disposed between adjacent pixels 10A, electrically isolating the signal detection circuits 14 therebetween. Here, the element isolation regions 69 are provided around the pair of the amplification transistor 22 and the address transistor 24 and around the reset transistor 26.

[0092] In the example shown in FIG. 4 , the pixel 10A is provided with an insulating layer 72 that covers the gate electrode 26e of the reset transistor 26, the gate electrode 22e of the amplifier transistor 22, and the gate electrode 24e of the address transistor 24. The insulating layer 72 is, for example, a silicon oxide film. In this example, an insulating layer 71 is further interposed between the insulating layer 72 and the gate electrode 26e, the gate electrode 22e, and the gate electrode 24e. The insulating layer 71 is, for example, a silicon oxide film. The insulating layer 71 may have a stacked structure including multiple insulating layers. Similarly, the above-mentioned insulating layer 72 may also have a stacked structure including multiple insulating layers.

[0093] The laminated structure of insulating layer 72 and insulating layer 71 includes a plurality of contact holes. Here, contact holes h1, h2, h3, h4, h5, h6, and h7 are provided in insulating layer 72 and insulating layer 71. Pixel 10A further includes contact plugs cp1, cp2, cp3, cp4, cp5, cp6, and cp7, each of which is partially disposed within contact holes h1, h2, h3, h4, h5, h6, and h7. Contact plug cp1 is an example of a first plug.

[0094] Contact holes h1, h2, h3, and h4 are formed at positions overlapping n-type impurity region 67n, n-type impurity region 68an, n-type impurity region 68bn, and n-type impurity region 68dn, respectively, in a plan view of semiconductor substrate 60. Contact holes h1, h2, h3, and h4 penetrate insulating layer 72, insulating layer 71, and insulating layer 70. Contact plugs cp1, cp2, cp3, and cp4 are disposed at the positions of contact holes h1, h2, h3, and h4, respectively. Contact plugs cp1, cp2, cp3, and cp4 are connected to n-type impurity region 67n, n-type impurity region 68an, n-type impurity region 68bn, and n-type impurity region 68dn, respectively.

[0095] Contact holes h5, h6, and h7 are formed at positions overlapping gate electrode 26e, gate electrode 22e, and gate electrode 24e, respectively, in a plan view of semiconductor substrate 60. Contact holes h5, h6, and h7 penetrate insulating layer 72 and insulating layer 71. Contact plugs cp5, cp6, and cp7 are disposed at the positions of contact holes h5, h6, and h7, respectively. Contact plugs cp5, cp6, and cp7 are connected to gate electrode 26e, gate electrode 22e, and gate electrode 24e, respectively.

[0096] The wiring layer 80a is disposed on the insulating layer 90a. In the configuration illustrated in FIG. 4 , the wiring layer 80a is a layer including contact plugs cp1, cp2, cp3, cp4, cp5, cp6, and cp7, and gate electrodes 22e, 24e, and 26e, and is, for example, a polysilicon layer doped with impurities such as n-type impurities. That is, the contact plugs cp1, cp2, cp3, cp4, cp5, cp6, and cp7, and the gate electrodes 22e, 24e, and 26e include, for example, polysilicon that has been doped with impurities to provide conductivity as a constituent material. This reduces metal diffusion into the semiconductor substrate 60 from the contact plugs connected to the amplification transistor 22, the address transistor 24, and the reset transistor 26. The main component element in each of the contact plugs cp1, cp2, cp3, cp4, cp5, cp6, and cp7 and the gate electrodes 22e, 24e, and 26e is, for example, silicon. Here, the main component element means a content of more than 50 atom %.

[0097] Of the wiring layers included in the wiring structure 80, the wiring layer 80a is arranged closest to the semiconductor substrate 60. The wiring layer 80b and the plugs pa1 and pa2 are arranged in the insulating layer 90a. The plug pa1 connects the contact plug cp1 to the wiring layer 80b, and the plug pa2 connects the contact plug cp6 to the wiring layer 80b. In other words, the n-type impurity region 67n and the gate electrode 22e of the amplification transistor 22 are electrically connected to each other via the contact plugs cp1 and cp6, the plugs pa1 and pa2, and the wiring layer 80b.

[0098] The contact plugs cp1, cp2, cp3, cp4, cp5, cp6, and cp7 each include a silicide region SR. The silicide region SR is, for example, a silicide layer containing metal silicide formed by depositing a metal on the surface of each of the contact plugs cp1, cp2, cp3, cp4, cp5, cp6, and cp7 and then reacting the metal with polysilicon. The silicide region SR is formed on at least the upper surface of each of the contact plugs cp1, cp2, cp3, cp4, cp5, cp6, and cp7. In the example shown in FIG. 4, the silicide region SR is also formed on the side surface of each of the contact plugs cp1, cp2, cp3, cp4, cp5, cp6, and cp7. Furthermore, the silicide regions SR are not formed on the surfaces of the contact plugs cp1, cp2, cp3, cp4, cp5, cp6, and cp7 that face the semiconductor substrate 60. Furthermore, no silicide regions are formed in the n-type impurity regions 67n, 68an, 68bn, 68cn, and 68dn, and, for example, in the pixel 10A, no silicide regions exist in the semiconductor substrate 60.

[0099] The contact plugs cp1, cp2, cp3, cp4, cp5, cp6, and cp7 each make contact with a plug included in the wiring structure 80 in the silicide region SR. This reduces the contact resistance between the contact plugs cp1, cp2, cp3, cp4, cp5, cp6, and cp7 and the plug. The contact plugs cp1, cp2, cp3, cp4, cp5, cp6, and cp7 are connection parts between the amplification transistor 22, the address transistor 24, and the reset transistor 26 and the wiring structure 80, and reducing the resistance of the connection parts can improve the drive capabilities of these transistors.

[0100] Examples of metals used to form the silicide region SR include nickel, platinum, titanium, tungsten, and cobalt. One type of metal or two or more types of metals may be used to form the silicide region SR. From the viewpoint of reducing contact resistance with the plug, the metal silicide of the silicide region SR may contain nickel.

[0101] The wiring layer 80b is disposed in the insulating layer 90a and may include, as part thereof, the above-mentioned vertical signal line 35, address signal line 34, power supply line 32, reset signal line 36, and feedback line 53. The vertical signal line 35, address signal line 34, power supply line 32, reset signal line 36, and feedback line 53 are electrically connected to the n-type impurity region 68dn, gate electrode 24e, n-type impurity region 68bn, gate electrode 26e, and n-type impurity region 68an via contact plugs cp4, cp7, cp3, cp5, and cp2, respectively.

[0102] At least one of the vertical signal line 35, the address signal line 34, the power supply line 32, the reset signal line 36, and the feedback line 53 may be included in the wiring layer 80c or 80d instead of the wiring layer 80b.

[0103] A plug pb disposed in the insulating layer 90b connects the wiring layer 80b to the wiring layer 80c. Similarly, a plug pc disposed in the insulating layer 90c connects the wiring layer 80c to the wiring layer 80d. A plug pd disposed in the insulating layer 90d connects the wiring layer 80d to the pixel electrode 12a of the photoelectric conversion unit 12. The wiring layers 80b, 80c, and 80d, as well as the plugs pa1, pa2, pb, pc, and pd, are formed of, for example, a metal such as copper or tungsten, or a metal compound such as a metal nitride or a metal oxide. Furthermore, the plugs other than the plugs pa1 and pa2 connected to the contact plugs cp2, cp3, cp4, cp5, and cp7 are also formed of, for example, a metal such as copper or tungsten, or a metal compound such as a metal nitride or a metal oxide.

[0104] The plugs pa1, pa2, pb, pc, and pd, the wiring layers 80b, 80c, and 80d, and the contact plugs cp1 and cp6 electrically connect the photoelectric conversion unit 12 to the signal detection circuit 14 formed on the semiconductor substrate 60. The plugs pa1, pa2, pb, pc, and pd, at least a part of the wiring layers 80b, 80c, and 80d, the contact plugs cp1 and cp6, the pixel electrode 12a of the photoelectric conversion unit 12, the gate electrode 22e of the amplifying transistor 22, and the n-type impurity region 67n function as a charge accumulation region that accumulates the signal charge generated by the photoelectric conversion unit 12.

[0105] Here, attention is focused on the n-type impurity regions formed in the semiconductor substrate 60. Of the n-type impurity regions formed in the semiconductor substrate 60, n-type impurity region 67n is disposed in p-type semiconductor layer 65p serving as a p-well. N-type impurity region 67n is formed near the surface of the semiconductor substrate 60, with at least a portion of it located on the surface of the semiconductor substrate 60. A junction capacitance formed by a pn junction between p-type semiconductor layer 65p and n-type impurity region 67n functions as a capacitance that stores at least a portion of the signal charge and constitutes a part of the charge storage region.

[0106] In the configuration illustrated in FIG. 4 , the n-type impurity region 67n includes a first region 67a and a second region 67b. The impurity concentration of the first region 67a of the n-type impurity region 67n is lower than, for example, the n-type impurity region 68an and the n-type impurity regions 68bn, 68cn, and 68dn. The second region 67b of the n-type impurity region 67n is formed within the first region 67a and has a higher impurity concentration than the first region 67a. A contact hole h1 is located on the second region 67b, and a contact plug cp1 is connected to the second region 67b through the contact hole h1. Note that the n-type impurity region 67n does not necessarily have to include the first region 67a and the second region 67b, and may instead be formed as a single region obtained by combining the first region 67a and the second region 67b with the same impurity concentration. In the example shown in FIG. 4, the n-type impurity region 68an and the n-type impurity regions 68bn and 68dn also include two regions with different impurity concentrations, but they may be formed from a single region.

[0107] The device structure of the pixel 10A in the imaging device 100A described above can be manufactured using, for example, a general semiconductor manufacturing process.

[0108] As described above, the imaging device 100A according to the present embodiment includes the photoelectric conversion unit 12, the semiconductor substrate 60 including the n-type impurity region 67 n that is a charge accumulation region electrically connected to the photoelectric conversion unit 12, and the contact plug cp1 that is connected to the n-type impurity region 67 n and includes the silicide region SR. The semiconductor substrate 60 includes a gettering layer 60 g at a position facing the silicide region SR of the contact plug cp1 with the n-type impurity region 67 n interposed therebetween.

[0109] As a result, since the contact plug cp1 includes the silicide region SR, the metal used to form the silicide region SR as a metal impurity is likely to diffuse into the semiconductor substrate 60, but the metal impurity is gettered by the gettering layer 60g, which reduces the occurrence of leakage current due to the diffusion of the metal impurity from the silicide region SR.

[0110] [Element Concentration in Pixel] Next, the element concentration in the pixel 10A will be described.

[0111] The present inventors have found that dark current flowing through the n-type impurity region 67 n can be effectively reduced by ensuring that the element concentrations in the pixel 10 A satisfy certain conditions. This point will be described in detail below with reference to the results of analysis conducted by the present inventors.

[0112] First, the gettering of metal impurities by the gettering layer 60g will be described.

[0113] FIG. 5A is a diagram showing the distribution of nickel (Ni) concentration in the contact plug cp1 and the n-type impurity region 67n. In FIG. 5A, the vertical axis represents the nickel concentration expressed on a logarithmic scale, and the horizontal axis represents the depth relative to the top surface of the semiconductor substrate 60. Here, the depth direction is the thickness direction of the semiconductor substrate 60. Also, in FIG. 5A, the negative depth side is the contact plug cp1 side, and the positive depth side is the n-type impurity region 67n side. FIG. 5B is a diagram showing the distribution of impurity concentration near the gettering layer 60g in the semiconductor substrate 60. In FIG. 5B, the vertical axis represents the impurity concentration expressed on a logarithmic scale, and the horizontal axis represents the depth relative to the top surface of the semiconductor substrate 60. In FIG. 5B, the concentrations of carbon (C), oxygen (O), and nickel (Ni) are shown as impurities. 5A and 5B show the results obtained by performing elemental analysis of the contact plug cp1 and the semiconductor substrate 60 along the depth direction by SIMS (Secondary Ion Mass Spectrometry). Also, FIGS. 5A and 5B show the SIMS analysis results when nickel is used as the metal for forming the silicide region SR and carbon is used as the impurity element for forming the gettering layer 60g. In FIGS. 5A and 5B, the element concentration is 1×10 １６ atoms / cm ３ The following results are below the detection limit of the SIMS analyzer used, so they are 1×10 １６ atoms / cm ３ is shown as:

[0114] As shown in FIG. 5A , the contact plug cp1 includes the silicide region SR, and therefore, at a depth corresponding to the position of the contact plug cp1, the nickel concentration is high due to the silicide region SR. Furthermore, as shown in FIG. 5B , the nickel concentration is also higher at a depth of approximately 5.0 μm, where the carbon and oxygen concentration peaks resulting from the gettering layer 60g are present, than at other positions. This indicates that nickel is being gettered by the gettering layer 60g. Therefore, as shown in FIG. 5A , due to the gettering of nickel by the gettering layer 60g, the nickel concentration is low at a depth corresponding to the position of the n-type impurity region 67n, near the lower detection limit of the analysis. Thus, even when the contact plug cp1 includes the silicide region SR to improve drive performance, the gettering layer 60g getter metal impurities in the semiconductor substrate 60 resulting from the formation of the silicide region SR. This reduces the generation of leakage current within the semiconductor substrate 60.

[0115] Next, the relationship between the element concentration in the pixel 10A and the dark current (leak current) flowing in the n-type impurity region 67n will be described.

[0116] FIG. 6 is a graph showing the relationship between the concentration ratio of nickel (Ni) to carbon (C) (Ni concentration / C concentration) and dark current. In FIG. 6, the vertical axis represents the dark current flowing in the n-type impurity region 67n, and the horizontal axis represents the concentration ratio of nickel to carbon (Ni concentration / C concentration) expressed on a logarithmic axis. FIG. 7 is a graph showing the relationship between the concentration ratio of nickel (Ni) to oxygen (O) (Ni concentration / O concentration) and dark current. In FIG. 7, the vertical axis represents the dark current flowing in the n-type impurity region 67n, and the horizontal axis represents the concentration ratio of nickel to oxygen (Ni concentration / O concentration) expressed on a logarithmic axis. FIGS. 6 and 7 show the results of measurements of how the dark current changes when nickel is used as the metal for forming the silicide region SR and carbon is used as the impurity element for forming the gettering layer 60g, and the amount of carbon ion implantation used in forming the gettering layer 60g is changed. The nickel concentration (Ni concentration) in this case is the peak value of the nickel concentration at a position corresponding to the contact plug cp1 measured by SIMS analysis. The carbon concentration (C concentration) is the peak value of the carbon concentration at a position corresponding to the gettering layer 60g measured by SIMS analysis. The oxygen concentration (O concentration) is the peak value of the oxygen concentration at a position corresponding to the gettering layer 60g measured by SIMS analysis. The rightmost plots in FIGS. 6 and 7 are the results when the gettering layer 60g was not formed.

[0117] As shown in FIG. 6 , compared to when the gettering layer 60g is not formed, the dark current decreases due to the higher C concentration and the lower Ni / C ratio. This is thought to be because the increase in C concentration relative to Ni concentration enhances the gettering layer 60g's ability to getter nickel, suppressing nickel diffusion into the n-type impurity region 67n. On the other hand, when the Ni / C ratio decreases by a certain level or more, the dark current increases. This is thought to be because an excessive increase in C concentration relative to Ni concentration increases the amount of carbon not involved in nickel gettering, facilitating carbon diffusion from the gettering layer 60g to the n-type impurity region 67n. As shown in FIG. 7 , the relationship between the Ni / O ratio and the dark current is similar to the relationship between the Ni / C ratio and the dark current. In other words, the dark current decreases as the Ni / O ratio decreases, but the dark current increases when the Ni / O ratio decreases by a certain level or more. This is also thought to be because an increase in the O concentration relative to the Ni concentration increases the amount of oxygen that is not involved in the gettering of nickel, making it easier for oxygen to diffuse from the gettering layer 60 g to the n-type impurity region 67 n. Note that in Figures 6 and 7, the dark current does not decrease by more than a predetermined amount, but this is thought to be due to dark current caused by contamination of the semiconductor substrate 60 due to causes other than those attributable to the silicide region SR and the gettering layer 60 g.

[0118] Thus, it can be seen that the impurity elements in the gettering layer 60g introduced to reduce dark current can act to suppress the reduction of dark current. Therefore, by controlling the concentration of the impurity elements in the gettering layer 60g within the concentration range required for gettering in accordance with the concentration of the metal element of the metal silicide in the silicide region SR, the leakage current in the semiconductor substrate 60 can be effectively reduced.

[0119] For example, when the concentration of the metal element of the metal silicide in the silicide region SR is A and the concentration of carbon in the gettering layer 60g is B, the image pickup device 100A satisfies 1 < A / B < 400,000. The image pickup device 100A may also satisfy 10 < A / B < 7,000. As shown in FIG. 6 , when A / B is within these ranges, dark current can be effectively reduced.

[0120] Furthermore, for example, the imaging device 100A satisfies 2<A / C<10,000 when the concentration of the metal element of the metal silicide in the silicide region SR is A and the concentration of oxygen in the gettering layer 60g is C. The imaging device 100A may also satisfy 40<A / C<200. As shown in FIG. 7 , when A / C is within these ranges, dark current can be effectively reduced.

[0121] Here, A is the peak value of the concentration of the metal element of the metal silicide at a position corresponding to the silicide region SR, B is the peak value of the concentration of carbon at a position corresponding to the gettering layer 60g, and C is the peak value of the concentration of oxygen at a position corresponding to the gettering layer 60g. A, B, and C are measured, for example, by the SIMS analysis described above.

[0122] [Position of Gettering Layer] As described above, the impurity elements in the gettering layer 60g can affect leakage currents such as dark currents. Therefore, the positional relationship between the gettering layer 60g and impurity regions such as the n-type impurity region 67n can also affect the leakage current. In the semiconductor substrate 60, the diffusion coefficient of a metal such as nickel used to form the silicide region SR is greater than the diffusion coefficients of carbon and oxygen contained in the gettering layer 60g. Because the gettering layer 60g faces the silicide region SR via the n-type impurity region 67n, although the gettering layer 60g is farther from the silicide region SR than the n-type impurity region 67n, due to the above-described diffusion coefficient relationship, the metal such as nickel diffuses beyond the n-type impurity region 67n to the gettering layer 60g and is gettered. 4, the distance L1 between the n-type impurity region 67n and the gettering layer 60g may be longer than the distance L2 between the silicide region SR of the contact plug cp1 and the n-type impurity region 67n. As described above, the diffusion coefficient of metals such as nickel is greater than that of carbon, oxygen, etc., so even if the distance L2 is short, metals such as nickel are likely to diffuse beyond the n-type impurity region 67n to the gettering layer 60g and be gettered. On the other hand, a long distance L1 prevents carbon, oxygen, etc. contained in the gettering layer 60g from diffusing into the n-type impurity region 67n. This reduces the leakage current in the n-type impurity region 67n.

[0123] The distance L1 between the n-type impurity region 67n and the gettering layer 60g is, for example, 2 μm or more. The distance L1 may be 3 μm or more. The distance L1 may also be 10 μm or less, or 5 μm or less.

[0124] 4, the n-type impurity region 67n is located in the epitaxial layer 60b, and the gettering layer 60g is located in the base substrate 60a rather than in the epitaxial layer 60b, thereby separating the gettering layer 60g from the n-type impurity region 67n. This reduces the influence of impurity elements in the gettering layer 60g diffusing into the n-type impurity region 67n located in the epitaxial layer 60b, thereby reducing leakage current. Furthermore, the n-type impurity region 67n is located in the highly crystalline epitaxial layer 60b, away from the gettering layer 60g, which is prone to crystallinity disturbance, thereby further reducing leakage current.

[0125] [Modifications] Next, a description will be given of modifications of embodiment 1. The following description will focus on differences from embodiment 1, and descriptions of commonalities will be omitted or simplified.

[0126] In the image pickup device 100A described above, the peripheral circuit 40 is disposed in the peripheral region R2 of the semiconductor substrate 60. However, this is not limiting. At least a portion of the peripheral circuit 40 may be disposed on a semiconductor substrate other than the semiconductor substrate 60 on which the plurality of pixels 10A are formed. In other words, at least a portion of the peripheral circuit 40 does not need to be disposed on the peripheral region R2. In this case, the other semiconductor substrate may be stacked on the semiconductor substrate 60. FIG. 8 is a schematic cross-sectional view of the device structure of the image pickup device 100A1 according to this modification. For clarity, FIG. 8 omits the cross-sectional shading of the insulating layers 70 and 72, the interlayer insulating layers 90 and 220, and the element isolation region in the semiconductor substrate 210. Also, FIG. 8 illustrates transistors and wiring as some circuit elements included in the peripheral circuit 40.

[0127] 8 , the imaging device 100A1 may further include a peripheral circuit layer 200. The peripheral circuit layer 200 is a logic circuit chip including a semiconductor substrate 210 on which a peripheral circuit 40 is formed and an interlayer insulating layer 220 on the semiconductor substrate 210. Note that a portion of the peripheral circuit 40 may be formed on the semiconductor substrate 60.

[0128] A semiconductor substrate 60 on which the pixels 10A are formed is stacked on the peripheral circuit layer 200. The semiconductor substrate 60 is stacked on the peripheral circuit layer 200, for example, after the base substrate 60a has been thinned so that the gettering layer 60g remains. The lower surface of the semiconductor substrate 60 and the upper surface of the interlayer insulating layer 220 are bonded together. In the imaging device 100A, for example, the thickness of the semiconductor substrate 60 is thinner than the thickness of the semiconductor substrate 210. This allows the wiring connecting the circuits formed on the semiconductor substrate 60 and the circuits formed on the semiconductor substrate 210 to be shorter, thereby reducing resistance and improving the transmission speed of signals from the pixels 10A. As a result, the influence of noise can also be reduced relatively.

[0129] The semiconductor wafer 210 includes a base wafer 210a and an epitaxial layer 210b including one or more semiconductor layers formed on the base wafer 210a. The base wafer 210a is, for example, a p-type silicon wafer. In the example shown in Figure 8, the epitaxial layer 210b includes an n-type semiconductor layer 211n on the base wafer 210a, an n-type semiconductor layer 212n on the n-type semiconductor layer 211n, and a p-type semiconductor layer 213p located in a region different from the n-type semiconductor layer 212n on the n-type semiconductor layer 211n.

[0130] The peripheral circuit 40 includes a plurality of transistors each having a source and a drain formed in the n-type semiconductor layer 212 n and the p-type semiconductor layer 213 p , and a wiring structure formed in the interlayer insulating layer 220 .

[0131] In this way, by stacking the semiconductor substrate 60 on the peripheral circuit layer 200 in which at least a part of the peripheral circuit 40 is provided, the imaging device 100A1 can be made smaller.

[0132] (Embodiment 2) Next, a description will be given of embodiment 2. The following description will focus on the differences from embodiment 1, and the description of commonalities will be omitted or simplified.

[0133] 9 is a schematic cross-sectional view showing the device structure of pixel 10B of the imaging device according to the present embodiment. For ease of viewing, the hatching showing the cross sections of insulating layers 70 and 72 and interlayer insulating layer 90 is omitted in FIG.

[0134] The imaging device according to the present embodiment has a configuration in which pixel 10A of imaging device 100A according to embodiment 1 is changed to pixel 10B. Pixel 10B shown in Fig. 9 differs from pixel 10A according to embodiment 1 in that it includes a contact plug cp1a instead of contact plug cp1.

[0135] Unlike the contact plugs cp2, cp3, cp4, cp5, cp6, and cp7, the contact plug cp1a does not include a silicide region SR. The contact plug cp1a is formed of polysilicon doped with impurities such as n-type impurities. The main component element of the contact plug cp1a is, for example, silicon. For example, by forming silicide regions SR in the contact plugs cp2, cp3, cp4, cp5, cp6, and cp7 while the contact plug cp1a is protected by a protective film, the contact plug cp1a that does not include the silicide region SR can be formed. In this embodiment, one of the contact plugs cp2, cp3, and cp4 is an example of a first plug. Also, in this embodiment, one of the n-type impurity regions 68an, 68bn, and 68dn connected to that one of the contact plugs cp2, cp3, and cp4 is an example of a first impurity region. In this embodiment, the contact plug cp1a is an example of a second plug. In this embodiment, the n-type impurity region 67n is an example of a second impurity region. A plug pa1 is connected to the upper surface of the contact plug cp1a. Although not shown, an oxide film is formed on the upper surface and side surfaces of the contact plug cp1a, and the plug pa1 penetrates the oxide film.

[0136] In pixel 10B, contact plug cp1a, which does not include a silicide region SR, is connected to n-type impurity region 67n, which serves as a charge storage region. This reduces the diffusion of metal impurities into n-type impurity region 67n, further suppressing dark current. Furthermore, contact plugs cp2, cp3, cp4, cp5, cp6, and cp7 include silicide regions SR, thereby improving the driving capabilities of transistors connected to these contact plugs. In particular, contact plugs cp3, cp4, cp6, and cp7 connected to amplifier transistor 22 and address transistor 24, which output pixel signals, include silicide regions SR, thereby reducing the contact resistance between these contact plugs and the metal. This allows, for example, faster pixel signal readout, which directly affects the frame rate. Furthermore, metal impurities diffusing from the silicide region SR are gettered by gettering layer 60g, thereby reducing leakage current in the semiconductor substrate 60.

[0137] In pixel 10B, the concentration of the Group 14 element other than silicon in gettering layer 60g does not have to be uniform in plan view, and for example, the concentration may be lower at a position overlapping n-type impurity region 67n in plan view than at a position not overlapping n-type impurity region 67n in plan view. In pixel 10B, gettering layer 60g does not have to be formed at a position overlapping n-type impurity region 67n in plan view.

[0138] In the imaging device according to this embodiment, the semiconductor substrate 60 may be stacked on the peripheral circuit layer 200 as in the imaging device 100A1.

[0139] (Embodiment 3) Next, a description will be given of embodiment 3. The following description will focus on the differences from embodiments 1 and 2, and the description of commonalities will be omitted or simplified.

[0140] Fig. 10 is a schematic cross-sectional view showing the device structure of the image pickup device 100C according to the present embodiment. For ease of viewing, the hatching showing the cross sections of the insulating layers 70 and 72, the interlayer insulating layers 90, 91 and 220, and the insulating film 95 has been omitted from Fig. 10. Fig. 10 also shows the device structure of the image pickup device 100C above the vicinity of the top surface of the peripheral circuit layer 200. The configuration of the peripheral circuit layer 200 is as described above with reference to Fig. 8.

[0141] The imaging device 100C according to the present embodiment has a configuration in which the pixel 10A of the imaging device 100A1 according to the modified example of the first embodiment is replaced with a pixel 10C. The main difference between the pixel 10C and the pixel 10A is that the amplification transistor 22, address transistor 24, and reset transistor 26 of the signal detection circuit 14 are separately arranged on semiconductor substrates 60 and 110 that are stacked on each other. The circuit configuration of the pixel 10C is the same as that of the pixel 10A.

[0142] Specifically, as shown in FIG. 10, the pixel 10C differs from the pixel 10A in that the pixel 10C further includes a semiconductor substrate 110 and a through electrode pt.

[0143] 10 , the pixel 10C generally includes a semiconductor substrate 60, a semiconductor substrate 110 arranged above the semiconductor substrate 60, a photoelectric conversion unit 12 arranged above the semiconductor substrate 110, and a wiring structure 81. The wiring structure 81 is arranged in the semiconductor substrate 110, in an interlayer insulating layer 90 formed between the photoelectric conversion unit 12 and the semiconductor substrate 110, and in an interlayer insulating layer 91 formed between the semiconductor substrate 110 and the semiconductor substrate 60. The semiconductor substrates 60 and 110 and the interlayer insulating layers 90 and 91 are formed continuously over at least the entire imaging region R1, for example, and are shared by a plurality of pixels 10C.

[0144] In the example shown in FIG. 10 , the interlayer insulating layer 91 has a stacked structure including three insulating layers: insulating layers 91a, 91b, and 91c. The number of insulating layers included in the interlayer insulating layer 91 is not particularly limited. The wiring structure 81 includes a through electrode pt penetrating the semiconductor substrate 110 and connection structures 81a and 81b electrically connected to each other by the through electrode pt. The through electrode pt and the connection structures 81a and 81b function as a charge storage region that stores signal charges generated by the photoelectric conversion unit 12. The connection structure 81a is located within the interlayer insulating layer 90 and electrically connects the through electrode pt to the gate electrode 22e and the pixel electrode 12a. The connection structure 81b is located within the interlayer insulating layer 91 and electrically connects the through electrode pt to the n-type impurity region 67n. The wiring structure 81 is the same as the wiring structure 80 in that it includes contact plugs cp1, cp2, cp3, cp4, cp5, cp6, and cp7, as well as plugs such as plugs pa1 and pa2 connected to these contact plugs. The contact plugs cp6 and pa2 are part of a connection structure 81a, and the contact plugs cp1 and pa1 are part of a connection structure 81b.

[0145] In pixel 10C, a reset transistor 26 is formed on the semiconductor substrate 60, and an amplifier transistor 22 and an address transistor 24 are formed on the semiconductor substrate 110. A wiring structure 81 electrically connects the photoelectric conversion unit 12 to the signal detection circuit 14 formed on the semiconductor substrates 60 and 110. The reset transistor 26 is disposed on the upper surface of the semiconductor substrate 60, and the amplifier transistor 22 and address transistor 24 are disposed on the upper surface of the semiconductor substrate 110. In other words, the surface of the semiconductor substrate 60 on which the reset transistor 26 is disposed and the surface of the semiconductor substrate 110 on which the amplifier transistor 22 and address transistor 24 are disposed do not face each other but face in the same direction. The upper surfaces of the semiconductor substrates 60 and 110 are the surfaces of the semiconductor substrates 60 and 110 on the photoelectric conversion unit 12 side, respectively.

[0146] The semiconductor substrate 110 is disposed between the semiconductor substrate 60 and the photoelectric conversion unit 12. The semiconductor substrate 110 includes a base substrate 110a and an epitaxial layer 110b including one or more semiconductor layers formed on the base substrate 110a. The one or more semiconductor layers included in the epitaxial layer 110b have, for example, a layer configuration of the same conductivity type as the one or more semiconductor layers included in the epitaxial layer 60b.

[0147] The base substrate 110a is, for example, a p-type silicon substrate. The impurity concentration of the base substrate 110a is, for example, the same as the impurity concentration of the base substrate 60a. In the example shown in FIG. 10 , a gettering layer is not provided in the base substrate 110a, but a gettering layer may also be provided in the base substrate 110a. In the example shown in FIG. 10 , the epitaxial layer 110b includes a p-type semiconductor layer 111p on the base substrate 110a, an n-type semiconductor layer 112n on the p-type semiconductor layer 111p, a p-type semiconductor layer 113p on the n-type semiconductor layer 112n, and a p-type semiconductor layer 115p on the p-type semiconductor layer 113p. The p-type semiconductor layer 111p, the p-type semiconductor layer 113p, and the p-type semiconductor layer 115p are semiconductor layers containing p-type impurities. The configuration of one or more semiconductor layers included in the epitaxial layer 110b is not particularly limited and can be designed according to the purpose. Furthermore, at least a portion of the semiconductor substrate 110 other than the p-type semiconductor layer 115p may be removed by thinning.

[0148] In this example, the semiconductor substrate 110 also includes a p-type region 114p provided between the p-type semiconductor layer 115p and the base substrate 110a, penetrating the p-type semiconductor layer 111p, the n-type semiconductor layer 112n, and the p-type semiconductor layer 113p. The p-type region 114p does not have to penetrate the p-type semiconductor layer 113p and reach the p-type semiconductor layer 115p, as long as it reaches the p-type semiconductor layer 113p. The p-type region 114p has a higher impurity concentration than the p-type semiconductor layers 113p and 115p, and electrically connects the p-type semiconductor layers 113p and 115p to the base substrate 110a.

[0149] During operation of the imaging device 100C, the potentials of the p-type semiconductor layers 113p and 115p and the base substrate 110a are controlled via contacts (not shown) provided outside the imaging region R1. By arranging the p-type semiconductor layer 115p so as to be in contact with the p-type semiconductor layer 113p, the potential of the p-type semiconductor layer 115p can also be controlled via the p-type semiconductor layer 113p during operation of the imaging device 100C. Note that a contact may be provided on the p-type semiconductor layer 115p on the side opposite to the base substrate 110a, and the potential may be controlled via the contact.

[0150] In the pixel 10C, the n-type impurity regions 67n and 68an are located in the p-type semiconductor layer 65p, and the n-type impurity regions 68bn, 68cn, and 68dn are located in the p-type semiconductor layer 115p.

[0151] The through electrode pt penetrates the semiconductor substrate 110 and electrically connects the wiring layer 80b and the plug pa1. Therefore, the n-type impurity region 67n and the gate electrode 22e of the amplification transistor 22 are electrically connected to each other via the contact plugs cp1 and cp6, the plugs pa1 and pa2, the through electrode pt, and the wiring layer 80b. The through electrode pt is formed of, for example, a metal such as copper or tungsten, polysilicon doped with impurities, or a metal compound such as a metal nitride or a metal oxide.

[0152] An insulating film 95 is disposed between the through electrode pt and the semiconductor substrate 110, and the through electrode pt is not in contact with the semiconductor substrate 110. The insulating film 95 is, for example, a silicon oxide film.

[0153] In the present embodiment, with the above-described configuration, the amplification transistor 22 and the address transistor 24 are provided in the p-type semiconductor layer 115p of the semiconductor substrate 110, and the reset transistor 26 is provided in the p-type semiconductor layer 65p of a semiconductor substrate 60 different from the semiconductor substrate 110. This allows for a reduction in pixel size in a planar view, thereby enabling the miniaturization of the imaging device 100C. Furthermore, since the n-type impurity region 67n, which is a charge accumulation region, is formed in the semiconductor substrate 60 provided with the gettering layer 60g, a gettering effect of metal impurities by the gettering layer 60g is obtained, thereby reducing dark current.

[0154] In the imaging device 100C, the positions of the semiconductor substrate 110 and the semiconductor substrate 60 may be interchanged in the example described above. That is, the semiconductor substrate 60 may be disposed between the semiconductor substrate 110 and the photoelectric conversion unit 12. In addition, in the imaging device 100C, at least a portion of the peripheral circuit 40 may be provided on at least one of the semiconductor substrate 60 and the semiconductor substrate 110 in the peripheral region R2, rather than on the peripheral circuit layer 200. Therefore, the imaging device 100C may not include the peripheral circuit layer 200. In addition, the pixel 10C may include a contact plug cp1a instead of the contact plug cp1, as in the pixel 10B.

[0155] (Fourth Embodiment) Next, a description will be given of a fourth embodiment. The following description will focus on the differences from the first to third embodiments, and the description of the commonalities will be omitted or simplified.

[0156] Fig. 11 is a schematic cross-sectional view showing the device structure of the image pickup device 100D according to the present embodiment. For ease of viewing, the hatching indicating the cross section of the insulating layers 70, 72, and 97, the interlayer insulating layers 91, 92, and 220, and the insulating film 96 has been omitted from Fig. 11. Fig. 11 also shows the device structure of the image pickup device 100D above the vicinity of the top surface of the peripheral circuit layer 200. The configuration of the peripheral circuit layer 200 is as described above with reference to Fig. 8.

[0157] The imaging device 100D according to the present embodiment has a configuration in which the pixel 10C of the imaging device 100C according to the third embodiment is replaced with a pixel 10D. The main difference between the pixel 10D and the pixel 10C is that the orientation of the semiconductor substrate 110 is reversed in the up-down direction. The circuit configuration of the pixel 10D is the same as that of the pixel 10A.

[0158] 11 , pixel 10D generally includes a semiconductor substrate 60, a semiconductor substrate 110 arranged above the semiconductor substrate 60, a photoelectric conversion unit 12 arranged above the semiconductor substrate 110, and a wiring structure 82. The wiring structure 82 is arranged in the semiconductor substrate 110, in an insulating layer 97 formed between the photoelectric conversion unit 12 and the semiconductor substrate 110, and in interlayer insulating layers 91 and 92 formed between the semiconductor substrate 110 and the semiconductor substrate 60. The semiconductor substrates 60 and 110 and the interlayer insulating layers 91 and 92 are formed continuously over at least the entire imaging region R1, for example, and are shared by a plurality of pixels 10D.

[0159] In the example shown in FIG. 11 , the interlayer insulating layer 92 has a stacked structure including three insulating layers: insulating layers 90a, 90b, and 90c. The number of insulating layers included in the interlayer insulating layer 92 is not particularly limited. The wiring structure 82 includes a through electrode pt1 penetrating the semiconductor substrate 110 and connection structures 82a and 82b connected to each other at a junction surface 85. The through electrode pt1 and the connection structures 82a and 82b function as a charge storage region that stores signal charges generated by the photoelectric conversion unit 12. The connection structure 82a is located within the interlayer insulating layer 92 and electrically connects the through electrode pt1, the connection structure 82b, and the gate electrode 22e. The connection structure 82b is located within the interlayer insulating layer 91 and electrically connects the connection structure 82a and the n-type impurity region 67n. The wiring structure 82 is similar to the wiring structure 80 in that it includes contact plugs cp1, cp2, cp3, cp4, cp5, cp6, and cp7, as well as plugs connected to these contact plugs. The contact plug cp6 and plug pa2 are part of the connection structure 82a, and the contact plug cp1 and plug pa1 are part of the connection structure 82b.

[0160] At the bonding surface 85, the insulating materials of the interlayer insulating layers 91 and 92 and the metal wirings of the connection structures 82a and 82b form a metal-dielectric hybrid junction. The bonding surface 85 is formed continuously over at least the entire imaging region R1, for example.

[0161] In pixel 10D, similarly to pixel 10C, a reset transistor 26 is formed on the semiconductor substrate 60, and an amplification transistor 22 and an address transistor 24 are formed on the semiconductor substrate 110. A wiring structure 82 electrically connects the photoelectric conversion unit 12 to the signal detection circuits 14 formed on the semiconductor substrates 60 and 110.

[0162] In pixel 10D, the stacking order in the semiconductor substrate 110 is reversed in the vertical direction from that in pixel 10C. That is, in pixel 10C, the epitaxial layer 110b is located above the base substrate 110a, and the p-type semiconductor layer 115p is the uppermost layer in the semiconductor substrate 110, but in pixel 10D, the epitaxial layer 110b is located below the base substrate 110a, and the p-type semiconductor layer 115p is the lowermost layer in the semiconductor substrate 110. In pixel 10D, the photoelectric conversion unit 12 is disposed on an insulating layer 97 on the upper surface of the semiconductor substrate 110.

[0163] In pixel 10D, the reset transistor 26 is disposed on the upper surface of the semiconductor substrate 60, and the amplifier transistor 22 and address transistor 24 are disposed on the lower surface of the semiconductor substrate 110. In other words, the surface of the semiconductor substrate 60 on which the reset transistor 26 is disposed faces the surface of the semiconductor substrate 110 on which the amplifier transistor 22 and address transistor 24 are disposed. The lower surface of the semiconductor substrate 110 is the surface of the semiconductor substrate 110 opposite to the photoelectric conversion unit 12 side.

[0164] The through electrode pt1 penetrates the semiconductor substrate 110 and electrically connects the wiring layer 80b and the pixel electrode 12a. The through electrode pt1 functions as a charge accumulation region that accumulates signal charges generated by the photoelectric conversion unit 12. The n-type impurity region 67n and the gate electrode 22e of the amplification transistor 22 are electrically connected to each other via contact plugs cp1 and cp6, plugs pa1 and pa2, and the wiring layer 80b, without going through the through electrode pt1. The through electrode pt1 is formed of, for example, a metal such as copper or tungsten, polysilicon doped with impurities, or a metal compound such as a metal nitride or a metal oxide.

[0165] An insulating film 96 is disposed between the through electrode pt1 and the semiconductor substrate 110, and the through electrode pt1 is not in contact with the semiconductor substrate 110. The insulating film 96 is, for example, a silicon oxide film.

[0166] With the above-described configuration, the amplifier transistor 22, address transistor 24, and reset transistor 26 are provided on different semiconductor substrates, which enables a reduction in pixel size and a miniaturization of the image pickup device 100D. Furthermore, the n-type impurity region 67n that accumulates signal charge is provided on the semiconductor substrate 60, which is farther from the photoelectric conversion unit 12 than the semiconductor substrate 110. This prevents light that is not absorbed by the photoelectric conversion unit 12 from being incident on the n-type impurity region 67n and generating charge. This allows the image pickup device 100D to have low noise.

[0167] Furthermore, in the pixel 10D, the surface of the semiconductor substrate 60 on which the reset transistor 26 is disposed faces the surface of the semiconductor substrate 110 on which the amplifier transistor 22 and address transistor 24 are disposed. Therefore, even when the amplifier transistor 22 and the reset transistor 26 are connected via the connection structures 82a and 82b, the connection can be achieved without the through-electrode pt1 that penetrates the semiconductor substrate 110, allowing the connection structures 82a and 82b to be short. This reduces the parasitic capacitance between the connection structures 82a and 82b between adjacent pixels 10D. As a result, the capacitance of the connection structures 82a and 82b, which function as charge accumulation regions, can be reduced, thereby increasing the potential change due to the accumulation of signal charge and increasing the conversion gain of the charge accumulation region. This increases the signal corresponding to the charge generated by photoelectric conversion, reducing the influence of noise, thereby enabling the imaging device 100D to achieve low noise.

[0168] In the image pickup device 100D, the positions of the semiconductor substrate 110 and the semiconductor substrate 60 may be interchanged in the example described above. That is, the semiconductor substrate 60 may be disposed between the semiconductor substrate 110 and the photoelectric conversion unit 12, and the up-down orientation of the semiconductor substrate 60 may be reversed compared to that of the pixel 10C. In addition, in the image pickup device 100D, at least a portion of the peripheral circuit 40 may be provided on at least one of the semiconductor substrate 60 and the semiconductor substrate 110 in the peripheral region R2, rather than on the peripheral circuit layer 200. Therefore, the image pickup device 100D may not include the peripheral circuit layer 200. In addition, the pixel 10D may include a contact plug cp1a instead of the contact plug cp1, as in the pixel 10B.

[0169] (Embodiment 5) Next, a description will be given of embodiment 5. The following description will focus on the differences from embodiments 1 to 4, and the description of commonalities will be omitted or simplified.

[0170] FIG. 12 is a diagram showing the configuration of an image pickup device 100E according to this embodiment. FIG. 13 is a schematic cross-sectional view showing the device structure of the image pickup device 100E according to this embodiment. FIG. 13 shows a cross section taken along a position corresponding to line XIII-XIII in FIG. 12. Note that FIG. 13 does not show a detailed illustration of the device structure of the pixel 10A formed in the image pickup region R1. The device structure of the pixel 10A is as described above with reference to FIG. 4. Furthermore, for ease of viewing, FIG. 13 does not include shading indicating the cross section of the interlayer insulating layer 90 and the element isolation region 169.

[0171] 12 and 13 , the imaging device 100E according to this embodiment has a configuration in which the semiconductor substrate 60 of the imaging device 100A is replaced with a semiconductor substrate 160. The main difference between the semiconductor substrate 60 and the semiconductor substrate 160 is that a substrate potential supply region R3 is present between the imaging region R1 in which the plurality of pixels 10A are arranged and the peripheral region R2 in which the peripheral circuit 40 is arranged, and an impurity region including a silicide region SR1 is arranged in the substrate potential supply region R3. The imaging device 100E also includes a plurality of contact plugs cpm1 and a plurality of contact plugs cpm2. The plurality of contact plugs cpm1 and the plurality of contact plugs cpm2 are formed, for example, from a metal such as copper or tungsten, or a metal compound such as a metal nitride or a metal oxide.

[0172] 12 , the substrate potential supply region R3 is disposed outside the imaging region R1 and surrounds the imaging region R1. The substrate potential supply region R3 can supply a voltage for controlling the potential of the well and semiconductor layer of the semiconductor substrate 160. Note that the substrate potential supply region R3 does not have to surround the imaging region R1 as long as it is disposed outside the imaging region R1. The substrate potential supply region R3 is disposed, for example, along at least one of the four outer periphery sides of the imaging region R1.

[0173] 13, the semiconductor substrate 160 includes a base substrate 60a and an epitaxial layer 160b including one or more semiconductor layers formed on the base substrate 60a. The base substrate 60a and the gettering layer 60g located within the base substrate 60a are formed continuously over the entire semiconductor substrate 160, for example.

[0174] 13 , the epitaxial layer 160b includes, in the imaging region R1, an n-type semiconductor layer 62n on the base substrate 60a, a p-type semiconductor layer 63p and a p-type semiconductor layer 165p on the n-type semiconductor layer 62n, a p-type semiconductor layer 65p on the p-type semiconductor layer 63p, and a p-type region 64p. In the substrate potential supply region R3, the epitaxial layer 160b includes the n-type semiconductor layer 62n on the base substrate 60a, a p-type semiconductor layer 165p located in a region different from the n-type semiconductor layer 62n on the base substrate 60a, a p-type semiconductor layer 161p on the n-type semiconductor layer 62n, an n-type semiconductor layer 162n located in a region different from the p-type semiconductor layer 161p on the n-type semiconductor layer 62n, a p-type semiconductor layer 163p on the p-type semiconductor layer 165p, and a p-type region 164p electrically connecting the base substrate 60a and the p-type semiconductor layer 161p or 163p. In the peripheral region R2, the epitaxial layer 160b includes an n-type semiconductor layer 62an on the base substrate 60a, and an n-type semiconductor layer 166n, a p-type semiconductor layer 167p, an n-type semiconductor layer 168n, and a p-type semiconductor layer 169p located in different regions on the n-type semiconductor layer 62an. The epitaxial layer 160b may further include a p-type semiconductor layer 61p on the base substrate 60a.

[0175] The semiconductor substrate 160 further includes p-type impurity regions 171p, 173p, and 178p, n-type impurity regions 172n, 177n, and 179n, and an element isolation region 169. The p-type impurity regions 171p, 173p, and 178p and n-type impurity regions 172n, 177n, and 179n are located in the epitaxial layer 160b and separated from the gettering layer 60g. The p-type impurity regions 171p, 173p, and 178p and n-type impurity regions 172n, 177n, and 179n are located at positions different from the impurity regions included in the pixel 10A, such as the n-type impurity region 67n, in a planar view. The element isolation region 169 is located in the epitaxial layer 160b and electrically isolates the impurity regions or transistors in the epitaxial layer 160b. The element isolation region 169 is formed using, for example, STI.

[0176] 13 , the p-type impurity region 171p, the n-type impurity region 172n, and the p-type impurity region 173p are located in the p-type semiconductor layer 161p, the n-type semiconductor layer 162n, and the p-type semiconductor layer 163p, respectively, and are provided so as to be exposed at the upper surfaces of the p-type semiconductor layer 161p, the n-type semiconductor layer 162n, and the p-type semiconductor layer 163p. The p-type impurity region 171p, the n-type impurity region 172n, and the p-type impurity region 173p have higher impurity concentrations than the p-type semiconductor layer 161p, the n-type semiconductor layer 162n, and the p-type semiconductor layer 163p, respectively. The p-type impurity region 171p, the n-type impurity region 172n, and the p-type impurity region 173p are each arranged so as to surround the imaging region R1 in a plan view, for example.

[0177] The p-type impurity region 171p, the n-type impurity region 172n, and the p-type impurity region 173p each include a silicide region SR1. The silicide region SR1 is, for example, a silicide layer containing a metal silicide formed by depositing a metal on the surface of each of the p-type impurity region 171p, the n-type impurity region 172n, and the p-type impurity region 173p and then reacting the metal with polysilicon. The silicide region SR1 is formed on the upper surface of each of the p-type impurity region 171p, the n-type impurity region 172n, and the p-type impurity region 173p.

[0178] P-type impurity region 171p, n-type impurity region 172n, and p-type impurity region 173p are each in contact with a plurality of contact plugs cpm1, which are an example of plugs, in silicide region SR1. The potential of base substrate 60a and p-type semiconductor layer 65p is controlled via a plurality of contact plugs cpm1, p-type impurity region 171p, and p-type impurity region 173p. The potential of n-type semiconductor layer 62n is controlled via a plurality of contact plugs cpm1 and n-type impurity region 172n. Contact between p-type impurity region 171p, n-type impurity region 172n, and p-type impurity region 173p and a plurality of contact plugs cpm1 in silicide region SR1 reduces contact resistance, enabling stable potential control.

[0179] In the substrate potential supply region R3, the gettering layer 60g faces the plurality of contact plugs cpm1 via the p-type impurity region 171p, the n-type impurity region 172n, and the p-type impurity region 173p. Metal impurities from the silicide region SR1 are gettered by the gettering layer 60g, making it difficult for the metal impurities to diffuse into the imaging region R1, thereby suppressing dark current.

[0180] Furthermore, the distance L3 between the silicide region SR1 of the p-type impurity region 171p closest to the imaging region R1 and the gettering layer 60g is shorter than the distance L4 between the silicide region SR1 and the n-type impurity region 67n closest to the substrate potential supply region R3. This makes it easier for metal impurities to be gettered by the gettering layer 60g before they reach the n-type impurity region 67n. This further suppresses the diffusion of metal impurities into the n-type impurity region 67n, thereby further suppressing dark current. In this embodiment, the n-type impurity region 67n is an example of a first impurity region, the p-type impurity region 171p is an example of a second impurity region, and the gettering layer 60g is an example of a third impurity region.

[0181] 14 is a plan view of the silicide region SR1 in the substrate potential supply region R3. For ease of viewing, the components shown in the plan view in FIG. 14 are shaded in the same manner as the components shown in the cross section in FIG. 13 . As shown in FIG. 14 , the p-type impurity region 171p, the n-type impurity region 172n, and the p-type impurity region 173p, which include the silicide region SR1, extend in a strip-like shape. Furthermore, a plurality of contact plugs cpm1 are arranged in a plurality of rows on the silicide region SR1 along the direction in which the silicide region SR1 extends in a strip-like shape. In this way, the plurality of contact plugs cpm1 are arranged in a plurality of rows and connected to the silicide region SR1, thereby further reducing the resistance for supplying a potential to the semiconductor substrate 160. Furthermore, since the substrate potential supply region R3 in which the silicide region SR1 is arranged is located between the imaging region R1 and the peripheral region R2, the multiple contact plugs cpm1 arranged in multiple columns can effectively suppress electrostatic coupling between the peripheral circuit 40 and the circuit of the pixel 10A.

[0182] 13, n-type impurity region 177n, p-type impurity region 178p, and n-type impurity region 179n are located in p-type semiconductor layer 167p, n-type semiconductor layer 168n, and p-type semiconductor layer 169p, respectively, and are provided so as to be exposed at the upper surfaces of p-type semiconductor layer 167p, n-type semiconductor layer 168n, and p-type semiconductor layer 169p. N-type impurity region 177n, p-type impurity region 178p, and n-type impurity region 179n are sources or drains of transistors included in peripheral circuit 40, respectively.

[0183] The n-type impurity region 177n, the p-type impurity region 178p, and the n-type impurity region 179n each include a silicide region SR2. The silicide region SR2 is, for example, a silicide layer containing a metal silicide formed by depositing a metal on the surface of each of the n-type impurity region 177n, the p-type impurity region 178p, and the n-type impurity region 179n and then reacting the metal with polysilicon. The silicide region SR2 is formed on the upper surface of each of the n-type impurity region 177n, the p-type impurity region 178p, and the n-type impurity region 179n.

[0184] The n-type impurity region 177n, the p-type impurity region 178p, and the n-type impurity region 179n are in contact with the contact plug cpm2 at the silicide region SR2. This reduces the contact resistance between the n-type impurity region 177n, the p-type impurity region 178p, and the n-type impurity region 179n and the contact plug cpm2. This improves the driving capability of the transistors in the peripheral circuit 40 that include the n-type impurity region 177n, the p-type impurity region 178p, and the n-type impurity region 179n as their sources or drains. Furthermore, the gate electrode 28e of the transistor included in the peripheral circuit 40 includes the silicide region SR3 at least on its upper surface. This also improves the driving capability of the transistors in the peripheral circuit 40.

[0185] In the peripheral region R2, the gettering layer 60g faces the plurality of contact plugs cpm2 via the n-type impurity region 177n, the p-type impurity region 178p, and the n-type impurity region 179n. The gettering layer 60g also faces the gate electrode 28e via the p-type semiconductor layer 167p, the n-type semiconductor layer 168n, and the p-type semiconductor layer 169p. Metal impurities from the silicide regions SR2 and SR3 are gettered by the gettering layer 60g, making it difficult for the metal impurities to diffuse into the imaging region R1, thereby suppressing dark current.

[0186] The plurality of pixels included in the imaging device 100E are not limited to the pixel 10A. The plurality of pixels included in the imaging device 100E are not particularly limited as long as they include an impurity region that functions as a charge storage region, and may be, for example, the above-described pixel 10B, 10C, or 10D.

[0187] (Embodiment 6) Next, a description will be given of embodiment 6. In embodiment 6, a camera system including an imaging device according to the present disclosure will be described.

[0188] FIG. 15 is a block diagram showing an example of the configuration of a camera system 400 according to this embodiment.

[0189] 15, camera system 400 according to this embodiment includes lens optical system 601, imaging device 602, system controller 603, and camera signal processing circuit 604. Camera system 400 may be, for example, a smartphone, a digital camera, a video camera, or an in-vehicle camera.

[0190] The lens optical system 601 focuses light onto an imaging surface of the imaging device 602. The lens optical system 601 may include, for example, a lens group including an autofocus lens and a zoom lens, and an aperture. The imaging device 602 may be, for example, an imaging device according to any one of the first to fifth embodiments described above.

[0191] The system controller 603 controls the entire camera system 400. The system controller 603 is, for example, a semiconductor integrated circuit, and a specific example is a CPU (Central Processing Unit).

[0192] The camera signal processing circuit 604 has a function of processing an output signal from the image capture device 602. The camera signal processing circuit 604 receives output data from the image capture device 602 and performs processes such as gamma correction, color interpolation, spatial interpolation, and auto white balance. The camera signal processing circuit 604 is, for example, a DSP (Digital Signal Processor). The image capture device 602 and the camera signal processing circuit 604 may be implemented as a single semiconductor device. The semiconductor device may be, for example, a so-called SoC (System on a Chip). This configuration allows for further miniaturization of electronic devices that include the image capture device 602 as a part thereof.

[0193] The camera system 400 according to this embodiment includes an imaging device 602 using an imaging device according to any one of the above-described embodiments 1 to 5, and therefore can realize a low-noise camera system with reduced leakage current.

[0194] While the imaging device and camera system according to the present disclosure have been described above based on the embodiments, the present disclosure is not limited to these embodiments. As long as they do not deviate from the gist of the present disclosure, various modifications conceivable by those skilled in the art to the embodiments, as well as other forms constructed by combining some of the components of the embodiments, are also included within the scope of the present disclosure.

[0195] For example, in the above embodiment, the n-type impurity region 67n is the source or drain of the reset transistor 26, but this is not limiting. For example, the imaging device according to the present disclosure may be configured in such a way that the n-type impurity region 67n is reset via the photoelectric conversion unit 12 without including the reset transistor 26, as in the imaging device disclosed in Patent Document 3.

[0196] Furthermore, for example, in the above embodiment, the imaging device includes the feedback circuit 16, but this is not limiting. The imaging device according to the present disclosure may not include the feedback circuit 16, and may instead supply a reset voltage from a voltage supply circuit to the charge accumulation region via the reset transistor 26 during a reset operation.

[0197] Furthermore, for example, in the above embodiment, the photoelectric conversion unit 12 of each pixel includes the pixel electrode 12 a, the transparent electrode 12 c, and the photoelectric conversion layer 12 b, but this is not limited thereto. The photoelectric conversion unit of each pixel may be a photodiode formed on a semiconductor substrate. Furthermore, each pixel may include a photoelectric conversion unit 12 and a photodiode as a plurality of photoelectric conversion units.

[0198] In the above embodiment, the gettering layer 60g is located in the base substrate 60a, but this is not limiting. The gettering layer 60g may be located in the epitaxial layer 60b or 160b.

[0199] In the above embodiments, the conductivity types and configurations of the layers and impurity regions in each semiconductor substrate are merely examples. For example, part or all of each semiconductor substrate may have a conductivity type opposite to that described above. Also, for example, each semiconductor substrate may not include all of the above layers and impurity regions, or may include at least one layer and impurity region other than the above layers and impurity regions.

[0200] Furthermore, various modifications, substitutions, additions, omissions, etc. can be made to each of the above-described embodiments within the scope of the claims or their equivalents.

[0201] The imaging device according to the present disclosure is useful, for example, in image sensors, digital cameras, etc. The imaging device according to the present disclosure can be used in medical cameras, robot cameras, security cameras, cameras mounted on vehicles, etc.

[0202] 10A, 10B, 10C, 10D Pixel 12 Photoelectric conversion section 12a Pixel electrode 12b Photoelectric conversion layer 12c Transparent electrode 14 Signal detection circuit 16 Feedback circuit 22 Amplifying transistor 22e, 24e, 26e, 28e Gate electrode 24 Address transistor 26 Reset transistor 32 Power supply wiring 34 Address signal line 35 Vertical signal line 36 Reset signal line 39 Storage control line 40 Peripheral circuit 42 Load circuit 44 Column signal processing circuit 46 Vertical scanning circuit 48 Horizontal signal readout circuit 49 Horizontal common signal line 50 Inverting amplifier 53 Feedback line 60, 110, 160, 210 Semiconductor substrate 60a, 110a, 210a Base substrate 60b, 110b, 160b, 210b Epitaxial layer 60g Gettering layer 61p, 63p, 65p, 111p, 113p, 115p, 161p, 163p, 165p, 167p, 169p, 213p P-type semiconductor layer 62n, 62an, 112n, 162n, 166n, 168n, 211n, 212n N-type semiconductor layer 64p, 114p, 164p p-type region 67a first region 67b second region 67n, 68an, 68bn, 68cn, 68dn, 172n, 177n, 179n n-type impurity region 69, 169 element isolation region 70, 71, 72, 90a, 90b, 90c, 90d, 91a, 91b, 91c, 97 Insulating layer 80, 81, 82 Wiring structure 80a, 80b, 80c, 80d Wiring layer 81a, 81b, 82a, 82b Connection structure 85 Bonding surface 90, 91, 92, 220 Interlayer insulating layer 95, 96 Insulating film 100A, 100A1, 100C, 100D, 100E, 602 Imaging device 171p, 173p, 178p P-type impurity region 200 Peripheral circuit layer 400 Camera system 601 Lens optical system 603 System controller 604 Camera signal processing circuit cp1, cp1a, cp2, cp3, cp4, cp5, cp6, cp7, cpm1, cpm2 Contact plug FD Charge storage node h1, h2, h3, h4, h5, h6, h7, h8: contact holes pa1, pa2, pb, pc, pd: plugs pt, pt1: through electrodes R1: imaging region R2: peripheral region R3: substrate potential supply region SR, SR1, SR2, SR3: silicide regions

Claims

1. An imaging device comprising: a photoelectric conversion unit that converts light into electric charges; a semiconductor substrate including a first impurity region and a second impurity region; and a first plug connected to the first impurity region and including a silicide region, wherein one of the first impurity region and the second impurity region is a charge accumulation region electrically connected to the photoelectric conversion unit, and the semiconductor substrate includes a third impurity region containing a Group 14 element other than silicon at a position facing the silicide region through the first impurity region.

2. The imaging device according to claim 1, wherein the first impurity region is the charge accumulation region.

3. The imaging device according to claim 1, further comprising a second plug connected to the second impurity region and not including a silicide region, wherein the second impurity region is a charge accumulation region.

4. The imaging device according to claim 1, wherein the distance between the first impurity region and the third impurity region is longer than the distance between the silicide region and the first impurity region.

5. The third impurity region contains carbon, and the concentration of the metal element of the metal silicide in the silicide region is A [atoms / cm ３ , and the concentration of carbon in the third impurity region is B [atoms / cm ３ . When 1 < A / B < 400000 is satisfied, the imaging device according to any one of claims 1 to 4.

6. The imaging device according to claim 5, satisfying 10 < A / B < 7000.

7. The third impurity region contains the Group 14 element and oxygen, and when the concentration of the metal element of the metal silicide in the silicide region is A [atoms / cm ３ , and the concentration of oxygen in the third impurity region is C, the imaging device according to any one of claims 1 to 4, satisfying 2 < A / C < 10000.

8. The imaging device according to claim 7, satisfying 40 < A / C < 200.

9. The imaging device according to any one of claims 1 to 4, wherein the semiconductor substrate includes a base substrate and an epitaxial layer on the base substrate, the first impurity region and the second impurity region are located in the epitaxial layer, and the third impurity region is located in the base substrate.

10. The imaging device according to any one of claims 1 to 4, wherein the semiconductor substrate includes an imaging region in which a plurality of pixels each including the photoelectric conversion unit, the first impurity region, the second impurity region, and the first plug are arranged, and the third impurity region is continuously arranged over the entire imaging region.

11. The imaging device according to any one of claims 1 to 4, wherein the third impurity region is continuously arranged over the entire semiconductor substrate.

12. An imaging device comprising: a photoelectric conversion unit that converts light into electric charge; a first impurity region electrically connected to the photoelectric conversion unit; a semiconductor substrate including a second impurity region disposed at a position different from the first impurity region in plan view and including a silicide region; and a plug connected to the silicide region of the second impurity region, wherein the semiconductor substrate includes a third impurity region containing a Group 14 element other than silicon at a position facing the plug via the second impurity region, the second impurity region and the third impurity region are separated from each other, and a distance between the silicide region and the third impurity region is shorter than a distance between the silicide region and the first impurity region.

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