Semiconductor element, light detection element, and method for manufacturing semiconductor element

Abstract

The present invention improves the characteristics of a semiconductor element including an oxide semiconductor.　The present technology provides a semiconductor element, for example, comprising an electrode, a semiconductor layer containing an oxide semiconductor, and an insulating layer disposed between the electrode and the semiconductor layer, wherein the oxide semiconductor contains a first element other than oxygen, and the insulating layer contains a second element other than oxygen, the first element and the second element having the same ionic valence. The present technology also provides a method for manufacturing a semiconductor element, the method including forming an insulating layer and laminating one or more layers of each of a plurality of types of oxide layers to form a semiconductor layer. Among the plurality of oxide layers constituting the semiconductor layer, the ionic valence of the oxide layer disposed at the interface with the insulating layer is the same as the ionic valence of the insulating layer.

Description

Semiconductor element, photodetector element, and method for manufacturing semiconductor element

[0001] The technology according to the present disclosure (hereinafter also referred to as "the technology") relates to a semiconductor element, a photodetector element, and a method for manufacturing the semiconductor element.

[0002] For example, Patent Document 1 discloses a technology relating to "a solid-state imaging device comprising a plurality of pixels arranged in a matrix, each of the pixels comprising: a first semiconductor layer; a photoelectric conversion unit arranged on a first surface side of the first semiconductor layer; a storage electrode arranged adjacent to a second surface side of the first semiconductor layer opposite to the first surface; wiring extending from the second surface of the first semiconductor layer; a floating diffusion region connected to the first semiconductor layer via the wiring; and a first gate electrode arranged adjacent to the wiring."

[0003] International Publication No. 2022 / 065153

[0004] However, there is room for improvement in the characteristics of semiconductor elements containing oxide semiconductors.

[0005] Therefore, a main object of the present technology is to improve the characteristics of a semiconductor element including an oxide semiconductor.

[0006] The present technology provides a semiconductor device including: an electrode; a semiconductor layer including an oxide semiconductor; and an insulating layer disposed between the electrode and the semiconductor layer; wherein the oxide semiconductor includes a first element other than oxygen; and the insulating layer includes a second element other than oxygen; and the ionic valence of the first element and the ionic valence of the second element are the same. The semiconductor device may be used in a photodetector. The semiconductor device may be used in a transistor. The semiconductor device may further include a photoelectric conversion layer, wherein the photoelectric conversion layer, the semiconductor layer, and the insulating layer are stacked in this order. A portion of the semiconductor layer may protrude from the side opposite the photoelectric conversion layer and be connected to a floating diffusion region. The ionic valence may be +2, +3, or +4. The semiconductor layer is configured by stacking one or more types of oxide layers, and the ionic valence of an oxide layer disposed at the interface with the insulating layer among the multiple oxide layers constituting the semiconductor layer may be the same as the ionic valence of the insulating layer. The oxide layer disposed at the interface with the insulating layer may contain In2O3. The oxide layer disposed at the interface with the insulating layer may contain Ga2O3. The oxide layer disposed at the interface with the insulating layer may contain Ga2O3. An oxide layer containing In2O3, an oxide layer containing Ga2O3, and the insulating layer may be stacked in this order. The ionic valence of at least one oxide layer among the multiple oxide layers constituting the semiconductor layer may be different from the ionic valence of the insulating layer. The present technology also provides a photodetector element including: a first electrode; a second electrode; a photoelectric conversion layer provided between the first electrode and the second electrode; and a semiconductor layer provided between the first electrode and the photoelectric conversion layer, wherein the semiconductor layer includes at least a first oxide layer containing a first element other than oxygen, a second oxide layer containing a second element other than oxygen, a third oxide layer containing the first element, and a fourth oxide layer containing the second element, wherein the first element is different from the second element. A portion of the semiconductor layer may protrude to a side opposite the photoelectric conversion layer and connect to the second electrode. The device may further include an insulating layer provided between the semiconductor layer and the first electrode.The present technology also provides a method for manufacturing a semiconductor element, comprising: forming an insulating layer; and forming a semiconductor layer by stacking one or more types of oxide layers, wherein, of the multiple oxide layers constituting the semiconductor layer, the ionic valence of an oxide layer disposed at the interface with the insulating layer is the same as the ionic valence of the insulating layer.

[0007] According to the present technology, it is possible to improve the characteristics of a semiconductor element including an oxide semiconductor. Note that the effects described herein are not necessarily limited to those described herein and may be any of the effects described in the present disclosure.

[0008] 13A is a schematic cross-sectional view showing an example of a configuration of a photodetector element (photodetector element 1A) using a semiconductor element according to an embodiment of the present technology. FIG. 13B is a schematic plan view showing an example of a pixel configuration of a photodetector device having the photodetector element 1A shown in FIG. 1. FIG. 13C is an equivalent circuit diagram of the photodetector element 1A shown in FIG. 1. FIG. 13D is a schematic representation of an arrangement of a lower electrode 11 and transistors constituting a control unit of the photodetector element 1A shown in FIG. 1. FIG. 13E is a schematic cross-sectional view showing a method for manufacturing a semiconductor element according to an embodiment of the present technology. FIG. 13F is a schematic cross-sectional view showing a method for manufacturing a semiconductor element according to an embodiment of the present technology. FIG. 13G is a schematic cross-sectional view showing a method for manufacturing a semiconductor element according to an embodiment of the present technology. FIG. 13H is a schematic cross-sectional view showing a method for manufacturing a semiconductor element according to an embodiment of the present technology. FIG. 13I is a schematic cross-sectional view showing a configuration example of a photodetector element 1C according to an embodiment of the present technology. FIG. 13I is a schematic cross-sectional view showing a configuration example of a photodetector element 1D according to an embodiment of the present technology. FIG. 13I is a schematic plan view of the photodetector element 1D shown in FIG. 13A. FIG. 13B is a schematic cross-sectional view showing a configuration example of a photodetector element 1E according to an embodiment of the present technology. FIG. 14B is a schematic plan view of the photodetector element 1E shown in FIG. 14A ; FIG. 14C is a diagram illustrating an example of an overall configuration of a photodetector including a semiconductor element according to an embodiment of the present technology; FIG. 14D is a block diagram illustrating an example of a configuration of an electronic device 1000 according to an embodiment of the present technology; FIG. 14E is a schematic cross-sectional view illustrating an example of a configuration of a semiconductor element according to an embodiment of the present technology; FIG. 14F is a schematic cross-sectional view illustrating an example of a configuration of a semiconductor element according to an embodiment of the present technology; FIG. 14G is a schematic cross-sectional view illustrating an example of a configuration of a semiconductor element according to an embodiment of the present technology; FIG. 14H is a schematic cross-sectional view illustrating an example of a configuration of a semiconductor element according to an embodiment of the present technology; FIG. 14H is a schematic cross-sectional view illustrating an example of a configuration of a semiconductor element according to an embodiment of the present technology;FIG. 1 is a schematic cross-sectional view showing a method for manufacturing a semiconductor element according to an embodiment of the present technology. FIG. 1 is a schematic cross-sectional view showing a method for manufacturing a semiconductor element according to an embodiment of the present technology. FIG. 2 is a schematic cross-sectional view showing a method for manufacturing a semiconductor element according to an embodiment of the present technology. FIG. 3 is a schematic cross-sectional view showing a method for manufacturing a semiconductor element according to an embodiment of the present technology. FIG. 4 is a schematic cross-sectional view showing a method for manufacturing a semiconductor element according to an embodiment of the present technology. FIG. 5 is a schematic cross-sectional view showing a method for manufacturing a semiconductor element according to an embodiment of the present technology. FIG. 6 is a schematic cross-sectional view showing a method for manufacturing a semiconductor element according to an embodiment of the present technology. FIG. 7 is a schematic cross-sectional view showing a method for manufacturing a semiconductor element according to an embodiment of the present technology. FIG. 8 is a schematic cross-sectional view showing a method for manufacturing a semiconductor element according to an embodiment of the present technology. FIG. 9 is a schematic cross-sectional view showing a method for manufacturing a semiconductor element according to an embodiment of the present technology. FIG. 10 is a schematic cross-sectional view showing a method for manufacturing a semiconductor element according to an embodiment of the present technology.

[0009] Hereinafter, preferred embodiments for implementing the present technology will be described with reference to the drawings. Note that the embodiment described below shows an example of a typical embodiment of the present technology, and does not limit the scope of the present technology. In addition, the present technology can be combined with any of the following examples and their modifications.

[0010] In the following description of the embodiments, configurations may be described using terms including "approximately," such as "approximately parallel" and "approximately perpendicular." For example, "approximately parallel" does not only mean completely parallel, but also means substantially parallel, i.e., including a state where the orientation is deviated from the completely parallel state by, for example, a few percent. The same applies to other terms including "approximately." Furthermore, each figure is a schematic diagram and is not necessarily an accurate depiction. The scale of the drawings has been exaggerated to make the features of the technology easier to understand. Therefore, it should be noted that the scale of the drawings and the scale of the actual device are not necessarily the same.

[0011] Unless otherwise specified, in the drawings, "top" means the top or upper side in the drawing, "bottom" means the bottom or lower side in the drawing, "left" means the left or left side in the drawing, and "right" means the right or right side in the drawing. Furthermore, in the drawings, the same or equivalent elements or members are given the same reference numerals, and redundant explanations will be omitted.

[0012] The description will be given in the following order: 1. First Embodiment of the Present Technology (Semiconductor Element Example 1) (1) Overall Configuration (2) Photoelectric Conversion Element (3) Upper Electrode (4) Semiconductor Substrate (5) Semiconductor Layer (6) Lower Electrode (7) Other Layer Configurations (8) Circuit Configuration (9) Example of Manufacturing Method of Photodetector Element (10) Signal Acquisition Operation of Photodetector Element (11) Actions and Effects (12) Modification 1 (13) Modification 2 (14) Modification 3 (15) Application Example 1 (16) Application Example 2 (17) Application Example 3 (18) Transistor 2. Second Embodiment of the Present Technology (Semiconductor Element Example 2) 3. Third Embodiment of the Present Technology (Semiconductor Element Example 3) 4. Fourth Embodiment of the Present Technology (Semiconductor Element Example 4) 5. Fifth Embodiment of the Present Technology (Semiconductor Element Example 5) 6. Sixth Embodiment of the Present Technology (Semiconductor Element Manufacturing Method Example) 7. Application examples of this technology: (1) Application to mobile objects (2) Application to endoscopic surgery systems

[0013] [1. First Embodiment of the Present Technology (First Example of Semiconductor Element)] [(1) Overall Configuration] The present technology provides a semiconductor element including an electrode, a semiconductor layer including an oxide semiconductor, and an insulating layer disposed between the electrode and the semiconductor layer, wherein the oxide semiconductor includes a first element other than oxygen, the insulating layer includes a second element other than oxygen, and the ionic valence of the first element and the ionic valence of the second element are the same.

[0014] A semiconductor element according to an embodiment of the present technology can be used, for example, in a photodetector. A configuration example of this photodetector will be described with reference to FIG. 1. FIG. 1 is a schematic cross-sectional view showing a configuration example of a photodetector (photodetector 1A) using a semiconductor element according to an embodiment of the present technology. FIG. 2 is a plan view schematic showing a pixel configuration example of a photodetector device having the photodetector 1A shown in FIG. 1. FIG. 1 shows a cross section taken along line II shown in FIG. 2.

[0015] The photodetector element 1A constitutes, for example, one pixel (unit pixel) that is repeatedly arranged in an array in the pixel section of the photodetector device. In the pixel section, as shown in Fig. 2, a pixel unit 1a, which is made up of, for example, four pixels arranged in two rows and two columns, serves as a repeating unit and is repeatedly arranged in an array consisting of row and column directions.

[0016] The photodetector element 1A is a so-called vertical spectroscopic type in which one photoelectric conversion layer formed using, for example, an organic material and two photoelectric conversion layers (photoelectric conversion regions 32B, 32R) made of, for example, an inorganic material are stacked vertically, selectively detecting light in different wavelength ranges and performing photoelectric conversion.

[0017] [(2) Photoelectric Conversion Element] The photoelectric conversion element 10 can be used as a photoelectric conversion layer constituting the photodetector element 1A. The photoelectric conversion element 10 absorbs light corresponding to some or all of the wavelengths in a selective wavelength range (e.g., the visible light region and near-infrared light region of 400 nm or more and less than 1300 nm) to generate excitons (electron-hole pairs). In the photoelectric conversion element 10, in a photodetector element (e.g., the photodetector element 1A), for example, electrons among the electron-hole pairs generated by photoelectric conversion are read out from the lower electrode 11 side as signal charges. Below, the configuration and materials of each part will be described using the example of reading out electrons as signal charges from the lower electrode 11 side.

[0018] The photoelectric conversion layer 13 absorbs, for example, 60% or more of a predetermined wavelength included in at least the visible light range to the near-infrared range and converts it into electric charges. The photoelectric conversion layer 13 absorbs, for example, some or all of the wavelengths in the visible light range and the near-infrared range, from 400 nm to 1300 nm. The photoelectric conversion layer 13 is composed of, for example, two or more organic materials that function as p-type or n-type semiconductors, and has a junction surface (p / n junction surface) between the p-type semiconductor and the n-type semiconductor within the layer. Alternatively, the photoelectric conversion layer 13 may have a stacked structure (p-type semiconductor layer / n-type semiconductor layer) of a layer made of a p-type semiconductor (p-type semiconductor layer) and a layer made of an n-type semiconductor (n-type semiconductor layer), a stacked structure (p-type semiconductor layer / bulk hetero layer) of a p-type semiconductor layer and a mixed layer (bulk hetero layer) of p-type and n-type semiconductors, or a stacked structure (n-type semiconductor layer / bulk hetero layer) of an n-type semiconductor layer and a bulk hetero layer. Alternatively, the layer may be formed solely from a mixed layer (bulk hetero layer) of p-type and n-type semiconductors.

[0019] The p-type semiconductor is a hole transport material that functions relatively as an electron acceptor, and the n-type semiconductor is an electron transport material that functions relatively as an electron donor. The photoelectric conversion layer 13 provides a field where excitons (electron-hole pairs) generated upon light absorption separate into electrons and holes. Specifically, the electron-hole pairs separate into electrons and holes at the interface (p / n junction) between the electron donor and electron acceptor.

[0020] Examples of p-type semiconductors include naphthalene derivatives, anthracene derivatives, phenanthrene derivatives, pyrene derivatives, perylene derivatives, tetracene derivatives, pentacene derivatives, quinacridone derivatives, thiophene derivatives, thienothiophene derivatives, benzothiophene derivatives, benzothienobenzothiophene (BTBT) derivatives, dinaphthothienothiophene (DNTT) derivatives, dianthracenothienothiophene (DATT) derivatives, benzobisbenzothiophene (BBBT) derivatives, thienothiophene derivatives, benzothienobenzothiophene (BTBT) derivatives, dibenzothienothiophene (DNTT) derivatives, dianthracenothienothiophene (DATT) derivatives, benzobisbenzothiophene (BBBT) derivatives, and thienothiophene derivatives. Examples of p-type semiconductors include thienoacene-based materials such as dibenzothienobisbenzothiophene (TBBT) derivatives, dibenzothienobisbenzothiophene (DBTBT) derivatives, dithienobenzodithiophene (DTBDT) derivatives, dibenzothienodithiophene (DBTDT) derivatives, benzodithiophene (BDT) derivatives, naphthodithiophene (NDT) derivatives, anthracenodithiophene (ADT) derivatives, tetracenodithiophene (TDT) derivatives, and pentacenodithiophene (PDT) derivatives. Examples of p-type semiconductors include triphenylamine derivatives, carbazole derivatives, picene derivatives, chrysene derivatives, fluoranthene derivatives, phthalocyanine derivatives, subphthalocyanine derivatives, subporphyrazine derivatives, metal complexes having heterocyclic compounds as ligands, polythiophene derivatives, polybenzothiadiazole derivatives, and polyfluorene derivatives.

[0021] Examples of n-type semiconductors include fullerenes and derivatives thereof, such as higher fullerenes such as fullerene C60, fullerene C70, and fullerene C74, and endohedral fullerenes. Examples of substituents contained in fullerene derivatives include halogen atoms, linear, branched, or cyclic alkyl groups or phenyl groups, groups having linear or condensed aromatic compounds, groups having halides, partial fluoroalkyl groups, perfluoroalkyl groups, silyl alkyl groups, silyl alkoxy groups, aryl silyl groups, aryl sulfanyl groups, alkyl sulfanyl groups, aryl sulfonyl groups, alkyl sulfonyl groups, aryl sulfide groups, alkyl sulfide groups, amino groups, alkyl amino groups, aryl amino groups, hydroxy groups, alkoxy groups, acyl amino groups, acyloxy groups, carbonyl groups, carboxy groups, carboxamido groups, carboalkoxy groups, acyl groups, sulfonyl groups, cyano groups, nitro groups, groups having chalcogenides, phosphine groups, phosphonic groups, and derivatives thereof. Specific examples of fullerene derivatives include fullerene fluorides, PCBM fullerene compounds, fullerene polymers, etc. Other examples of n-type semiconductors include organic semiconductors and optically transparent inorganic metal oxides whose HOMO and LUMO levels are smaller (shallower) than those of p-type semiconductors.

[0022] Examples of n-type organic semiconductors include heterocyclic compounds containing nitrogen atom, oxygen atom or sulfur atom.Specific examples include pyridine derivatives, pyrazine derivatives, pyrimidine derivatives, triazine derivatives, quinoline derivatives, quinoxaline derivatives, isoquinoline derivatives, acridine derivatives, phenazine derivatives, phenanthroline derivatives, tetrazole derivatives, pyrazole derivatives, imidazole derivatives, thiazole derivatives, oxazole derivatives, imidazole derivatives, benzimidazole derivatives, benzotriazole derivatives, benzoxazole derivatives, benzoxazole derivatives, carbazole derivatives, benzofuran derivatives, dibenzofuran derivatives, subporphyrazine derivatives, polyphenylenevinylene derivatives, polybenzothiadiazole derivatives, polyfluorene derivatives, etc., which have such organic molecules as a part of molecular skeleton, organic metal complexes, subphthalocyanine derivatives, quinacridone derivatives, cyanine derivatives and merocyanine derivatives. In addition to the p-type and n-type semiconductors, the photoelectric conversion layer 13 may further include an organic material, a so-called dye material, that absorbs light in a predetermined wavelength range while transmitting light in other wavelength ranges. When the photoelectric conversion layer 13 is formed using three types of organic materials, i.e., a p-type semiconductor, an n-type semiconductor, and a dye material, the p-type and n-type semiconductors are preferably materials that are optically transparent in the visible light range. This allows the photoelectric conversion layer 13 to selectively convert light in the wavelength range absorbed by the dye material.

[0023] The photoelectric conversion layer 13 has a thickness of, for example, 10 nm or more and 500 nm or less, and preferably has a thickness of 100 nm or more and 400 nm or less.

[0024] The electron blocking layer 14 selectively transports holes, among the charges generated in the photoelectric conversion layer 13, to the upper electrode 16, and blocks the injection of electrons from the upper electrode 16 side. Examples of materials that can be used to form the electron blocking layer 14 include thienoacene-based materials such as naphthalene derivatives, anthracene derivatives, phenanthrene derivatives, pyrene derivatives, perylene derivatives, tetracene derivatives, quinacridone derivatives, thiophene derivatives, thienothiophene derivatives, benzothiophene derivatives, benzothienobenzothiophene (BTBT) derivatives, dinaphthothienothiophene (DNTT) derivatives, benzobisbenzothiophene (BBBT) derivatives, thienobisbenzothiophene (TBBT) derivatives, dibenzothienobisbenzothiophene (DBTBT) derivatives, dithienobenzodithiophene (DTBDT) derivatives, dibenzothienodithiophene (DBTDT) derivatives, benzodithiophene (BDT) derivatives, naphthodithiophene (NDT) derivatives, and anthracenodithiophene (ADT) derivatives. Other examples of p-type semiconductors include fluorene derivatives, triphenylene derivatives, triphenylamine derivatives, carbazole derivatives, picene derivatives, and chrysene derivatives.

[0025] The electron blocking layer 14 has a thickness of, for example, 5 nm to 100 nm, preferably 5 nm to 50 nm. More preferably, the electron blocking layer 14 has a thickness of 5 nm to 20 nm. The work function adjustment layer 15 has an electron affinity or work function greater than the work function of the upper electrode 16, and improves the electrical connection between the electron blocking layer 14 and the upper electrode 16. Examples of materials that can be used for the work function adjustment layer 15 include dipyrazino[2,3-f:2',3'v-h]quinoxaline-2,3,6,7,10,11-hexacarbonitrile (HAT-CN). Other examples of materials that can be used for the work function adjustment layer 15 include PEDOT / PSS and polyaniline, as well as metal oxides such as MoOx, RuOx, VOx, and WOx.

[0026] In the photodetector element 1A, the photoelectric conversion layer 10 is provided on the back surface (first surface 30S1) of the semiconductor substrate 30. The photoelectric conversion regions 32B and 32R are embedded within the semiconductor substrate 30 and stacked in the thickness direction of the semiconductor substrate 30. The photoelectric conversion layer 10 and the photoelectric conversion regions 32B and 32R selectively detect light in different wavelength ranges and perform photoelectric conversion. For example, the photoelectric conversion layer 10 acquires a green (G) color signal. The photoelectric conversion regions 32B and 32R acquire blue (B) and red (R) color signals, respectively, due to differences in absorption coefficients. This allows the photodetector element 1A to acquire multiple types of color signals in a single pixel without using color filters.

[0027] The photoelectric conversion regions 32B and 32R are configured, for example, by PIN (Positive Intrinsic Negative) type photodiodes, and each has a pn junction in a predetermined region of the semiconductor substrate 30. The photoelectric conversion regions 32B and 32R are capable of splitting light in the vertical direction by utilizing the fact that the wavelength range absorbed varies depending on the depth of incidence of light in the silicon substrate.

[0028] The photoelectric conversion region 32B selectively detects blue light and accumulates signal charges corresponding to the blue color, and is formed at a depth that allows efficient photoelectric conversion of the blue light. The photoelectric conversion region 32R selectively detects red light and accumulates signal charges corresponding to the red color, and is formed at a depth that allows efficient photoelectric conversion of the red light. Note that blue (B) corresponds to a wavelength range of, for example, 400 nm or more and less than 495 nm, and red (R) corresponds to a wavelength range of, for example, 620 nm or more and less than 750 nm. Each of the photoelectric conversion regions 32B and 32R may be capable of detecting light in some or all of the wavelength ranges.

[0029] 1, the photoelectric conversion regions 32B and 32R each have, for example, a p+ region that serves as a hole accumulation layer and an n region that serves as an electron accumulation layer (having a p-n-p stacked structure). The n region of the photoelectric conversion region 32B is connected to the vertical transistor Tr2. The p+ region of the photoelectric conversion region 32B bends along the vertical transistor Tr2 and is connected to the p+ region of the photoelectric conversion region 32R.

[0030] A protective layer 51 is provided above the photoelectric conversion layer 10. Within the protective layer 51, for example, a light-shielding film 53 and wiring that electrically connects the upper electrode 16 and the peripheral circuit unit around the pixel unit 100A are provided. Optical members such as a planarization layer (not shown) and an on-chip lens 52L are further provided above the protective layer 51.

[0031] In the photodetector element 1A, the electrons of the electron-hole pairs generated by photoelectric conversion are read out as signal charges. In the diagram, the "+ (plus)" next to "p" and "n" indicates that the p-type or n-type impurity concentration is high.

[0032] [(3) Upper Electrode] The upper electrode 16 (anode), like the lower electrode 11, is formed of, for example, a light-transmitting conductive film. Examples of materials for the upper electrode 16 include indium tin oxide (ITO), which is In2O3 doped with tin (Sn) as a dopant. The crystallinity of the ITO thin film may be high or low (approaching amorphous). In addition to the above, examples of materials for the lower electrode 11 include tin oxide (SnO2)-based materials doped with a dopant, such as ATO doped with Sb and FTO doped with fluorine. Zinc oxide (ZnO) or zinc oxide-based materials doped with a dopant may also be used. Examples of ZnO-based materials include aluminum zinc oxide (AZO) doped with aluminum (Al), gallium zinc oxide (GZO) doped with gallium (Ga), boron zinc oxide doped with boron (B), and indium zinc oxide (IZO) doped with indium (In). Zinc oxide doped with indium and gallium (IGZO, In-GaZnO) may also be used. Additionally, the lower electrode 11 may be made of CuI, InSbO, ZnMgO, CuInO, MgIN, O, CdO, ZnSnO, or TiO, or may be made of a spinel oxide or an oxide having a YbFeO structure.

[0033] Furthermore, if optical transparency is not required for the upper electrode 16, a single metal or alloy having a high work function (for example, φ=4.5 eV to 5.5 eV) can be used. Specific examples include Au, Ag, Cr, Ni, Pd, Pt, Fe, iridium (Ir), germanium (Ge), osmium (Os), rhenium (Re), tellurium (Te), and alloys thereof.

[0034] Furthermore, examples of materials constituting the upper electrode 16 include metals such as Pt, Au, Pd, Cr, Ni, Al, Ag, Ta, W, Cu, Ti, In, Sn, Fe, Co, and Mo, or alloys containing these metal elements, or conductive particles made of these metals, conductive particles of alloys containing these metals, polysilicon containing impurities, carbon-based materials, oxide semiconductors, carbon nanotubes, graphene, and other conductive substances. Other examples of materials constituting the upper electrode 16 include organic materials (conductive polymers) such as PEDOT / PSS. Furthermore, the above materials may be mixed with a binder (polymer) to form a paste or ink, which may then be cured and used as an electrode.

[0035] The upper electrode 16 can be formed as a single layer or a multilayer film made of the above materials. The thickness of the upper electrode 16 is, for example, 20 nm to 200 nm, preferably 30 nm to 150 nm.

[0036] (4) Semiconductor Substrate The semiconductor substrate 30 is, for example, an n-type silicon (Si) substrate and has a p-well 31 in a predetermined region. A second surface 30S2 (the surface of the semiconductor substrate 30) of the p-well 31 is provided with, for example, various floating diffusions (FD) (e.g., n+ regions that become FD1, FD2, and FD3) and various transistors Tr (e.g., a vertical transistor (transfer transistor) Tr2, a transfer transistor Tr3, an amplifier transistor (modulation element) AMP, and a reset transistor RST). A multilayer wiring layer 40 is further provided on the second surface 30S2 of the semiconductor substrate 30 via a gate insulating layer 33. The multilayer wiring layer 40 has, for example, a configuration in which wiring layers 41, 42, and 43 are stacked within an insulating layer 44. A peripheral circuit (not shown) consisting of a logic circuit or the like is provided around the periphery of the semiconductor substrate 30.

[0037] In FIG. 1, the first surface 30S1 side of the semiconductor substrate 30 is represented as a light incident surface S1, and the second surface 30S2 side is represented as a wiring layer side S2.

[0038] The structure and materials of each part will be described in detail below.

[0039] The photoelectric conversion layer 10 includes a hole blocking layer 12 (first layer 12A and second layer 12B), a photoelectric conversion layer 13, an electron blocking layer 14, and a work function adjustment layer 15 stacked in this order between a lower electrode 11 and an upper electrode 16 arranged opposite each other.

[0040] The hole blocking layer 12 selectively transports electrons, among the charges generated in the photoelectric conversion layer 13, to the lower electrode 11, and inhibits the injection of holes from the lower electrode 11. The hole blocking layer 12 of this embodiment is composed of two layers: a first layer 12A and a second layer 12B.

[0041] The first layer 12A selectively transports electrons to the lower electrode 11 and inhibits hole injection from the lower electrode 11. The first layer 12A can be formed using, for example, an organic material having a HOMO level that is 1 eV or more deeper than the work function of the lower electrode 11 and a LUMO level that is 3.7 eV or more and 4.8 eV or less. Furthermore, the organic material preferably has a band gap of 2.6 eV or more. Furthermore, the organic material preferably has a HOMO level that is deeper than 6.3 eV.

[0042] The second layer 12B selectively extracts electrons from electron-hole pairs generated in the photoelectric conversion layer 13 and transports them to the lower electrode 11. It is preferable that the sum of the density of states in the intra-gap levels at the interface with the photoelectric conversion layer 13 of the second layer 12B is smaller than the sum of the density of states in the intra-gap levels in the photoelectric conversion layer 13. Such a second layer 12B can be formed using, for example, an electron transport material that functions as an electron acceptor in the photoelectric conversion layer 13. Specifically, the second layer 12B is formed using fullerenes and derivatives thereof, such as higher fullerenes such as fullerene C60, fullerene C70, and fullerene C74, and endohedral fullerenes.

[0043] The second layer 12B may further contain other materials. Examples of the other materials include the compounds constituting the first layer 12A. Examples of the other materials include the dye material used in the photoelectric conversion layer 13. Examples of the dye material include subphthalocyanine derivatives. Other examples of the dye material include subphthalocyanine, porphyrin, phthalocyanine, dipyrromethane, azadipyrromethane, dipyridyl, azadipyridyl, coumarin, perylene, perylene diimide, pyrene, naphthalenediimide, quinacridone, xanthene, xanthenoxanthene, phenoxazine, indigo, azo, oxazine, benzodithiophene, naphthodithiophene, anthradithiophene, rubicene, anthracene, tetracene, pentacene, anthraquinone, tetraquinone, pentaquinone, dinaphthothienothiophene, diketopyrrolopyrrole, oligothiophene, cyanine, merocyanine, squalium, croconium, and boron-dipyrromethene (BODIPY), or derivatives thereof.

[0044] The first layer 12A and the second layer 12B each have a thickness of, for example, 1 nm or more and 30 nm or less.

[0045] [(5) Semiconductor Layer] In the photodetector element 1A, the lower electrode 11 is made up of a plurality of electrodes (for example, two electrodes: a readout electrode 11A and a storage electrode 11B), and an insulating layer 17 and a semiconductor layer 18, for example, are stacked in this order between the lower electrode 11 and the hole blocking layer 12. That is, the semiconductor element used in the photodetector element 1A has the lower electrode 11, the semiconductor layer 18, and the insulating layer 17 disposed between the electrode 11 and the semiconductor layer 18. The photodetector element 1A further includes a photoelectric conversion layer 13, and the photoelectric conversion layer 13, the semiconductor layer 18, and the insulating layer 17 are stacked in this order.

[0046] The insulating layer 17 serves to electrically separate the storage electrode 11B from the semiconductor layer 18. The insulating layer 17 is provided, for example, on the interlayer insulating layer 23 so as to cover the lower electrode 11. The insulating layer 17 is formed, for example, of a single layer film made of one of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), etc., or a stacked film made of two or more of these materials. The thickness of the insulating layer 17 is, for example, 20 nm to 500 nm.

[0047] The semiconductor layer 18 is for storing signal charges generated in the photoelectric conversion layer 13. The semiconductor layer 18 is preferably formed using a material that has a higher charge mobility and a larger band gap than the photoelectric conversion layer 13. For example, the band gap of the material that constitutes the semiconductor layer 18 is preferably 3.0 eV or more.

[0048] The semiconductor layer 18 includes an oxide semiconductor. Generally, an oxide semiconductor is composed of an element that can be a cation and oxygen atoms. The element that can be a cation may be called by several names, such as a cation, a metal ion, or a metal atom.

[0049] The oxide semiconductor contained in the semiconductor layer 18 includes a first element other than oxygen. The insulating layer 17 includes a second element other than oxygen. Each of the first element and the second element may be, for example, a metal element. In this case, the ionic valence of the first element and the ionic valence of the second element are preferably the same. The ionic valence may be +2, +3, or +4.

[0050] This makes it possible to suppress the formation of traps at the interface between the semiconductor layer 18 and the insulating layer 17. The semiconductor element according to this embodiment controls the movement of electrons and holes at the interface between the semiconductor layer 18 and the insulating layer 17. By making the valence of ions the same at this interface, the formation of traps at the interface can be suppressed, making it difficult for electrons and holes to be captured. As a result, the mobility and movement speed of electrons and holes are improved. In other words, the characteristics of the semiconductor element are improved. This semiconductor element can be used, for example, in a photodetector element, and therefore the characteristics of the photodetector element are improved. Note that this effect also occurs in the other embodiments described below. Therefore, repeated description may be omitted in the description of other embodiments.

[0051] The thickness of the semiconductor layer 18 is, for example, 10 nm or more and 300 nm or less. By providing the semiconductor layer 18 made of the above material between the lower electrode 11 and the photoelectric conversion layer 13, it is possible to prevent recombination of charges during charge accumulation and improve transfer efficiency.

[0052] [(6) Lower Electrode] The lower electrode 11 is composed of, for example, a light-transmitting conductive film. It is preferable that the lower electrode 11 has a work function of 4.0 eV or more and 5.5 eV or less, and has a LUMO level or conduction band minimum energy deeper than the organic material constituting the first layer 12A (described later). Examples of materials constituting such a lower electrode 11 include indium tin oxide (ITO), which is In2O3 doped with tin (Sn) as a dopant. The crystallinity of the ITO thin film may be high or low (approaching amorphous). Other examples of materials constituting the lower electrode 11 include tin oxide (SnO2)-based materials doped with a dopant, such as ATO doped with Sb and FTO doped with fluorine. Zinc oxide (ZnO) or zinc oxide-based materials doped with a dopant may also be used. Examples of ZnO-based materials include aluminum zinc oxide (AZO) doped with aluminum (Al), gallium zinc oxide (GZO) doped with gallium (Ga), boron zinc oxide doped with boron (B), and indium zinc oxide (IZO) doped with indium (In). Furthermore, zinc oxide doped with indium and gallium (IGZO, In-GaZnO) may also be used. Additionally, the lower electrode 11 may be made of CuI, InSbO, ZnMgO, CuInO, MgIN, O, CdO, ZnSnO, or TiO, or may be made of a spinel oxide or an oxide having a YbFeO structure.

[0053] Furthermore, when optical transparency is not required for the lower electrode 11 (for example, when light is incident from the upper electrode 16 side), a single metal or alloy having a low work function (for example, φ=3.5 eV to 4.5 eV) can be used. Specific examples include alkali metals (for example, lithium (Li), sodium (Na), and potassium (K)) and their fluorides or oxides, and alkaline earth metals (for example, magnesium (Mg) and calcium (Ca)) and their fluorides or oxides. Other examples include aluminum (Al), Al—Si—Cu alloys, zinc (Zn), tin (Sn), thallium (Tl), Na—K alloys, Al—Li alloys, Mg—Ag alloys, and rare earth metals such as In and ytterbium (Yb), or alloys thereof.

[0054] Furthermore, examples of materials constituting the lower electrode 11 include metals such as platinum (Pt), gold (Au), palladium (Pd), chromium (Cr), nickel (Ni), aluminum (Al), silver (Ag), tantalum (Ta), tungsten (W), copper (Cu), titanium (Ti), indium (In), tin (Sn), iron (Fe), cobalt (Co), and molybdenum (Mo), alloys containing these metal elements, conductive particles made of these metals, conductive particles of alloys containing these metals, polysilicon containing impurities, carbon-based materials, oxide semiconductors, carbon nanotubes, and graphene. Other examples of materials constituting the lower electrode 11 include organic materials (conductive polymers) such as poly(3,4-ethylenedioxythiophene) / polystyrene sulfonate (PEDOT / PSS). Alternatively, the above materials may be mixed with a binder (polymer) to form a paste or ink, which may then be cured and used as an electrode.

[0055] The lower electrode 11 can be formed as a single layer or a laminated film made of the above materials. The film thickness of the lower electrode 11 in the lamination direction (hereinafter simply referred to as thickness) is, for example, 20 nm to 200 nm, and preferably 30 nm to 150 nm.

[0056] Of the lower electrodes 11 , the readout electrode 11 A is electrically connected to the semiconductor layer 18 through an opening 17 H provided in the insulating layer 17 .

[0057] The readout electrode 11A is intended to transfer charges generated in the photoelectric conversion layer 13 to the floating diffusion FD1 (source / drain region 36B), and is connected to the floating diffusion FD1 (source / drain region 36B) via, for example, an upper second contact 24B, a pad portion 39B, an upper first contact 29A, a pad portion 39A, a through electrode 34, a connection portion 41A, and a lower second contact 46.

[0058] The storage electrode 11B is used to store electrons, which are generated in the photoelectric conversion layer 13, as signal charges in the semiconductor layer 18. The storage electrode 11B is provided in a region that directly faces the light-receiving surfaces of the photoelectric conversion regions 32B and 32R formed in the semiconductor substrate 30 and covers these light-receiving surfaces. The storage electrode 11B preferably has a larger area than the readout electrode 11A, which allows it to store a larger amount of charge. As shown in FIG. 4 (described later), a voltage application unit 54 is connected to the storage electrode 11B via wiring such as an upper third contact 24C and a pad unit 39C.

[0059] 1 shows an example in which the semiconductor layer 18, the hole blocking layer 12 (first layer 12A and second layer 12B), the photoelectric conversion layer 13, the electron blocking layer 14, the work function adjustment layer 15, and the upper electrode 16 are provided as a continuous layer common to a plurality of pixels (unit pixels P, see FIG. 15 ), but this is not limiting. The semiconductor layer 18, the hole blocking layer 12, the photoelectric conversion layer 13, the electron blocking layer 14, the work function adjustment layer 15, and the upper electrode 16 may be formed separately for each unit pixel P, for example.

[0060] [(7) Other Layer Configurations] Between the semiconductor substrate 30 and the lower electrode 11, for example, a layer having a fixed charge (fixed charge layer) 21, a dielectric layer 22 having insulating properties, and an interlayer insulating layer 23 are provided in this order from the first surface 30S1 side of the semiconductor substrate 30.

[0061] The fixed charge layer 21 may be a film having a positive fixed charge or a film having a negative fixed charge. The fixed charge layer 21 is preferably formed using a semiconductor or conductive material having a wider band gap than the semiconductor substrate 30. This makes it possible to suppress the generation of dark current at the interface of the semiconductor substrate 30. Examples of the material for the fixed charge layer 21 include hafnium oxide (HfOx), aluminum oxide (AlOx), zirconium oxide (ZrOx), tantalum oxide (TaOx), titanium oxide (TiOx), lanthanum oxide (LaOx), praseodymium oxide (PrOx), cerium oxide (CeOx), neodymium oxide (NdOx), promethium oxide (PmOx), samarium oxide (SmOx), europium oxide (EuOx), Examples of the oxide include gadolinium oxide (GdOx), terbium oxide (TbOx), dysprosium oxide (DyOx), holmium oxide (HoOx), thulium oxide (TmOx), ytterbium oxide (YbOx), lutetium oxide (LuOx), yttrium oxide (YOx), hafnium nitride (HfNx), aluminum nitride (AlNx), hafnium oxynitride (HfOxNy), and aluminum oxynitride (AlOxNy).

[0062] The dielectric layer 22 is intended to prevent light reflection caused by the difference in refractive index between the semiconductor substrate 30 and the interlayer insulating layer 23. The constituent material of the dielectric layer 22 is preferably a material having a refractive index between the refractive index of the semiconductor substrate 30 and the refractive index of the interlayer insulating layer 23. Examples of constituent materials of the dielectric layer 22 include SiOx, TEOS, SiNx, and SiOxNy.

[0063] The interlayer insulating layer 23 is formed of, for example, a single layer film made of one of SiOx, SiNx, SiOxNy, etc., or a laminated film made of two or more of these materials.

[0064] A shield electrode 28 is provided on the interlayer insulating layer 23 together with the lower electrode 11. The shield electrode 28 is intended to prevent capacitive coupling between adjacent pixel units 1a, and is provided around each pixel unit 1a, for example, each of which includes four pixels arranged in two rows and two columns, to which a fixed potential is applied. The shield electrode 28 also extends between adjacent pixels in the row and column directions within the pixel unit 1a.

[0065] The gate insulating layer 33 is configured, for example, as a single layer film made of one of SiOx, SiNx, SiOxNy, etc., or as a laminated film made of two or more of these materials.

[0066] A through electrode 34 is provided between the first surface 30S1 and the second surface 30S2 of the semiconductor substrate 30. The through electrode 34 functions as a connector between the photoelectric conversion layer 10 and the gate Gamp of the amplifier transistor AMP and the floating diffusion FD1, and also serves as a transmission path for charges generated in the photoelectric conversion layer 10. A reset gate Grst of the reset transistor RST is disposed adjacent to the floating diffusion FD1 (one of the source / drain regions 36B of the reset transistor RST). This allows the charges accumulated in the floating diffusion FD1 to be reset by the reset transistor RST.

[0067] The upper end of the through electrode 34 is connected to the readout electrode 11A via, for example, a pad portion 39A, an upper first contact 24A, a pad electrode 38B, and an upper second contact 24B provided in the interlayer insulating layer 23. The lower end of the through electrode 34 is connected to a connection portion 41A in the wiring layer 41, and the connection portion 41A and the gate Gamp of the amplifier transistor AMP are connected via a lower first contact 45. The connection portion 41A and the floating diffusion FD1 (region 36B) are connected via, for example, a lower second contact 46.

[0068] The upper first contact 24A, the upper second contact 24B, the upper third contact 24C, the pad portions 39A, 39B, 39C, the wiring layers 41, 42, 43, the lower first contact 45, the lower second contact 46, and the gate wiring layer 47 can be formed using, for example, a doped silicon material such as PDAS (Phosphorus Doped Amorphous Silicon), or a metal material such as Al, W, Ti, Co, Hf, and Ta.

[0069] The insulating layer 44 is configured, for example, as a single layer film made of one of SiOx, SiNx, SiOxNy, etc., or as a laminated film made of two or more of these materials.

[0070] The protective layer 51 and the on-chip lens 52L are made of a light-transmitting material, and are, for example, a single-layer film made of one of SiOx, SiNx, SiOxNy, etc., or a stacked film made of two or more of these materials. The thickness of the protective layer 51 is, for example, 100 nm or more and 30,000 nm or less.

[0071] The light-shielding film 53 is provided, for example, so as to not cover at least the storage electrode 11B but to cover the region of the readout electrode 21A that is in direct contact with the semiconductor layer 18. The light-shielding film 53 can be formed using, for example, W, Al, an alloy of Al and Cu, or the like.

[0072] [(8) Circuit Configuration] Fig. 3 is an equivalent circuit diagram of the photodetector element 1A shown in Fig. 1. Fig. 4 is a schematic diagram showing the arrangement of the lower electrode 11 and transistors constituting the control unit of the photodetector element 1A shown in Fig. 1.

[0073] The reset transistor RST (reset transistor TR1rst) resets the charge transferred from the photoelectric conversion layer 10 to the floating diffusion FD1, and is configured, for example, by a MOS transistor. Specifically, the reset transistor TR1rst is configured by a reset gate Grst, a channel formation region 36A, and source / drain regions 36B and 36C. The reset gate Grst is connected to a reset line RST1, and one source / drain region 36B of the reset transistor TR1rst also serves as the floating diffusion FD1. The other source / drain region 36C constituting the reset transistor TR1rst is connected to a power supply line VDD.

[0074] The amplifier transistor AMP is a modulation element that modulates the amount of charge generated in the photoelectric conversion layer 10 into a voltage, and is composed of, for example, a MOS transistor. Specifically, the amplifier transistor AMP is composed of a gate Gamp, a channel formation region 35A, and source / drain regions 35B and 35C. The gate Gamp is connected to the readout electrode 11A and one source / drain region 36B (floating diffusion FD1) of the reset transistor TR1rst via a lower first contact 45, a connection portion 41A, a lower second contact 46, a through-electrode 34, etc. Furthermore, one source / drain region 35B shares an area with the other source / drain region 36C that constitutes the reset transistor TR1rst, and is connected to the power supply line VDD.

[0075] The select transistor SEL (select transistor TR1sel) is composed of a gate Gsel, a channel formation region 34A, and source / drain regions 34B and 34C. The gate Gsel is connected to a select line SEL1. One source / drain region 34B shares an area with the other source / drain region 35C that constitutes the amplifier transistor AMP, and the other source / drain region 34C is connected to a signal line (data output line) VSL1.

[0076] The transfer transistor TR2 (transfer transistor TR2trs) transfers signal charges corresponding to blue, which are generated and accumulated in the photoelectric conversion region 32B, to the floating diffusion FD2. Because the photoelectric conversion region 32B is formed deep below the second surface 30S2 of the semiconductor substrate 30, the transfer transistor TR2trs in the photoelectric conversion region 32B is preferably configured as a vertical transistor. The transfer transistor TR2trs is connected to a transfer gate line TG2. A floating diffusion FD2 is provided in the region 37C near the gate Gtrs2 of the transfer transistor TR2trs. The charges accumulated in the photoelectric conversion region 32B are read out to the floating diffusion FD2 via a transfer channel formed along the gate Gtrs2.

[0077] The transfer transistor TR3 (transfer transistor TR3trs) transfers the signal charge corresponding to red generated and accumulated in the photoelectric conversion region 32R to the floating diffusion FD3, and is configured, for example, by a MOS transistor. The transfer transistor TR3trs is connected to a transfer gate line TG3. A floating diffusion FD3 is provided in the region 38C near the gate Gtrs3 of the transfer transistor TR3trs. The charge accumulated in the photoelectric conversion region 32R is read out to the floating diffusion FD3 via a transfer channel formed along the gate Gtrs3.

[0078] Further provided on the second surface 30S2 side of the semiconductor substrate 30 are a reset transistor TR2rst, an amplifier transistor TR2amp, and a selection transistor TR2sel that constitute the control section of the photoelectric conversion region 32B. Further provided are a reset transistor TR3rst, an amplifier transistor TR3amp, and a selection transistor TR3sel that constitute the control section of the photoelectric conversion region 32R.

[0079] The reset transistor TR2rst is composed of a gate, a channel forming region, and source / drain regions. The gate of the reset transistor TR2rst is connected to a reset line RST2, and one of the source / drain regions of the reset transistor TR2rst is connected to a power supply line VDD. The other source / drain region of the reset transistor TR2rst also serves as a floating diffusion FD2.

[0080] The amplifier transistor TR2amp is composed of a gate, a channel forming region, and source / drain regions. The gate is connected to the other source / drain region (floating diffusion FD2) of the reset transistor TR2rst. One of the source / drain regions constituting the amplifier transistor TR2amp shares the same region with one of the source / drain regions constituting the reset transistor TR2rst and is connected to the power supply line VDD.

[0081] The selection transistor TR2sel is composed of a gate, a channel formation region, and source / drain regions. The gate is connected to a selection line SEL2. One of the source / drain regions constituting the selection transistor TR2sel is shared with the other source / drain region constituting the amplifier transistor TR2amp. The other source / drain region constituting the selection transistor TR2sel is connected to a signal line (data output line) VSL2.

[0082] The reset transistor TR3rst is composed of a gate, a channel forming region, and source / drain regions. The gate of the reset transistor TR3rst is connected to a reset line RST3, and one of the source / drain regions constituting the reset transistor TR3rst is connected to a power supply line VDD. The other source / drain region constituting the reset transistor TR3rst also serves as a floating diffusion FD3.

[0083] The amplifier transistor TR3amp is composed of a gate, a channel forming region, and source / drain regions. The gate is connected to the other source / drain region (floating diffusion FD3) constituting the reset transistor TR3rst. One of the source / drain regions constituting the amplifier transistor TR3amp shares the same region with one of the source / drain regions constituting the reset transistor TR3rst and is connected to the power supply line VDD.

[0084] The selection transistor TR3sel is composed of a gate, a channel formation region, and source / drain regions. The gate is connected to a selection line SEL3. One of the source / drain regions constituting the selection transistor TR3sel shares the same region with the other of the source / drain regions constituting the amplifier transistor TR3amp. The other of the source / drain regions constituting the selection transistor TR3sel is connected to a signal line (data output line) VSL3.

[0085] The reset lines RST1, RST2, and RST3, the selection lines SEL1, SEL2, and SEL3, and the transfer gate lines TG2 and TG3 are connected to vertical drive circuits that constitute the drive circuit, and the signal lines (data output lines) VSL1, VSL2, and VSL3 are connected to a column signal processing circuit 112 that constitutes the drive circuit.

[0086] (9) Example of a Method for Manufacturing a Photodetector Element An example of a method for manufacturing the photodetector element 1A of this embodiment will be described with reference to Fig. 5 to Fig. 10. Fig. 5 to Fig. 10 show the manufacturing method of the photodetector element 1A in the order of steps.

[0087] 5, for example, a p-well 31 is formed in a semiconductor substrate 30, and for example, n-type photoelectric conversion regions 32B and 32R are formed in this p-well 31. A p+ region is formed in the vicinity of the first surface 30S1 of the semiconductor substrate 30.

[0088] 5, n+ regions that will become floating diffusions FD1 to FD3 are formed on the second surface 30S2 of the semiconductor substrate 30, followed by the formation of a gate insulating layer 33 and a gate wiring layer 47 including the gates of the transfer transistor Tr2, the transfer transistor Tr3, the select transistor SEL, the amplifier transistor AMP, and the reset transistor RST. This results in the formation of the transfer transistor Tr2, the transfer transistor Tr3, the select transistor SEL, the amplifier transistor AMP, and the reset transistor RST. Furthermore, a multilayer wiring layer 40 is formed on the second surface 30S2 of the semiconductor substrate 30, which includes wiring layers 41 to 43, each including a lower first contact 45, a lower second contact 46, and a connection portion 41A, and an insulating layer 44.

[0089] The base of the semiconductor substrate 30 is, for example, an SOI (Silicon on Insulator) substrate in which the semiconductor substrate 30, a buried oxide film (not shown), and a holding substrate (not shown) are stacked. Although not shown in FIG. 5, the buried oxide film and the holding substrate are bonded to the first surface 30S1 of the semiconductor substrate 30. After the ion implantation, an annealing process is performed.

[0090] Next, a support substrate (not shown) or another semiconductor substrate is bonded to the multilayer wiring layer 40 provided on the second surface 30S2 side of the semiconductor substrate 30, and the semiconductor substrate 30 is then turned upside down. Subsequently, the semiconductor substrate 30 is separated from the buried oxide film of the SOI substrate and the support substrate, exposing the first surface 30S1 of the semiconductor substrate 30. The above steps can be performed using techniques used in ordinary CMOS processes, such as ion implantation and CVD (Chemical Vapor Deposition).

[0091] 6, the semiconductor substrate 30 is processed from the first surface 30S1 side by, for example, dry etching to form, for example, an annular opening 34H. As shown in FIG. 7, the depth of the opening 34H is such that it penetrates from the first surface 30S1 to the second surface 30S2 of the semiconductor substrate 30 and reaches, for example, the connection portion 41A.

[0092] Next, for example, a negative fixed charge layer 21 and a dielectric layer 22 are sequentially formed on the first surface 30S1 of the semiconductor substrate 30 and the side surface of the opening 34H. The fixed charge layer 21 can be formed, for example, by depositing an HfOx film using atomic layer deposition (ALD). The dielectric layer 22 can be formed, for example, by depositing an SiOx film using plasma CVD. Next, a pad portion 39A is formed at a predetermined position on the dielectric layer 22. The pad portion 39A includes a barrier metal layer made of, for example, a titanium / titanium nitride layer (Ti / TiN film) and a W film. Thereafter, an interlayer insulating layer 23 is formed on the dielectric layer 22 and the pad portion 39A, and the surface of the interlayer insulating layer 23 is planarized using CMP (chemical mechanical polishing).

[0093] 7, an opening 23H1 is formed on the pad portion 39A, and then a conductive material such as Al is filled into this opening 23H1 to form the upper first contact 24A. Next, in the same manner as for the pad portion 39A, pad portions 39B and 39C are formed, and then the interlayer insulating layer 23, the upper second contact 24B, and the upper third contact 24C are formed in this order.

[0094] 8, a conductive film 11X is formed on the interlayer insulating layer 23 by, for example, sputtering, and then patterned by photolithography. Specifically, a photoresist PR is formed at a predetermined position on the conductive film 11X, and then the conductive film 11X is processed by dry etching or wet etching.

[0095] Thereafter, the photoresist PR is removed, thereby forming the readout electrode 11A and the storage electrode 11B as shown in FIG.

[0096] Next, as shown in FIG. 10 , the insulating layer 17, the semiconductor layer 18, the hole blocking layer 12 (first layer 12A and second layer 12B), the photoelectric conversion layer 13, the electron blocking layer 14, the work function adjustment layer 15, and the upper electrode 16 are sequentially formed. The insulating layer 17 is formed by depositing a SiOx film using, for example, the ALD method, and then planarizing the surface of the insulating layer 17 using the CMP method. Thereafter, an opening 17H is formed on the readout electrode 11A using, for example, dry etching. The semiconductor layer 18 can be formed using, for example, atomic layer deposition (ALD) or sputtering. The hole blocking layer 12 (first layer 12A and second layer 12B), the photoelectric conversion layer 13, the electron blocking layer 14, and the work function adjustment layer 15 are formed using, for example, vacuum deposition. The upper electrode 16 is formed, like the lower electrode 11, using, for example, the sputtering method. Finally, the protective layer 51, the light-shielding film 53, and the on-chip lens 52L are disposed on the upper electrode 16. In this manner, the photodetector 1A shown in FIG.

[0097] It is desirable to form each of the hole blocking layer 12 (first layer 12A and second layer 12B), photoelectric conversion layer 13, electron blocking layer 14, and work function adjustment layer 15 consecutively in a vacuum process (through a vacuum integrated process). Organic layers such as the hole blocking layer 12 (first layer 12A and second layer 12B), photoelectric conversion layer 13, electron blocking layer 14, and work function adjustment layer 15, as well as conductive films such as the lower electrode 11 and upper electrode 16, can be formed using a dry film formation method or a wet film formation method. Examples of dry film formation methods include vacuum deposition using resistance heating or high-frequency heating, electron beam (EB) deposition, various sputtering methods (magnetron sputtering, RF-DC coupled bias sputtering, ECR sputtering, facing target sputtering, and high-frequency sputtering), ion plating, laser ablation, molecular beam epitaxy, and laser transfer. Other examples of dry film formation methods include chemical vapor deposition methods such as plasma CVD, thermal CVD, MOCVD, and photo-CVD. Examples of wet film formation methods include spin coating, inkjet printing, spray coating, stamping, microcontact printing, flexographic printing, offset printing, gravure printing, and dipping.

[0098] For patterning, in addition to photolithography, chemical etching such as shadow mask and laser transfer, physical etching using ultraviolet light or laser, etc. can be used. As for planarization techniques, in addition to CMP, laser planarization, reflow, etc. can be used.

[0099] [(10) Signal Acquisition Operation of Photodetection Element] The operation of the photodetection element 1A will be described with reference to Fig. 1. In the photodetection element 1A, when light is incident on the photoelectric conversion layer 10 via the on-chip lens 52L, the light passes through the photoelectric conversion layer 10 and the photoelectric conversion regions 32B and 32R in that order, and is photoelectrically converted into green, blue, and red light during the passage. The signal acquisition operation for each color will be described below.

[0100] Of the light incident on the photodetector element 1A, green light (G) is first selectively detected (absorbed) in the photoelectric conversion layer 10 and photoelectrically converted.

[0101] The photoelectric conversion layer 10 is connected to the gate Gamp of the amplifier transistor AMP and the floating diffusion FD1 via the through electrode 34. Therefore, electrons of the excitons generated in the photoelectric conversion layer 10 are extracted from the lower electrode 11 side, transferred to the second surface 30S2 side of the semiconductor substrate 30 via the through electrode 34, and accumulated in the floating diffusion FD1. At the same time, the amount of charge generated in the photoelectric conversion layer 10 is modulated into a voltage by the amplifier transistor AMP.

[0102] In addition, a reset gate Grst of the reset transistor RST is disposed next to the floating diffusion FD1, so that the charge accumulated in the floating diffusion FD1 is reset by the reset transistor RST.

[0103] Since the photoelectric conversion layer 10 is connected not only to the amplifier transistor AMP but also to the floating diffusion FD1 via the through electrode 34, the charge accumulated in the floating diffusion FD1 can be easily reset by the reset transistor RST.

[0104] On the other hand, if the through electrode 34 and the floating diffusion FD1 are not connected, it becomes difficult to reset the charge accumulated in the floating diffusion FD1, and a large voltage must be applied to extract the charge to the upper electrode 16 side, which may damage the photoelectric conversion layer 24. Furthermore, a structure that enables resetting in a short time increases dark noise, which is a trade-off, making this structure difficult to implement.

[0105] 11 shows an example of operation of the photodetector element 1A. (A) shows the potential at the storage electrode 11B, (B) shows the potential at the floating diffusion FD1 (readout electrode 11A), and (C) shows the potential at the gate (Gsel) of the reset transistor TR1rst. In the photodetector element 1A, voltages are applied to the readout electrode 11A and the storage electrode 11B individually.

[0106] In the photodetector element 1A, during the accumulation period, a potential V1 is applied from the drive circuit to the readout electrode 11A, and a potential V2 is applied to the storage electrode 11B. Here, the relationship between potentials V1 and V2 is V2 > V1. As a result, the charge (signal charge; electrons) generated by photoelectric conversion is attracted to the storage electrode 11B and accumulated in the region of the semiconductor layer 18 facing the storage electrode 11B (accumulation period). Incidentally, the potential of the region of the semiconductor layer 18 facing the storage electrode 11B becomes more negative as the photoelectric conversion time elapses. Note that holes are sent from the upper electrode 16 to the drive circuit.

[0107] In the photodetector element 1A, a reset operation is performed in the latter half of the accumulation period. Specifically, at timing t1, the scanning unit changes the voltage of the reset signal RST from low to high. This turns on the reset transistor TR1rst in the unit pixel P, and as a result, the voltage of the floating diffusion FD1 is set to the power supply voltage and the voltage of the floating diffusion FD1 is reset (reset period).

[0108] After the reset operation is completed, the charge is read out. Specifically, at timing t2, the drive circuit applies a potential V3 to the readout electrode 11A and a potential V4 to the storage electrode 11B. Here, the potentials V3 and V4 are set to V3 > V4. As a result, the charge stored in the region corresponding to the storage electrode 11B is read out from the readout electrode 11A to the floating diffusion FD1. That is, the charge stored in the semiconductor layer 18 is read out to the control unit (transfer period).

[0109] After the read operation is completed, the drive circuit again applies potential V1 to the read electrode 11A and potential V2 to the storage electrode 11B, causing the charges generated by photoelectric conversion to be attracted to the storage electrode 11B and stored in the region of the photoelectric conversion layer 24 facing the storage electrode 11B (storage period).

[0110] Subsequently, of the light transmitted through the photoelectric conversion layer 10, blue light (B) is absorbed and photoelectrically converted in the photoelectric conversion region 32B, and red light (R) is absorbed and photoelectrically converted in the photoelectric conversion region 32R. In the photoelectric conversion region 32B, electrons corresponding to the incident blue light (B) are accumulated in the n-region of the photoelectric conversion region 32B, and the accumulated electrons are transferred to the floating diffusion FD2 by the transfer transistor Tr2. Similarly, in the photoelectric conversion region 32R, electrons corresponding to the incident red light (R) are accumulated in the n-region of the photoelectric conversion region 32R, and the accumulated electrons are transferred to the floating diffusion FD3 by the transfer transistor Tr3.

[0111] [(11) Function and Effect] In the photoelectric conversion element 10 of the present embodiment, the formation of traps can be suppressed at the interface between the semiconductor layer 18 and the insulating layer 17, making it difficult for electrons and holes to be captured. As a result, the mobility and migration speed of electrons and holes are improved.

[0112] As a result, the photoelectric conversion element 10 of this embodiment can improve the element characteristics.

[0113] 12 is a schematic diagram illustrating a cross-sectional configuration of a photodetector element 1C according to a first modification of the present disclosure. Similar to the photodetector element 1A of the above embodiment, the photodetector element 1C is a photodetector element such as a CMOS image sensor used in electronic devices such as digital still cameras and video cameras. The photodetector element 1C of this modification has two photoelectric conversion layers 10, 80 and one photoelectric conversion region 32 stacked vertically.

[0114] The photoelectric conversion layers 10 and 80 and the photoelectric conversion region 32 selectively detect light in different wavelength ranges and perform photoelectric conversion. For example, the photoelectric conversion layer 10 acquires a green (G) color signal. For example, the photoelectric conversion layer 80 acquires a blue (B) color signal. For example, the photoelectric conversion region 32 acquires a red (R) color signal. This makes it possible for the photodetector 1C to acquire multiple types of color signals in one pixel without using color filters.

[0115] The photoelectric conversion layers 10 and 80 have the same configuration as the photodetector element 1A of the above embodiment. Specifically, the photoelectric conversion layer 10 includes a lower electrode 11, a hole blocking layer 12 (first layer 12A and second layer 12B), a photoelectric conversion layer 13, an electron blocking layer 14, a work function adjustment layer 15, and an upper electrode 16 stacked in this order, similar to the photodetector element 1A.

[0116] The lower electrode 11 is made up of a plurality of electrodes (for example, a readout electrode 11A and a storage electrode 11B), and an insulating layer 17 and a semiconductor layer 18 are stacked in this order between the lower electrode 11 and the hole blocking layer 12. Of the lower electrode 11, the readout electrode 11A is electrically connected to the semiconductor layer 18 through an opening 17H provided in the insulating layer 17.

[0117] Like the photoelectric conversion layer 10, the photoelectric conversion layer 80 also has a lower electrode 81, a hole blocking layer 82 (first layer 82A and second layer 82B), a photoelectric conversion layer 83, an electron blocking layer 84, a work function adjustment layer 85, and an upper electrode 86 stacked in this order.

[0118] The lower electrode 81 is made up of a plurality of electrodes (for example, a readout electrode 81A and a storage electrode 81B), and an insulating layer 87 and a semiconductor layer 88 are stacked in this order between the lower electrode 81 and the hole-blocking layer 82 (a first layer 82A and a second layer 82B). Of the lower electrode 81, the readout electrode 81A is electrically connected to the semiconductor layer 88 through an opening 87H provided in the insulating layer 87. Note that at least one of the semiconductor layer 88 and the semiconductor layer 88 is required.

[0119] A through electrode 91 is connected to the readout electrode 81A, which penetrates the interlayer insulating layer 89 and the photoelectric conversion layer 10 and is electrically connected to the readout electrode 11A of the photoelectric conversion layer 10. Furthermore, the readout electrode 81A is electrically connected to a floating diffusion FD provided in the semiconductor substrate 30 via the through electrodes 34 and 91, and can temporarily store charges generated in the photoelectric conversion layer 83. Furthermore, the readout electrode 81A is electrically connected to an amplifier transistor AMP and the like provided in the semiconductor substrate 30 via the through electrodes 34 and 91.

[0120] [(13) Modification 2] Fig. 13A is a schematic diagram illustrating a cross-sectional configuration of a photodetector element 1D according to Modification 3 of the present disclosure. Fig. 13B is a schematic diagram illustrating an example of the planar configuration of the photodetector element 1D illustrated in Fig. 13A, and Fig. 13A illustrates a cross section taken along line II-II illustrated in Fig. 13B.

[0121] The photodetector element 1D is, for example, a stacked-type photodetector element in which a photoelectric conversion region 32 and a photoelectric conversion layer 60 are stacked. In a pixel section 100A of a photodetector device (for example, a photodetector device 100) including this photodetector element 1D, pixel units 1a each consisting of four pixels arranged in two rows and two columns are repeated as shown in Fig. 13B, for example, and are arranged repeatedly in an array in the row and column directions.

[0122] In the photodetector element 1D of this modification, a color filter 55 that selectively transmits red light (R), green light (G), and blue light (B) is provided for each unit pixel P above the photoelectric conversion layer 60 (on the light incident side S1). Specifically, in a pixel unit 1a consisting of four pixels arranged in two rows and two columns, two color filters that selectively transmit green light (G) are arranged diagonally, and one color filter that selectively transmits red light (R) and blue light (B) is arranged on each diagonal that is perpendicular to the pixel unit 1a. In the unit pixels (Pr, Pg, Pb) provided with each color filter, the corresponding color light is detected, for example, in the photoelectric conversion layer 60. That is, in the pixel section 100A, pixels (Pr, Pg, Pb) that detect red light (R), green light (G), and blue light (B), respectively, are arranged in a Bayer pattern.

[0123] The photoelectric conversion layer 60 absorbs light corresponding to some or all of the wavelengths in the visible light region of 400 nm or more and less than 750 nm, for example, to generate excitons (electron-hole pairs), and includes a lower electrode 61, an insulating layer (interlayer insulating layer 67), a semiconductor layer 68, a hole blocking layer 62 (first layer 62A and second layer 62B), a photoelectric conversion layer 63, an electron blocking layer 64, a work function adjustment layer 65, and an upper electrode 66 stacked in this order. The lower electrode 61, the interlayer insulating layer 67, the semiconductor layer 68, the hole blocking layer 62 (first layer 62A and second layer 62B), the photoelectric conversion layer 63, the electron blocking layer 64, the work function adjustment layer 65, and the upper electrode 66 have the same configurations as the lower electrode 11, the insulating layer 17, the semiconductor layer 18, the hole blocking layer 12, the photoelectric conversion layer 13, the electron blocking layer 14, the work function adjustment layer 15, and the upper electrode 16 of the photodetector element 1A in the above embodiment, respectively. The lower electrode 61 has, for example, a readout electrode 61A and a storage electrode 61B that are independent of each other, and the readout electrode 61A is shared by, for example, four pixels.

[0124] The photoelectric conversion region 32 detects, for example, an infrared light region of 750 nm or more and 1300 nm or less.

[0125] In the photodetector element 1D, light in the visible light region (red light (R), green light (G), and blue light (B)) that passes through the color filters 55 is absorbed by the photoelectric conversion layer 60 of the unit pixels (Pr, Pg, Pb) to which each color filter is provided, while other light, for example, light in the infrared light region (e.g., 750 nm or more and 1000 nm or less) (infrared light (IR)), passes through the photoelectric conversion layer 60. The infrared light (IR) that passes through the photoelectric conversion layer 60 is detected in the photoelectric conversion region 32 of each unit pixel Pr, Pg, Pb, and signal charges corresponding to the infrared light (IR) are generated in each unit pixel Pr, Pg, Pb. In other words, a photodetector device 100 including the photodetector element 1D is capable of simultaneously generating both visible light images and infrared light images.

[0126] Furthermore, the photodetector device 100 including the photodetector element 1D can acquire a visible light image and an infrared light image at the same position in the XZ in-plane direction, thereby enabling high integration in the XZ in-plane direction.

[0127] [(14) Modification 3] Fig. 14A is a schematic diagram illustrating a cross-sectional configuration of a photodetector element 1E according to Modification 3 of the present disclosure. Fig. 14B is a schematic diagram illustrating an example of the planar configuration of the photodetector element 1E illustrated in Fig. 14A, and Fig. 14A illustrates a cross section taken along line III-III illustrated in Fig. 14B. In Modification 2 described above, the color filter 55 is provided above the photoelectric conversion layer 60 (on the light incident side S1). However, the color filter 55 may be provided, for example, between the photoelectric conversion region 32 and the photoelectric conversion layer 60, as illustrated in Fig. 14A.

[0128] In the photodetector element 1E, for example, the color filter 55 has a configuration in which a color filter (color filter 55R) that selectively transmits at least red light (R) and a color filter (color filter 55B) that selectively transmits at least blue light (B) are arranged diagonally to each other within the pixel unit 1a. The photoelectric conversion layer 60 (photoelectric conversion layer 63) is configured to selectively absorb light having a wavelength corresponding to, for example, green light (G). The photoelectric conversion region 32R selectively absorbs light having a wavelength corresponding to red light (R), and the photoelectric conversion region 32B selectively absorbs light having a wavelength corresponding to blue light (B). This makes it possible to obtain signals corresponding to red light (R), green light (G), or blue light (B) in the photoelectric conversion regions 32 (photoelectric conversion regions 32R and 32B) that are arranged below the photoelectric conversion layer 60 and the color filters 55R and 55B, respectively. In the photodetector element 1E of this modified example, the area of ​​the photoelectric conversion layer for each of the RGB components can be enlarged compared to a photoelectric conversion element having a general Bayer array, thereby making it possible to improve the S / N ratio.

[0129] (15) Application Example 1 FIG. 15 shows an example of the overall configuration of a photodetector (photodetector 100) including the semiconductor element shown in FIG. 1 and the like.

[0130] The photodetector 100 is, for example, a CMOS image sensor that takes in incident light (image light) from a subject via an optical lens system (not shown), converts the amount of incident light imaged on a photodetector surface into an electrical signal on a pixel-by-pixel basis, and outputs the signal as a pixel signal. The photodetector 100 has a pixel section 100A as a photodetection area on a semiconductor substrate 30, and also has, in a peripheral region of the pixel section 100A, for example, a vertical drive circuit 111, a column signal processing circuit 112, a horizontal drive circuit 113, an output circuit 114, a control circuit 115, and input / output terminals 116.

[0131] The pixel section 100A has, for example, a plurality of unit pixels P arranged two-dimensionally in a matrix. For example, pixel drive lines Lread (specifically, row selection lines and reset control lines) are wired to each unit pixel P for each pixel row, and vertical signal lines Lsig are wired to each pixel column. The pixel drive lines Lread transmit drive signals for reading signals from the pixels. One end of each pixel drive line Lread is connected to an output terminal of the vertical drive circuit 111 corresponding to each row.

[0132] The vertical drive circuit 111 is a pixel drive unit that includes a shift register, an address decoder, etc., and drives each unit pixel P of the pixel unit 100A, for example, row by row. Signals output from each unit pixel P of a pixel row selected and scanned by the vertical drive circuit 111 are supplied to a column signal processing circuit 112 through each vertical signal line Lsig. The column signal processing circuit 112 is configured with an amplifier, a horizontal selection switch, etc., provided for each vertical signal line Lsig.

[0133] The horizontal drive circuit 113 is configured with a shift register, an address decoder, etc., and scans and sequentially drives each horizontal selection switch of the column signal processing circuit 112. By selective scanning by this horizontal drive circuit 113, signals of each pixel transmitted through each vertical signal line Lsig are output in sequence to horizontal signal lines 121 and transmitted to the outside of the semiconductor substrate 30 through the horizontal signal lines 121.

[0134] The output circuit 114 processes and outputs signals sequentially supplied from each of the column signal processing circuits 112 via the horizontal signal line 121. The output circuit 114 may perform only buffering, or may perform black level adjustment, column variation correction, various digital signal processing, and the like, for example.

[0135] The circuit portion consisting of the vertical drive circuit 111, the column signal processing circuit 112, the horizontal drive circuit 113, the horizontal signal line 121, and the output circuit 114 may be formed directly on the semiconductor substrate 30, or may be disposed on an external control IC. Furthermore, these circuit portions may be formed on another substrate connected by a cable or the like.

[0136] The control circuit 115 receives a clock and data instructing an operation mode from outside the semiconductor substrate 30, and outputs data such as internal information of the photodetector 100. The control circuit 115 further has a timing generator that generates various timing signals, and controls the driving of peripheral circuits such as the vertical drive circuit 111, the column signal processing circuit 112, and the horizontal drive circuit 113 based on the various timing signals generated by the timing generator.

[0137] The input / output terminal 116 is used to exchange signals with the outside.

[0138] (16) Application Example 2 The photodetector 100 as described above can be applied to various electronic devices, such as imaging systems such as digital still cameras and digital video cameras, mobile phones with imaging functions, and other devices with imaging functions.

[0139] Fig. 16 is a block diagram showing an example of the configuration of electronic device 1000. As shown in Fig. 16, electronic device 1000 includes optical system 1001, photodetector 100, and DSP (Digital Signal Processor) 1002, and is configured by connecting DSP 1002, memory 1003, display device 1004, recording device 1005, operation system 1006, and power supply system 1007 via bus 1008, and is capable of capturing still images and moving images.

[0140] The optical system 1001 is configured to have one or more lenses, and receives incident light (image light) from an object and forms an image on the photodetection surface of the photodetector 100 .

[0141] The above-described photodetector 100 is applied as the photodetector 100. The photodetector 100 converts the amount of incident light imaged on the photodetection surface by the optical system 1001 into an electrical signal on a pixel-by-pixel basis and supplies the signal to the DSP 1002 as a pixel signal.

[0142] The DSP 1002 performs various signal processing on the signal from the photodetector 100 to acquire an image, and temporarily stores the image data in a memory 1003. The image data stored in the memory 1003 is recorded in a recording device 1005 or supplied to a display device 1004 to display the image. An operation system 1006 accepts various operations by a user and supplies operation signals to each block of the electronic device 1000, and a power supply system 1007 supplies power necessary to drive each block of the electronic device 1000.

[0143] 17A is a schematic diagram illustrating an example of the overall configuration of a light detection system 2000 including the light detection device 100. FIG. 17B is a diagram illustrating an example of the circuit configuration of the light detection system 2000.

[0144] The light detection system 2000 includes a light emitting device 2001 as a light source unit that emits infrared light L2, and a light detecting device 2002 as a light receiving unit having a photoelectric conversion element. The light detecting device 2002 may be the light detecting device 100 described above. The light detecting system 2000 may further include a system control unit 2003, a light source driving unit 2004, a sensor control unit 2005, a light source side optical system 2006, and a camera side optical system 2007.

[0145] The photodetector 2002 can detect light L1 and light L2. Light L1 is external ambient light reflected by a subject (object to be measured) 2100 ( FIG. 17A ). Light L2 is light emitted by the light-emitting device 2001 and then reflected by the subject 2100. Light L1 is, for example, visible light, and light L2 is, for example, infrared light. Light L1 can be detected by a photoelectric conversion unit in the photodetector 2002, and light L2 can be detected by a photoelectric conversion region in the photodetector 2002. Image information of the subject 2100 can be obtained from light L1, and distance information between the subject 2100 and the photodetector system 2000 can be obtained from light L2.

[0146] The light detection system 2000 can be mounted on, for example, an electronic device such as a smartphone or a mobile object such as a car. The light emitting device 2001 can be configured by, for example, a semiconductor laser, a surface emitting semiconductor laser, or a vertical cavity surface emitting laser (VCSEL).

[0147] The method of detecting the light L2 emitted from the light emitting device 2001 by the photodetector 2002 can be, for example, an iTOF system, but is not limited to this. In the iTOF system, the photoelectric conversion unit can measure the distance to the subject 2100 by, for example, time-of-flight (TOF).

[0148] As a method for detecting the light L2 emitted from the light emitting device 2001 by the light detection device 2002, for example, a structured light method or a stereo vision method can be adopted. For example, in the structured light method, a predetermined pattern of light is projected onto the subject 2100, and the distance between the light detection system 2000 and the subject 2100 can be measured by analyzing the degree of distortion of the pattern. In addition, in the stereo vision method, for example, two or more cameras are used to acquire two or more images of the subject 2100 viewed from two or more different viewpoints, thereby making it possible to measure the distance between the light detection system 2000 and the subject.

[0149] The light emitting device 2001 and the light detecting device 2002 can be controlled synchronously by a system control unit 2003 .

[0150] [(18) Transistor] A semiconductor device according to an embodiment of the present technology can be used in, for example, a transistor. The semiconductor device may include an electrode, a semiconductor layer including an oxide semiconductor, and an insulating layer disposed between the electrode and the semiconductor layer. The oxide semiconductor includes a first element other than oxygen, and the insulating layer includes a second element other than oxygen, and the ionic valence of the first element and the ionic valence of the second element are preferably the same.

[0151] According to the present technology, it is possible to improve the characteristics of a semiconductor element including an oxide semiconductor, that is, to improve the characteristics of a transistor.

[0152] The above description of the semiconductor element according to the first embodiment of the present technology can be applied to other embodiments of the present technology unless there is a particular technical contradiction.

[0153] 2. Second Embodiment of the Present Technology (Second Example of Semiconductor Element) A configuration example of a semiconductor element according to an embodiment of the present technology will be described with reference to Fig. 18. Fig. 18 is a schematic cross-sectional view showing a configuration example of a semiconductor element according to an embodiment of the present technology.

[0154] 18, conductive layers 20A and insulating layers 20B are alternately stacked. The conductive layers 20A are, for example, transparent conductive layers, and may be made of ITO (indium tin oxide), IZO (indium zinc oxide), etc. The insulating layers 20B may be made of, for example, SiO (silicon dioxide), etc.

[0155] Fine openings 20H are formed in the laminate 20, in which conductive layers 20A and insulating layers 20B are alternately stacked. Semiconductor layers 18 are embedded in the openings 20H. The semiconductor layers 18 may be made of a composite oxide called IGZO (Indium Gallium Zinc Oxide), which contains, for example, In, Ga, and the like.

[0156] The semiconductor layer 18 is configured by stacking one or more layers of multiple oxide layers. When filling such a minute opening 20H with the semiconductor layer 18, the semiconductor layer 18 can be formed using, for example, atomic layer deposition (ALD) to achieve high-precision coverage. Atomic layer deposition is a technique for forming a semiconductor layer by stacking multiple thin films. Because multiple thin films are formed, the semiconductor layer 18 can be formed even in the minute opening 20H. Each of the multiple oxide layers constituting the semiconductor layer 18 can be 0.1 nm or greater. In this configuration example, a portion of the semiconductor layer 18 is formed by stacking GaO, ZnO, InO, GaO, ZnO, and InO in this order.

[0157] The order in which the oxide layers are stacked is not particularly limited. For example, part of the semiconductor layer 18 may be formed by stacking GaO, ZnO, GaO, ZnO, and InO in this order.

[0158] When the diameter of the opening 20H is, for example, 100 nm and the thickness of the semiconductor layer 18 is, for example, 20 nm, the diameter of the opening 20H becomes larger than the thickness of the semiconductor layer 18, which may result in a gap being formed in the semiconductor layer 18. Therefore, in this configuration example, the gap is filled with the filling portion 18A. The filling portion 18A may be made of, for example, GaO. After the filling portion 18A is formed, the semiconductor layer 18 is further formed using physical vapor deposition (PVD) or the like.

[0159] An insulating layer 19 is formed between a stack 20 in which conductive layers 20A and insulating layers 20B are alternately stacked, and the semiconductor layer 18. Because a part of the insulating layer 19 is open, a part of the semiconductor layer 18 and the conductive layer 20A are in contact with each other. This contacting conductive layer 20A is a floating diffusion region FD.

[0160] A part of the semiconductor layer 18 protrudes from the side opposite to the photoelectric conversion layer 13 and is connected to an electrode connected to the floating diffusion region FD. This protruding part of the semiconductor layer 18 is a semiconductor wiring 60.

[0161] In order to increase the driving force of the semiconductor element, it is preferable that the insulating layer 19 contains an oxide material with a high relative dielectric constant, which allows voltage to be transmitted more efficiently to the semiconductor layer 18. Examples of oxide materials with a high relative dielectric constant include Al2O3 and HfO2.

[0162] In this case, it is preferable that the ionic valence of the oxide layer disposed at the interface with the insulating layer 19, among the multiple oxide layers constituting the semiconductor layer 18, is the same as the ionic valence of the insulating layer 19. This ionic valence can be +2, +3, or +4.

[0163] This makes it possible to suppress the formation of traps at the interface between the semiconductor layer 18 and the insulating layer 19. For example, a semiconductor element controls the movement of electrons and holes at the interface between the semiconductor layer 18 and the insulating layer 19. By making the valence of ions the same at this interface, it is possible to suppress the formation of traps at the interface, making it difficult for electrons and holes to be captured. As a result, the characteristics of the semiconductor element are improved.

[0164] In this configuration example, the oxide layer disposed at the interface with the insulating layer 19 contains In2O3. To make the ionic valence the same (+3), the insulating layer 19 preferably contains, for example, Al2O3. Other examples of materials that the insulating layer 19 may contain include HfO2, ZrO2, HFO2, Ga2O3, Al2O3, and YO3.

[0165] Furthermore, among the multiple oxide layers constituting semiconductor layer 18, it is preferable that the ionic valence of the oxide layer disposed at the interface with filling portion 18A be the same as the ionic valence of filling portion 18A. This makes it possible to suppress the formation of traps at the interface between semiconductor layer 18 and filling portion 18A, as well. As a result, the characteristics of the semiconductor element are improved.

[0166] The thickness of the insulating layer 19 can be set to any value, but it is preferable to set it to an equivalent oxide thickness (EOT) of 10 nm or less. The thickness of the insulating layer 19 is t, the dielectric constant of the insulating layer 19 is ε, and the dielectric constant of SiO is ε. SiO Then, EOT can be calculated by the following formula (1).

[0167]

[0168] Here, it is preferable that the value of t / ε satisfies the following formula (2): t / ε<10 / ε SiO ...(2)

[0169] Dielectric constant ε of SiO SiO is approximately 3.9, so the value of t / ε is preferably less than 2.6.

[0170] The above description of the semiconductor element according to the second embodiment of the present technology can be applied to other embodiments of the present technology unless there is a particular technical contradiction.

[0171] 3. Third Embodiment of the Present Technology (Third Example of Semiconductor Element) A configuration example of a semiconductor element according to an embodiment of the present technology will be described with reference to Fig. 19. Fig. 19 is a schematic cross-sectional view showing a configuration example of a semiconductor element according to an embodiment of the present technology.

[0172] Fig. 19 shows another example of the configuration of the enlarged portion surrounded by the dotted line in Fig. 18. In this example, the semiconductor layer 18 is formed by laminating ZnO, In2O3, Ga2O3, ZnO, In2O3, and Ga2O3 in this order.

[0173] In this configuration example, the oxide layer disposed at the interface with the insulating layer 19 contains GaO. To make the ionic valence the same (+3), the insulating layer 19 preferably contains, for example, AlO.

[0174] Furthermore, it is preferable that the ionic valence of at least one of the multiple oxide layers constituting the semiconductor layer 18 is different from the ionic valence of the insulating layer 19. In this configuration example, an oxide layer containing In2O3, an oxide layer containing Ga2O3, and the insulating layer 19 are stacked in this order. Because the oxide layer containing Ga2O3 has insulating properties, the In2O3, which transfers electrons, is located away from the insulating layer 19.

[0175] According to this embodiment, the ionic valence of the oxide layer disposed at the interface with the insulating layer 19 is the same as the ionic valence of the insulating layer 19, thereby suppressing the formation of traps at the interface. Furthermore, since the oxide layer containing GaO has insulating properties, InO, which transports electrons, is disposed at a position away from the insulating layer 19, thereby further suppressing the formation of traps.

[0176] The above description of the semiconductor element according to the third embodiment of the present technology can be applied to other embodiments of the present technology unless there is a particular technical contradiction.

[0177] [4. Fourth Embodiment of the Present Technology (Fourth Example of Semiconductor Element)] The present technology provides a semiconductor element including a first electrode, a second electrode, a photoelectric conversion layer provided between the first electrode and the second electrode, and a semiconductor layer provided between the first electrode and the photoelectric conversion layer, wherein the semiconductor layer includes at least a first oxide layer containing a first element other than oxygen, a second oxide layer containing a second element other than oxygen, a third oxide layer containing the first element, and a fourth oxide layer containing the second element, wherein the first element is different from the second element.

[0178] A semiconductor element according to an embodiment of the present technology will be described with reference to FIGS. 20A and 20B . FIG. 20A is a vertical cross-sectional view showing a configuration example of a semiconductor element according to an embodiment of the present technology. FIG. 20B is a horizontal cross-sectional view showing the A-A cross section in FIG. 20A . Note that, here, "vertical" means "perpendicular to the element formation surface of a semiconductor substrate 50," and "horizontal" means "horizontal to the element formation surface."

[0179] 20A and 20B , the semiconductor element has a first electrode 37, a second electrode 16, a photoelectric conversion layer 13, and a semiconductor layer 18. The photoelectric conversion layer 13 is provided between the first electrode 37 and the second electrode 16. The semiconductor layer 18 is provided between the first electrode 37 and the photoelectric conversion layer 13.

[0180] A portion of the semiconductor layer 18 protrudes to the side opposite the photoelectric conversion layer 13 and is connected to the readout electrode 36. In the following description, this protruding portion is referred to as semiconductor wiring 60. A storage electrode 37 with an opening in the center is arranged on the semiconductor layer 18 side of the semiconductor wiring 60 so as to surround the semiconductor wiring 60. The semiconductor element further includes an insulating layer 19 provided between the semiconductor layer 18 and the first electrode (storage electrode) 37. This electrically isolates the storage electrode 37 and the semiconductor wiring 60.

[0181] Furthermore, a charge transfer control electrode 11 is disposed on the readout electrode 36 side of the semiconductor wiring 60. The charge transfer control electrode 11 has a shape with an opening in the center, similar to the storage electrode 37, and is disposed so as to surround the semiconductor wiring 60. The charge transfer control electrode 11 and the semiconductor wiring 60 are electrically isolated from each other by the insulating layer 53 therebetween.

[0182] When the semiconductor layer 18 is configured to have a protruding portion as in this embodiment, the semiconductor layer 18 can be formed using, for example, atomic layer deposition (ALD) to achieve high-precision coating. The semiconductor layer 18 is configured by stacking one or more oxide layers of different types. Specifically, the semiconductor layer 18 includes at least a first oxide layer containing a first element other than oxygen, a second oxide layer containing a second element other than oxygen, a third oxide layer containing the first element, and a fourth oxide layer containing the second element. The first element is different from the second element.

[0183] With this configuration, it is possible to locally modulate each oxide layer, thereby controlling the characteristics of the semiconductor element, thereby improving the characteristics of the semiconductor element.

[0184] Furthermore, among the multiple oxide layers constituting the semiconductor layer, it is preferable that the ionic valence of the oxide layer disposed at the interface with the insulating layer 19 is the same as the ionic valence of the insulating layer. This can suppress the formation of traps at the interface between the semiconductor layer 18 and the insulating layer 19, making it difficult for electrons and holes to be captured. As a result, the mobility and migration speed of electrons and holes are improved.

[0185] The operation of the semiconductor element will be described. For example, if the charges generated in the photoelectric conversion layer PD1 are electrons, a drive signal (also referred to as a control voltage) that lowers the potential in the semiconductor layer 18 near the storage electrode 37 is applied to the storage electrode 37 from the vertical drive circuit 102 during the exposure period. On the other hand, if the charges generated in the photoelectric conversion layer PD1 are holes, a drive signal that raises the potential in the semiconductor layer 18 near the storage electrode 37 is applied to the storage electrode 37 from the vertical drive circuit 102 during the exposure period. Therefore, the charges 58 that are generated in the photoelectric conversion film 34 and enter the semiconductor layer 18 are accumulated in a region of the semiconductor layer 18 near the storage electrode 37.

[0186] In this case, by forming a potential barrier in the semiconductor wiring 60 between the region where the charges are accumulated and the charge transfer control electrode 11, it is possible to prevent the accumulated charges from leaking to the readout electrode 36 side, thereby improving the quantum efficiency. Note that the following description will exemplify a case where the charges generated by the photoelectric conversion layers PD1 and PD2 through photoelectric conversion are electrons, but this is not limiting, and the technology according to the present disclosure can also be applied to a case where the charges are holes by reversing the direction of potential control.

[0187] In this configuration example, a shield electrode 57 is disposed so as to surround the storage electrode 37 of each pixel 10. The shield electrode 57 is connected to the vertical drive circuit 102 via a wiring (not shown) that is one of the pixel drive lines LD. When the vertical drive circuit 102 drives each pixel 10 individually, it applies a drive signal to the shield electrode 57 to form a potential barrier in the semiconductor layer 18 located between adjacent pixels 10. This prevents charge generated in the photoelectric conversion film 34 of a pixel 10 and entering the semiconductor layer 18 from flowing out to an adjacent pixel 10, thereby further improving the quantum efficiency of the pixel 10.

[0188] In addition, in Figure 20B, the horizontal cross section of the semiconductor wiring 60 and the opening shapes of the storage electrode 37 and the charge transfer control electrode 11 are illustrated as being circular, but they may be changed to various shapes, for example, a polygon such as a square or a regular octagon, or an ellipse.

[0189] In this configuration example, one on-chip lens 51 is provided for a plurality of (two in this example) pixels 10. With such a configuration, it is possible to acquire image plane phase difference information between the pixels 10 that share one on-chip lens 51, and therefore it is possible for the system control unit 1050 that controls the image sensor 100 to perform control such as autofocus based on the image plane phase difference information.

[0190] The above description of the semiconductor element according to the fourth embodiment of the present technology can be applied to other embodiments of the present technology unless there is a particular technical contradiction.

[0191] 5. Fifth Embodiment of the Present Technology (Semiconductor Element Example 5) A configuration example of a semiconductor element according to an embodiment of the present technology will be described with reference to FIG. 21 . FIG. 21 is a vertical cross-sectional view showing a configuration example of a semiconductor element according to an embodiment of the present technology. As shown in FIG. 21 , of two adjacent pixels 10a and 10b, while one pixel 10 is performing an exposure operation, the other pixel 10 is not performing an exposure operation. Note that the two pixels 10a and 10b may each have a configuration similar to the pixel 10 described above.

[0192] The semiconductor device according to this embodiment achieves global shutter driving. Specifically, for example, while pixel 10b is performing an exposure operation, a drive signal (also referred to as a control voltage) for lowering the potential in the semiconductor layer 18 near the storage electrode 37 is applied from the vertical drive circuit 102 to the storage electrode 37 of pixel 10b, while a drive signal (also referred to as a control voltage) for lowering the potential in the semiconductor layer 18 near the storage electrode 37 is not applied from the vertical drive circuit 102 to the storage electrode 37 of pixel 10a. Furthermore, a drive signal for forming a potential barrier in the semiconductor layer 18 located between the adjacent pixels 10 is not applied from the vertical drive circuit 102 to the shield electrode 57 located between these two pixels 10a and 10b. Furthermore, the charge transfer control electrode A11 and charge transfer control electrode B15 of pixel 10a, and the charge transfer control electrode A11, memory electrode 16 and charge transfer control electrode B15 of pixel 10b are in a state where no drive signal is applied to each electrode from the vertical drive circuit 102, and the memory electrode 16 of pixel 10a is in a state where a drive signal is applied from the vertical drive circuit 102.

[0193] In this state, the charges 58 generated in the photoelectric conversion film 34 corresponding to the photoelectric conversion layer PD1 of each of the pixels 10a and 10b are attracted to the storage electrode 37 of the pixel 10b, and as a result, the charges 58 generated in the photoelectric conversion film 34 are accumulated in the semiconductor layer 18 near the storage electrode 37 of the pixel 10b. Note that the destination of the charges 58 that have overflowed from the semiconductor layer 18 near the storage electrode 37 of the pixel 10b may be the floating diffusion region FD connected to the readout electrode 36 of the pixel 10b.

[0194] On the other hand, in pixel 10a, the charge 59 accumulated in the semiconductor layer 18 near the storage electrode 37 in the previous frame is held in the semiconductor layer 18 near the memory electrode 16. The charge 59 accumulated in the semiconductor layer 18 near the memory electrode 16 is sequentially read out by a readout operation for pixel 10a that is executed in parallel during exposure of pixel 10b, and is used to generate a pixel signal.

[0195] By performing the above-described operations, it is possible to suppress a decrease in parasitic light receiving sensitivity caused by charge overflowing from the storage region formed by the storage electrode 37 in the semiconductor layer 18 flowing into the semiconductor layer 18 near the memory electrode 16.

[0196] The above description of the semiconductor element according to the fifth embodiment of the present technology can be applied to other embodiments of the present technology unless there is a particular technical contradiction.

[0197] [6. Sixth Embodiment of the Present Technology (Example of Manufacturing Method of Semiconductor Element)] The present technology provides a manufacturing method of a semiconductor element, including forming an insulating layer and stacking one or more oxide layers of a plurality of types to form a semiconductor layer, wherein, of the plurality of oxide layers constituting the semiconductor layer, the ionic valence of an oxide layer disposed at the interface with the insulating layer is the same as the ionic valence of the insulating layer.

[0198] A method for manufacturing the semiconductor element shown in Fig. 18 will be described with reference to Fig. 22 to Fig. 26. Fig. 22 to Fig. 26 are schematic cross-sectional views showing a method for manufacturing a semiconductor element according to an embodiment of the present technology.

[0199] First, as shown in FIG. 22, conductive layers 20A and insulating layers 20B are alternately stacked.

[0200] Next, as shown in FIG. 23, an opening 20H is formed by, for example, dry etching.

[0201] Next, as shown in FIG. 24, an insulating layer 19 is formed by, for example, atomic layer deposition.

[0202] 25, an opening 20H1 is formed by, for example, dry etching, thereby exposing a part of the conductive layer 20A.

[0203] 26, a semiconductor layer is formed by stacking one or more oxide layers of different types, for example, by atomic layer deposition. At this time, it is preferable to select a material such that the ionic valence of the oxide layer disposed at the interface with insulating layer 19, among the multiple oxide layers constituting semiconductor layer 18, is the same as the ionic valence of the insulating layer.

[0204] Another method for manufacturing a semiconductor element will be described with reference to Figures 27 to 29. Figures 27 to 29 are schematic cross-sectional views showing a method for manufacturing a semiconductor element according to an embodiment of the present technology.

[0205] First, the conductive layers 20A and the insulating layers 20B are alternately stacked by the method shown in FIGS. 22 and 23, and then the openings 20H are formed.

[0206] 27, a first insulating layer 19A is formed by, for example, atomic layer deposition, etc. This first insulating layer 19A can contain, for example, SiO or the like.

[0207] 28 , a second insulating layer (insulating layer) 19 is formed by, for example, atomic layer deposition. This second insulating layer 19 may contain, for example, AlO. According to this manufacturing method, the first insulating layer 19A acts as a base for the second insulating layer 19, so that the second insulating layer 19 grows uniformly.

[0208] 29, an opening 20H2 is formed by, for example, dry etching, thereby exposing the conductive layer 20A.

[0209] 30, a semiconductor layer is formed by stacking one or more oxide layers of different types, for example, by atomic layer deposition. At this time, it is preferable to select a material such that the ionic valence of the oxide layer disposed at the interface with the second insulating layer (insulating layer) 19, among the multiple oxide layers constituting the semiconductor layer 18, is the same as the ionic valence of the insulating layer.

[0210] Another method for manufacturing a semiconductor element will be described with reference to Fig. 31 to Fig. 34. Fig. 31 to Fig. 34 are schematic cross-sectional views showing a method for manufacturing a semiconductor element according to an embodiment of the present technology.

[0211] First, by the method shown in FIGS. 22 to 26, conductive layers 20A and insulating layers 20B are alternately stacked, and then insulating layers 19 and semiconductor layers 18 are formed.

[0212] 31, the filling portion 18A is formed by, for example, atomic layer deposition, etc. The material of this filling portion 18A can be, for example, Ga 2 O 3 .

[0213] Next, as shown in FIG. 32, etch back is performed by, for example, dry etching.

[0214] Next, as shown in FIG. 33, the surface is planarized by, for example, CMP (Chemical Mechanical Polishing).

[0215] 34, filling portion 18A is formed by, for example, physical vapor deposition. At this time, it is preferable to select a material such that the ionic valence of elements other than oxygen contained in semiconductor layer 18 is the same as the ionic valence of elements other than oxygen contained in filling portion 18A. This makes it possible to suppress the formation of traps even at the interface between semiconductor layer 18 and filling portion 18A.

[0216] The above description of the semiconductor device manufacturing method according to the sixth embodiment of the present technology can be applied to other embodiments of the present technology unless there is a particular technical contradiction.

[0217] [7. Application Examples of the Present Technology] [(1) Application Examples to Mobile Bodies] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0218] FIG. 35 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0219] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 35, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053.

[0220] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0221] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0222] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0223] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0224] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0225] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0226] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0227] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0228] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 35, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0229] FIG. 36 is a diagram showing an example of the installation position of the imaging unit 12031.

[0230] In FIG. 36, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0231] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0232] 36 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0233] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0234] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation.

[0235] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0236] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0237] The above describes an example of a vehicle control system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to, for example, the image capturing unit 12031 and the like among the components described above.

[0238] (2) Application Example to Endoscopic Surgery System The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be applied to an endoscopic surgery system.

[0239] FIG. 37 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0240] 37 shows an operator (doctor) 11131 performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 is composed of an endoscope 11100, other surgical tools 11110 such as an insufflation tube 11111 and an energy treatment tool 11112, a support arm device 11120 that supports the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are mounted.

[0241] The endoscope 11100 is composed of a lens barrel 11101, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 11132, and a camera head 11102 connected to the base end of the lens barrel 11101. In the example shown, the endoscope 11100 is configured as a so-called rigid scope having a rigid lens barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible scope having a flexible lens barrel.

[0242] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 11101. A light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 11101, and is irradiated via the objective lens toward an object to be observed inside the body cavity of the patient 11132. The endoscope 11100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0243] An optical system and an image sensor are provided inside the camera head 11102, and light reflected from the object of observation (observation light) is collected onto the image sensor by the optical system. The observation light is photoelectrically converted by the image sensor to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. The image signal is sent to a camera control unit (CCU) 11201 as RAW data.

[0244] The CCU 11201 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and comprehensively controls the operations of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102 and performs various types of image processing on the image signal, such as development processing (demosaic processing), to display an image based on the image signal.

[0245] Under the control of the CCU 11201, the display device 11202 displays an image based on an image signal that has been subjected to image processing by the CCU 11201.

[0246] The light source device 11203 is composed of a light source such as an LED (light emitting diode), and supplies irradiation light to the endoscope 11100 when photographing the surgical site, etc.

[0247] The input device 11204 is an input interface for the endoscopic surgery system 11000. A user can input various information and instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user inputs an instruction to change the imaging conditions (type of irradiation light, magnification, focal length, etc.) of the endoscope 11100.

[0248] The treatment tool control device 11205 controls the driving of the energy treatment tool 11112 for cauterizing tissue, incising, sealing blood vessels, etc. The insufflation device 11206 inflates the body cavity of the patient 11132 through the insufflation tube 11111 in order to ensure a clear field of view for the endoscope 11100 and a working space for the surgeon. The recorder 11207 is a device capable of recording various types of information related to the surgery. The printer 11208 is a device capable of printing various types of information related to the surgery in various formats such as text, images, or graphs.

[0249] The light source device 11203, which supplies illumination light to the endoscope 11100 when photographing the surgical site, can be configured from a white light source, such as an LED, a laser light source, or a combination of these. When the white light source is configured from a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, allowing the light source device 11203 to adjust the white balance of the captured image. In this case, it is also possible to time-share images corresponding to each RGB by irradiating the object of observation with laser light from each RGB laser light source and controlling the drive of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, color images can be obtained without providing a color filter to the image sensor.

[0250] Furthermore, the light source device 11203 may be controlled to change the intensity of light it outputs at predetermined time intervals. By controlling the driving of the image sensor of the camera head 11102 in synchronization with the timing of the change in light intensity to acquire images in a time-division manner and combining the images, it is possible to generate an image with a high dynamic range that is free from so-called blocked-up shadows and blown-out highlights.

[0251] The light source device 11203 may also be configured to supply light in a predetermined wavelength band corresponding to special light observation. Special light observation, for example, utilizes the wavelength dependence of light absorption in body tissues to irradiate light with a narrower band than the light irradiated during normal observation (i.e., white light), thereby capturing high-contrast images of specific tissues, such as blood vessels on the surface of mucous membranes, known as narrow-band imaging. Alternatively, special light observation may involve fluorescence observation, in which images are obtained using fluorescence generated by irradiating excitation light. Fluorescence observation may involve irradiating excitation light onto body tissues and observing the fluorescence from the tissue (autofluorescence observation), or by locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the tissue with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 11203 may be configured to supply narrow-band light and / or excitation light corresponding to such special light observation.

[0252] FIG. 38 is a block diagram showing an example of the functional configuration of the camera head 11102 and the CCU 11201 shown in FIG.

[0253] The camera head 11102 has a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 has a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other via a transmission cable 11400 so that they can communicate with each other.

[0254] The lens unit 11401 is an optical system provided at the connection portion with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401. The lens unit 11401 is composed of a combination of multiple lenses including a zoom lens and a focus lens.

[0255] The imaging unit 11402 may include one imaging element (a so-called single-chip type) or multiple imaging elements (a so-called multi-chip type). When the imaging unit 11402 is configured as a multi-chip type, for example, each imaging element may generate an image signal corresponding to each of RGB, and a color image may be obtained by combining these signals. Alternatively, the imaging unit 11402 may be configured to have a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to a 3D (dimensional) display. The 3D display allows the surgeon 11131 to more accurately grasp the depth of the biological tissue at the surgical site. Note that when the imaging unit 11402 is configured as a multi-chip type, multiple lens units 11401 may be provided corresponding to each imaging element.

[0256] Furthermore, the imaging unit 11402 does not necessarily have to be provided in the camera head 11102. For example, the imaging unit 11402 may be provided inside the lens barrel 11101, immediately after the objective lens.

[0257] The driving unit 11403 is configured by an actuator, and moves the zoom lens and focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera head control unit 11405. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted appropriately.

[0258] The communication unit 11404 is configured by a communication device for transmitting and receiving various types of information to and from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

[0259] Furthermore, the communication unit 11404 receives a control signal for controlling the driving of the camera head 11102 from the CCU 11201 and supplies the control signal to the camera head control unit 11405. The control signal includes information on the imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value at the time of imaging, and / or information specifying the magnification and focus of the captured image.

[0260] The image capturing conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by the user, or may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 is equipped with a so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.

[0261] The camera head control unit 11405 controls the driving of the camera head 11102 based on a control signal received from the CCU 11201 via the communication unit 11404 .

[0262] The communication unit 11411 is configured by a communication device for transmitting and receiving various information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.

[0263] Furthermore, the communication unit 11411 transmits to the camera head 11102 a control signal for controlling the driving of the camera head 11102. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.

[0264] The image processing unit 11412 performs various image processing operations on the image signal, which is RAW data transmitted from the camera head 11102 .

[0265] The control unit 11413 performs various controls related to the imaging of the surgical site, etc. by the endoscope 11100 and the display of the captured image obtained by imaging the surgical site, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.

[0266] Furthermore, the control unit 11413 displays the captured image showing the surgical site, etc., on the display device 11202 based on the image signal subjected to image processing by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 11413 can recognize surgical tools such as forceps, specific biological parts, bleeding, mist generated when using the energy treatment tool 11112, etc., by detecting the shape and color of the edges of objects included in the captured image. When displaying the captured image on the display device 11202, the control unit 11413 may use the recognition results to superimpose various surgical support information on the image of the surgical site. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can proceed with the surgery reliably.

[0267] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable for electrical signal communication, an optical fiber for optical communication, or a composite cable of these.

[0268] In the illustrated example, communication is performed wired using a transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may also be performed wirelessly.

[0269] The above describes an example of an endoscopic surgery system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to, for example, the imaging unit 11402 among the components described above. By applying the technology according to the present disclosure, it is possible to improve the characteristics of the semiconductor elements in the imaging unit 11402.

[0270] Although an endoscopic surgery system has been described as an example here, the technology disclosed herein may also be applied to other systems, such as a microsurgery system.

[0271] The above describes an example of an in-vivo information acquisition system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to, for example, the image capturing unit 10112 and the like among the above-described configurations.

[0272] It should be noted that the embodiments of the present technology are not limited to the above-described embodiments, and various modifications are possible within the scope of the present technology. The specific numerical values, shapes, materials (including compositions), etc. described in each embodiment are merely examples, and the present technology is not limited to these.

[0273] The present technology may also have the following configurations. [1] A semiconductor device including an electrode, a semiconductor layer including an oxide semiconductor, and an insulating layer disposed between the electrode and the semiconductor layer, wherein the oxide semiconductor includes a first element other than oxygen, and the insulating layer includes a second element other than oxygen, and wherein the ionic valence of the first element and the ionic valence of the second element are the same. [2] The semiconductor device according to [1], which is used as a light-detecting element. [3] The semiconductor device according to [1], which is used as a transistor. [4] The semiconductor device according to [2], which further includes a photoelectric conversion layer, wherein the photoelectric conversion layer, the semiconductor layer, and the insulating layer are stacked in this order. [5] The semiconductor device according to [4], in which a portion of the semiconductor layer protrudes from the side opposite the photoelectric conversion layer and is connected to a floating diffusion region. [6] The semiconductor device according to any one of [1] to [5], in which the ionic valence is +2, +3, or +4. [7] The semiconductor device according to any one of [1] to [6], wherein the semiconductor layer is configured by laminating one or more oxide layers of different types, and wherein, of the multiple oxide layers constituting the semiconductor layer, the oxide layer disposed at the interface with the insulating layer has the same ionic valence as the insulating layer. [8] The semiconductor device according to [7], wherein the oxide layer disposed at the interface with the insulating layer contains In2O3. [9] The semiconductor device according to [7], wherein the oxide layer disposed at the interface with the insulating layer contains Ga2O3.

[10] The semiconductor device according to [9], wherein the oxide layer disposed at the interface with the insulating layer contains Ga2O3, and wherein an oxide layer containing In2O3, an oxide layer containing Ga2O3, and the insulating layer are laminated in this order.

[11] The semiconductor device according to any one of [7] to

[10] , wherein, of the multiple oxide layers constituting the semiconductor layer, at least one oxide layer has an ionic valence different from the ionic valence of the insulating layer.

[12] A photodetector element comprising a first electrode, a second electrode, a photoelectric conversion layer provided between the first electrode and the second electrode, and a semiconductor layer provided between the first electrode and the photoelectric conversion layer, wherein the semiconductor layer includes at least a first oxide layer containing a first element other than oxygen, a second oxide layer containing a second element other than oxygen, a third oxide layer containing the first element, and a fourth oxide layer containing the second element, wherein the first element is different from the second element.

[13] The photodetector element according to

[12] , wherein a portion of the semiconductor layer protrudes to a side opposite the photoelectric conversion layer and is connected to the second electrode.

[14] The photodetector element according to

[12] , further comprising an insulating layer provided between the semiconductor layer and the first electrode.

[15] A method for manufacturing a semiconductor element, comprising: forming an insulating layer; and forming a semiconductor layer by stacking one or more oxide layers of a plurality of types, wherein the ionic valence of an oxide layer disposed at an interface with the insulating layer among the plurality of oxide layers constituting the semiconductor layer is the same as the ionic valence of the insulating layer.

[0274] REFERENCE SIGNS LIST 10 Pixel 13 Photoelectric conversion layer 11 Lower electrode 16 Upper electrode 17 Insulating layer 18 Semiconductor layer 19 Insulating layer 30 Semiconductor substrate 60 Semiconductor wiring 100 Photodetector 1000 Electronic device 2000 Photodetection system 2001 Light-emitting device 2002 Photodetector 2003 System control unit 2004 Light source driving unit 2005 Sensor control unit 2006 Light source side optical system 2007 Camera side optical system

Claims

1. A semiconductor device having an electrode, a semiconductor layer including an oxide semiconductor, and an insulating layer disposed between the electrode and the semiconductor layer, wherein the oxide semiconductor contains a first element other than oxygen, the insulating layer contains a second element other than oxygen, and the valence of the first element is the same as the valence of the second element.

2. The semiconductor device according to claim 1, which is used for a photodetector.

3. The semiconductor device according to claim 1, which is used for a transistor.

4. The semiconductor device according to claim 2, further comprising a photoelectric conversion layer, wherein the photoelectric conversion layer, the semiconductor layer, and the insulating layer are laminated in this order.

5. The semiconductor device according to claim 4, wherein a part of the semiconductor layer protrudes from the side opposite to the photoelectric conversion layer and is connected to a floating diffusion region.

6. The semiconductor device according to claim 1, wherein the valence is +2, +3, or +4.

7. The semiconductor device according to claim 1, wherein the semiconductor layer has a structure in which a plurality of types of oxide layers are laminated one or more layers each, and among the plurality of oxide layers constituting the semiconductor layer, the valence of the oxide layer disposed at the interface with the insulating layer is the same as the valence of the insulating layer.

8. The semiconductor device according to claim 7, wherein the oxide layer disposed at the interface with the insulating layer contains In2O3.

9. The semiconductor device according to claim 7, wherein the oxide layer disposed at the interface with the insulating layer contains Ga2O3.

10. The semiconductor device according to claim 9, wherein the oxide layer disposed at the interface with the insulating layer contains Ga2O3, and an oxide layer containing In2O3, an oxide layer containing Ga2O3, and the insulating layer are laminated in this order.

11. The semiconductor device according to claim 7, wherein among the plurality of oxide layers constituting the semiconductor layer, the valence of at least one oxide layer is different from the valence of the insulating layer.

12. A photodetector having a first electrode, a second electrode, a photoelectric conversion layer provided between the first electrode and the second electrode, and a semiconductor layer provided between the first electrode and the photoelectric conversion layer, wherein the semiconductor layer includes at least a first oxide layer containing a first element other than oxygen, a second oxide layer containing a second element other than oxygen, a third oxide layer containing the first element, and a fourth oxide layer containing the second element, and the first element is different from the second element.

13. The photodetector according to claim 12, wherein a part of the semiconductor layer protrudes to the side opposite to the photoelectric conversion layer and is connected to the second electrode.

14. The photodetector according to claim 12, further comprising an insulating layer provided between the semiconductor layer and the first electrode.

15. A method for manufacturing a semiconductor device, including forming an insulating layer and laminating one or more oxide layers of a plurality of types to form a semiconductor layer, wherein the valence of the oxide layer disposed at the interface with the insulating layer among the plurality of oxide layers constituting the semiconductor layer is the same as the valence of the insulating layer.

Images