Multilayer wiring board

Abstract

The present invention provides a multilayer wiring board comprising: a glass substrate; and a wiring laminate which is arranged on the glass substrate, and which includes repeatedly stacked wiring layers, insulating layers, and interlayer connection conductors. A passive element formed by the wiring layers, the interlayer connection conductors or the insulating layers are integrated into the wiring laminate. The glass substrate is provided as a support substrate of the wiring laminate so as to suppress overall warpage of the multilayer wiring board. A through glass via that penetrates the glass substrate is formed such that the wiring layers included in the wiring laminate can be electrically connected to the through glass via.

Description

multilayer wiring board

[0001] The present invention relates to a multilayer wiring board. More specifically, it relates to a multilayer wiring board including multiple insulating layers and wiring layers.

[0002] For example, a multilayer wiring board, such as a printed circuit board, is used to connect semiconductor chips such as an AP (Application Processor) chip and memory devices included in a smart phone to a circuit. The multilayer wiring board may include a plurality of insulating layers and a plurality of wiring layers repeatedly laminated therein. The AP chip or semiconductor chip can be mounted on the multilayer wiring board through soldering, wire connection, etc. using the outermost insulating layer and wiring layer.

[0003] Recently, as electronic components become more highly integrated, multilayer wiring boards may include a greater number of wiring layers. In this case, substrate warpage may occur due to differences in the coefficients of thermal expansion of the insulating and wiring layers. Furthermore, the heat generated during signal transmission to the AP chip or semiconductor chip may exacerbate this substrate warpage.

[0004] In addition, when passive elements such as capacitors, inductors, and resistors are included in the substrate, substrate warpage, substrate cracks, etc. may occur more easily due to differences in thermal expansion coefficients between the passive elements and the multilayer wiring substrate.

[0005] An object of the present invention is to provide a multilayer wiring board having improved mechanical stability and electrical efficiency.

[0006] 1. A multilayer wiring board comprising: a glass substrate including a through-via hole; a through-glass via (TGV) partially filling the through-via hole; a filling insulating pattern filling the remaining portion of the through-via hole; and a wiring laminate disposed on an upper surface of the glass substrate and having a passive component embedded therein.

[0007] 2. A multilayer wiring board, wherein in the above 1, the filling insulating pattern includes a resin material having a lower elastic modulus than the through glass via.

[0008] 3. In the above 1, the wiring laminate is a multilayer wiring board including repeatedly laminated wiring layers, insulating layers, and interlayer connection conductors.

[0009] 4. A multilayer wiring board according to the above 3, wherein the filling insulating pattern includes an organic resin material having a lower elastic modulus than the insulating layers.

[0010] 5. A multilayer wiring board according to the above 3, wherein the filling insulating pattern includes an organic resin material having a lower thermal expansion coefficient than the insulating layers.

[0011] 6. A multilayer wiring board in the above 3, wherein the filling insulating pattern and the insulating layers contain different organic resin materials.

[0012] 7. In the above 3, the passive element is formed by the wiring layers, the interlayer connection conductors or the insulating layers, a multilayer wiring board.

[0013] 8. A multilayer wiring board according to 7 above, wherein the passive element includes at least one of a resistor, a capacitor, and an inductor.

[0014] 9. In the above 8, the register is a multilayer wiring board including a line pattern included in one of the wiring layers.

[0015] 10. In the above 7, the capacitor is a multilayer wiring board including first electrodes and second electrodes included in different levels of wiring layers among the wiring layers, and an insulating layer disposed between the first electrode and the second electrode among the insulating layers.

[0016] 11. In the above 8, the capacitor,

[0017] A first terminal electrode and a second terminal electrode spaced apart from each other and included in the above wiring layers; and first internal electrodes and second internal electrodes included in an interlayer connection conductor of one layer among the interlayer connection conductors,

[0018] A multilayer wiring board, wherein one end of the first internal electrodes is connected to the first terminal electrode, and the other end of the second internal electrodes is connected to the second terminal electrode.

[0019] 12. A multilayer wiring board in the above 11, wherein the first internal electrodes and the second internal electrodes are alternately repeated within one of the insulating layers.

[0020] 13. In the above 8, the inductor is a multilayer wiring board including a first coil part and a second coil part respectively included in different wiring layers among the wiring layers, and a coil via connecting the first coil part and the second coil part.

[0021] 14. In the above 8, the inductor

[0022] A multilayer wiring board comprising: first terminal electrodes and lower connection electrodes included in one of the wiring layers; second terminal electrodes and upper connection electrodes included in another of the wiring layers; and coil vias zigzag-connected by the lower connection electrodes and the upper connection electrodes.

[0023] 15. A multilayer wiring board according to the above 14, wherein the coil vias are included in an interlayer connection conductor disposed within an insulating layer between the one wiring layer and the other wiring layer.

[0024] According to embodiments of the present invention, a wiring laminate can be laminated on a glass substrate. The glass substrate serves as a support substrate for the wiring laminate, and can suppress overall warpage of the multilayer wiring substrate.

[0025] According to exemplary embodiments, a through glass via penetrating the glass substrate can be formed to electrically connect wiring layers included in the wiring laminate to the through glass via. Accordingly, electrical signal loss from the lower surface of the glass substrate to the upper surface of the wiring laminate can be reduced, and high-Q characteristics can be implemented.

[0026] According to exemplary embodiments, a filling insulating pattern including an organic material can be formed within a through-glass via. The filling insulating pattern can suppress mechanical failure due to differences in physical properties between the glass substrate and the through-glass via, while enhancing the mechanical and electrical stability of the through-glass via.

[0027] According to exemplary embodiments, the wiring laminate may include passive components embedded therein. Therefore, the high-temperature SMT process for mounting passive components on the outer surface of the substrate can be omitted, thereby further preventing thermal damage and warpage of the substrate. Furthermore, the passive components can be designed utilizing the wiring layers included in the wiring laminate. Therefore, the manufacturing cost of the passive components can be reduced, while facilitating the design of a highly integrated circuit structure.

[0028] FIG. 1 is a schematic cross-sectional view showing a multilayer wiring board according to exemplary embodiments.

[0029] FIG. 2 is a schematic cross-sectional view illustrating one implementation example of a passive component included in a multilayer wiring board according to exemplary embodiments.

[0030] FIG. 3 is a schematic cross-sectional view illustrating one embodiment of a passive component included in a multilayer wiring board according to exemplary embodiments.

[0031] FIG. 4 is a schematic perspective view illustrating implementation examples of passive components included in a multilayer wiring board according to exemplary embodiments.

[0032] FIG. 5 is a schematic plan view illustrating one implementation example of a passive component included in a multilayer wiring board according to exemplary embodiments.

[0033] FIGS. 6A and 6B are schematic perspective and cross-sectional views, respectively, illustrating one implementation example of a passive component included in a multilayer wiring board according to exemplary embodiments.

[0034]

[0035] Embodiments of the present invention provide a multilayer wiring substrate including a glass substrate and a wiring laminate.

[0036] Hereinafter, embodiments of the present invention will be described in more detail with reference to the drawings. However, the following drawings attached to this specification illustrate preferred embodiments of the present invention and, together with the contents of the invention described above, serve to further understand the technical concept of the present invention. Therefore, the present invention should not be interpreted as being limited to the matters described in such drawings.

[0037] The terms “first”, “second”, “third”, “fourth”, “first”, “other”, “top”, “bottom”, etc. used in this application do not limit absolute positions or orders, but are used in a relative sense to distinguish different components or parts.

[0038] FIG. 1 is a schematic cross-sectional view showing a multilayer wiring board according to exemplary embodiments.

[0039] Referring to FIG. 1, a multilayer wiring board (100) may include a glass substrate (105) and a wiring laminate (107) laminated on the glass substrate (105).

[0040] The glass substrate (105) may be manufactured from a glass product or bare glass that substantially does not contain organic materials. For example, the term "glass substrate" used in the present application may be used to mean a structure in which glass particles or glass fibers are impregnated into an organic layer. In one embodiment, the glass substrate may include tempered glass.

[0041] In some embodiments, the glass substrate (105) may not include any vacancies or etched spaces (e.g., recesses, grooves, cavities, etc.) other than through via holes for forming through glass vias as described below.

[0042] The dielectric constant of the glass substrate (105) may be 1 to 10, 1 to 7, 1 to 5, or 1 to 3 at 1 MHz. The loss tangent (dielectric loss) of the glass substrate (105) may be 0.00005 to 0.001, for example, 0.0005 to 0.001. The thermal expansion coefficient of the glass substrate (105) may be 1*10 -6 / K to 10 -5 / K, for example, 1*10 -6 / K to 5*10 -6 / K could be.

[0043] The thickness of the glass substrate (105) may be 25 µm to 1,000 µm, 50 µm to 1,000 µm, 100 µm to 1,000 µm, or 500 µm to 1,000 µm. The thickness of the glass substrate (105) may be appropriately adjusted within the above range in consideration of the thickness and number of layers of the wiring laminate (107).

[0044] The glass substrate (105) has a low dielectric loss value and can be applied as a support substrate to a multilayer wiring substrate described later to improve the low loss and high Q characteristics of the wiring substrate. In addition, the glass substrate (105) has a low coefficient of thermal expansion and can effectively suppress warpage occurring during high-temperature operation and build-up processes of the wiring substrate.

[0045] A through glass via (TGV) (110) may be formed inside the glass substrate (105). The through glass via (110) may extend as a single integral structure across the upper and lower surfaces of the glass substrate (105). The upper and lower surfaces of the through glass via (110) may be exposed to the upper and lower surfaces of the glass substrate (105), respectively.

[0046] According to embodiments of the present invention, a filling insulating pattern (115) may be formed inside a through-glass via (110). The through-glass via (110) may have a shape that surrounds the outer surface of the filling insulating pattern (115). According to exemplary embodiments, the through-glass via (110) may entirely surround the outer surface of the filling insulating pattern (115).

[0047] For example, a through via hole (103) penetrating the upper and lower surfaces of the glass substrate (105) can be formed through laser drilling, etc. A through glass via (110) can be formed by partially filling the through via hole (103) with a metal material through a plating process (e.g., copper plating).

[0048] The through glass via (110) contacts the sidewall of the through via hole (103) and can partially fill the through via hole (103). Thereafter, an organic material can be filled into the through via hole (103) to form a filling insulating pattern (115) that fills the remaining portion of the through via hole (103).

[0049] The filling insulating pattern (115) may include an organic resin material such as an epoxy resin, an acrylic resin, or a polyresist. In one embodiment, the filling insulating pattern (115) may be formed of an epoxy resin.

[0050] The filling insulating pattern (115) may include an organic resin material having a lower elastic modulus or elasticity than the through glass via (110). Accordingly, it may absorb stress due to thermal expansion of the through glass via (110) and serve as a buffer layer that blocks stress propagation to the glass substrate (105).

[0051] In addition, as the filling insulating pattern (115) partially fills the through-via hole (103), the amount of metal material included in the glass substrate (105) can be reduced. Accordingly, while maintaining the conductive properties through the through-glass via (110), damage to the substrate and deterioration of electrical interconnection due to differences in physical properties such as the coefficient of thermal expansion and elastic modulus of the glass and the metal can be prevented.

[0052] The elastic modulus of the material included in the filling insulating pattern (115) may be smaller than the elastic modulus of the through glass via (110). In some embodiments, the elastic modulus of the filling insulating pattern (115) is 0.02x10 6 kgf / cm 2 0.04x10 6 kgf / cm 2 may be. For example, the elastic modulus of the filling insulating pattern (115) may be 0.02x10 6 kgf / cm 2 0.03x10 6 kgf / cm 2 , or 0.02x10 6 kgf / cm 2 0.025x10 6 kgf / cm 2 It could be.

[0053] For example, the elastic modulus of the metal material included in the through glass via (110) is 0.5x10 6 kgf / cm 2 4x10 inland 6 kgf / cm 2 , 1.0x10 6 kgf / cm 2 3.7x10 6 kgf / cm 2 , or 1.0x10 6 kgf / cm 2 3.0x10 6 kgf / cm 2 It could be.

[0054] In some embodiments, the maximum diameter of the through via hole (103) may be 25 μm to 300 μm. Within this range, sufficient conductivity can be secured while securing space for forming a filling insulating pattern (115) and preventing an excessive increase in the difference in thermal expansion coefficient due to an increase in the amount of conductive material.

[0055] In one embodiment, the diameter of the through via hole (103) may be 50 μm to 300 μm, or 100 μm to 200 μm.

[0056] In some embodiments, the thickness of the through glass via (110) from the sidewall of the through via hole (103) may be 1 μm to 20 μm. Within this range, excessive thermal expansion of the through glass via (110) can be prevented and sufficient conductivity can be secured.

[0057] In one embodiment, the thickness of the through glass via (110) may be from 1 μm to 10 μm, or from 1 μm to 5 μm.

[0058] As illustrated in FIG. 1, the through glass via (110) and the filling insulating pattern (115) may be exposed together to the upper surface and the lower surface of the glass substrate (105), respectively. Accordingly, the upper surfaces of the through glass via (110) and the filling insulating pattern (115) may be exposed to the upper surface of the glass substrate (105) and may be arranged substantially on the same plane. The lower surfaces of the through glass via (110) and the filling insulating pattern (115) may be exposed to the lower surface of the glass substrate (105) and may be arranged substantially on the same plane.

[0059] The wiring laminate (107) may be an organic substrate including wiring layers. According to exemplary embodiments, the wiring laminate (107) may include insulating layers (120) and wiring layers (130) that are repeatedly laminated from the upper surface of the glass substrate (105). According to exemplary embodiments, the wiring layers (130) and insulating layers (120) may be build-up wiring layers and build-up insulating layers that are alternately and repeatedly laminated.

[0060] For example, the wiring layers (130) may include a first wiring layer (130a), a second wiring layer (130b), a third wiring layer (130c), a fourth wiring layer (130d), and a fifth wiring layer (130e). The insulating layers (120) may include a first insulating layer (120a), a second insulating layer (120b), a third insulating layer (120c), and a fourth insulating layer (120d).

[0061] According to exemplary embodiments, on the upper surface of the glass substrate (105), wiring layers (130) and insulating layers (120) may be alternately and repeatedly laminated in the following order: a first wiring layer (130a), a first insulating layer (120a), a second wiring layer (130b), a second insulating layer (120b), a third wiring layer (130c), a third insulating layer (120c), etc.

[0062] However, the number of wiring layers (130) and insulating layers (120) illustrated in FIG. 1 is only an example provided for convenience of explanation, and the number of layers and circuit design of the wiring laminate (107) are not limited as illustrated in FIG. 1.

[0063] The wiring layers (130) can be formed by forming a conductive layer on the upper surface of the glass substrate (105) or on any one of the insulating layers (120), and then patterning the conductive layer through an etching process. The conductive layer can be formed through a deposition process such as a plating process or a sputtering process.

[0064] In some embodiments, the wiring layers (130) may be formed through a SAP process (Semi-Additive Process), an M-SAP process (Modified Semi-Additive Process), or a tenting process.

[0065] The wiring layers (130) may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof, and may include, for example, copper (Cu).

[0066] The insulating layers (120) may each be formed to cover the wiring layer (130). The insulating layers (120) may be formed using a photosensitive resin such as an acrylic resin and / or a thermosetting resin such as an epoxy resin. In one embodiment, the insulating layers (120) may include an acrylic resin.

[0067] According to exemplary embodiments, the filling insulating pattern (115) and the insulating layers (120) may include different organic resin materials.

[0068] In some embodiments, the elastic modulus of the filling insulating pattern (115) may be less than the elastic modulus of the insulating layer (120). In some embodiments, the thermal expansion coefficient of the filling insulating pattern (115) may be less than the thermal expansion coefficient of the insulating layer (120).

[0069] Therefore, as described above, the heat-induced stress of the glass substrate (105) can be effectively absorbed / buffered through the filling insulating pattern (115).

[0070] In some embodiments, the filling insulating pattern (115) may include a resin having a lower viscosity than the insulating layer (120). Accordingly, a highly reliable filling insulating pattern (115) can be formed without voids within the through via hole (103) while easily implementing a low elastic modulus. In addition, the insulating layer (120) can implement improved coverage characteristics while having relatively high flatness.

[0071] The wiring laminate (107) may further include interlayer connection conductors (140) that connect the wiring layers (130) to each other. The interlayer connection conductors (140) are disposed between wiring layers (130) of different levels and refer to conductors formed within the insulating layer (120).

[0072] In some embodiments, the interlayer interconnect conductor (140) may include interlayer vias that connect wiring layers (130) arranged at different levels.

[0073] In some embodiments, the interlayer interconnect conductor (140) may include a wiring-TGV via (140a) that interconnects the through-glass via (110) and the wiring layer (130) (e.g., the second wiring layer (130b)). The wiring-TGV via (140a) may be in direct contact with the through-glass via (110) and the second wiring layer (130b). The wiring-TGV via (140a) may also be in direct contact with the filling insulating pattern (115).

[0074] In some embodiments, the interlayer interconnect conductor (140) may include an interlayer via (140b) that interconnects the upper and lower wiring layers (130) with each other.

[0075] According to embodiments of the present invention, a passive element may be included within the wiring laminate (107). For example, the wiring laminate (107) may be provided as an integrated passive device (IPD) substrate having the passive element built into it.

[0076] According to exemplary embodiments, the passive component may be implemented as an inherent component formed by the arrangement of wiring layers (130) and insulating layers (120) rather than being inserted into the wiring laminate (107) as a separate chip.

[0077] The passive components may include inductors, capacitors, resistors, and the like. In some embodiments, the passive components may include a first passive component (PE1), a second passive component (PE2), and a third passive component (PE3).

[0078] The first passive element (PE1), the second passive element (PE2), and the third passive element (PE3) may each be different types of passive elements. For example, the first passive element (PE1) may include a conductor pattern included in the second wiring layer (130b) and a conductor pattern included in the third wiring layer (130c), and the conductor patterns may face each other with the second insulating layer (120b) interposed therebetween. Accordingly, the first passive element (PE1) may be provided as a capacitor.

[0079] The second passive element (PE2) may include, for example, a line pattern having a relatively large length included in the fourth wiring layer (130d). Accordingly, the second passive element (PE2) may be provided as a resistor.

[0080] The third passive element (PE3) may include a coil in which at least two layers of wiring layers are connected through interlayer connecting conductors (140) (e.g., interlayer vias). Accordingly, the third passive element (PE3) may be provided as an inductor.

[0081] As described above, a passive component embedded in a wiring substrate (100) or a wiring laminate (107) can be designed by utilizing the wiring layers (130), insulating layers (120) and / or interlayer connection conductors (140) included in the wiring laminate (107). According to exemplary embodiments, the passive component may not include any other configuration / structure other than the wiring layer (130), insulating layer (120) and / or interlayer connection conductor (140).

[0082] Accordingly, a separate, isolated chip-shaped passive element having a material different from that included in the wiring laminate (107) is not included, and an increase in warpage due to a difference in physical properties, such as a coefficient of thermal expansion, of the chip-shaped passive element can be prevented.

[0083] In addition, the integration density of passive components can be easily controlled by adjusting the line and space of the wiring layers (130). Accordingly, high integration density of passive components can be efficiently implemented, and an RF substrate can be effectively provided.

[0084] As described above, the passive element can be designed to be integrated with the wiring layer (130). Therefore, compared to a case where a separate chip is embedded, signal loss can be reduced and high Q characteristics can be enhanced.

[0085] According to exemplary embodiments, the wiring laminate (107) and the glass substrate (105) may not include a chip receiving space, such as a cavity, recess, or through hole, for inserting / embedding an electric element in the form of a chip (e.g., a passive element and an active element such as an IC chip), within the chip. Accordingly, mechanical defects, such as a decrease in substrate rigidity or warping due to the chip receiving space, can be prevented.

[0086] Through-glass vias (110) can be classified according to the conductive pattern included in the wiring laminate (107) to which they are connected. In some embodiments, the through-glass vias (110) can include a first through-glass via (110a), a second through-glass via (110b), and a third through-glass via (110c).

[0087] Interlayer connection conductors (140) and wiring layers (130) may be alternately and sequentially laminated on the first through-glass via (110a) to form a common interconnect structure (CI). For example, the common interconnect structure (CI) may provide the shortest distance electrical signal path across the glass substrate (105) and the wiring laminate (107) in the vertical direction or thickness direction of the wiring substrate (100).

[0088] The above-described wiring-TGV via (140a) may be laminated or in contact with the upper surface of the first through-glass via (110a). Wiring layers (130) and interlayer vias (140b) may be alternately and repeatedly laminated on the wiring-TGV via (140a) to form a common interconnect structure (CI).

[0089] The common interconnect structure (CI) may be provided as a substantially single pillar. For example, a virtual centerline vertically penetrating the first through-glass via (110a) may penetrate the entire common interconnect structure (CI).

[0090] The second through-glass via (110b) can be connected to a passive element. For example, it can be connected to the first passive element (PE1) through a wiring-TGV via (140a).

[0091] The third through-glass via (110c) may be connected to the wiring layer (130). For example, the third through-glass via (110c) may be electrically connected to the first wiring layer (130a) through a wiring-TGV via (140a) and an interlayer via (140b).

[0092] A lower wiring layer (190) and a lower insulating layer (180) can be laminated on the lower surface of the glass substrate (105). A lower wiring via (195) can be connected or in contact with the lower wiring layer (190).

[0093] The common interconnect structure (CI) may further include a TGV connecting via (197) that contacts the lower surface of the through glass via (110).

[0094] The wiring laminate (107) may be provided as an upper wiring / insulating structure of the wiring board (100). The uppermost wiring layer (e.g., the fifth wiring layer (130e)) included in the wiring laminate (107) may include a pad for mounting an electronic component. For example, an active component such as a semiconductor die, an AP chip, an IC chip, etc. may be mounted on the pad by soldering or wire bonding.

[0095] In some embodiments, the TGV connection via (197) and the lower wiring via (195) may be connected to the motherboard via conductive balls or soldering.

[0096] FIG. 2 is a schematic cross-sectional view illustrating an example implementation of a passive component included in a multilayer wiring board according to exemplary embodiments. For example, FIG. 2 illustrates an example implementation of a second passive component (PE2) provided as a resistor.

[0097] Referring to FIG. 2, a line pattern (132a) included in the wiring layers (130) may be placed on a lower insulating layer (e.g., a third insulating layer (120c)). An upper insulating layer (e.g., a fourth insulating layer (120d)) may be in direct contact with the line pattern (132a) and cover the line pattern (132a). Resistance may be adjusted depending on the length of the line pattern (132a), thereby providing a passive element that functions as a resistor.

[0098] A connection electrode (141) may be formed at each end of the line pattern (132a). The connection electrode (141) may penetrate the upper insulating layer and contact or be connected to the line pattern (132a). A terminal electrode (132b) may be formed on the upper insulating layer and contact or be connected to the connection electrode (141).

[0099] The line pattern (132a) is included as a configuration of one of the wiring layers (130), and can be formed at the same level with substantially the same material and the same process as the wiring layer (130). The terminal electrode (132b) is also included as a configuration of one of the wiring layers (130) (e.g., the uppermost wiring layer (e.g., the fifth wiring layer (130e))) among the wiring layers (130), and can be formed at the same level with substantially the same material and the same process as the wiring layer (130).

[0100] The connecting electrode (141) is included as a component of one layer of the interlayer connecting conductor (140) among the interlayer connecting conductors (140), and can be formed at the same level using substantially the same material and the same process as the interlayer connecting conductor (140).

[0101] FIG. 3 is a schematic cross-sectional view illustrating an example implementation of a passive component included in a multilayer wiring board according to exemplary embodiments. For example, FIG. 3 illustrates an example implementation of a first passive component (PE1) provided as a capacitor.

[0102] Referring to FIG. 3, the first electrode (131) and the second electrode (133) can be positioned facing each other with an insulating layer (120) therebetween. Accordingly, a passive element of a MIM (Metal-Insulator-Metal) capacitor structure can be implemented.

[0103] The first electrode (131) and the second electrode (133) are each included as a component of one of the wiring layers (130), and can be formed at the same level using substantially the same material and the same process as the wiring layer (130).

[0104] As illustrated in FIG. 1, the first electrode (131) and the second electrode (133) may each be connected to an interlayer connection conductor (140) (see the first passive element (PE1)). The interlayer connection conductor (140) connected to the first electrode (131) and the second electrode (133) may be provided as a terminal electrode or an external electrode.

[0105] Figure 4 is a schematic perspective view illustrating implementation examples of passive components included in a multilayer wiring board according to exemplary embodiments. Figure 4 illustrates one implementation example of a capacitor as a passive component.

[0106] Referring to FIG. 4, one of the wiring layers (130) may be provided as a first terminal electrode (134) (or a first external electrode), and one of the wiring layers (130) may be provided as a second terminal electrode (136) (or a second external electrode). In one embodiment, the first terminal electrode (134) and the second terminal electrode (136) may be included in a wiring layer (130) of the same level. Alternatively, the first terminal electrode (134) and the second terminal electrode (136) may be included in wiring layers (130) of different levels.

[0107] Internal electrodes may be distributed within the insulating layer (120). For example, first internal electrodes (142) and second internal electrodes (144) may be alternately repeated in the horizontal direction.

[0108] One end of the first internal electrodes (142) can be in contact with or connected to the first terminal electrode (134). The other end of the second internal electrodes (144) (the ends opposite to the one end of the first internal electrodes (152)) can be in contact with or connected to the second terminal electrode (136).

[0109] A capacitance can be formed in the insulating layer (120) portion between the first internal electrode (142) and the second internal electrode (144) that are adjacent to each other. Accordingly, a passive element having a multilayer capacitor structure can be implemented.

[0110] The first internal electrodes (142) and the second internal electrodes (144) are included as a configuration of one layer of the interlayer connection conductor (140) among the interlayer connection conductors (140), and can be formed at the same level using substantially the same material and the same process as the interlayer connection conductor (140).

[0111] FIG. 5 is a schematic plan view illustrating an example implementation of a passive component included in a multilayer wiring board according to exemplary embodiments. For example, FIG. 5 illustrates an example implementation of a third passive component (PE3) provided as an inductor.

[0112] Referring to FIG. 5, a first coil part (138) is placed on a lower insulating layer (not shown) (e.g., a second insulating layer (120b)), and an upper insulating layer (not shown) (e.g., a third insulating layer (120c)) may be in contact with the first coil part (138) and cover the first coil part (138). A second coil part (139) may be placed on the upper insulating layer.

[0113] The first coil section (138) and the second coil section (139) can be connected to each other by a coil via (not shown) penetrating the upper insulating layer. Accordingly, a coil-shaped inductor having multiple turns can be implemented.

[0114] The first coil portion (138) and the second coil portion (139) are each included as a configuration of one of the wiring layers (130), and can be formed at the same level using substantially the same material and the same process as the wiring layer (130).

[0115] The above coil via is included as a component of one layer of the interlayer connection conductor (140) among the interlayer connection conductors (140), and can be formed at the same level with substantially the same material and the same process as the interlayer connection conductor (140).

[0116] Terminal electrodes (not shown) may be contacted or connected to the ends of the first coil portion (138) and the second coil portion (139), respectively. The terminal electrodes are included as a component of one layer of the interlayer connection conductors (140) among the interlayer connection conductors (140), and may be formed at the same level using substantially the same material and the same process as the interlayer connection conductor (140).

[0117] Figures 6a and 6b are schematic perspective views and cross-sectional views, respectively, illustrating one embodiment of a passive component included in a multilayer wiring board according to exemplary embodiments. For example, Figure 6b is a cross-sectional view taken vertically or in the thickness direction along line II' of Figure 6a.

[0118] Referring to FIGS. 6A and 6B, one of the wiring layers (130) may include a first terminal electrode (135) (or a first external electrode) and lower connection electrodes (135a). The upper wiring layer (130) may include a second terminal electrode (137) (or a second external electrode) and upper connection electrodes (137a) with an insulating layer (120) therebetween relative to the first terminal electrode (135) and lower connection electrodes (135a).

[0119] Coil vias (145) may be distributed within the insulating layer (120). The coil vias (145) are included as a component of one layer of the interlayer connection conductors (140) among the interlayer connection conductors (140), and may be formed at the same level using substantially the same material and the same process as the interlayer connection conductor (140).

[0120] A first terminal electrode (135) and a second terminal electrode (137) may be connected through coil vias (145) and connection electrodes (135a, 137a) to form a coil-shaped inductor. According to exemplary embodiments, neighboring coil vias (145) in the width direction may be connected to each other by an upper connection electrode (137a), and neighboring coil vias (145) in a diagonal direction with respect to the width direction may be connected to each other by a lower connection electrode (135a). Accordingly, a conductor may be repeated in a zigzag pattern across the lower and upper layers to form a coil.

[0121] The multilayer wiring board (100) described above can be applied as a circuit board for highly integrated electronic devices such as smart phones, PCs, semiconductor packages, etc. A glass substrate (105) and a passive component-embedded wiring laminate can be combined to provide a thin circuit board with low loss, high Q, and high speed.

Claims

1. A glass substrate including a through via hole; Through glass vias (TGVs) that partially fill the above through via holes; A filling insulating pattern filling the remainder of the above through via hole; and A multilayer wiring board comprising a wiring laminate having a passive component built into it and arranged on the upper surface of the glass substrate.

2. A multilayer wiring board according to claim 1, wherein the filling insulating pattern includes a resin material having a lower elastic modulus than the through-glass via.

3. A multilayer wiring board according to claim 1, wherein the wiring laminate comprises repeatedly laminated wiring layers, insulating layers, and interlayer connection conductors.

4. A multilayer wiring board according to claim 3, wherein the filling insulating pattern includes an organic resin material having a lower elastic modulus than the insulating layers.

5. A multilayer wiring board according to claim 3, wherein the filling insulating pattern includes an organic resin material having a lower thermal expansion coefficient than the insulating layers.

6. A multilayer wiring board according to claim 3, wherein the filling insulating pattern and the insulating layers contain different organic resin materials.

7. A multilayer wiring board according to claim 3, wherein the passive element is formed by the wiring layers, the interlayer connection conductors or the insulating layers.

8. A multilayer wiring board according to claim 7, wherein the passive component includes at least one of a resistor, a capacitor, and an inductor.

9. A multilayer wiring board according to claim 8, wherein the register includes a line pattern included in one of the wiring layers.

10. A multilayer wiring board according to claim 8, wherein the capacitor includes first electrodes and second electrodes respectively included in different levels of wiring layers among the wiring layers, and an insulating layer disposed between the first electrode and the second electrode among the insulating layers.

11. In claim 8, the capacitor, First terminal electrodes and second terminal electrodes spaced apart from each other and included in the above wiring layers; and Including first internal electrodes and second internal electrodes included in one layer of the interlayer connection conductors among the above interlayer connection conductors, A multilayer wiring board, wherein one end of the first internal electrodes is connected to the first terminal electrode, and the other end of the second internal electrodes is connected to the second terminal electrode.

12. A multilayer wiring board according to claim 11, wherein the first internal electrodes and the second internal electrodes are alternately repeated within one of the insulating layers.

13. A multilayer wiring board according to claim 8, wherein the inductor includes a first coil part and a second coil part respectively included in different wiring layers among the wiring layers, and a coil via connecting the first coil part and the second coil part.

14. In claim 8, the inductor First terminal electrodes and lower connection electrodes included in one of the above wiring layers; Second terminal electrodes and upper connection electrodes included in another wiring layer among the above wiring layers; and A multilayer wiring board comprising coil vias connected in a zigzag manner by the lower connecting electrodes and the upper connecting electrodes.

15. A multilayer wiring board according to claim 14, wherein the coil vias are included in interlayer connection conductors disposed within an insulating layer between the one wiring layer and the other wiring layer.

Images