Hfn-ge-sb-te phase change material and low-power-consumption phase change memory

Abstract

The present invention belongs to the field of micro-nano electronics, and provided are an HfN-Ge-Sb-Te phase change material and a low-power-consumption phase change memory. The general formula of the phase change material is (HfN)x(Ge-Sb-Te)1-x, wherein x is the percentage of the number of molecules of HfN in the total number of molecules. The lattice mismatch degree of a Ge-Sb-Te alloy and HfN is greater than 20%, so as to inhibit the crystallization degree of a Ge-Sb-Te phase change memory material. In the present invention, HfN is doped into the Ge-Sb-Te alloy, and it is ensured that the lattice mismatch degree of HfN and the Ge-Sb-Te alloy is greater than 20%, such that the HfN-Ge-Sb-Te phase change material can form a more stable amorphous structure, thereby significantly inhibiting the crystallization degree thereof and reducing the crystallization area thereof, such that the amorphous stability of the Ge-Sb-Te phase change material is improved, and the RESET power consumption of a Ge-Sb-Te phase change memory device is greatly reduced.

Description

HfN-Ge-Sb-Te phase change material and low power phase change memory Technical Field

[0001] The present invention belongs to the field of micro-nano electronics, and more specifically, relates to a HfN-Ge-Sb-Te phase change material and a low-power phase change memory. Background Art

[0002] In today's era of rapid development in electronic technology and the information industry, coupled with the explosive growth of data, the performance requirements for non-volatile memory are increasing. Phase change memory (PCM), with its advantages such as high integration, fast response speed, and long cycle life, is considered by the International Semiconductor Industry Association to be the most likely to replace flash memory and dynamic random access memory and become the mainstream memory of the future. The basic principle of PCM is to apply an electrical pulse signal to a memory cell, causing the phase change material to undergo a reversible phase transition between amorphous and crystalline states to store "0" and "1." Applying a narrow pulse width, high amplitude electrical pulse to the cell causes it to reset, causing the crystalline phase change material to melt and rapidly cool to an amorphous, disordered state, thereby achieving a rapid resistance change from a low-resistance state "0" to a high-resistance state "1." Conversely, applying a wide pulse width, low amplitude electrical pulse to the cell causes it to set, causing the amorphous phase change material to crystallize through an annealing-like process, returning to a low-resistance state, enabling the "1" to be erased and written back to a "0." Phase-change materials are primarily chalcogenides, with compounds composed of Ge, Sb, and Te being the most common. While current phase-change memories offer the advantages of non-volatility and fast erase and write times (tens to hundreds of nanoseconds), they also suffer from high reset power consumption, hindering device energy efficiency and the high integration of memory chips. Further reduction of reset power is needed.

[0003] Optimizing the properties of phase-change materials (PCMs) is key to improving the performance of PCMs, and the microstructure of PCMs determines their macroscopic properties. Currently, the primary method for optimizing the performance of conventional Ge-Sb-Te PCMs is doping. Compared to multilayer fabrication processes like superlattices and heterostructures, doping is simpler, less costly, and more popular within the industry. However, doping typically improves PCM properties such as crystallization speed and amorphous stability, and reports on doping reducing PCM power consumption are rare. PCM power consumption is not only related to the melting point of the PCM but also closely linked to the efficiency of electrothermal utilization within the device, including heat generation and dissipation. Existing methods for reducing PCM power consumption primarily include reducing the contact area between the electrode and the PCM through device structural design, thereby reducing the phase change region and reducing the energy required for the phase change; and doping with single elements such as O to form a low-thermal-conductivity oxide layer within the PCM, creating a localized thermal insulation effect and improving energy utilization. However, these methods also have significant limitations: the design of the device structure does not reduce power consumption from the root of the material, and changes in the device structure require changes in the production process, which is costly and difficult to implement. It is difficult to implement in highly integrated architectures such as three-dimensional phase-change memory. Elemental elements such as O doped in the phase-change material react with other elements to form phase separation, which will adversely affect other phase-change properties of the device, such as cycle life and crystallization speed.

[0004] Summary of the Invention

[0005] In view of the defects of the prior art, the purpose of the present invention is to provide a HfN-Ge-Sb-Te phase change material and a low-power phase change memory, aiming to solve the problem that the existing methods for reducing power consumption of phase change memory are too complicated.

[0006] To achieve the above object, according to one aspect of the present invention, a HfN-Ge-Sb-Te phase change material is provided, the general formula of which is (HfN) x (Ge-Sb-Te) 1-x , x is the percentage of HfN molecules to the total number of molecules, wherein the lattice mismatch between HfN and the crystalline Ge-Sb-Te alloy is greater than 20% to suppress the crystallization degree of the Ge-Sb-Te phase change material.

[0007] As a further preference, the Ge-Sb-Te alloy is Ge2Sb2Te5, Ge1Sb2Te4 or Ge1Sb4Te7.

[0008] As a further preference, the value range of x is 0<x<30%.

[0009] As a further preference, the HfN-Ge-Sb-Te phase change material is in the form of a thin film with a thickness of 5 nm to 300 nm.

[0010] According to another aspect of the present invention, a low-power phase-change memory is provided, comprising a bottom electrode, an isolation layer, a phase-change memory material thin film layer, and a top electrode stacked in sequence, wherein the isolation layer has a through-hole extending therethrough, the phase-change memory material thin film layer is deposited within the through-hole and contacts the bottom electrode and the top electrode, and the phase-change memory material thin film layer is made of the above-mentioned HfN-Ge-Sb-Te phase-change material.

[0011] As a further preference, the thickness of the bottom electrode and the top electrode is 5nm-1μm, the thickness of the phase change memory material film layer is 5nm-300nm, the thickness of the isolation layer is 5nm-300nm, and the through hole diameter of the isolation layer is 10nm-1μm.

[0012] As a further preferred embodiment, the material of the bottom electrode and the top electrode is Al, Ag, Cu, Ti3W7, Pt, Au, W, Ti or TiN, and the material of the isolation layer is SiO2, SiC or (ZnS) z (SiO2) 100-z , where z is an integer greater than 0 and less than 100.

[0013] According to another aspect of the present invention, a method for preparing the low-power phase-change memory is provided, the method comprising the following steps:

[0014] S1: preparing a bottom electrode and an isolation layer on a substrate in sequence;

[0015] S2 etches a through hole inside the isolation layer, the through hole penetrating the isolation layer and directly reaching the surface contact of the bottom electrode;

[0016] S3 depositing a phase change memory material thin film layer inside the through hole;

[0017] S4 deposits a top electrode on the surface of the phase change memory material thin film layer, thereby manufacturing the low power consumption phase change memory.

[0018] As a further preferred embodiment, in step S3, the phase change memory material thin film layer is prepared by magnetron sputtering, chemical vapor deposition, atomic layer deposition, electroplating or electron beam evaporation.

[0019] As a further preferred embodiment, in step S3, when the magnetron sputtering method is adopted, the phase change memory material thin film layer is prepared by co-sputtering an HfN target and a Ge-Sb-Te alloy target.

[0020] In general, the above technical solutions conceived by the present invention have the following beneficial effects compared with the prior art:

[0021] 1. The present invention dopes HfN into a Ge-Sb-Te alloy and ensures that the lattice mismatch between HfN and the Ge-Sb-Te alloy is greater than 20%. This enables the HfN-Ge-Sb-Te phase-change material to form a more stable amorphous structure, significantly suppresses its crystallization degree, and reduces its crystallized area, thereby improving the amorphous stability of the HfN-Ge-Sb-Te phase-change material and suppressing the resistance drift of the HfN-Ge-Sb-Te phase-change material.

[0022] 2. The present invention also proposes a low-power phase-change memory fabricated using the aforementioned HfN-Ge-Sb-Te phase-change material. This reduces RESET power consumption by optimizing the composition of the phase-change memory material thin film layer without changing the memory structure. By doping HfN into the Ge-Sb-Te alloy, the crystallization of the phase-change material is significantly suppressed, thereby effectively reducing the device's RESET power consumption, increasing the device's SET speed, and suppressing the device's resistance drift. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] FIG1 is a schematic structural diagram of a low-power phase-change memory provided by an embodiment of the present invention;

[0024] FIG2 is an RT test graph of the phase change materials prepared in Example 1, Example 2, and Comparative Example 1 of the present invention, with a heating rate of 12° C. / min;

[0025] 3 is a graph showing the data retention capability of phase change materials prepared in Example 1, Example 2, and Comparative Example 1 of the present invention;

[0026] FIG4 is a resistance drift test graph of the phase change materials prepared in Example 1, Example 2, and Comparative Example 1 of the present invention, where V is the resistance drift coefficient;

[0027] FIG5a is an XRD test pattern of the phase change material prepared in Comparative Example 1 of the present invention after annealing at 250° C. and 450° C. for 30 minutes;

[0028] FIG5 b is an XRD test pattern of the phase change material prepared in Example 1 of the present invention after annealing at 250° C. and 450° C. for 30 minutes;

[0029] FIG6a is a TEM photograph and a selected area electron diffraction pattern of the phase change material prepared in Comparative Example 1 of the present invention after annealing;

[0030] FIG6 b is a TEM photograph and a selected area electron diffraction pattern of the phase change material prepared in Example 1 of the present invention after annealing;

[0031] 7 is a VR curve of the phase change memory RESET process in Comparative Example 2 of the present invention, with a pulse width of 10 ns;

[0032] FIG8 a is a VR curve of the phase change memory in comparative example 2 of the present invention, which fails to be successfully SET using a 50 ns electric pulse;

[0033] FIG8 b is a VR curve of the phase change memory in Comparative Example 2 of the present invention when a SET process is successfully performed using a 60 ns electric pulse;

[0034] FIG9 is a VR curve of the phase change memory RESET process in Example 3 of the present invention, with a pulse width of 10 ns;

[0035] FIG10 is a VR curve of the phase change memory cell SET process in Example 3 of the present invention, where a 10 ns electric pulse is used for successful SET;

[0036] FIG11 is a mean square displacement (MSD) diagram obtained by modeling the phase change materials prepared in Comparative Example 1 and Example 1 of the present invention;

[0037] FIG12 is a phonon density of states (VDOS) diagram obtained by modeling the phase change materials prepared in Comparative Example 1 and Example 1 of the present invention.

[0038] Throughout the drawings, the same reference numerals are used to denote the same elements or structures, wherein:

[0039] 1-bottom electrode, 2-isolation layer, 3-phase change memory material thin film layer, 4-top electrode, 5-substrate. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0041] According to one aspect of the present invention, a HfN-Ge-Sb-Te phase change material is provided, which has the general formula (HfN) x (Ge-Sb-Te) 1-x , x is the percentage of HfN molecules in the total number of molecules, wherein the lattice mismatch between HfN and the crystalline Ge-Sb-Te alloy is greater than 20%, thereby forming a more stable amorphous structure in the HfN-Ge-Sb-Te phase change memory material, suppressing its crystallization degree and reducing the crystallized area, thereby improving the amorphous stability of the HfN-Ge-Sb-Te phase change material and suppressing its resistance drift.

[0042] Furthermore, the Ge-Sb-Te alloy with a lattice mismatch with HfN greater than 20% is preferably Ge2Sb2Te5, Ge1Sb2Te4, or Ge1Sb4Te7. By optimizing the selection of the Ge-Sb-Te alloy, the amorphous stability of the HfN-Ge-Sb-Te phase change material can be further improved.

[0043] Furthermore, the value range of x is 0<x<30%. When x is too large, HfN will spontaneously form HfN clusters or grains, and cannot utilize its large lattice mismatch with the Ge-Sb-Te matrix material to inhibit the crystallization degree of the matrix material.

[0044] Furthermore, the HfN-Ge-Sb-Te phase change material is in the form of a thin film with a thickness of 5 nm to 300 nm, which is convenient for subsequent applications.

[0045] As shown in FIG1 , according to another aspect of the present invention, a low-power phase change memory is provided, which includes a bottom electrode 1, an isolation layer 2, a phase change memory material thin film layer 3 and a top electrode 4 stacked in sequence, wherein the isolation layer 2 has a through hole extending therethrough, the phase change memory material thin film layer 3 is deposited in the through hole and contacts the bottom electrode 1 and the top electrode 4, and the phase change memory material thin film layer is made of the above-mentioned HfN-Ge-Sb-Te phase change material.

[0046] Unlike traditional low-power phase-change memory devices, which require significant changes to the device and array structure, the present invention only improves the material composition of the phase-change memory thin film layer, achieving low power consumption without modifying the device or array structure. Specifically, the present invention significantly suppresses the crystallization of the Ge-Sb-Te phase-change material by doping it with HfN, reducing the crystallized area, thereby reducing the device's RESET power consumption and increasing the device's SET speed. Simultaneously, HfN doping creates a more stable amorphous structure within the HfN-Ge-Sb-Te phase-change material, improving its amorphous stability and suppressing resistance drift.

[0047] Furthermore, the thickness of the bottom electrode 1 and the top electrode 4 is 5nm to 1μm, the thickness of the phase change memory material thin film layer 3 is 5nm to 300nm, the thickness of the isolation layer 2 is 5nm to 300nm, and the diameter of the through hole of the isolation layer 2 is 10nm to 1μm. The materials of the bottom electrode 1 and the top electrode 4 are Al, Ag, Cu, Ti3W7, Pt, Au, W, Ti or TiN, and the material of the isolation layer 2 is SiO2, SiC or (ZnS) z (SiO2) 100-z , where z is an integer greater than 0 and less than 100.

[0048] According to another aspect of the present invention, a method for preparing the low-power phase-change memory is provided, the method comprising the following steps:

[0049] S1: preparing a bottom electrode 1 and an isolation layer 2 on a substrate 5 in sequence;

[0050] S2: etching a through hole inside the isolation layer 2, wherein the through hole penetrates the isolation layer 2 and contacts the surface of the bottom electrode 1;

[0051] S3 depositing a phase change memory material thin film layer 3 inside the through hole;

[0052] S4 deposits a top electrode 4 on the surface of the phase change memory material thin film layer 3, thereby manufacturing a low power consumption phase change memory.

[0053] Furthermore, in step S3, a phase change memory material thin film layer is prepared by magnetron sputtering, chemical vapor deposition, atomic layer deposition, electroplating or electron beam evaporation. When magnetron sputtering is used, the preparation is performed by co-sputtering an HfN target and a Ge-Sb-Te alloy target.

[0054] The technical solution provided by the present invention is further described below with reference to specific embodiments.

[0055] Example 1

[0056] The general chemical formula of the HfN-Ge-Sb-Te phase change material prepared in this embodiment is (HfN) x (Ge1Sb4Te7) 1-x , x=0.06, the average bond length of HfN is about The average bond length of Ge1Sb4Te7 is about The lattice mismatch rate is about 29%, and the two cannot form lattice matching.

[0057] (HfN) 0.06 (Ge1Sb4Te7) 0.94 The target is produced by magnetron sputtering, with high-purity argon gas as the sputtering gas at a pressure of 0.6 Pa. The Ge1Sb4Te7 target uses a DC power supply of 30W; the HfN target uses an AC power supply of 15W. The specific preparation process includes the following steps:

[0058] 1. Select a SiO2 / Si substrate (lattice orientation is 100 direction) with a size of 1cm×1cm, clean the surface and back, and remove dust particles, organic and inorganic impurities;

[0059] a) Place a SiO2 / Si substrate (lattice orientation is 100) in an acetone solution and vibrate ultrasonically at 40W for 10 minutes, then rinse with deionized water;

[0060] b) The acetone-treated substrate was subjected to ultrasonic vibration at a power of 40 W for 10 minutes in an ethanol solution, rinsed with deionized water, and the surface and back surface were blown dry with high-purity N2 gas to obtain a substrate to be sputtered;

[0061] 2. Prepare HfN-Ge-Sb-Te phase change material by DC and AC power co-sputtering method;

[0062] a) Place HfN target and Ge1Sb4Te7 alloy target, both of which have a purity of 99.99% (atomic percentage), and pump the background vacuum to 10 -4 Pa;

[0063] b) Use high-purity Ar gas as the sputtering gas, adjust the sputtering pressure to 0.6 Pa, and the distance between the target and the substrate is 120 mm;

[0064] c) Set the DC power supply power to 30W and the AC power supply power to 15W;

[0065] d) Pre-sputtering the HfN target and Ge1Sb4Te7 target for 10 min to clean the target surface;

[0066] e) After the pre-sputtering is completed, the shutter is opened, and when the sputtering time is 250 s, the thickness of the prepared film is about 100 nm.

[0067] Example 2

[0068] The general chemical formula of the HfN-Ge-Sb-Te phase change material prepared in this embodiment is (HfN) x (Ge1Sb4Te7) 1-x , x=0.28.

[0069] (HfN) 0.28 (Ge1Sb4Te7) 0.72 The target is produced by magnetron sputtering, with high-purity argon gas as the sputtering gas at a pressure of 0.6 Pa. The Ge1Sb4Te7 target uses a DC power supply of 30W; the HfN target uses an AC power supply of 25W. The specific preparation process includes the following steps:

[0070] 1. Select a SiO2 / Si substrate (lattice orientation is 100 direction) with a size of 1cm×1cm, clean the surface and back, and remove dust particles, organic and inorganic impurities;

[0071] a) Place a SiO2 / Si substrate (lattice orientation is 100) in an acetone solution and vibrate ultrasonically at 40W for 10 minutes, then rinse with deionized water.

[0072] b) The substrate treated with acetone was subjected to ultrasonic vibration at a power of 40 W for 10 minutes in an ethanol solution, rinsed with deionized water, and the surface and back were blown dry with high-purity N2 gas to obtain a substrate to be sputtered.

[0073] 2. Prepare HfN-Ge-Sb-Te phase change material by DC and AC power co-sputtering method;

[0074] a) Place HfN target and Ge1Sb4Te7 alloy target, both of which have a purity of 99.99% (atomic percentage), and pump the background vacuum to 10 -4 Pa;

[0075] b) Use high-purity Ar gas as the sputtering gas, adjust the sputtering pressure to 0.6 Pa, and the distance between the target and the substrate is 120 mm;

[0076] c) Set the DC power supply power to 30W and the AC power supply power to 25W;

[0077] d) Pre-sputtering the HfN target and Ge1Sb4Te7 target for 10 min to clean the target surface;

[0078] e) After the pre-sputtering is completed, the shutter is opened, and when the sputtering time is 250 s, the thickness of the prepared film is about 100 nm.

[0079] Comparative Example 1

[0080] In this comparative example, pure Ge1Sb4Te7 phase change material was prepared.

[0081] Pure Ge1Sb4Te7 phase change material was prepared by magnetron sputtering. During the preparation, high-purity argon was introduced as the sputtering gas with a sputtering pressure of 0.6 Pa. The Ge1Sb4Te7 target used a DC power supply with a power of 30 W. The specific preparation process includes the following steps:

[0082] 1. Select a SiO2 / Si substrate (lattice orientation is 100 direction) with a size of 1cm×1cm, clean the surface and back, and remove dust particles, organic and inorganic impurities;

[0083] a) Place a SiO2 / Si substrate (lattice orientation is 100) in an acetone solution and vibrate ultrasonically at 40W for 10 minutes, then rinse with deionized water;

[0084] b) The acetone-treated substrate was subjected to ultrasonic vibration at a power of 40 W for 10 minutes in an ethanol solution, rinsed with deionized water, and the surface and back surface were blown dry with high-purity N2 gas to obtain a substrate to be sputtered;

[0085] 2. Prepare pure Ge1Sb4Te7 phase change memory thin film material using DC power sputtering method;

[0086] a) Place the Ge1Sb4Te7 alloy target with a purity of 99.99% (atomic percentage) and pump the background vacuum to 10 -4 Pa;

[0087] b) Use high-purity Ar gas as the sputtering gas, adjust the sputtering pressure to 0.6 Pa, and the distance between the target and the substrate is 120 mm;

[0088] c) Set the DC power supply to 30W;

[0089] d) Pre-sputtering the Ge1Sb4Te7 target for 10 minutes to clean the target surface;

[0090] e) After the pre-sputtering is completed, the shutter is opened, and when the sputtering time is 250 s, the thickness of the prepared film is about 100 nm.

[0091] The phase change materials in Example 1, Example 2, and Comparative Example 1 were tested.

[0092] Figure 2 is a RT test diagram of the phase change material in Example 1, Example 2, and Comparative Example 1, with a heating rate of 12°C / min, pure Ge1Sb4Te7, (HfN) 0.06 (Ge1Sb4Te7) 0.94 and (HfN) 0.28 (Ge1Sb4Te7) 0.72 The crystallization temperatures of the HfN-Ge-Sb-Te phase change materials are 131°C, 163°C and 175°C respectively. By comparison, it can be seen that HfN doping increases the crystallization temperature of the film, thereby improving the amorphous stability of the HfN-Ge-Sb-Te phase change material.

[0093] Figure 3 is a test chart of the data retention capability of the phase change materials in Example 1, Example 2, and Comparative Example 1. By comparison, it can be seen that HfN doping improves the ten-year data retention temperature of the HfN-Ge-Sb-Te phase change material. Pure Ge1Sb4Te7, (HfN) 0.06 (Ge1Sb4Te7) 0.94 and (HfN) 0.28 (Ge1Sb4Te7) 0.72 The ten-year data retention temperatures of the films were 42.8°C, 76.4°C, and 95.2°C, respectively. This ten-year data retention temperature increases with increasing HfN doping levels, further demonstrating that HfN doping is beneficial for improving the amorphous stability of Ge-Sb-Te phase-change materials.

[0094] Figure 4 is a graph showing the resistance drift of the phase change materials in Example 1, Example 2, and Comparative Example 1. It can be seen from the comparison that HfN doping significantly reduces the resistance drift coefficient of the HfN-Ge-Sb-Te phase change material. Pure Ge1Sb4Te7, (HfN)0.06 (Ge1Sb4Te7) 0.94 and (HfN) 0.28 (Ge1Sb4Te7) 0.72 The resistance drift coefficients are 0.15039, 0.00627, and 0.00253 respectively. The reduction of the resistance drift coefficient is conducive to maintaining the stability of the resistance state of the phase change memory.

[0095] Figures 5a and 5b are the XRD test patterns of the phase change materials in Comparative Example 1 and Example 1, respectively. HfN doping significantly reduces the diffraction peak intensity of Ge1Sb4Te7 after annealing. Even with further increasing the annealing temperature, the diffraction peak intensity of Ge1Sb4Te7 remains very low, indicating that HfN doping inhibits the crystallization of the HfN-Ge-Sb-Te phase change material.

[0096] Figure 6a and Figure 6b are TEM photos and selected area electron diffraction patterns of the phase change material films after annealing in Comparative Example 1 and Example 1, respectively. The degree of crystallization in pure Ge1Sb4Te7 is very high, and all regions are single crystals and highly crystallized polycrystalline, while (HfN) 0.06 (Ge1Sb4Te7) 0.94 Part of the area is crystalline, and the other part is amorphous. Overall, after annealing (HfN) 0.06 (Ge1Sb4Te7) 0.94 The degree of crystallization of the film is lower than that of pure Ge1Sb4Te7, which further verifies the inhibitory effect of HfN doping on the crystallization degree of HfN-Ge-Sb-Te phase change material.

[0097] Example 3

[0098] In this embodiment, the (HfN) in embodiment 1 is used. 0.06 (Ge1Sb4Te7) 0.94 A phase-change memory (PCM) was prepared as a phase-change memory material, wherein the PCM material thin film layer 3 was produced using magnetron sputtering. High-purity argon was used as the sputtering gas at a pressure of 0.6 Pa. A DC power supply of 30 W was used for the Ge1Sb4Te7 target, while an AC power supply of 15 W was used for the HfN target. The specific preparation process included the following steps:

[0099] 1. Select a 1cm×1cm SiO2 / Si substrate (lattice orientation is 100 degrees) and clean the surface and back to remove dust particles, organic and inorganic impurities.

[0100] a) Place a SiO2 / Si substrate (lattice orientation is 100) in an acetone solution and vibrate ultrasonically at 40W for 10 minutes, then rinse with deionized water;

[0101] b) The acetone-treated substrate was subjected to ultrasonic vibration at a power of 40 W for 10 minutes in an ethanol solution, rinsed with deionized water, and the surface and back surface were blown dry with high-purity N2 gas to obtain a substrate to be sputtered;

[0102] 2. Prepare 100nm Pt bottom electrode by DC power sputtering method;

[0103] 3. Deposit a 100nm SiO2 insulating layer on the Pt bottom electrode using chemical vapor deposition;

[0104] 4. Form a through hole with a depth of 100 nm and a diameter of 250 nm in the SiO2 insulating layer by electron beam lithography and other processes;

[0105] 5. Forming a memory array through photolithography;

[0106] 6. Use DC and AC power co-sputtering method to fill (HfN) in the through hole 0.06 (Ge1Sb4Te7) 0.94 Phase change memory thin film materials;

[0107] a) Place HfN target and Ge1Sb4Te7 alloy target, both of which have a purity of 99.99% (atomic percentage), and pump the background vacuum to 10 -4 Pa;

[0108] b) Use high-purity Ar gas as the sputtering gas, adjust the sputtering pressure to 0.6 Pa, and the distance between the target and the substrate is 120 mm;

[0109] c) Set the DC power supply power to 30W and the AC power supply power to 15W;

[0110] d) Pre-sputtering the HfN target and Ge1Sb4Te7 target for 10 min to clean the target surface;

[0111] e) After the pre-sputtering is completed, the shutter is opened, and when the total sputtering time is 250 s, the thickness of the prepared phase change layer is about 100 nm;

[0112] 7. Prepare 100nm Pt top electrode by DC power sputtering method to obtain complete (HfN) 0.06 (Ge1Sb4Te7) 0.94 Low-power phase change memory with phase change layer.

[0113] Comparative Example 2

[0114] In this comparative example, the pure Ge1Sb4Te7 phase change material of Comparative Example 1 was used as the material for the phase change storage material thin film layer to prepare a memory device, wherein the Ge1Sb4Te7 phase change layer was prepared by magnetron sputtering. The devices prepared in Comparative Example 2 and Example 3 formed a control group. Except for the difference in whether the phase change layer material was doped, the other device structures, materials, and preparation processes were the same as those in Example 3. During preparation, high-purity argon gas was introduced as the sputtering gas with a sputtering pressure of 0.6 Pa. A DC power supply with a power of 30 W was used for the Ge1Sb4Te7 target. The specific preparation process includes the following steps:

[0115] 1. Select a 1cm×1cm SiO2 / Si substrate (lattice orientation is 100 degrees) and clean the surface and back to remove dust particles, organic and inorganic impurities.

[0116] a) Place a SiO2 / Si substrate (lattice orientation is 100) in an acetone solution and vibrate ultrasonically at 40W for 10 minutes, then rinse with deionized water;

[0117] b) The acetone-treated substrate was subjected to ultrasonic vibration at a power of 40 W for 10 minutes in an ethanol solution, rinsed with deionized water, and the surface and back surface were blown dry with high-purity N2 gas to obtain a substrate to be sputtered;

[0118] 2. Prepare 100nm Pt bottom electrode by DC power sputtering method;

[0119] 3. Deposit a 100nm SiO2 insulating layer on the Pt bottom electrode using chemical vapor deposition;

[0120] 4. Form a through hole with a depth of 100 nm and a diameter of 250 nm in the SiO2 insulating layer by electron beam lithography and other processes;

[0121] 5. Forming a memory array through photolithography;

[0122] 6. Use DC power sputtering method to fill Ge1Sb4Te7 phase change memory thin film material in the through hole;

[0123] a) Place the Ge1Sb4Te7 alloy target, the purity of which reaches 99.99% (atomic percentage), and pump the background vacuum to 10 -4 Pa;

[0124] b) Use high-purity Ar gas as the sputtering gas, adjust the sputtering pressure to 0.6 Pa, and the distance between the target and the substrate is 120 mm;

[0125] c) Set the DC power supply to 30W;

[0126] d) Pre-sputtering the Ge1Sb4Te7 target for 10 minutes to clean the target surface;

[0127] e) After the pre-sputtering is completed, the shutter is opened, and when the sputtering time is 250 s, the thickness of the prepared phase change layer is about 100 nm;

[0128] 7. A 100nm Pt top electrode was prepared by DC power sputtering to obtain a phase change memory array with a complete Ge1Sb4Te7 phase change layer.

[0129] The phase change memories in Example 3 and Comparative Example 2 were subjected to electrical performance tests.

[0130] FIG7 is a VR curve of the RESET process of the Ge1Sb4Te7 phase change memory in Example 2, where the pulse width is 10 ns, and the formula W=U 2 / R*t calculates the RESET power consumption, where U is the voltage when it jumps to high resistance, R is the resistance before the resistance jump, and t is the pulse width. The calculated RESET power consumption is 14pJ.

[0131] FIG8a and FIG8b are VR curves of the SET process of the Ge1Sb4Te7 phase change memory in Example 2. FIG8a shows that the SET fails when a 50ns electric pulse is used, and FIG8b shows that the SET is successful when a 60ns electric pulse is used. It can be seen that the SET speed of the pure Ge1Sb4Te7 phase change memory is 60ns.

[0132] FIG9 is a diagram of (HfN) in Example 3 0.06 (Ge1Sb4Te7) 0.94 VR curve of the phase change memory RESET process, the pulse width is 10ns, through the formula W=U 2 / R*t calculates the RESET power consumption, where U is the voltage when it jumps to high resistance, R is the resistance before the resistance jump, and t is the pulse width. The calculated value is (HfN) 0.06 (Ge1Sb4Te7) 0.94 The RESET power consumption of the phase change memory is 17 fJ, which is much lower than the RESET power consumption of the pure Ge1Sb4Te7 phase change memory in Comparative Example 2.

[0133] FIG10 is a diagram of (HfN) in Example 3 0.06 (Ge1Sb4Te7) 0.94 VR curve of the SET process of the phase change memory unit. SET was successfully achieved using a 10ns electric pulse. Therefore, the SET speed of the HfN-doped Ge1Sb4Te7 phase change memory is faster than that of the pure Ge1Sb4Te7 phase change memory. HfN doping can effectively improve the SET speed of the Ge-Sb-Te phase change memory.

[0134] The pure Ge1Sb4Te7 of comparative example 1 and (HfN) of embodiment 1 were compared using Materials Studio software. 0.06 (Ge1Sb4Te7) 0.94 Modeling was carried out and the relaxation, melting and quenching processes of the two models were simulated using the first principle to obtain pure Ge1Sb4Te7 and (HfN) 0.06 (Ge1Sb4Te7) 0.94 amorphous model.

[0135] Figure 11 shows the mean square displacement (MSD) images of two groups of amorphous models after molecular dynamics simulation at 300K. The mean square displacement calculation of the amorphous model at 300K reflects the spontaneous change and movement of the atomic structure inside the material at room temperature. The results show that (HfN) 0.06 (Ge1Sb4Te7) 0.94 The mean square displacement of the model is significantly reduced, which is beneficial to suppressing the drift of its amorphous resistance.

[0136] Figure 12 shows the phonon density of states (VDOS) images of two groups of amorphous models after molecular dynamics simulation at 300K. The amorphous model has fewer vibration modes in the low-frequency region and more vibration modes in the high-frequency region, which means that the amorphous model is more stable. The results show that compared with the pure Ge1Sb4Te7 model, (HfN) 0.06 (Ge1Sb4Te7) 0.94 The vibration modes in the low-frequency region of the model are reduced, and new vibration modes appear in the high-frequency region, which theoretically verifies (HfN) 0.06 (Ge1Sb4Te7) 0.94 Has better amorphous stability.

[0137] The matrix materials in the above embodiments and comparative examples are all Ge1Sb4Te7. In specific implementations, Ge-Sb-Te matrix materials with other component proportions can also be used, such as Ge2Sb2Te5, Ge1Sb2Te4, etc. As long as the lattice mismatch between HfN and the crystalline Ge-Sb-Te alloy is greater than 20%, the purpose of the present invention of using HfN doping to suppress the degree of crystallization of the Ge-Sb-Te matrix material and reduce the crystallization area can be achieved, thereby improving the amorphous stability of the matrix phase change material and suppressing its resistance drift, and ultimately achieving the technical effect of reducing the RESET power consumption of the phase change memory device.

[0138] The average bond length of HfN is about The average bond length of Ge2Sb2Te5 is about The lattice mismatch between the two is about 27%. The average bond length of Ge1Sb2Te4 is about The lattice mismatch between HfN and Ge1Sb2Te4 is about 29%. Therefore, in the specific implementation of the present invention, Ge2Sb2Te5 and Ge1Sb2Te4 can also be used as the matrix phase change material.

[0139] Compared with the undoped Ge-Sb-Te system phase change memory materials and devices in the prior art, in the HfN-Ge-Sb-Te phase change material and device of the present invention, HfN doping significantly suppresses the crystallization degree of the crystalline Ge-Sb-Te phase change material, reduces the crystallized area, thereby reducing the RESET power consumption of the device and improving the SET speed of the device; at the same time, HfN doping also makes the amorphous structure of the Ge-Sb-Te phase change material more stable, improves the amorphous stability of the material and the device, and suppresses the resistance drift of the material and the device.

[0140] It will be easily understood by those skilled in the art that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A HfN-Ge-Sb-Te phase change material, characterized in that, The general formula of the HfN-Ge-Sb-Te phase change material is (HfN) x (Ge-Sb-Te) 1-x , where x is the percentage of the number of molecules of HfN in the total number of molecules, and the lattice mismatch between HfN and the crystalline Ge-Sb-Te based alloy is greater than 20% to inhibit the crystallization degree of the Ge-Sb-Te phase change material.

2. The HfN-Ge-Sb-Te phase change material according to claim 1, wherein The Ge-Sb-Te based alloy is Ge2Sb2Te5, Ge1Sb2Te4 or Ge1Sb4Te7.

3. The HfN-Ge-Sb-Te phase change material according to claim 1, characterized in that, The value range of x is 0 < x < 30%.

4. The HfN-Ge-Sb-Te phase change material according to any one of claims 1 to 3, characterized in that, The HfN-Ge-Sb-Te phase change material is in the form of a thin film with a thickness of 5 nm to 300 nm.

5. A low-power phase change memory, characterized in that, The low-power phase change memory includes a bottom electrode, an isolation layer, a phase change memory material thin film layer, and a top electrode stacked in sequence. A through hole is provided in the isolation layer, and the phase change memory material thin film layer is deposited in the through hole and contacts the bottom electrode and the top electrode. The phase change memory material thin film layer is made of the above-mentioned HfN-Ge-Sb-Te phase change material.

6. The low-power phase change memory according to claim 5, wherein The thickness of the bottom electrode and the top electrode is 5 nm to 1 μm, the thickness of the phase change memory material thin film layer is 5 nm to 300 nm, the thickness of the isolation layer is 5 nm to 300 nm, and the diameter of the through hole in the isolation layer is 10 nm to 1 μm.

7. The low-power phase change memory according to claim 5 or 6, wherein The materials of the bottom electrode and the top electrode are Al, Ag, Cu, Ti3W7, Pt, Au, W, Ti or TiN, and the material of the isolation layer is SiO2, SiC or (ZnS) z (SiO2) 100-z , where z is an integer greater than 0 and less than 100.

8. The manufacturing method of the low-power phase change memory according to any one of claims 5 to 7, characterized in that The preparation method includes the following steps: S1: A bottom electrode and an isolation layer are sequentially prepared on a substrate. S2: A through hole is etched inside the isolation layer, and the through hole penetrates the isolation layer and reaches the surface of the bottom electrode. S3: A phase change memory material thin film layer is deposited inside the through hole. S4: A top electrode is deposited on the surface of the phase change memory material thin film layer, thereby manufacturing the low-power phase change memory.

9. The manufacturing method of the low-power phase change memory according to claim 8, characterized in that, In step S3, the phase change memory material thin film layer is prepared by magnetron sputtering, chemical vapor deposition, atomic layer deposition, electroplating or electron beam evaporation.

10. The manufacturing method of the low-power phase change memory according to claim 9, characterized in that, In step S3, when using magnetron sputtering, the phase change memory material thin film layer is prepared by co-sputtering with an HfN target and a Ge-Sb-Te based alloy target.

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