Reference clock signal transceiver and terminal device

Abstract

A reference clock signal transceiver and a terminal device. The reference clock signal transceiver comprises a terminal matching circuit, a receiver and a transmitter, wherein the terminal matching circuit is suitable for: receiving a first control signal and a second control signal; performing configuration on the basis of the level of the first control signal to form a reference clock signal receiver together with the receiver or to form a reference clock signal transmitter together with the transmitter; and when determining to form the reference clock signal receiver together with the receiver, on the basis of the level of the second control signal, configuring a received reference clock signal to be in an alternating-current coupling mode or a direct-current coupling mode. By means of the solution, a reference clock signal transceiver can be switched between an input mode and an output mode, and can also realize direct-current coupling or alternating-current coupling of a reference clock signal in the input mode.

Description

Reference clock signal transceiver and terminal equipment

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on January 5, 2024, with application number 202410020679.4 and invention name “Reference Clock Signal Transceiver and Terminal Equipment”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present invention relates to the field of circuit technology, and in particular to a reference clock signal transceiver and terminal equipment. Background Art

[0003] A high-speed serializer-deserializer (SerDes) is an interface resource within a field programmable gate array (FPGA) that enables data exchange with external systems. A SerDes receives an external reference clock signal through a reference clock signal transceiver and generates a high-speed clock signal through a configurable frequency synthesizer. A SerDes can also use an internal clock data recovery (CDR) module to recover the clock signal from the received data and provide it to external devices as a reference clock through a reference clock signal transceiver.

[0004] The reference clock signal transceiver in the prior art has low flexibility. Summary of the Invention

[0005] The technical problem solved by the present invention is that the existing reference clock signal transceiver has low flexibility.

[0006] To solve the above technical problems, the present invention provides a reference clock signal transceiver, comprising: a terminal matching circuit, a receiver and a transmitter, wherein: the terminal matching circuit is suitable for receiving a first control signal and a second control signal; based on the level of the first control signal, it is configured to form a reference clock signal receiver with the receiver or to form a reference clock signal transmitter with the transmitter; and when determining to form a reference clock signal receiver with the receiver, based on the level of the second control signal, the received reference clock signal is configured to be in AC coupling mode or DC coupling mode.

[0007] Optionally, when the first control signal is at a first level and the second control signal is at a first level, the terminal matching circuit and the receiver form a reference clock signal receiver, and the reference clock signal received by the reference clock signal receiver is in an AC coupling mode; when the first control signal is at a first level and the second control signal is at a second level, the terminal matching circuit and the receiver form a reference clock signal receiver, and the reference clock signal received by the reference clock signal receiver is in a DC coupling mode; when the first control signal is at a second level and the second control signal is at a second level, the terminal matching circuit and the receiver form a reference clock signal transmitter to transmit the reference clock signal.

[0008] Optionally, the terminal matching circuit includes: a first resistor, a second resistor, a DC bias voltage source, a first switch unit, a second switch unit, a third switch unit and a fourth switch unit, wherein: the first switch unit, whose first end is coupled to the first reference clock signal port and the first output end of the terminal matching circuit, and whose second end is coupled to the first end of the first resistor; the first resistor, whose second end is coupled to the first end of the second resistor, the first end of the third switch unit and the first end of the fourth switch unit; the second resistor, whose second end is coupled to the first end of the second switch unit; the second switch unit, whose second end is coupled to the second reference clock signal port; the third switch unit, whose second end is input to the power supply voltage; the fourth switch unit, whose second end is coupled to the first end of the DC bias voltage source; and the second end of the DC bias voltage source is grounded.

[0009] Optionally, the first switch unit, the second switch unit, the third switch unit and the fourth switch unit are all MOS tubes, and the size of the third switch unit is larger than that of the first switch unit, the second switch unit and the fourth switch unit.

[0010] Optionally, the receiver includes: a differential amplification unit and an operational amplifier, wherein: the first input terminal of the differential amplification unit is coupled to the first output terminal of the terminal matching circuit, the second input terminal of the differential amplification unit is coupled to the second output terminal of the terminal matching circuit, the first output terminal of the differential amplification unit is coupled to the first input terminal of the operational amplifier, and the second output terminal of the differential amplification unit is coupled to the second input terminal of the operational amplifier; the first output terminal and the second output terminal of the operational amplifier differentially output a logic low level and a logic high level.

[0011] Optionally, the differential amplification unit includes: a third resistor, a fourth resistor, a first NMOS tube and a second NMOS tube, wherein: the first end of the third resistor is input with the power supply voltage, and the second end of the third resistor is coupled with the drain of the first NMOS tube; the first end of the fourth resistor is input with the power supply voltage, and the second end of the fourth resistor is coupled with the drain of the second NMOS tube; the gate of the first NMOS tube is coupled with the first input end of the differential amplification unit, and the source of the first NMOS tube is grounded; the gate of the second NMOS tube is coupled with the second input end of the differential amplification unit, and the source of the second NMOS tube is grounded.

[0012] Optionally, the receiver further includes: a bias current source adapted to output a first bias current, wherein: a first end of the bias current source is coupled to the sources of the first NMOS transistor and the second NMOS transistor, and a second end thereof is grounded.

[0013] Optionally, the transmitter includes: N differential current mode logic CML amplifiers, any one of which includes: a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor and a fifth switch unit, wherein: the third NMOS transistor has a drain coupled to the first output end of the terminal matching circuit, a gate input of the first differential reference clock signal, and a source coupled to the drain of the fifth NMOS transistor; the fourth NMOS transistor has a drain coupled to the second output end of the terminal matching circuit, a gate input of the second differential reference clock signal, and a source coupled to the drain of the fifth NMOS transistor; the fifth NMOS transistor has a gate coupled to the second end of the fifth switch unit, and a source grounded; the fifth switch unit has a first end input of the second bias current, and a control end input of the third control signal.

[0014] The present invention also provides a terminal device, comprising any one of the reference clock signal transceivers provided above.

[0015] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0016] The terminal matching circuit can receive a first control signal and a second control signal. Based on the level of the first control signal, the terminal matching circuit can form a reference clock signal receiver with a receiver, or form a reference clock signal transmitter with a transmitter. When the terminal matching circuit and the receiver form a reference clock signal receiver, the received reference clock signal can be configured to operate in either AC coupling mode or DC coupling mode based on the second control signal. This allows for flexible configuration of the reference clock signal transceiver's reception and transmission modes, as well as its reception mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] FIG1 is a schematic structural diagram of a reference clock signal transceiver according to an embodiment of the present invention;

[0018] FIG2 is a schematic structural diagram of a terminal matching circuit in an embodiment of the present invention;

[0019] FIG3 is a schematic structural diagram of a receiver according to an embodiment of the present invention;

[0020] FIG4 is a schematic structural diagram of a transmitter according to an embodiment of the present invention. DETAILED DESCRIPTION

[0021] In the prior art, the reference clock signal transceiver has low flexibility and can usually only be configured as an input mode or an output mode, or can only be configured as an AC coupling mode or a DC coupling mode.

[0022] In an embodiment of the present invention, a terminal matching circuit can receive a first control signal and a second control signal. Based on the level of the first control signal, the terminal matching circuit can form a reference clock signal receiver with a receiver, or form a reference clock signal transmitter with a transmitter. When the terminal matching circuit and the receiver form a reference clock signal receiver, the received reference clock signal can be configured to operate in either AC coupling mode or DC coupling mode based on the second control signal. This allows for flexible configuration of the reference clock signal transceiver's reception and transmission modes, as well as its reception mode.

[0023] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0024] 1 , there is shown a schematic structural diagram of a reference clock signal transceiver according to an embodiment of the present invention.

[0025] In the embodiment of the present invention, the reference clock signal transceiver 10 may include a terminal matching circuit term, a receiver rx, and a transmitter tx. The reference clock signal transceiver 10 may include a first reference clock signal port REFCLKP and a second reference clock signal port REFCLKN.

[0026] In a specific implementation, the terminal matching circuit term can receive a first control signal en_tx output by an external control module. Based on the level of the first control signal en_tx, the terminal matching circuit term is configured to form a reference clock signal receiver with a receiver rx to receive the reference clock signal; or configured to form a reference clock signal transmitter with a transmitter tx to transmit the reference clock signal recovered by the clock data recovery module.

[0027] Furthermore, when the terminal matching circuit term and the receiver rx form a reference clock signal receiver, the reference clock signal receiver can further configure the received reference clock signal to be in an alternating current (AC) coupling mode or a direct current (DC) coupling mode based on the level of the received second control signal enb_dc.

[0028] Specifically, when the level of the first control signal en_tx is a first level, the terminal matching circuit term and the receiver rx form a reference clock signal receiver; when the level of the first control signal en_tx is a second level, the terminal matching circuit term and the receiver rx form a reference clock signal transmitter.

[0029] When the level of the second control signal enb_dc is a first level, the reference clock signal received by the reference clock signal receiver is in an alternating current (AC) coupling mode; when the level of the second control signal enb_dc is a second level, the reference clock signal received by the reference clock signal receiver is in a direct current (DC) coupling mode.

[0030] In a specific implementation, the first level is not equal to the second level. Specifically, the first level is not equal to the second level, which may mean that the voltage corresponding to the first level is not equal to the voltage corresponding to the second level.

[0031] In some embodiments, the first level is a low level and the second level is a high level. In other embodiments, the first level is a high level and the second level is a low level.

[0032] In an embodiment of the present invention, the reference clock signal may include two differential reference clock signals. When the terminal matching circuit term and the receiver rx form a reference clock signal receiver, the first reference clock signal port REFCLKP inputs the first differential reference clock signal CKP, and the second reference clock signal port REFCLKN inputs the second differential reference clock signal CKN.

[0033] The above-mentioned reference clock signal transceiver is described in detail below.

[0034] 2 , a schematic structural diagram of a terminal matching circuit term in an embodiment of the present invention is shown.

[0035] In an embodiment of the present invention, the terminal matching circuit term may include: a first resistor R1, a second resistor R2, a DC bias voltage source Vcm, a first switch unit S1, a second switch unit S2, a third switch unit S3, and a fourth switch unit S4, wherein:

[0036] A first end of the first switch unit S1 is coupled to the first reference clock signal port REFCLKP and the first output terminal VP of the terminal matching circuit term, and a second end of the first switch unit S1 is coupled to the first end of the first resistor R1;

[0037] The second end of the first resistor R1 may be coupled to the first end of the second resistor R2, the first end of the third switch unit S3, and the first end of the fourth switch unit S4;

[0038] A first end of the second resistor R2 is coupled to the second end of the first resistor R1, and a second end of the second resistor R2 is coupled to the first end of the second switch unit S2;

[0039] The second end of the second switch unit S2 is coupled to the second reference clock signal port REFCLKN and the second output end VN of the terminal matching circuit term;

[0040] The second terminal of the third switch unit S3 is input with the power supply voltage Vdd;

[0041] The second end of the fourth switch unit S4 is coupled to the first end of the DC bias voltage source Vcm;

[0042] A second terminal of the DC bias voltage source Vcm is grounded, and the DC bias voltage source Vcm can output a DC bias voltage.

[0043] In a specific implementation, the switching states of the first switch unit S1 and the second switch unit S2 can be controlled by the first control signal en_tx or the second control signal enb_dc. The switching states of the first switch unit S1 and the second switch unit S2 are the same. That is, the first switch unit S1 and the second switch unit S2 are turned on or off at the same time.

[0044] Specifically, the control terminals of the first switch unit S1 and the second switch unit S2 can simultaneously receive the first control signal en_tx or the second control signal enb_dc. When the first control signal en_tx is high, both the first switch unit S1 and the second switch unit S2 are turned on; when the first control signal en_tx is low, both the first switch unit S1 and the second switch unit S2 are turned off. When the second control signal enb_dc is high, both the first switch unit S1 and the second switch unit S2 are turned on; when the second control signal enb_dc is low, both the first switch unit S1 and the second switch unit S2 are turned off.

[0045] The switching state of the third switch unit S3 can be controlled by the first control signal en_tx. When the first control signal en_tx is at a high level, the third switch unit S3 is turned on; when the first control signal en_tx is at a low level, the third switch unit S3 is turned off.

[0046] Specifically, the control terminal of the third switch unit S3 may input the first control signal en_tx, thereby achieving control of the switching state of the third switch unit S3 by the first control signal en_tx.

[0047] The switching state of the fourth switch unit S4 can be controlled by the second control signal enb_dc. When the second control signal enb_dc is high, the fourth switch unit S4 is turned on; when the second control signal enb_dc is low, the fourth switch unit S4 is turned off.

[0048] Specifically, the control terminal of the fourth switch unit S4 may input the second control signal enb_dc, thereby controlling the switching state of the fourth switch unit S4 through the second control signal enb_dc.

[0049] In some embodiments, the first switch unit S1, the second switch unit S2, the third switch unit S3 and the fourth switch unit S4 can all be MOS transistors (such as PMOS transistors or NMOS transistors), or other devices or modules or circuit units that can realize switching functions.

[0050] In the embodiment of the present invention, when the first switch unit S1 , the second switch unit S2 , the third switch unit S3 and the fourth switch unit S4 are all MOS transistors, the sizes of the first switch unit S1 , the second switch unit S2 and the fourth switch unit S4 may be the same or different.

[0051] Because the third switch unit S3 is connected to the power supply voltage Vdd, a large-sized MOS transistor can be used for the third switch unit S3. The size of the MOS transistor used in the third switch unit S3 can be larger than that of the first switch unit S1, the second switch unit S2, and the fourth switch unit S4. Using a large-sized MOS transistor in the third switch unit S3 can reduce the on-resistance voltage drop.

[0052] In combination with the terminal matching circuit term provided in FIG. 2 , when the first control signal en_tx is at a low level, the terminal matching circuit term and the receiver rx form a reference clock signal receiver.

[0053] When the second control signal enb_dc is at a low level, the first resistor R1, the second resistor R2, and the DC bias voltage source Vcm are not connected to the first output terminal VP and the second output terminal VN of the terminal matching circuit term. In this scenario, the DC coupling mode of the input reference clock signal is realized.

[0054] When the second control signal enb_dc is at a high level, the first switch unit S1, the second switch unit S2, and the fourth switch unit S4 are turned on, and the first resistor R1, the second resistor R2, and the DC bias voltage source Vcm all operate. The DC bias voltage output by the DC bias voltage source Vcm is output to the first resistor R1 and the second resistor R2. After voltage division by the first resistor R1 and the second resistor R2, the DC bias voltage is input to the first output terminal VP and the second output terminal VN of the terminal matching circuit term, respectively. At this time, the input reference clock signal can be coupled to the first output terminal VP and the second output terminal VN of the terminal matching circuit term after passing through the off-chip capacitors. The input reference clock signal is in AC coupling mode.

[0055] When the first control signal en_tx is high, the first, second, and third switch units S1, S2, and S3 are turned on, and the fourth switch unit S4 is turned off. At this point, the terminal matching circuit term and the transmitter tx form a reference clock signal transmitter. The power supply voltage Vdd is output through the first and second resistors R1 and R2, serving as the power supply for the transmitter tx. The first and second resistors R1 and R2 function as pull-up resistors for the transmitter tx.

[0056] In a specific implementation, the resistance of the first resistor R1 and the second resistor R2 can both be 50 ohms.

[0057] In an embodiment of the present invention, the receiver rx may include a differential amplifier unit and an operational amplifier, wherein:

[0058] A first input terminal of the differential amplifier unit is coupled to a first output terminal of the terminal matching circuit term, a second input terminal of the differential amplifier unit is coupled to a second output terminal of the terminal matching circuit term, a first output terminal of the differential amplifier unit is coupled to a first input terminal of the operational amplifier, and a second output terminal of the differential amplifier unit is coupled to a second input terminal of the operational amplifier.

[0059] The first output terminal and the second output terminal of the operational amplifier can be inversely proportional to each other and differentially output a logic low level and a logic high level. That is, when one output terminal of the operational amplifier outputs a logic low level, the other output terminal outputs a logic high level.

[0060] In a specific implementation, the aforementioned logic low level may be a logic level “0”, and the aforementioned logic high level may be a logic level “1”.

[0061] In a specific implementation, the first input terminal of the differential amplifier unit inputs VP, and the second input terminal of the differential amplifier unit inputs VN. The differential amplifier unit converts the differential logic level at the first and second output terminals of the terminal matching circuit term into a current mode (CML) logic level. The rail-to-rail operational amplifier converts the CML logic level into a CMOS logic level.

[0062] 3 , a schematic structural diagram of a receiver rx according to an embodiment of the present invention is shown.

[0063] In a specific implementation, the differential amplification unit may include a third resistor R3, a fourth resistor R4, a first NMOS transistor M1, and a second NMOS transistor M2, wherein:

[0064] A first end of the third resistor R3 is input with a power supply voltage Vdd, and a second end of the third resistor R3 is coupled to the drain of the first NMOS transistor M1;

[0065] A first end of the fourth resistor R4 is input with a power supply voltage Vdd, and a second end of the fourth resistor R4 is coupled to the drain of the second NMOS transistor M2;

[0066] The gate of the first NMOS transistor M1 is coupled to the first input terminal of the differential amplifier unit (or serves as the first input terminal of the differential amplifier unit), and the source of the first NMOS transistor M1 is grounded;

[0067] The gate of the second NMOS transistor M2 is coupled to the second input terminal of the differential amplifier unit (or serves as the second input terminal of the differential amplifier unit), and the source of the second NMOS transistor M2 is grounded.

[0068] The gate input of the first NMOS transistor M1 is VP, and the gate input of the second NMOS transistor M2 is VN. The drain of the first NMOS transistor M1 is coupled to the first input terminal of the operational amplifier OP and can serve as the first output terminal of the differential amplifier unit; the drain of the second NMOS transistor M2 is coupled to the second input terminal of the operational amplifier OP and can serve as the second output terminal of the differential amplifier unit.

[0069] In a specific implementation, the receiver rx may further include: a bias current source Ibias outputting a first bias current, wherein:

[0070] A first terminal of the bias current source Ibias is coupled to the source of the first NMOS transistor M1 and the source of the second NMOS transistor M2 , and a second terminal of the bias current source Ibias is grounded.

[0071] In some embodiments, the first bias current output by the bias current source Ibias may be a fixed value.

[0072] In the embodiment of the present invention, the transmitter tx may include N differential CML amplifiers 41. The structure of any differential CML amplifier 41 may be the same. Referring to FIG4 , a schematic diagram of the structure of a transmitter tx in the embodiment of the present invention is shown.

[0073] In a specific implementation, any differential CML amplifier may include: a third NMOS transistor M3, a fourth NMOS transistor M4, a fifth NMOS transistor M5, and a fifth switch unit S5, wherein:

[0074] The gate of the third NMOS transistor M3 can input the first differential reference clock signal clkp, the drain of the third NMOS transistor M3 can be coupled to the first output terminal VP of the terminal matching circuit term, and the source of the third NMOS transistor M3 is coupled to the drain of the fifth NMOS transistor M5;

[0075] The gate of the fourth NMOS transistor M4 can input the second differential reference clock signal clkn, the drain of the fourth NMOS transistor M4 is coupled to the second output terminal VN of the terminal matching circuit term, and the source of the fourth NMOS transistor M4 can be coupled to the drain of the fifth NMOS transistor M5;

[0076] The gate of the fifth NMOS transistor M5 may be coupled to the second end of the fifth switch unit S5, and the source of the fifth NMOS transistor M5 is grounded;

[0077] The second bias current biasn is input to a first terminal of the fifth switch unit S5 , and the third control signal is input to a control terminal of the fifth switch unit S5 .

[0078] In a specific implementation, the first differential reference clock signal clkp and the second differential reference clock signal clkn are reference clock signals recovered by a clock recovery circuit.

[0079] In a specific implementation, the differential CML amplifier 41 may reuse the first resistor R1 , the second resistor R2 , and the power supply voltage Vdd in the terminal matching circuit term.

[0080] In a specific implementation, the tail current of the transmitter tx is configurable. By configuring the tail current of the transmitter tx, the pull-down current strength of the first output terminal VP and the second output terminal VN of the terminal matching circuit term can be adjusted, thereby changing the output stage driving capability.

[0081] For specific output requirements, the power supply voltage Vdd of the terminator and the number of enabled differential CML amplifiers (M) can be determined based on logic level specifications. Specifically, assuming a 100-ohm resistor at both output terminals of the transmitter tx, for a logic-high level, VOH = Vdd - Itx × M × 12.5Ω; for a logic-low level, VOH = Vdd - Itx × M × 37.5Ω.

[0082] Specifically, the number of the turned-on differential CML amplifiers 41 can be controlled by controlling the switching state of the fifth switch unit S5 through the third control signal.

[0083] In summary, using the reference clock signal transceiver provided in the above embodiments, the terminal matching circuit can receive the first control signal and the second control signal. Based on the level of the first control signal, the terminal matching circuit can form a reference clock signal receiver with a receiver, or form a reference clock signal transmitter with a transmitter. When the terminal matching circuit and the receiver form a reference clock signal receiver, the received reference clock signal can be configured to be in AC coupling mode or DC coupling mode based on the second control signal. This allows for flexible configuration of the reference clock signal transceiver's reception and transmission, reception mode, and other aspects.

[0084] An embodiment of the present invention further provides a terminal device, comprising the reference clock signal transceiver provided by any of the above embodiments.

[0085] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A reference clock signal transceiver, characterized in that, Comprising: A terminal matching circuit, a receiver, and a transmitter, wherein: The terminal matching circuit is adapted to receive a first control signal and a second control signal; configure to form a reference clock signal receiver with the receiver or a reference clock signal transmitter with the transmitter based on the level of the first control signal; and, when determining to form a reference clock signal receiver with the receiver, configure the received reference clock signal to be in an AC coupling mode or a DC coupling mode based on the level of the second control signal.

2. The reference clock signal transceiver according to claim 1, characterized in that When the first control signal is at a first level and the second control signal is at a first level, the terminal matching circuit forms a reference clock signal receiver with the receiver, and the reference clock signal received by the reference clock signal receiver is in an AC coupling mode; When the first control signal is at a first level and the second control signal is at a second level, the terminal matching circuit forms a reference clock signal receiver with the receiver, and the reference clock signal received by the reference clock signal receiver is in a DC coupling mode; When the first control signal is at a second level and the second control signal is at a second level, the terminal matching circuit forms a reference clock signal transmitter with the receiver and transmits the reference clock signal.

3. The reference clock signal transceiver according to claim 2, wherein The terminal matching circuit includes: a first resistor, a second resistor, a DC bias voltage source, a first switch unit, a second switch unit, a third switch unit, and a fourth switch unit, wherein: The first switch unit, its first end is coupled to a first reference clock signal port and the first output end of the terminal matching circuit, and its second end is coupled to the first end of the first resistor; The first resistor, its second end is coupled to the first end of the second resistor, the first end of the third switch unit, and the first end of the fourth switch unit; The second resistor, its second end is coupled to the first end of the second switch unit; The second switch unit, its second end is coupled to a second reference clock signal port; The third switch unit, its second end inputs a power supply voltage; The fourth switch unit, its second end is coupled to the first end of the DC bias voltage source; The second end of the DC bias voltage source is grounded.

4. The reference clock signal transceiver according to claim 3, wherein The first switch unit, the second switch unit, the third switch unit, and the fourth switch unit are all MOS transistors, and the size of the third switch unit is larger than that of the first switch unit, the second switch unit, and the fourth switch unit.

5. The reference clock signal transceiver according to claim 2, wherein The receiver includes: a differential amplification unit and an operational amplifier, wherein: The differential amplification unit, its first input end is coupled to the first output end of the terminal matching circuit, its second input end is coupled to the second output end of the terminal matching circuit, its first output end is coupled to the first input end of the operational amplifier, and its second output end is coupled to the second input end of the operational amplifier; The operational amplifier, its first output end and second output end differentially output a logic low level and a logic high level.

6. The reference clock signal transceiver according to claim 5, wherein The differential amplification unit includes: a third resistor, a fourth resistor, a first NMOS transistor, and a second NMOS transistor, wherein: For the third resistor, its first terminal receives the power supply voltage, and its second terminal is coupled to the drain of the first NMOS transistor; For the fourth resistor, its first terminal receives the power supply voltage, and its second terminal is coupled to the drain of the second NMOS transistor; For the first NMOS transistor, its gate is coupled to the first input terminal of the differential amplification unit, and its source is grounded; For the second NMOS transistor, its gate is coupled to the second input terminal of the differential amplification unit, and its source is grounded.

7. The reference clock signal transceiver according to claim 6, wherein The receiver further includes: a bias current source adapted to output a first bias current, wherein: For the bias current source, its first terminal is coupled to the sources of the first NMOS transistor and the second NMOS transistor, and its second terminal is grounded.

8. The reference clock signal transceiver according to claim 2, wherein, The transmitter includes: N differential current mode logic (CML) amplifiers, and any one of the differential CML amplifiers includes: a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a fifth switching unit, wherein: For the third NMOS transistor, its drain is coupled to the first output terminal of the terminal matching circuit, its gate receives a first differential reference clock signal, and its source is coupled to the drain of the fifth NMOS transistor; For the fourth NMOS transistor, its drain is coupled to the second output terminal of the terminal matching circuit, its gate receives a second differential reference clock signal, and its source is coupled to the drain of the fifth NMOS transistor; For the fifth NMOS transistor, its gate is coupled to the second terminal of the fifth switching unit, and its source is grounded; For the fifth switching unit, its first terminal receives a second bias current, and its control terminal receives a third control signal.

9. A terminal device, characterized in that, Including the reference clock signal transceiver according to any one of claims 1 to 8.

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