Field-effect transistor

Abstract

This field-effect transistor comprises a gate interconnect (103), a first gate electrode (103a), a second gate electrode (103b), a drain interconnect (104), a source interconnect (105), a drain electrode connected to the drain interconnect (104), and a source electrode connected to the source interconnect (105). The drain electrode is formed from a first drain electrode (104a) and a second drain electrode (104b), and the source electrode is formed from a first source electrode (105a) and a second source electrode (105b). The first gate electrode (103a) and the second gate electrode (103b) are on top of an element region 102 and extending in the gate width direction from both sides of the gate interconnect (103).

Description

field-effect transistor

[0001] The present invention relates to a field effect transistor.

[0002] The terahertz frequency band (0.3 to 3.0 THz) is expected to be used in a wide range of applications, including not only next-generation high-speed wireless communications but also non-destructive testing using terahertz wave imaging, security applications using transmission imaging, material analysis using absorption spectra, and obtaining weather-related information using radiometers mounted on satellites. For this reason, attention is being drawn to electronic devices and integrated circuits that can directly handle the terahertz frequency band. Generally, field-effect transistors using compound semiconductors with high electron mobility are used as electronic devices with excellent high-frequency characteristics.

[0003] A high-frequency field-effect transistor generally has a structure in which a buffer layer, a channel layer, and a barrier layer are stacked on a semiconductor substrate, an ohmic cap layer and source and drain electrodes are formed on these, and a gate electrode is formed between the source and drain electrodes. A carrier supply layer called a delta-doped layer, for example, is formed in the barrier layer. The delta-doped layer is heavily doped with impurities. Electrons, which act as carriers when these impurities are ionized, accumulate in the channel layer, which has a smaller band gap than the barrier layer, forming a two-dimensional electron gas.

[0004] The two-dimensional electron gas in the channel layer is spatially separated from the ionized impurities by the barrier layer, and therefore can travel between the source and drain at high speed without being affected by mobility degradation due to impurity scattering.

[0005] In addition, the ohmic cap layer may be doped with impurities in the same manner as the carrier supply layer in order to facilitate carrier injection from the source electrode to the channel layer and carrier conduction from the channel layer to the drain electrode, i.e., to reduce the source resistance and the drain resistance.

[0006] In the above-mentioned field-effect transistor, the two-dimensional electron gas concentration in the channel layer is controlled by applying a voltage to the gate electrode to modulate the band structure directly below the gate electrode, thereby controlling the amount of current flowing between the source and drain. Therefore, in a configuration in which the source electrode is grounded, by inputting a high-frequency signal to be amplified to the gate electrode, the amplified signal can be output from the drain electrode.

[0007] As an index for evaluating the operating frequency of such a high-frequency field-effect transistor, the maximum oscillation frequency f given by the following formula is used: max There is.

[0008]

[0009] where f t is the current gain cutoff frequency, R i , R s , R g are the channel resistance, source resistance, and gate resistance, respectively, and g d,int is the drain conductance of the device intrinsic region, C gd is the gate-drain capacitance. t is often written as equation (2), but more precisely, the source resistance R s , drain resistance R d Taking into account the influence of (3), it is sometimes written as (Non-Patent Document 1, Non-Patent Document 2).

[0010]

[0011] Here, C gs is the gate-source capacitance, g m,int is the transconductance of the intrinsic region of the device. From these equations, in order to increase the frequency of field-effect transistors and circuits that consist of these field-effect transistors, C gs and C gd It is clear that reducing

[0012] On the other hand, there are applications that require not only higher frequencies but also higher output power, such as power amplifier circuits on the transmitting side. To achieve higher output power, it is essential to increase the drive current of individual transistors, that is, to extract more output from the drain relative to the input to the gate.

[0013] In order to increase the driving current, a field effect transistor consisting of a gate electrode 303, a drain electrode 304, and a source electrode 305 formed in an element region 302 shown in FIG. 14 has a channel width W g The simplest and most common method is to stretch the

[0014] However, when the channel width is extended, the distance from the terminal portion of the gate electrode to the other end of the gate electrode becomes longer, and the gate resistance R g is typically the channel width W g It increases linearly with R g From equation (1), the increase in f max This leads to deterioration of the amplifier circuit. Furthermore, as the frequency of the signals handled increases, it becomes more difficult for the high-frequency signals input from the terminal to reach the other end of the gate electrode. This can result in the gate width not being as long as designed, or in areas where the electric field from the gate does not act on the channel, which can cause distortion in the amplifier circuit.

[0015] In comparison, the conventional multi-finger structure can more efficiently increase the channel width and achieve a higher drive current. However, with the multi-finger structure, if the number of gate electrodes is increased or each gate electrode is extended in order to further increase the drive current, the same problems as those described above arise.

[0016] In contrast to such conventional electrode layouts, electrode layouts that utilize advanced three-dimensional wiring at the device level have been proposed. For example, Non-Patent Document 3 proposes an electrode layout consisting of a honeycomb structure and three-layer wiring. It has been reported that this technology can disperse heat sources compared to conventional structures and suppress current reduction due to "self-heating." In principle, this technology differs from simple channel width extension or conventional multi-fingering, and enables high drive current by effectively utilizing the element region. Furthermore, the increase in capacitance due to such multi-layer wiring can be reduced by "air bridge" technology, which creates a cavity between the wiring.

[0017] PJ Tasker and B. Hughes, "Importance of Source and Drain Resistance to the Maximum fT of Millimeter-Wave MODFET's", IEEE Electron Device Lett, vol. 10, No. 7, pp. 291-293, 1989.H. -B. Jo et al., "Sub-30-nm In0.8Ga0.2As Composite-Channel High-Electron-Mobility Transistors with Record High-Frequency Characteristics", IEEE Transactions on Electron Devices, vol. 68, no. 4, pp. 2010-2016, 2021. K. Shinohara et al., "Design and Fabrication of Millimeter-Wave GaN HEMTs", in Proc. of CS Mantech, 4.2.2023, 2023.

[0018] However, with three-dimensional wiring, the process becomes more complicated as the number of wiring layers increases, and productivity decreases. For example, the technology in Non-Patent Document 3 employs a three-layer structure for device wiring, but from the viewpoint of productivity, two layers are preferable. Also, the gate-source distance L gs and the gate-drain distance Lgd is an important engineering target for achieving higher frequencies and lower noise, and it is desirable that it can be easily adjusted. gs and L gd Although it is possible to adjust the value, electrons flow from the source electrode in the center of the honeycomb to the drain electrode on the outside of the honeycomb, which is different from the conventional L gs / L gd It is difficult to apply engineering knowledge directly.

[0019] On the other hand, in the conventional multi-finger structure, the wiring of the device can generally be formed in two layers, and the source electrode, drain electrode, and gate electrode are arranged in parallel, so gs / L gd Although it is possible to apply engineering knowledge, since the input signal travels from one end of the element region to the other end via the gate electrode, the gate resistance R g will increase.

[0020] Therefore, the three-dimensional wiring structure of the device that efficiently utilizes the element area is formed in two layers from the viewpoint of productivity, and is different from the conventional L gs / L gd Engineering knowledge can be applied as is, and the gate resistance R g It is required that the structure be such that the above can be reduced.

[0021] The present invention has been made to solve the above problems, and gs / L gd The objective is to make it possible to apply engineering knowledge as is and to reduce gate resistance compared to conventional structures.

[0022] A field effect transistor according to the present invention comprises: an element region including a channel layer made of a compound semiconductor and a barrier layer made of a compound semiconductor formed on a substrate; a gate wiring arranged on the element region and extending across the element region in the gate length direction in a plan view; a drain wiring and a source wiring arranged on both sides of the element region, extending in the gate length direction with the gate wiring sandwiched between them in a plan view; a first gate electrode and a second gate electrode extending in the gate width direction from both sides of the gate wiring above the element region; and a drain electrode and a source electrode arranged on both sides of the first gate electrode and the second gate electrode and extending in the gate width direction, wherein the drain electrode is connected to the drain wiring and the source electrode is connected to the source wiring.

[0023] As described above, according to the present invention, two gate electrodes are extended in the gate width direction around the gate wiring. gs / L gd Engineering knowledge can be applied directly, and gate resistance can be reduced compared to conventional structures.

[0024] FIG. 1A is a plan view showing a configuration of a field-effect transistor according to a first embodiment of the present invention. FIG. 1B is a cross-sectional view showing a partial configuration of the field-effect transistor according to the first embodiment of the present invention. FIG. 1C is a cross-sectional view showing a partial configuration of the field-effect transistor according to the first embodiment of the present invention. FIG. 2A is a cross-sectional view showing a state of a field-effect transistor in an intermediate step for explaining a method for manufacturing a field-effect transistor according to the first embodiment of the present invention. FIG. 2B is a cross-sectional view showing a state of a field-effect transistor in an intermediate step for explaining a method for manufacturing a field-effect transistor according to the first embodiment of the present invention. FIG. 2C is a cross-sectional view showing a state of a field-effect transistor in an intermediate step for explaining a method for manufacturing a field-effect transistor according to the first embodiment of the present invention. FIG. 2D is a cross-sectional view showing a state of a field-effect transistor in an intermediate step for explaining a method for manufacturing a field-effect transistor according to the first embodiment of the present invention. FIG. 2E is a cross-sectional view showing a state of a field-effect transistor in an intermediate step for explaining a method for manufacturing a field-effect transistor according to the first embodiment of the present invention. FIG. 2F is a cross-sectional view showing a state of a field-effect transistor in an intermediate step for explaining a method for manufacturing a field-effect transistor according to the first embodiment of the present invention. FIG. 2G is a cross-sectional view showing a state of a field-effect transistor in an intermediate step for explaining a method for manufacturing a field-effect transistor according to the first embodiment of the present invention. Fig. 2H is a cross-sectional view showing the state of a field effect transistor in an intermediate step for explaining the method for manufacturing a field effect transistor according to embodiment 1 of the present invention. Fig. 2I is a cross-sectional view showing the state of a field effect transistor in an intermediate step for explaining the method for manufacturing a field effect transistor according to embodiment 1 of the present invention. Fig. 2J is a cross-sectional view showing the state of a field effect transistor in an intermediate step for explaining the method for manufacturing a field effect transistor according to embodiment 1 of the present invention. Fig. 2K is a cross-sectional view showing the state of a field effect transistor in an intermediate step for explaining the method for manufacturing a field effect transistor according to embodiment 1 of the present invention. Fig. 3A is a plan view showing a partial configuration of the field effect transistor according to embodiment 1 of the present invention. Fig. 3B is a plan view showing the configuration of a conventional field effect transistor.FIG. 4 is a plan view showing a partial configuration of a field-effect transistor according to embodiment 1 of the present invention. FIG. 5A is a plan view showing a partial configuration of a field-effect transistor according to embodiment 2 of the present invention. FIG. 5B is a cross-sectional view showing a partial configuration of a field-effect transistor according to embodiment 2 of the present invention. FIG. 5C is a cross-sectional view showing a partial configuration of a field-effect transistor according to embodiment 2 of the present invention. FIG. 6A is a cross-sectional view showing a state of a field-effect transistor in an intermediate step for explaining a method for manufacturing a field-effect transistor according to embodiment 2 of the present invention. FIG. 6B is a cross-sectional view showing a state of a field-effect transistor in an intermediate step for explaining a method for manufacturing a field-effect transistor according to embodiment 2 of the present invention. FIG. 6C is a cross-sectional view showing a state of a field-effect transistor in an intermediate step for explaining a method for manufacturing a field-effect transistor according to embodiment 2 of the present invention. FIG. 6D is a cross-sectional view showing a state of a field-effect transistor in an intermediate step for explaining a method for manufacturing a field-effect transistor according to embodiment 2 of the present invention. FIG. 6E is a cross-sectional view showing a state of a field-effect transistor in an intermediate step for explaining a method for manufacturing a field-effect transistor according to embodiment 2 of the present invention. FIG. 6F is a cross-sectional view showing a state of a field-effect transistor in an intermediate step for explaining a method for manufacturing a field-effect transistor according to embodiment 2 of the present invention. FIG. 6G is a cross-sectional view showing a state of a field-effect transistor in an intermediate step for explaining a method for manufacturing a field-effect transistor according to embodiment 2 of the present invention. Fig. 6H is a cross-sectional view showing the state of a field effect transistor in an intermediate step for explaining the method for manufacturing a field effect transistor according to embodiment 2 of the present invention. Fig. 6I is a cross-sectional view showing the state of a field effect transistor in an intermediate step for explaining the method for manufacturing a field effect transistor according to embodiment 2 of the present invention. Fig. 6J is a cross-sectional view showing the state of a field effect transistor in an intermediate step for explaining the method for manufacturing a field effect transistor according to embodiment 2 of the present invention. Fig. 7 is a plan view showing a partial configuration of a field effect transistor according to embodiment 3 of the present invention. Fig. 8A is a cross-sectional view showing the state of a field effect transistor in an intermediate step for explaining the method for manufacturing a field effect transistor according to embodiment 3 of the present invention.FIG. 8B is a plan view showing a state of a field-effect transistor in an intermediate step for explaining the method for manufacturing a field-effect transistor according to embodiment 3 of the present invention. FIG. 8C is a cross-sectional view showing a state of a field-effect transistor in an intermediate step for explaining the method for manufacturing a field-effect transistor according to embodiment 3 of the present invention. FIG. 8D is a cross-sectional view showing a state of a field-effect transistor in an intermediate step for explaining the method for manufacturing a field-effect transistor according to embodiment 3 of the present invention. FIG. 8E is a cross-sectional view showing a state of a field-effect transistor in an intermediate step for explaining the method for manufacturing a field-effect transistor according to embodiment 3 of the present invention. FIG. 8F is a cross-sectional view showing a state of a field-effect transistor in an intermediate step for explaining the method for manufacturing a field-effect transistor according to embodiment 3 of the present invention. FIG. 8G is a cross-sectional view showing a state of a field-effect transistor in an intermediate step for explaining the method for manufacturing a field-effect transistor according to embodiment 3 of the present invention. FIG. 9 is a plan view showing a partial configuration of a field-effect transistor according to embodiment 4 of the present invention. FIG. 10 is a plan view showing a partial configuration of a field-effect transistor according to embodiment 5 of the present invention. FIG. 11 is a plan view showing a partial configuration of another field-effect transistor according to embodiment 5 of the present invention. FIG. 12 is a plan view showing a partial configuration of another field-effect transistor according to embodiment 5 of the present invention. FIG. 13 is a plan view showing a partial configuration of another field-effect transistor according to embodiment 5 of the present invention. FIG. 14 is a plan view showing the configuration of a conventional field effect transistor.

[0025] Hereinafter, a field effect transistor according to an embodiment of the present invention will be described.

[0026] First Embodiment First, a field-effect transistor according to a first embodiment of the present invention will be described with reference to Figures 1A, 1B, and 1C. Figure 1B shows a cross section taken along a line aa' in Figure 1A. Figure 1C shows a cross section taken along a line bb' in Figure 1A.

[0027] This field effect transistor includes a gate wiring 103, a first gate electrode 103a, a second gate electrode 103b, a drain wiring 104, a source wiring 105, a drain electrode connected to the drain wiring 104, and a source electrode connected to the source wiring 105. In the first embodiment, the drain electrode is composed of a first drain electrode 104a and a second drain electrode 104b, and the source electrode is composed of a first source electrode 105a and a second source electrode 105b.

[0028] The gate wiring 103 is disposed on a pillar-shaped device region 102 formed on the substrate 101. The gate wiring 103 is disposed so as to extend across the device region 102 in the gate length direction (the vertical direction on the paper surface of FIG. 1A) in a plan view. The gate wiring 103 is connected to a terminal 107 disposed outside the device region 102. The device region 102 includes a channel layer 111 made of a compound semiconductor such as InGaAs, and a barrier layer 112 made of a compound semiconductor such as InAlAs. The channel layer 111 may have a thickness of 5 to 20 nm. The barrier layer 112 may have a thickness of 5 to 20 nm.

[0029] The drain wiring 104 and the source wiring 105 extend in the first direction in plan view, sandwiching the gate wiring 103 therebetween, and are arranged on both sides of the element region 102. Each of the drain wiring 104 and the source wiring 105 can be arranged, for example, parallel to the gate wiring 103.

[0030] The first gate electrode 103a and the second gate electrode 103b are formed on the element region 102, extending from both sides of the gate wiring 103 in the gate width direction.

[0031] The first drain electrode 104a and the second source electrode 105b are arranged to sandwich the first gate electrode 103a, and the second drain electrode 104b and the first source electrode 105a are arranged to sandwich the second gate electrode 103b. The first drain electrode 104a, the second drain electrode 104b, the first source electrode 105a, and the second source electrode 105b are formed to extend in the gate width direction.

[0032] The first drain electrode 104a and the second drain electrode 104b are connected by a first connection wiring 141. The first source electrode 105a and the second source electrode 105b are connected by a second connection wiring 151. The first drain electrode 104a is connected to the drain wiring 104, and the first source electrode 105a is connected to the source wiring 105.

[0033] In the first embodiment, the first connection wiring 141 is arranged above the gate wiring 103 and intersects with the gate wiring 103. Furthermore, the second connection wiring 151 is arranged above the gate wiring 103 and intersects with the gate wiring 103. The first connection wiring 141 and the second connection wiring 151 are formed on the interlayer insulating layer 116. Note that each connection wiring can be arranged below the gate wiring 103 and intersects with the gate wiring 103. Furthermore, the first connection wiring 141 is connected to the first drain electrode 104 a and the second drain electrode 104 b by a through wiring 106 that penetrates the interlayer insulating layer 116.

[0034] For example, the device region 102 has a buffer layer 121 made of InAlAs formed on a substrate 101 made of semi-insulating InP, and a channel layer 111 and a barrier layer 112 formed on the buffer layer 121. The buffer layer 121 may have a thickness of, for example, 100 to 300 nm. Although not shown, the barrier layer 112 is doped with 1×10 Si as an impurity by well-known sheet doping. 19 cm -3 A doped carrier supply layer called a δ-doped layer is formed.

[0035] An etching stop layer 113 is provided on the barrier layer 112, an ohmic cap layer 114 is formed on the etching stop layer 113, and a first drain electrode 104a, a second drain electrode 104b, a first source electrode 105a, and a second source electrode 105b are formed on the ohmic cap layer 114. The etching stop layer 113 can be made of a material that has high etching selectivity with respect to an etching solution used to etch the ohmic cap layer 114 to form the recess region 114a, which will be described later. The ohmic cap layer 114 can be made of a material that has high etching selectivity with respect to an etching solution used to etch the ohmic cap layer 114 to form the recess region 114a, for example.19 ~2 x 10 19 cm -3 The semiconductor layer may be made of highly doped InGaAs.

[0036] Furthermore, the drain wiring 104, the source wiring 105, the first drain electrode 104a, the second drain electrode 104b, the first source electrode 105a, and the second source electrode 105b can be constructed from a laminated structure of metals such as Ti, Pt, Au, Ni, and Mo.

[0037] Furthermore, insulating layers 115 are formed on the ohmic cap layer 114 between the first drain electrode 104a (first source electrode 105a) and the second drain electrode 104b (second source electrode 105b) in the gate width direction and between the first drain electrode 104a (second drain electrode 104b) and the first source electrode 105a (second source electrode 105b) in the gate length direction. The insulating layer 115 has a gate opening 115a. The insulating layer 115 can be made of an insulating material such as SiO2, SiN, Al2O3, or HfO2.

[0038] The recess regions 114a are formed in the ohmic cap layer 114 between the first drain electrode 104a (first source electrode 105a) and the second drain electrode 104b (second source electrode 105b) in the gate width direction, and between the first drain electrode 104a (second drain electrode 104b) and the first source electrode 105a (second source electrode 105b) in the gate length direction.

[0039] The recess region 114a can be referred to as a depression or groove formed in the ohmic cap layer 114. The gate wiring 103, the first gate electrode 103a, and the second gate electrode 103b are formed on the insulating layer 115, and a portion of each of them is embedded in the recess region 114a through the gate opening 115a. The gate wiring 103, the first gate electrode 103a, and the second gate electrode 103b are formed from the gate opening 115a in the depth direction to the etching stop layer 113.

[0040] The gate wiring 103, the first gate electrode 103a, and the second gate electrode 103b can be formed from a composite structure mainly of Ti, Pt, Au, Ni, and Mo. In order to achieve a short gate length while minimizing gate resistance, the gate wiring 103, the first gate electrode 103a, and the second gate electrode 103b can be T-shaped, Y-shaped, or Γ-shaped, with the upper part having a larger area than the lower part in a plan view.

[0041] The first gate electrode 103a and the second gate electrode 103b, the first drain electrode 104a and the second drain electrode 104b, and the first source electrode 105a and the second source electrode 105b are formed insulated and separated from each other.

[0042] In this example, the first drain electrode 104a and the second drain electrode 104b are three electrodes, and the first source electrode 105a and the second source electrode 105b are three electrodes, but only one electrode of each is required. The number of first drain electrodes 104a and the second drain electrode 104b does not need to be the same as the number of first source electrodes 105a and the second source electrode 105b. For example, in a plan view, the electrodes can be arranged from one end to the other in the gate length direction as follows: "first source electrode 105a and the second source electrode 105b" - "first gate electrode 103a and the second gate electrode 103b" - "first drain electrode 104a and the second drain electrode 104b" - "first gate electrode 103a and the second gate electrode 103b" - "first source electrode 105a and the second source electrode 105b."

[0043] According to the first embodiment described above, the gate wiring, gate electrode, drain wiring, drain electrode, source wiring, and source electrode can be formed in the same wiring layer, and the connection wiring can be formed in the wiring layer formed above this, allowing the wiring layer to be configured with two layers. Furthermore, according to the first embodiment, two gate electrodes are extended in the gate width direction with the gate wiring at the center. With this configuration, in the first embodiment, the length of each gate electrode in the gate width direction can be approximately half that of a conventional multi-finger gate. As a result, according to the first embodiment, an increase in gate resistance can be suppressed.

[0044] Next, a method for manufacturing the field effect transistor according to the first embodiment will be described with reference to FIGS. 2A to 2K.

[0045] First, as shown in FIG. 2A, a buffer layer 121, a channel layer 111, a barrier layer 112, a carrier supply layer (not shown), an etching stop layer 113, and an ohmic cap layer 114 are formed on a substrate 101 in this order.

[0046] For example, on a substrate 101, a buffer layer 121 made of InAlAs and having a thickness of 100 to 300 nm, a channel layer 111 made of InGaAs and having a thickness of 5 to 20 nm, a barrier layer 112 made of InAlAs and having a thickness of 5 to 20 nm, and a Si layer of 1×10 19 ~2 x 10 19 cm -3 The ohmic cap layer 114 made of InGaAs doped with 1×10 is then deposited by crystal growth using metal organic chemical vapor deposition, molecular beam epitaxy, or the like. The barrier layer 112 is doped with 1×10 Si as an impurity using well-known sheet doping. 19 cm -3 A doped carrier supply layer is formed. In addition, an etching stop layer 113 made of InP and having a thickness of 2 to 5 nm is formed between the barrier layer 112 and the ohmic cap layer 114.

[0047] 2B , a columnar (rectangular) element region 102 is formed. For example, a mask pattern (not shown) is formed by standard lithography technology, and the ohmic cap layer 114, the etching stop layer 113, the barrier layer 112, the channel layer 111, and a portion of the buffer layer 121 in the thickness direction are etched using the formed mask pattern as a mask, thereby forming the element region 102. For example, citric acid is used as an etchant for InGaAs or InAlAs, and a mixture of hydrochloric acid, phosphoric acid, and water is used as an etchant for InP.

[0048] In order to avoid electrical contact with the electrodes formed on the side surfaces of the element region 102, the channel layer 111 can be side-etched to extend inward from the side surfaces (side walls).

[0049] Next, as shown in Figures 2C and 2D, the drain wiring 104, the source wiring 105, the first drain electrode 104a, the second drain electrode 104b, the first source electrode 105a, and the second source electrode 105b are formed. The first drain electrode 104a, the second drain electrode 104b, the first source electrode 105a, and the second source electrode 105b are formed by ohmic contact with the ohmic cap layer 114. Note that Figure 2C shows a partial cross section taken along line aa' in Figure 1A. Also, Figure 2D shows a cross section taken along line cc' in Figure 1A. The drain wiring 104 and the source wiring 105 are disposed on the buffer layer 121 on both sides of the element region 102 in the gate width direction.

[0050] For example, first, a lift-off mask having openings at locations where the wiring and electrodes will be formed is formed by known lithography techniques. Next, a metal film of Ni, Ti, Pt, Au, Mo, or the like, or a composite deposited film of these metals is formed on top of the formed lift-off mask by electrolytic plating, electroless plating, vacuum deposition, sputtering, or the like. Thereafter, the lift-off mask is removed to form the drain wiring 104, the source wiring 105, the first drain electrode 104a, the second drain electrode 104b, the first source electrode 105a, and the second source electrode 105b.

[0051] 2E and 2F, an insulating layer 115 is formed, a gate opening 115a is formed in the formed insulating layer 115, and a recess region 114a is further formed. Note that Fig. 2E shows a partial cross section taken along line aa' in Fig. 1A. Fig. 2F shows a cross section taken along line cc' in Fig. 1A.

[0052] For example, first, an insulating film is deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, or the like. The insulating film can typically be SiO, SiN, or a composite deposited film of these. Next, the region where the gate wiring and gate electrode are to be formed is patterned by lithography and etching to form a gate opening 115a with the desired gate length, and the insulating layer 115 is formed.

[0053] The insulating film can be etched by dry etching using etching gas such as C2F6 or SF6, or by wet etching using HF, etc. Thereafter, the resist mask used in the etching is removed using an organic solvent or the like.

[0054] The size of the gate electrode is the gate length L of the field effect transistor. g In order to determine the size of the gate electrode, it is necessary to form the gate opening 115a finely. g Since it is not related to g In order to reduce the gate electrode thickness, the gate opening 115a in the portion to be the gate wiring can be made wider than the portion to be the gate electrode. Here, if an effective etching process utilizing the battery effect or the like is aimed at in the subsequent formation of the recess region 114a, part or all of the insulating layer 115 on the source electrode and the drain electrode can be etched and removed to expose each electrode.

[0055] Next, an etching solution (etchant) is poured through the gate opening 115a to etch the ohmic cap layer 114 directly below the gate opening 115a, forming a recess region 114a. For example, if the cap layer is composed of InGaAs, InAlAs, or a composite layer of these, a citric acid-based etchant can be used for the etching process. The length of the recess region 114a is called the recess length. A typical recess length is 50 to 500 nm.

[0056] Next, as shown in Figures 2G and 2H, gate wiring 103 and, although not shown, first gate electrode 103a, second gate electrode 103b, and terminal 107 are formed. Note that Figure 2G shows a partial cross section taken along line aa' in Figure 1A. Also, Figure 2H shows a cross section taken along line cc' in Figure 1A. Note that in this example, a gate that is T-shaped in cross section, which is generally used in high-frequency transistors, will be described as an example, but the cross-sectional shape of gate wiring 103 (first gate electrode 103a, second gate electrode 103b) can have another structure, such as a Y-shape.

[0057] First, a lift-off mask is formed having openings where the gate wiring 103, the first gate electrode 103a, the second gate electrode 103b, and the terminal 107 will be formed. Next, a metal film of Ni, Ti, Pt, Au, Mo, or the like, or a composite deposited film of these metals, is formed on top of the formed lift-off mask by electrolytic plating, electroless plating, vacuum deposition, sputtering, or the like. Thereafter, the lift-off mask is removed, thereby forming the gate wiring 103, the first gate electrode 103a, the second gate electrode 103b, and the terminal 107.

[0058] Next, as shown in Figures 2I and 2J, an interlayer insulating layer 116 is formed on the gate wiring 103 and the first gate electrode 103a, second gate electrode 103b, and terminal 107 (not shown). Also, as shown in Figure 2I, a through wiring 106 is formed penetrating the interlayer insulating layer 116, and a second connection wiring 151 (first connection wiring 141) connected to the through wiring 106 is formed on the interlayer insulating layer 116. Note that Figure 2I shows a partial cross section taken along line aa' in Figure 1A. Also, Figure 2J shows a cross section taken along line cc' in Figure 1A.

[0059] For example, SiO, SiN, or a combination of these is deposited by CVD, PVD, ALD, sputtering, or the like to form an interlayer insulating layer 116 that covers the gate wiring 103, the first gate electrode 103a, the second gate electrode 103b, and the terminal 107. Next, contact holes are formed in the interlayer insulating layer 116 at the locations where the through wiring 106 is to be formed by known lithography and etching techniques.

[0060] Next, a lift-off mask is formed having openings where the first connection wiring 141 and the second connection wiring 151 will be formed. Next, a metal film of Ni, Ti, Pt, Au, Mo, or the like, or a composite deposited film of these, is formed on top of the formed lift-off mask by electrolytic plating, electroless plating, vacuum deposition, sputtering, or the like. Thereafter, the lift-off mask is removed, thereby forming the through wiring 106, the first connection wiring 141, and the second connection wiring 151.

[0061] Incidentally, the first connection wiring 141 and the second connection wiring 151 intersect with the gate wiring 103, and therefore, the parasitic capacitance C gs , C gd In order to reduce this parasitic capacitance, as shown in FIG. 2K, by etching away a portion of the interlayer insulating layer 116 using an air bridge technique or the like, it is possible to form a gap 123 at the location where the first connection wiring 141 and the second connection wiring 151 intersect with the gate wiring 103. Note that FIG. 2K shows a partial cross section taken along line aa' in FIG. 1A.

[0062] For example, a resist pattern having openings at locations where the voids 123 are to be formed is formed by a known lithography technique. Next, using the formed resist pattern as a mask, the interlayer insulating layer 116 is etched and removed to a predetermined thickness by dry etching using C2F6 or SF6 or wet etching using HF or the like. Thereafter, the resist pattern is removed using an organic solvent or the like. As a result, a C formed by the three-dimensionally arranged first connection wiring 141 and second connection wiring 151 is formed. gs , C gd This allows the device to operate at a higher frequency.

[0063] Next, the characteristics of the field-effect transistor according to the first embodiment will be described. First, as shown in FIG. 3A, the field-effect transistor according to the first embodiment has three source electrodes and three drain electrodes. The distance from the top drain electrode to the edge of the device region 102 and the distance from the bottom source electrode to the edge of the device region 102 are 0.5 μm, the width of the source electrode and the drain electrode are 2.0 μm, and the distance between the source electrode and the drain electrode is 1.5 μm. This results in a height of 20.5 μm in the device region 102. The width of the device region 102 is 10 μm, and the gap between the lower source electrode and the lower drain electrode due to the bridge structure is 5.0 μm. The direction of current in the channel layer is from the source electrode to the drain electrode. Note that the scale in FIG. 3 is different.

[0064] 3B shows a conventional field effect transistor. The distance from the drain electrode 304 and the source electrode 305 to the end of the element region 302 is 0.5 μm, the length of the drain electrode 304 and the source electrode 305 in the gate width direction is 19.5 μm, and the area of ​​the element region 302 is 10.0 μm × 20.5 μm in plan view.

[0065] In the first embodiment shown in Fig. 3A, the total channel width is 2.5 μm × 10 = 25 μm, whereas the channel width in the conventional structure shown in Fig. 3B is 19.5 μm. Thus, according to the first embodiment, in a typical dimension, by more effectively utilizing the element region 102, the channel width can be increased by about 1.3 times without changing the area of ​​the element region 102, and if the drain current per unit channel width is the same, the drain current can be increased by 1.3 times.

[0066] Next, referring to FIG. 4, according to the first embodiment, gs and L gd From the above equations (1) to (3), C gs and C gd Reduction of R s and R d Reduction of L is effective for increasing the frequency of the device. gsThe extension of C gs While this leads to a reduction in R s This also leads to an increase in gd The extension of C gd While this leads to a reduction in R d This also leads to an increase in L gs and L gd is the subject of engineering efforts aimed at increasing frequencies.

[0067] Generally, when the layout of the source electrode, drain electrode, and gate electrode is significantly changed by adopting three-dimensional wiring, the L gs and L gd In contrast, according to the first embodiment, the first gate electrode 103a and the second gate electrode 103b, the first drain electrode 104a and the second drain electrode 104b, and the first source electrode 105a and the second source electrode 105b are arranged in parallel with each other, so that the L gs , L gd For example, in the example shown in FIG. gd f by reducing t ,f max Aiming to improve L gd >L gs It is said that. C gd is also called "feedback capacitance" and is known to have a significant effect on high frequency characteristics.

[0068] In the above example, a single L gs , L gd However, different values ​​may be used for each set of the first gate electrode 103a and the second gate electrode 103b, the first drain electrode 104a and the second drain electrode 104b, and the first source electrode 105a and the second source electrode 105b.

[0069] Furthermore, in the first embodiment, the input signal does not propagate across the entire element region 102 as in the conventional multi-finger structure, but propagates from the central gate wiring 103 to both ends of the element region 102 in the gate width direction. Therefore, the propagation path of the input signal can be designed to be short, and the gate resistance R g can be reduced.

[0070] Second Embodiment Next, a field-effect transistor according to a second embodiment of the present invention will be described with reference to Figures 5A, 5B, and 5C. Figure 5B shows a cross section taken along line aa' in Figure 5A. Figure 5C shows a cross section taken along line bb' in Figure 5A.

[0071] This field effect transistor includes a gate wiring 103 ′, a first gate electrode 103 a, a second gate electrode 103 b, a drain wiring 104, a source wiring 105, a drain electrode 104 ′ connected to the drain wiring 104 , and a source electrode 105 ′ connected to the source wiring 105 .

[0072] In the second embodiment, a first element region 102a and a second element region 102b are disposed adjacent to each other with a predetermined gap between them at two locations on a substrate 101. A gate wiring 103' is disposed between the first element region 102a and the second element region 102b. The gate wiring 103' is disposed between the first element region 102a and the second element region 102b, extending in the gate length direction (the vertical direction on the paper surface of FIG. 5A ) in a plan view. The gate wiring 103' is connected to a terminal 107. The first element region 102a and the second element region 102b include a channel layer 111 and a barrier layer 112.

[0073] The drain wiring 104 and the source wiring 105 extend in the first direction across the gate wiring 103′ in a plan view and are arranged on both sides of the gate wiring 103′. Each of the drain wiring 104 and the source wiring 105 can be arranged, for example, parallel to the gate wiring 103′.

[0074] The first gate electrode 103a and the second gate electrode 103b are formed extending in the gate width direction from both sides of the gate wiring 103'. The first gate electrode 103a is disposed on the first element region 102a, and the second gate electrode 103b is disposed on the second element region 102b. The first gate electrode 103a and the second gate electrode 103b are connected by a connection wiring 131 provided between the first element region 102a and the second element region 102b. The connection wiring 131 is also connected to the gate wiring 103'.

[0075] The gate wiring 103′ is formed between the first element region 102a and the second element region 102b, buried in the interlayer insulating layer 117, and is connected to the connection wiring 131 by a through wiring formed to penetrate the interlayer insulating layer 117. The interlayer insulating layer 117 can be made of an insulating material such as SiO, SiN, AlO, or HfO.

[0076] The drain electrode 104′ and the source electrode 105′ are disposed with the first gate electrode 103a and the second gate electrode 103b interposed therebetween. The drain electrode 104′, the source electrode 105′, the first gate electrode 103a, and the second gate electrode 103b are formed to extend in the gate width direction.

[0077] In addition, in the second embodiment, a drain electrode 104' formed continuously and a source electrode 105' formed continuously are provided over the entire area of ​​the first gate electrode 103a and the second gate electrode 103b in the gate width direction.

[0078] In the second embodiment, a drain electrode 104' and a source electrode 105' are disposed above the gate wiring 103' and intersect with the gate wiring 103'.

[0079] For example, in each of the first element region 102a and the second element region 102b, a buffer layer 121 made of InAlAs is formed on a substrate 101 made of semi-insulating InP, and a channel layer 111 and a barrier layer 112 are formed on the buffer layer 121. The buffer layer 121 may have a thickness of, for example, 100 to 300 nm. Although not shown, the barrier layer 112 is doped with 1×10 Si as an impurity by well-known sheet doping.19 cm -3 A doped carrier supply layer called a δ-doped layer is formed.

[0080] An etching stop layer 113 is provided on the barrier layer 112, an ohmic cap layer 114 is formed on the etching stop layer 113, and a drain electrode 104' and a source electrode 105' are formed on the ohmic cap layer 114. The etching stop layer 113 can be made of a material that has high etching selectivity with respect to an etching solution used to etch the ohmic cap layer 114 to form the recess region 114a, which will be described later. The ohmic cap layer 114 can be made of a material that has high etching selectivity with respect to an etching solution used to etch the ohmic cap layer 114 to form the recess region 114a, for example. 19 ~2 x 10 19 cm -3 The semiconductor layer may be made of highly doped InGaAs.

[0081] The drain wiring 104, the source wiring 105, the drain electrode 104', and the source electrode 105' may be formed from a laminated structure of metals such as Ti, Pt, Au, Ni, and Mo.

[0082] 5A, 5B, and 5C, an insulating layer 115 is formed on the ohmic cap layer 114 between the drain electrode 104′ and the source electrode 105′ in the gate width direction. The insulating layer 115 has a gate opening 115a. The insulating layer 115 can be made of an insulating material such as SiO, SiN, AlO, or HfO.

[0083] Although not shown in FIGS. 5A, 5B, and 5C, a recess region 114a is formed in the ohmic cap layer 114 between the drain electrode 104' and the source electrode 105' in the gate width direction.

[0084] The first gate electrode 103 a and the second gate electrode 103 b are formed on the insulating layer 115, and a portion of the gate electrode 103 a is embedded in the recess region 114 a through the gate opening 115 a. The first gate electrode 103 a and the second gate electrode 103 b are formed from the gate opening 115 a to the etching stop layer 113 in the depth direction.

[0085] The gate wiring 103′, the first gate electrode 103a, and the second gate electrode 103b can be formed from a composite structure mainly of Ti, Pt, Au, Ni, and Mo. In order to achieve a short gate length while minimizing gate resistance, the gate wiring 103′, the first gate electrode 103a, and the second gate electrode 103b can be T-shaped, Y-shaped, or Γ-shaped, with the upper portion having a larger area than the lower portion in a plan view.

[0086] The first gate electrode 103a and the second gate electrode 103b are electrically isolated from the drain electrode 104' and the source electrode 105'.

[0087] In this example, there are three drain electrodes 104' and three source electrodes 105', but it is sufficient if there is only one of each. The number of drain electrodes 104' and the number of source electrodes 105' do not need to be the same. For example, in a plan view, they can be arranged from one end to the other in the gate length direction as follows: "drain electrode 104'" - "first gate electrode 103a and second gate electrode 103b" - "source electrode 105'" - "first gate electrode 103a and second gate electrode 103b" - "drain electrode 104'".

[0088] According to the second embodiment described above, the gate electrode, drain wiring, drain electrode, source wiring, and source electrode can be formed in the same wiring layer, and the wiring layer can be configured with two layers (two different layers). Furthermore, according to the second embodiment, two gate electrodes are extended in the gate width direction with the gate wiring at the center. With this configuration, in the second embodiment, the length of each gate electrode in the gate width direction can be approximately half that of a conventional multi-finger gate. As a result, an increase in gate resistance can also be suppressed in the second embodiment.

[0089] Next, a method for manufacturing a field effect transistor according to the second embodiment will be described with reference to FIGS. 6A to 6J.

[0090] First, on the substrate 101, a buffer layer 121, a channel layer 111, a barrier layer 112, a carrier supply layer (not shown), an etching stop layer 113, and an ohmic cap layer 114 are formed in this order.

[0091] For example, on a substrate 101, a buffer layer 121 made of InAlAs and having a thickness of 100 to 300 nm, a channel layer 111 made of InGaAs and having a thickness of 5 to 20 nm, a barrier layer 112 made of InAlAs and having a thickness of 5 to 20 nm, and a Si layer of 1×10 19 ~2 x 10 19 cm -3 The ohmic cap layer 114 made of InGaAs doped with 1×10 is then deposited by crystal growth using metal organic chemical vapor deposition, molecular beam epitaxy, or the like. The barrier layer 112 is doped with 1×10 Si as an impurity using well-known sheet doping. 19 cm -3 A doped carrier supply layer is formed. In addition, an etching stop layer 113 made of InP and having a thickness of 2 to 5 nm is formed between the barrier layer 112 and the ohmic cap layer 114.

[0092] Next, as shown in FIG. 6A , the first and second rectangular element regions 102 a and 102 b are formed adjacent to each other with a predetermined gap between them. Note that FIG. 6A shows a cross section taken along line aa′ in FIG. 5A . For example, a mask pattern (not shown) is formed using standard lithography techniques, and the ohmic cap layer 114, the etching stop layer 113, the barrier layer 112, the channel layer 111, and a portion of the buffer layer 121 in the thickness direction are etched using the formed mask pattern as a mask, thereby forming the first and second element regions 102 a and 102 b. For example, citric acid is used as an etchant for InGaAs and InAlAs, and a mixture of hydrochloric acid, phosphoric acid, and water is used as an etchant for InP.

[0093] In each of the first element region 102a and the second element region 102b, in order to avoid electrical contact with the electrodes formed on the side surfaces, side etching can be performed on the channel layer 111 to make it extend inward from the side surfaces (side walls).

[0094] Next, as shown in Fig. 6B, gate wiring 103' and terminal 107 are formed in a region not shown on buffer layer 121 in the region between first element region 102a and second element region 102b. Fig. 6B shows a cross section taken along line aa' in Fig. 5A.

[0095] Next, as shown in Fig. 6C, an interlayer insulating layer 117 is formed to cover the gate wiring 103'. Fig. 6C shows a cross section taken along line aa' in Fig. 5A. For example, the interlayer insulating layer 117 is formed by depositing SiO2, SiN, Al2O3, HfO2, or a combination of these by CVD, PVD, ALD, sputtering, or the like.

[0096] Next, as shown in Fig. 6D, known lithography and etching techniques are used to remove the interlayer insulating layer 117 from areas other than the area between the first element region 102a and the second element region 102b. Fig. 6D shows a cross section taken along line aa' in Fig. 5A. This removal can be performed by dry etching using an etching gas such as SF or C2F6, or wet etching using HF or the like.

[0097] Next, as shown in FIG. 6E, a drain electrode 104' is formed. Note that FIG. 6E shows a cross section taken along line aa' in FIG. 5A. At the same time, a source electrode 105', drain wiring 104, and source wiring 105 are formed in regions not shown. For example, a lift-off mask having openings where the electrodes and wiring will be formed is formed. Next, a metal film such as Ni, Ti, Pt, Au, or Mo, or a composite deposited film of these, is formed on top of the formed lift-off mask by electrolytic plating, electroless plating, vacuum deposition, sputtering, or the like. Thereafter, the lift-off mask is removed, thereby forming the above-mentioned electrodes and wiring.

[0098] Next, as shown in FIG. 6F, the interlayer insulating layer 117 in the area where the through-hole 106 is to be formed is patterned by lithography and etching to form a contact hole 117a. Note that FIG. 6F shows a cross section taken along line cc' in FIG. 5A. The contact hole 117a is formed in the region between the drain electrode 104' and the source electrode 105'. The etching for forming the contact hole 117a can be performed by dry etching using an etching gas such as SF or C2F6, or wet etching using HF or the like.

[0099] 6G, an insulating layer 115 is formed, a gate opening 115a is formed in the formed insulating layer 115, and a recess region 114a is formed. Note that FIG. 6G shows a partial cross section taken along line dd' in FIG. 5A.

[0100] For example, first, an insulating film is deposited by CVD, PVD, ALD, sputtering, or the like. The insulating film can typically be SiO, SiN, or a composite deposited film of these. Next, the formation regions of the first gate electrode 103a and the second gate electrode 103b are patterned by lithography and etching to form gate openings 115a and an insulating layer 115 so as to achieve the desired gate length. During this patterning and etching, the insulating film above the contact hole 117a is also removed in the same manner, so that the gate wiring 103 is electrically connected to the first gate electrode 103a and the second gate electrode 103b in the subsequent gate electrode formation process.

[0101] The insulating film can be etched by dry etching using etching gas such as C2F6 or SF6, or by wet etching using HF, etc. Thereafter, the resist mask used in the etching is removed using an organic solvent, etc.

[0102] The size of the gate electrode is the gate length L of the field effect transistor. g In order to determine the size of the gate electrode, it is necessary to form the gate opening 115a finely. g Since it is not related tog In order to reduce this, the gate wiring 103' can be made wider than the gate opening 115a.

[0103] Next, an etching solution (etchant) is poured through the gate opening 115a to etch the ohmic cap layer 114 directly below the gate opening 115a, thereby forming a recess region 114a. Note that Fig. 6H shows a cross section taken along line cc' in Fig. 5A after the recess region 114a has been formed.

[0104] Here, when forming the recess region 114a, if an effective etching process utilizing the battery effect or the like is aimed for, as shown in FIG. 6G, part or all of the insulating layer 115 on the source electrode and the drain electrode can be etched and removed to expose each electrode.

[0105] Next, as shown in Figures 6I and 6J, a first gate electrode 103a, a second gate electrode 103b, and a connection wiring 131 are formed. Figure 6I shows a cross section taken along line cc' in Figure 5A. Figure 6J shows a cross section taken along line dd' in Figure 5A.

[0106] For example, a lift-off mask having openings at locations where the first gate electrode 103 a, the second gate electrode 103 b, the connection wiring 131, and the terminal 107 are to be formed is formed. Next, a metal film of Ni, Ti, Pt, Au, Mo, or the like, or a composite deposited film of these metals is formed on the formed lift-off mask by electrolytic plating, electroless plating, vacuum deposition, sputtering, or the like. Thereafter, the lift-off mask is removed, thereby forming the first gate electrode 103 a, the second gate electrode 103 b, the connection wiring 131, and the terminal 107.

[0107] In the second embodiment, the gate wiring 103' and the connection wiring 131 can be designed to be relatively thick, so that the gate resistance can be reduced.

[0108] Third Embodiment Next, a field effect transistor according to a third embodiment of the present invention will be described with reference to FIG.

[0109] This field effect transistor includes a gate wiring 103 ′, a first gate electrode 103 a, a second gate electrode 103 b, a drain wiring 104, a source wiring 105, a drain electrode 104 ′ connected to the drain wiring 104 , and a source electrode 105 ′ connected to the source wiring 105 .

[0110] In the third embodiment, the gate wiring 103' is disposed above the drain electrode 104' and the source electrode 105' when viewed from the substrate (not shown) side. The other configurations are generally similar to those of the second embodiment described above, but in the third embodiment, the gate wiring 103', the first gate electrode 103a, the second gate electrode 103b, the drain electrode 104', and the source electrode 105' are disposed on one element region 102.

[0111] The gate wiring 103′ is disposed to extend in the gate length direction (the vertical direction on the paper surface of FIG. 7) in a plan view on the element region 102. The gate wiring 103′ is connected to a terminal 107. The element region 102 includes a channel layer 111 and a barrier layer 112.

[0112] The drain wiring 104 and the source wiring 105 extend in the first direction across the gate wiring 103′ in a plan view and are arranged on both sides of the gate wiring 103′. Each of the drain wiring 104 and the source wiring 105 can be arranged, for example, parallel to the gate wiring 103′.

[0113] The first gate electrode 103a and the second gate electrode 103b are formed extending in the gate width direction from both sides of the gate wiring 103'. In the third embodiment, the first gate electrode 103a and the second gate electrode 103b are formed integrally. Furthermore, a through wiring 106 is formed between the first gate electrode 103a and the second gate electrode 103b, and the through wiring 106 connects the first gate electrode 103a and the second gate electrode 103b to the gate wiring 103'.

[0114] The gate wiring 103′ is formed on an interconnection layer on which the first gate electrode 103 a, the second gate electrode 103 b, the drain electrode 104′, and the source electrode 105′ are formed, with an interlayer insulating layer (not shown) interposed therebetween. The interlayer insulating layer can be made of an insulating material such as SiO2, SiN, Al2O3, or HfO2.

[0115] The drain electrode 104′ and the source electrode 105′ are disposed with the first gate electrode 103a and the second gate electrode 103b interposed therebetween. The drain electrode 104′, the source electrode 105′, the first gate electrode 103a, and the second gate electrode 103b are formed to extend in the gate width direction.

[0116] In addition, in the third embodiment, a drain electrode 104' formed continuously and integrally and a source electrode 105' formed continuously and integrally are provided over the entire area of ​​the first gate electrode 103a and the second gate electrode 103b in the gate width direction.

[0117] In the third embodiment, a drain electrode 104' and a source electrode 105' are disposed below the gate wiring 103' and intersect with the gate wiring 103'.

[0118] In this example, there are three drain electrodes 104' and three source electrodes 105', but it is sufficient if there is only one of each. The number of drain electrodes 104' and the number of source electrodes 105' do not need to be the same. For example, in a plan view, they can be arranged from one end to the other in the gate length direction as follows: "drain electrode 104'" - "first gate electrode 103a and second gate electrode 103b" - "source electrode 105'" - "first gate electrode 103a and second gate electrode 103b" - "drain electrode 104'".

[0119] According to the third embodiment described above, the gate electrode, drain wiring, drain electrode, source wiring, and source electrode can be formed in the same wiring layer, allowing the wiring layer to be configured with two layers. Furthermore, according to the third embodiment, two gate electrodes are extended in the gate width direction with the gate wiring at the center. With this configuration, in the third embodiment, the length of each gate electrode in the gate width direction can be approximately half that of a conventional multi-finger gate. As a result, an increase in gate resistance can also be suppressed in the third embodiment.

[0120] Next, a method for manufacturing a field effect transistor according to the third embodiment will be described with reference to FIGS. 8A to 8G.

[0121] First, on the substrate 101, a buffer layer 121, a channel layer 111, a barrier layer 112, a carrier supply layer (not shown), an etching stop layer 113, and an ohmic cap layer 114 are formed in this order.

[0122] For example, on a substrate 101, a buffer layer 121 made of InAlAs and having a thickness of 100 to 300 nm, a channel layer 111 made of InGaAs and having a thickness of 5 to 20 nm, a barrier layer 112 made of InAlAs and having a thickness of 5 to 20 nm, and a Si layer of 1×10 19 ~2 x 10 19 cm -3 The ohmic cap layer 114 made of InGaAs doped with 1×10 is then deposited by crystal growth using metal organic chemical vapor deposition, molecular beam epitaxy, or the like. The barrier layer 112 is doped with 1×10 Si as an impurity using well-known sheet doping. 19 cm -3 A doped carrier supply layer is formed. In addition, an etching stop layer 113 made of InP and having a thickness of 2 to 5 nm is formed between the barrier layer 112 and the ohmic cap layer 114.

[0123] 8A , a rectangular parallelepiped element region 102 is formed. For example, a mask pattern (not shown) is formed by standard lithography technology, and the ohmic cap layer 114, the etching stop layer 113, the barrier layer 112, the channel layer 111, and a portion of the buffer layer 121 in the thickness direction are etched using the formed mask pattern as a mask, thereby forming the element region 102. For example, citric acid is used as an etchant for InGaAs or InAlAs, and a mixture of hydrochloric acid, phosphoric acid, and water is used as an etchant for InP.

[0124] In the element region 102, in order to avoid electrical contact with the electrodes formed on the side surfaces, side etching can be performed on the channel layer 111 to form a structure in which the channel layer 111 extends inward from the side surfaces (side walls).

[0125] Next, as shown in FIG. 8B , a drain electrode 104′, a source electrode 105′, a drain wiring 104, and a source wiring 105 are formed. For example, a lift-off mask having openings where each electrode and wiring will be formed is formed. Next, a metal film of Ni, Ti, Pt, Au, Mo, or the like, or a composite deposited film of these, is formed on top of the formed lift-off mask by electrolytic plating, electroless plating, vacuum deposition, sputtering, or the like. Thereafter, the lift-off mask is removed, thereby forming the above-mentioned electrodes and wiring.

[0126] 8C, an insulating layer 115 is formed, a gate opening 115a is formed in the formed insulating layer 115, and a recess region 114a is formed. Note that FIG. 8C shows a cross section taken along line aa' in FIG.

[0127] For example, first, an insulating film is deposited by CVD, PVD, ALD, sputtering, or the like. The insulating film can typically be SiO, SiN, or a composite deposited film of these. Next, the region where the gate electrode is to be formed is patterned by lithography and etching to form a gate opening 115a with the desired gate length, and then the insulating layer 115 is formed.

[0128] The insulating film can be etched by dry etching using etching gas such as C2F6 or SF6, or by wet etching using HF, etc. Thereafter, the resist mask used in the etching is removed using an organic solvent, etc.

[0129] The size of the gate electrode is the gate length L of the field effect transistor. g In order to determine the size of the gate electrode, it is necessary to form the gate opening 115a finely. g Since it is not related to g In order to reduce this, the gate wiring 103' can be made wider than the gate opening 115a.

[0130] Next, an etching solution (etchant) is poured through the gate opening 115a to etch the ohmic cap layer 114 directly below the gate opening 115a, thereby forming a recess region 114a.

[0131] Here, when forming the recess region 114a, if an effective etching process using the battery effect or the like is desired, part or all of the insulating layer 115 on the source electrode and the drain electrode can be etched to expose each electrode.

[0132] Next, as shown in Fig. 8D, a first gate electrode 103a and a second gate electrode 103b are formed in a region not shown in the figure. Fig. 8D shows a cross section taken along line aa' in Fig. 7.

[0133] For example, a lift-off mask having openings at positions where the first gate electrode 103 a and the second gate electrode 103 b are to be formed is formed. Next, a metal film of Ni, Ti, Pt, Au, Mo, or the like, or a composite deposited film of these metals is formed on the formed lift-off mask by electrolytic plating, electroless plating, vacuum deposition, sputtering, or the like. Thereafter, the lift-off mask is removed, thereby forming the first gate electrode 103 a and the second gate electrode 103 b.

[0134] Next, as shown in Fig. 8E, an interlayer insulating layer 117 is formed to cover the first gate electrode 103a, the drain electrode 104', the source electrode 105', and the second gate electrode 103b (not shown). For example, the interlayer insulating layer 117 is formed by depositing SiO2, Si3N4, or a combination of these by CVD, PVD, ALD, sputtering, or the like. Note that Fig. 8E shows a cross section taken along line aa' in Fig. 7.

[0135] Next, as shown in FIG. 8F, the interlayer insulating layer 117 is patterned using lithography and etching techniques to form a contact hole 117a. The contact hole 117a is formed in the region between the drain electrode 104' and the source electrode 105'. The etching for forming the contact hole 117a can be performed by dry etching using an etching gas such as SF or C2F6, or wet etching using HF or the like. Note that FIG. 8F shows a cross section taken along line bb' in FIG. 7.

[0136] 8G, the gate wiring 103' and the terminal 107 are formed in a region not shown on the interlayer insulating layer 117. Note that FIG. 8G shows a cross section taken along line bb' in FIG.

[0137] For example, a lift-off mask having openings at locations where the gate wiring 103′ and the terminal 107 are to be formed is formed. Next, a metal film of Ni, Ti, Pt, Au, Mo, or the like, or a composite deposited film of these metals is formed on top of the formed lift-off mask by electrolytic plating, electroless plating, vacuum deposition, sputtering, or the like. Thereafter, the lift-off mask is removed, thereby forming the gate wiring 103′ and the terminal 107.

[0138] According to the third embodiment, the region where the gate wiring is disposed in the first and second embodiments can be utilized as a channel, thereby enabling a higher driving current.

[0139] Fourth Embodiment Next, a field effect transistor according to a fourth embodiment of the present invention will be described with reference to FIG.

[0140] This field-effect transistor includes a first gate wiring 143a, a second gate wiring 143b, and a third gate wiring 143c, and a first gate electrode 103a, a second gate electrode 103b, a third gate electrode 103c, and a fourth gate electrode 103d. Each gate wiring extends in the gate length direction. The first gate wiring 143a, the second gate wiring 143b, and the third gate wiring 143c are connected to a terminal 107 located outside the element region 102. The gate electrodes are arranged in the gate width direction. In this example, five pairs of first gate electrodes 103a, second gate electrodes 103b, third gate electrodes 103c, and fourth gate electrodes 103d are provided.

[0141] The gate electrode also includes drain wiring 104 and source wiring 105 extending in the gate length direction. The gate wirings are arranged parallel to each other and are arranged between the drain wiring 104 and the source wiring 105.

[0142] A first gate electrode 103a is connected to the first gate wiring 143a on the drain wiring 104 side, and a second gate electrode 103b is connected to the first gate wiring 143a on the source wiring 105 side. Further, a second gate electrode 103b is connected to the second gate wiring 143b on the drain wiring 104 side, and a third gate electrode 103c is connected to the second gate wiring 143b on the source wiring 105 side. Further, a third gate electrode 103c is connected to the third gate wiring 143c on the drain wiring 104 side, and a fourth gate electrode 103d is connected to the third gate wiring 143c on the source wiring 105 side.

[0143] The gate electrode 104 also includes a first drain electrode 104a, a second drain electrode 104b, a third drain 104c, and a fourth drain 104d arranged in the gate width direction, and the first drain electrode 104a is connected to the drain wiring 104. In this example, three sets of the first drain electrode 104a, the second drain electrode 104b, the third drain 104c, and the fourth drain 104d are provided.

[0144] This field effect transistor also includes a first source electrode 105a, a second source electrode 105b, a third source electrode 105c, and a fourth source electrode 105d arranged in the gate width direction, and the first source electrode 105a is connected to a source wiring 105. In this example, three sets of the first source electrode 105a, the second source electrode 105b, the third source electrode 105c, and the fourth source electrode 105d are provided.

[0145] As described above, the gate wirings pass between the drain electrodes and source electrodes arranged in the gate width direction. The first gate electrode 103 a, the second gate electrode 103 b, the third gate electrode 103 c, and the fourth gate electrode 103 d are arranged between the array of drain electrodes and the array of source electrodes.

[0146] The gate wirings, gate electrodes, drain wirings 104, source wirings 105, drain electrodes, and source electrodes are formed in the same wiring layer. Adjacent drain electrodes in the gate width direction are connected by first connection wirings 141 formed in different wiring layers via through wirings 106. Adjacent source electrodes in the gate width direction are connected by second connection wirings 151 formed in different wiring layers via through wirings 106.

[0147] According to the fourth embodiment, the number of signal propagation paths from the gate electrode increases, making it possible to reduce the gate resistance, thereby enabling higher frequencies and lower noise.

[0148] Fifth Embodiment Next, a field-effect transistor according to a fifth embodiment of the present invention will be described with reference to FIGS. 10 and 11 . The fifth embodiment has two adjacent element regions 102 on a substrate, and a field-effect transistor 100 having a configuration similar to that of the first embodiment is formed in each of the element regions 102. For example, as shown in FIG. 10 , a field-effect transistor 100 can be formed in each of the element regions 102 arranged adjacent to each other in two locations aligned in the gate width direction. In this case, the drain wiring 104 can be shared between the two field-effect transistors 100 formed in the two element regions 102. Furthermore, the terminal 107 can be shared between the two field-effect transistors 100.

[0149] 11 , element regions 102 can be arranged adjacent to each other at four locations aligned in the gate width direction, and a field-effect transistor 100 can be formed in each element region 102. In this case, the two central field-effect transistors 100 can share a source wiring 105, and the two adjacent field-effect transistors 100 at the end and the center can share a drain wiring 104. Furthermore, the four field-effect transistors 100 can share a terminal 107. In this case, wiring for providing the drain wirings with the same potential and wiring for providing the source wirings with the same potential intersect. At this intersection, connection wiring is formed in a different wiring layer, similar to the other connection wirings.

[0150] By operating more field effect transistors 100 in parallel in this way, it is possible to achieve a higher driving current.

[0151] Sixth Embodiment Next, a field effect transistor according to a sixth embodiment of the present invention will be described with reference to FIGS. 12 and 13. In the sixth embodiment, as shown in FIG. 12, there are element regions 102 arranged at the four vertices of a rectangle on a substrate. The four element regions 102 are arranged in a lattice pattern. A field effect transistor 100 having a configuration similar to that of the first embodiment described above is formed in each element region 102.

[0152] In the lattice arrangement of the four element regions 102, the field effect transistors 100 facing each other in the gate width direction can share the drain wiring 104. In addition, all the field effect transistors 100 can share the terminal 107.

[0153] Also, as shown in FIG. 13, 16 element regions can be arranged in a lattice, and a field effect transistor 100 having the same configuration as that of the first embodiment can be formed in each element region.

[0154] By operating more field effect transistors 100 in parallel in this way, it is possible to achieve a higher driving current.

[0155] As described above, according to the present invention, two gate electrodes are extended in the gate width direction around the gate wiring. gs / L gd Engineering knowledge can be applied directly, and gate resistance can be reduced compared to conventional structures.

[0156] It should be noted that the present invention is not limited to the embodiments described above, and it is clear that many modifications and combinations can be made by a person having ordinary knowledge in the art within the technical concept of the present invention.

[0157] 101...substrate, 102...element region, 103...gate wiring, 103a...first gate electrode, 103b...second gate electrode, 104...drain wiring, 104a...first drain electrode, 104b...second drain electrode, 105...source wiring, 105a...first source electrode, 105b...second source electrode, 106...through wiring, 111...channel layer, 112...barrier layer, 113...etching stop layer, 114...ohmic cap layer, 114a...recess region, 115...insulating layer, 115a...gate opening, 116...interlayer insulating layer, 141...first connecting wiring, 151...second connecting wiring.

Claims

1. An electric field effect transistor comprising: an element region including a channel layer made of a compound semiconductor and a barrier layer made of a compound semiconductor, formed on a substrate; a gate wiring disposed on the element region and extending across the element region in the gate length direction in a plan view; a drain wiring and a source wiring disposed on both sides of the element region in the gate length direction with the gate wiring interposed therebetween in a plan view; a first gate electrode and a second gate electrode extending in the gate width direction from both sides of the gate wiring on the element region; and a drain electrode and a source electrode disposed with the first gate electrode and the second gate electrode interposed therebetween and extending in the gate width direction on the element region, wherein the drain electrode is connected to the drain wiring, and the source electrode is connected to the source wiring.

2. The electric field effect transistor according to claim 1, wherein the drain electrode and the source electrode include a first drain electrode and a first source electrode disposed with the first gate electrode interposed therebetween, and a second drain electrode and a second source electrode disposed with the second gate electrode interposed therebetween, the first drain electrode and the second drain electrode are connected by a first connection wiring, the first source electrode and the second source electrode are connected by a second connection wiring, the first drain electrode is connected to the drain wiring, and the second source electrode is connected to the source wiring.

3. The electric field effect transistor according to claim 2, wherein the first connection wiring is disposed above the gate wiring and intersects the gate wiring, and the second connection wiring is disposed above the gate wiring and intersects the gate wiring.

4. The electric field effect transistor according to claim 2, wherein the first connection wiring is disposed below the gate wiring and intersects the gate wiring, and the second connection wiring is disposed below the gate wiring and intersects the gate wiring.

5. The electric field effect transistor according to claim 4, wherein the first connection wiring and the second connection wiring are disposed on the element region via an insulating layer.

6. The field-effect transistor according to any one of claims 1 to 5, comprising: the element regions arranged adjacent to each other at two locations on the substrate; a drain wiring of the element regions arranged adjacent to each other being common and arranged between the element regions arranged adjacent to each other; and a gate terminal to which gate wirings of each of the element regions arranged adjacent to each other are commonly connected.

7. The field-effect transistor according to claim 6, comprising: the element regions arranged adjacent to each other at four locations on the substrate.

8. The field-effect transistor according to any one of claims 1 to 5, comprising: the element regions arranged at locations that are the four vertices of a rectangle on the substrate.

Images