Display panel and display apparatus

Abstract

A display panel and a display apparatus, which relate to the technical field of display. The display panel comprises a driving circuit layer (FA). The driving circuit layer (FA) comprises a top gate trace (GT3L) electrically connected to a gate electrode of a threshold compensation transistor (T2), and a first source-drain metal layer (SD1) having a first conductive structure (ML1), wherein at least one side of the top gate trace (GT3L) is provided with a first protruding portion (SA1), and the first protruding portion (SA1) at least partially overlaps the first conductive structure (ML1); and / or in a row direction, at least one side of the first conductive structure (ML1) is provided with a second protruding portion (SA2), and the second protruding portion (SA2) at least partially overlaps the top gate trace (GT3L).

Description

Display panel and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In recent years, with the advancement of smart display technology, organic light emitting diodes (OLEDs) have become a hot topic in display research. As display panels become thinner and bezels narrower, the demands for display quality are becoming increasingly stringent. During the display process, the threshold compensation transistors of display panels are susceptible to positive or negative threshold voltage bias, resulting in large fluctuations in the organic light emitting layer (EL) current and degraded image quality.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field.

[0004] Summary of the Invention

[0005] The purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art and provide a display panel and a display device to improve the image quality of the display panel.

[0006] According to one aspect of the present disclosure, a display panel is provided, comprising a base substrate, a driving circuit layer, and a pixel layer stacked in sequence; the pixel layer is provided with sub-pixels; the driving circuit layer is provided with a pixel driving circuit for driving the sub-pixels;

[0007] The pixel driving circuit includes a threshold compensation transistor, a storage capacitor, and a driving transistor for generating a driving current; a source of the threshold compensation transistor and a drain of the driving transistor are electrically connected to a second node; the threshold compensation transistor is a metal oxide transistor, and is used to compensate for a threshold voltage of the driving transistor in response to a threshold compensation control signal;

[0008] The driving circuit layer includes a metal oxide semiconductor layer, a top gate layer, an interlayer dielectric layer and a first source-drain metal layer stacked in sequence;

[0009] The top gate layer includes a top gate trace extending in a row direction, the top gate trace being electrically connected to the gate of the threshold compensation transistor; the first source-drain metal layer includes a first conductive structure, the first conductive structure being electrically connected to the drain of the threshold compensation transistor through a first via, and being electrically connected to the first electrode plate of the storage capacitor through a second via; the first via and the second via are located on both sides of the top gate trace;

[0010] At least one side of the top gate wiring has a first protrusion, and the first protrusion is at least partially overlapped with the first conductive structure; and / or, along the row direction, at least one side of the first conductive structure has a second protrusion, and the second protrusion is at least partially overlapped with the top gate wiring.

[0011] In one embodiment of the present disclosure, the top gate wiring includes a wiring body, the wiring body has a first size along the column direction; the first conductive structure has a second size along the row direction;

[0012] The top gate trace further includes a first protrusion located on one side of the trace body, and a dimension of the first protrusion along the column direction is a third dimension, or the top gate trace further includes two first protrusions located on both sides of the trace body, and a sum of dimensions of the two first protrusions along the column direction is the third dimension;

[0013] The first protrusion is rectangular; and a dimension of the first protrusion along the row direction is not smaller than the second dimension.

[0014] In one embodiment of the present disclosure, the orthographic projection of the side of the first protrusion away from the wiring body on the substrate is a first projection line;

[0015] Along the row direction, the first projection line crosses the orthographic projection of the first conductive structure on the substrate.

[0016] In one embodiment of the present disclosure, the third size is equal to the first size.

[0017] In one embodiment of the present disclosure, the top gate trace includes a trace body; the trace body has a first size along a column direction; the first conductive structure has a second size along a row direction;

[0018] The top gate trace further includes a first protrusion located on one side of the trace body, and the maximum dimension of the first protrusion along the column direction is a fourth dimension; or the top gate trace further includes two first protrusions located on both sides of the trace body, and the sum of the maximum dimensions of the two first protrusions along the column direction is the fourth dimension;

[0019] The first protrusion is trapezoidal, and any one of the first protrusions includes a first long side and a first short side extending along the row direction, and the first short side is arranged on the side of the first long side away from the wiring body; the size of any one of the first long sides is not less than the second size.

[0020] In one embodiment of the present disclosure, the orthographic projection of the first short side of the first protrusion on the base substrate is a second projection line;

[0021] Along the row direction, the second projection line crosses the orthographic projection of the first conductive structure on the substrate.

[0022] In one embodiment of the present disclosure, the fourth size is equal to the first size.

[0023] In one embodiment of the present disclosure, the size of the first short side is half of the size of the first long side.

[0024] In one embodiment of the present disclosure, the first conductive structure includes a conductive structure body, and further includes a second protrusion located on one side of the conductive structure body or two second protrusions located on both sides of the conductive structure body;

[0025] The size of the top gate wiring along the column direction is a first size; the second protrusion is rectangular, and the size of the second protrusion along the column direction is not less than the first size.

[0026] In one embodiment of the present disclosure, the orthographic projection of the side of the second protrusion away from the conductive structure body on the substrate is a third projection line;

[0027] Along the column direction, the third projection line crosses the orthographic projection of the top gate trace on the substrate.

[0028] In one embodiment of the present disclosure, the first conductive structure includes a conductive structure body, and further includes a second protrusion located on one side of the conductive structure body or two second protrusions located on both sides of the conductive structure body;

[0029] The second protrusion is trapezoidal; any one of the second protrusions includes a second long side and a second short side extending along the column direction, and the second short side is arranged on a side of the second long side away from the conductive structure body;

[0030] The size of the top gate wiring along the column direction is a first size; the size of the second long side is not less than the first size.

[0031] In one embodiment of the present disclosure, the orthographic projection of the second short side of the second protrusion on the base substrate is a fourth projection line;

[0032] Along the column direction, the fourth projection line crosses the orthographic projection of the top gate trace on the substrate.

[0033] In one embodiment of the present disclosure, the top gate trace includes a trace body and a first protrusion located at least on one side of the trace body, and the first conductive structure includes a conductive structure body and a second protrusion located at least on one side of the conductive structure body.

[0034] In one embodiment of the present disclosure, the first protrusion is rectangular or trapezoidal, and the second protrusion is rectangular or trapezoidal.

[0035] According to another aspect of the present disclosure, a display device is provided, including the above-mentioned display panel.

[0036] The display panel provided by the present disclosure optimizes the capacitance of the first node by increasing the overlapping area between the first source-drain metal layer and the top gate layer of the threshold compensation transistor, thereby reducing the sensitivity of the voltage of the first node to the change in the threshold voltage of the threshold compensation transistor, improving the display performance of the display panel and the quality of the displayed image.

[0037] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0039] FIG1 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure.

[0040] FIG2 is an equivalent circuit diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0041] 3 is a schematic diagram of a stacked structure of a polysilicon semiconductor layer, a first gate layer, a second gate layer, a metal oxide semiconductor layer, a top gate layer, and a first source-drain metal layer of a pixel driving circuit in one embodiment of the present disclosure.

[0042] FIG4 is a schematic diagram of a partial structure of a metal light-shielding layer in one embodiment of the present disclosure.

[0043] FIG5 is a schematic diagram of a partial structure of a polysilicon semiconductor layer in one embodiment of the present disclosure.

[0044] FIG6 is a schematic diagram of a partial structure of a first gate layer in one embodiment of the present disclosure.

[0045] FIG7 is a schematic diagram of a partial structure of a second gate layer in one embodiment of the present disclosure.

[0046] FIG8 is a schematic diagram of a partial structure of a metal oxide semiconductor layer in one embodiment of the present disclosure.

[0047] FIG9 is a schematic diagram of the partial structure of a metal oxide semiconductor layer, a top gate layer, and a first source / drain metal layer in one embodiment of the present disclosure.

[0048] FIG10 is a schematic diagram of the partial structure of a metal oxide semiconductor layer, a top gate layer, and a first source-drain metal layer in one embodiment of the present disclosure.

[0049] FIG11 is a schematic diagram of the partial structure of a metal oxide semiconductor layer, a top gate layer, and a first source-drain metal layer in one embodiment of the present disclosure.

[0050] FIG12 is a schematic diagram of the partial structure of a metal oxide semiconductor layer, a top gate layer, and a first source-drain metal layer in one embodiment of the present disclosure.

[0051] FIG13 is a schematic diagram of the partial structure of a metal oxide semiconductor layer, a top gate layer, and a first source-drain metal layer in one embodiment of the present disclosure.

[0052] FIG14 is a schematic diagram of the partial structure of a metal oxide semiconductor layer, a top gate layer, and a first source-drain metal layer in one embodiment of the present disclosure.

[0053] FIG15 is a schematic diagram of the partial structure of a metal oxide semiconductor layer, a top gate layer, and a first source-drain metal layer in one embodiment of the present disclosure.

[0054] FIG16 is a schematic diagram of the partial structure of a metal oxide semiconductor layer, a top gate layer, and a first source-drain metal layer in one embodiment of the present disclosure.

[0055] FIG17 is a schematic diagram of the partial structure of a metal oxide semiconductor layer, a top gate layer, and a first source-drain metal layer in one embodiment of the present disclosure.

[0056] Explanation of the reference numerals: ANL, pixel electrode layer; Barr, inorganic barrier layer; BP, base substrate; Buff1, first buffer layer; Buff2, second buffer layer; COML, common electrode layer; CP1, first electrode plate; Cst, storage capacitor; Data, data voltage; EL, organic light-emitting functional layer; EM, light-emitting control signal; FA, driving circuit layer; FB, pixel layer; GI1, first gate insulating layer; GI2, second gate insulating layer; GI3, top gate insulating layer; GN1, threshold compensation signal; GT1, first gate layer; GT2, second gate layer; GT3, top gate layer; ILD, interlayer dielectric layer; LS, metal light-shielding layer; N1, first node; N2, second node; N3, third Node; N4, fourth node; PDL, pixel definition layer; PLN1, first planarization layer; PLN2, second planarization layer; PS, support pillar layer; SBP, support substrate; SD1, first source and drain metal layer; SD2, second source and drain metal layer; SEMI1, polysilicon semiconductor layer; SEMI2, metal oxide semiconductor layer; T1, capacitor reset transistor; T2, threshold compensation transistor; T3, drive transistor; T4, data write transistor; T5, first light-emitting control transistor; T6, second light-emitting control transistor; T7, pixel electrode reset transistor; TFE, thin film encapsulation layer; VDD, drive voltage; Vinit1, first initialization voltage; GN2, capacitor reset signal; GP, data Scan signal; Vinit2, second initialization voltage; RP, pixel electrode reset signal; Vth, threshold compensation voltage; GT3L, top gate line; ML1, first conductive structure; VH1, first via hole; VH2, second via hole; SA1, first protrusion; SA2, second protrusion; LSP, metal light shielding portion; LSL, connecting line; T3Act, channel region of driving transistor T3; PL1, first polysilicon strip; PL2, second polysilicon strip; PL3, third polysilicon strip; GPL, data scan line; CP2, second electrode plate; GN2L, capacitor reset line; CP2G, notch; T2Act, channel region of threshold compensation transistor T2; OL1, first metal oxide portion; O L2, second metal oxide portion; ML2, second conductive structure; VH3, third via; VH4, fourth via; VH5, fifth via; GT3LB, trace body; S1, first dimension; S2, second dimension; H1, third dimension; H11, first subdimension; H12, second subdimension; H2, fourth dimension; ML1B, conductive structure body; W1, fifth dimension; W11, third subdimension; W12, fourth subdimension; W2, sixth dimension; DH, row direction; DV, column direction; L1, first projection line; L2, second projection line; L3, third projection line; L4, fourth projection line; 100, trace body edge line; 200, first boundary line; 300, conductive structure body edge line;400, Second Boundary Line. ; DETAILED DESCRIPTION

[0057] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0058] The terms "a", "an", "the", "said" and "at least one side" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0059] A transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), through which current can flow. The channel region is the area where current primarily flows.

[0060] The first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" may be interchanged.

[0061] In the present disclosure, when describing the overlapping arrangement of structure A and structure B, it means that structure A and structure B are arranged in different film layers, and the orthographic projection of structure A on the substrate overlaps with the orthographic projection of structure B on the substrate.

[0062] In the present disclosure, the structural layer E is located on the side of the structural layer F away from the base substrate. This can be understood as the structural layer E being formed on the side of the structural layer F away from the base substrate. When the structural layer F is a patterned structure, part of the structure layer E may also be located at the same physical height as the structural layer E or lower than the physical height of the structural layer E, where the base substrate serves as a height reference.

[0063] Embodiments of the present disclosure provide a display panel. Figure 1 illustrates a cross-sectional structural diagram of a display panel according to an embodiment of the present disclosure. Referring to Figure 1 , the display panel includes a base substrate BP, a drive circuit layer FA, and a pixel layer FB, which are stacked in sequence. The pixel layer is provided with sub-pixels, and the drive circuit layer is provided with pixel drive circuits for driving the sub-pixels.

[0064] The substrate substrate BP may be a substrate substrate BP of an inorganic material, or a substrate substrate BP of an organic material. For example, in one embodiment of the present disclosure, the material of the substrate substrate BP may be a glass material such as soda-lime glass, quartz glass, sapphire glass, or may be a metal material such as stainless steel, aluminum, nickel, etc. In another embodiment of the present disclosure, the material of the substrate substrate BP may be polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl phenol (PVP), polyether sulfone (PES), polyimide, polyamide, polyacetal, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN) or a combination thereof. In another embodiment of the present disclosure, the substrate substrate BP may also be a flexible substrate substrate BP, for example, the material of the substrate substrate BP may be polyimide (PI). The substrate BP can also be a composite of multiple layers of materials. For example, in one embodiment of the present disclosure, the substrate BP can include a bottom film layer (Bottom Film), a pressure-sensitive adhesive layer, a first polyimide layer and a second polyimide layer stacked in sequence.

[0065] For example, in Figure 1, the base substrate BP is made of polyimide, enabling the display panel to be flexible. Referring to Figure 1 , the display panel can be initially formed on a supporting substrate SBP, which can then be peeled off after fabrication. This allows the supporting substrate SBP to provide support for the display panel during the manufacturing process.

[0066] The driving circuit layer FA is provided with a pixel driving circuit for driving sub-pixels. In the driving circuit layer FA, any pixel driving circuit may include a transistor and a storage capacitor. Referring to Figures 1 and 2, the driving circuit layer is provided with a polycrystalline silicon semiconductor layer SEMI1 and a metal oxide semiconductor layer SEMI2, so that the transistors in the driving circuit layer include at least metal oxide transistors and polycrystalline silicon transistors (such as low-temperature polycrystalline silicon transistors). Furthermore, these transistors may be thin film transistors. Of course, in other embodiments of the present disclosure, the polycrystalline silicon transistor may also be an amorphous silicon transistor; accordingly, the polycrystalline silicon semiconductor layer SEMI1 of the driving circuit layer may be replaced by an amorphous silicon semiconductor layer.

[0067] In the present disclosure, the polysilicon transistor can be a top-gate thin film transistor, a bottom-gate thin film transistor or a dual-gate thin film transistor, whichever is more effective in controlling the transistor. The metal oxide transistor is a dual-gate thin film transistor, that is, the channel region of the transistor is sandwiched between the top gate (the gate on the side away from the substrate) and the bottom gate (the gate on the side close to the substrate); in this way, the bottom gate can block the light from the side of the substrate, preventing the light from irradiating the channel region of the transistor and causing abnormal operation of the transistor. Of course, the metal oxide transistor can also be a top-gate thin film transistor or a bottom-gate thin film transistor.

[0068] In some embodiments of the present disclosure, the gate of the polysilicon transistor can be disposed in the same layer as a gate of a metal oxide transistor. For example, the gate of the polysilicon transistor and the bottom gate of the metal oxide transistor are disposed in the same gate layer. In other embodiments, the gate of the polysilicon transistor and the top gate and bottom gate of the metal oxide transistor can be disposed in different gate layers, respectively.

[0069] As an example, referring to FIG1 , the driving circuit layer includes a polysilicon semiconductor layer SEMI1, a first gate insulating layer GI1, a first gate layer GT1, a second buffer layer Buff2, a second gate layer GT2, a second gate insulating layer GI2, a metal oxide semiconductor layer SEMI2, a top gate insulating layer GI3, and a top gate layer GT3, which are sequentially stacked on one side of a substrate BP. The polysilicon semiconductor layer SEMI1 is provided with an active region of a polysilicon transistor, and the first gate layer GT1 is provided with a gate of the polysilicon transistor. The metal oxide semiconductor layer SEMI2 is provided with an active region of a metal oxide transistor; the second gate layer GT2 is provided with a bottom gate of the metal oxide transistor; and the top gate layer GT3 is provided with a top gate of the metal oxide transistor. In the present disclosure, the active region of a transistor includes a channel region of the transistor and a source and drain located on either side of the channel region; the channel region maintains semiconductor properties, and the source and drain are conductive.

[0070] In an embodiment of the present disclosure, the driving circuit layer further includes a source-drain metal layer, which is located on the side of each gate layer and semiconductor layer away from the substrate BP. In the present disclosure, the source-drain metal layer can be one layer, two layers, or three layers. In the example of Figure 1 , the source-drain metal layer is two layers, including a first source-drain metal layer SD1 and a second source-drain metal layer SD2 stacked in layers; an interlayer dielectric layer ILD is provided on the surface of the first source-drain metal layer SD1 close to the substrate BP, a first planarization layer PLN1 is provided between the first source-drain metal layer SD1 and the second source-drain metal layer SD2, and a second planarization layer PLN2 is provided on the side of the second source-drain metal layer SD2 away from the substrate BP.

[0071] Optionally, the drive circuit layer FA may further include a first buffer layer Buff1 disposed between the base substrate BP and the semiconductor layer, with the semiconductor layer and gate layer located on a side of the first buffer layer Buff1 away from the base substrate BP. The first buffer layer Buff1 may be made of an inorganic insulating material such as silicon oxide or silicon nitride. The first buffer layer Buff1 may be a single inorganic material layer or a plurality of stacked inorganic material layers.

[0072] Optionally, the driving circuit layer FA may further include a metal light-shielding layer LS located between the first buffer layer Buff1 and the base substrate BP, and the metal light-shielding layer LS may shield at least part of the channel region of the transistor. Furthermore, in some embodiments, the metal light-shielding layer LS may be electrically connected to the source and drain metal layers through vias, so that the metal light-shielding layer LS may perform signal transmission, signal shielding or other functions as needed. For example, the metal light-shielding layer LS may be loaded with a common electrode voltage so that the metal light-shielding layer LS can achieve the function of signal shielding. For another example, a portion of the metal light-shielding layer LS is patterned into a conductive wire so that the conductive wire located in the metal light-shielding layer LS can be used to transmit signals, such as transmitting touch signals.

[0073] Optionally, an inorganic barrier layer Barr may be further provided between the metal light-shielding layer LS and the first buffer layer Buff1 to prevent the material in the base substrate BP from penetrating into the driving circuit layer.

[0074] The pixel layer FB is provided with light-emitting elements distributed in an array, and each light-emitting element emits light under the control of the pixel driving circuit. These light-emitting elements can serve as sub-pixels in the embodiment of the present disclosure. In the present disclosure, the light-emitting element can be an organic light-emitting diode (OLED), a micro light-emitting diode (Micro LED), a quantum dot-organic light-emitting diode (QD-OLED), a quantum dot light-emitting diode (QLED) or other types of light-emitting elements. For example, referring to Figure 2, in one embodiment of the present disclosure, the light-emitting element is an organic light-emitting diode (OLED), and the display panel is an OLED display panel. As follows, taking the light-emitting element as an organic light-emitting diode as an example, a feasible structure of the pixel layer is exemplarily introduced.

[0075] In this example, the pixel layer FB can be arranged on the side of the driving circuit layer FA away from the base substrate BP, which may include a pixel electrode layer ANL, a pixel definition layer PDL, a support column layer PS, an organic light-emitting functional layer EL and a common electrode layer COML stacked in sequence. The pixel electrode layer ANL has a plurality of pixel electrodes in the display area of ​​the display panel; the pixel definition layer PDL has a plurality of through pixel openings arranged in a one-to-one correspondence with the plurality of pixel electrodes in the display area, and any pixel opening exposes at least a portion of the corresponding pixel electrode. The support column layer PS includes a plurality of support columns in the display area, and the support columns are located on the surface of the pixel definition layer PDL away from the base substrate BP so as to support the fine metal mask (FMM) during the evaporation process. The organic light-emitting functional layer EL at least covers the pixel electrode exposed by the pixel definition layer PDL. The organic light-emitting functional layer EL may include an organic electroluminescent material layer, and may include one or more of a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer and an electron injection layer. Each film layer of the organic light-emitting functional layer EL can be prepared by an evaporation process, and a fine metal mask or an open mask can be used to define the pattern of each film layer during evaporation. The common electrode layer COML can cover the organic light-emitting functional layer EL in the display area. In this way, the pixel electrode, the common electrode layer COML and the organic light-emitting functional layer EL located between the pixel electrode and the common electrode layer COML form an organic electroluminescent diode, and any organic electroluminescent diode can serve as a sub-pixel of the display panel.

[0076] Optionally, the display panel may further include a thin-film encapsulation layer (TFE). This thin-film encapsulation layer (TFE) is disposed on the surface of the pixel layer FB facing away from the base substrate BP and may include alternating inorganic and organic encapsulation layers. The inorganic encapsulation layer effectively blocks external moisture and oxygen, preventing moisture and oxygen from invading the organic light-emitting functional layer EL and causing material degradation. Optionally, the edge of the inorganic encapsulation layer may be located in the peripheral region. The organic encapsulation layer is located between two adjacent inorganic encapsulation layers to achieve planarization and reduce stress between the inorganic encapsulation layers. The edge of the organic encapsulation layer may be located between the edge of the display area and the edge of the inorganic encapsulation layer. Exemplarily, the thin-film encapsulation layer (TFE) includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer, sequentially stacked on the side of the pixel layer FB facing away from the base substrate BP. The first inorganic encapsulation layer covers the display area and extends outside the barrier wall; the organic encapsulation layer covers the display area and extends inside the barrier wall; and the second inorganic encapsulation layer covers the organic encapsulation layer and extends outside the barrier wall. Outside the barrier wall, the second inorganic encapsulation layer contacts the first inorganic encapsulation layer. In this way, the organic encapsulation layer is encapsulated by the first and second inorganic encapsulation layers, balancing the stress of the first and second inorganic encapsulation layers. The first and second inorganic encapsulation layers encapsulate the organic encapsulation layer, isolating the organic encapsulation layer from contact with water and oxygen.

[0077] In the display panel provided herein, a pixel driving circuit includes a storage capacitor Cst and multiple transistors, some of which are polysilicon transistors and others are metal oxide transistors. The pixel driving circuit may include a core module for providing a driving current. The core module may include a storage capacitor Cst, a threshold compensation transistor T2, and a driving transistor T3; wherein the drain of the threshold compensation transistor T2, the gate of the driving transistor T3, and the first electrode plate CP1 of the storage capacitor Cst are electrically connected to a first node N1, and the source of the threshold compensation transistor T2 and the drain of the driving transistor T3 are electrically connected to a second node N2. The threshold compensation transistor T2 is a metal oxide transistor and is used to compensate for the threshold voltage of the driving transistor T3 in response to a threshold compensation signal GN1. The driving transistor T3 is a polysilicon transistor and can generate a driving current under the control of the first node N1.

[0078] At the initial moment of the data writing phase of the pixel driving circuit, the first node N1 has been pre-reset (to a negative voltage), causing the driving transistor T3 to be turned on. After entering the data writing phase, the data voltage Data is written to the first node N1. The threshold compensation transistor T2 is turned on under the control of the threshold compensation signal GN1, electrically connecting the first node N1 to the second node N2. At this time, the third node N3 can be charged to the first node N1 through the driving transistor T3 and the threshold compensation transistor T2, so that the voltage of the first node N1 is pulled up to the point that the driving transistor T3 is turned off. The voltage difference between the voltage of the first node N1 and the voltage of the third node N3 is the threshold voltage of the driving transistor T3. In this way, after the data writing phase, the voltage of the first node N1 is related to the threshold voltage of the driving transistor T3 and the data voltage Data, overcoming the problem of uneven threshold voltage of the driving transistor T3 due to process reasons. Of course, in the display panel of the present disclosure, in addition to the core module mentioned above, the pixel driving circuit also needs to include other transistors to realize functions such as resetting the pixel driving circuit, writing the data voltage Data, and controlling the light emission of sub-pixels.

[0079] FIG2 provides an example of a pixel driving circuit. In addition to the core module described above, this exemplary pixel driving circuit also includes a capacitor reset transistor T1, a data write transistor T4, a first light emission control transistor T5, a second light emission control transistor T6, and a pixel electrode reset transistor T7. It is understood that in other examples of the present disclosure, the pixel driving circuit may further include other transistors or a storage capacitor Cst, or may have fewer transistors, subject to the core module described above.

[0080] As follows, the structure, principle and effect of the display panel according to the embodiment of the present disclosure are further introduced and illustrated by taking the pixel driving circuit illustrated in FIG2 as an example.

[0081] In the pixel driving circuit illustrated in FIG2 , the first electrode plate CP1 of the storage capacitor Cst is electrically connected to the first node N1, and the second electrode plate of the storage capacitor Cst is used to load the driving voltage VDD. In this way, the voltage loaded on the second electrode plate of the storage capacitor Cst is stable. In some other embodiments of the present disclosure, the second electrode plate of the storage capacitor Cst can be loaded with other power supply voltages, such as the same common voltage as the common electrode layer. Of course, in other embodiments of the present disclosure, the voltage of the second electrode plate of the storage capacitor may not be constant, for example, the drain of the capacitor reset transistor T1 and the drain of the data write transistor T4 are electrically connected to the second electrode plate of the storage capacitor Cst; the capacitor reset transistor is used to reset the voltage of the second electrode plate of the storage capacitor Cst, and the data write transistor is used to load the data voltage to the second electrode plate of the storage capacitor; through coupling, the voltage of the first node can be adjusted as the voltage of the second electrode plate of the storage capacitor is adjusted.

[0082] In the pixel driving circuit illustrated in FIG2 , the pixel driving circuit further includes a first emission control transistor T5 and a second emission control transistor T6. The source of the first emission control transistor T5 is applied with a driving voltage VDD. The drain of the first emission control transistor T5 is electrically connected to a third node N3. The source of the second emission control transistor T6 is electrically connected to a second node N2, and the drain of the second emission control transistor T6 is electrically connected to a fourth node N4, which is also electrically connected to the pixel electrode of the subpixel. The gates of the first emission control transistor T5 and the second emission control transistor T6 are applied with an emission control signal EM. When the first emission control transistor T5 and the second emission control transistor T6 are turned on in response to the emission control signal EM, the drive current generated by the driving transistor T3 can flow to the subpixel, thereby driving the subpixel to emit light. Furthermore, the first emission control transistor T5 and the second emission control transistor T6 are polysilicon transistors. Of course, in other embodiments of the present disclosure, the pixel driving circuit may include only one of the first emission control transistor T5 and the second emission control transistor T6.

[0083] In the pixel driving circuit shown in FIG2 , the pixel driving circuit further includes a capacitor reset transistor T1 and a data write transistor T4. The source of the capacitor reset transistor T1 is used to apply a first initialization voltage Vinit1, and the drain of the capacitor reset transistor T1 is electrically connected to the second node N2. The capacitor reset transistor T1 is configured to apply the first initialization voltage Vinit1 to the first node N1 via T2 in response to a capacitor reset signal GN2, thereby resetting the first node N1. In this example, the capacitor reset transistor T1 is a polysilicon transistor. The data write transistor T4 is a polysilicon transistor, and the source of the data write transistor T4 is configured to apply a data voltage Data. The drain of the data write transistor T4 is electrically connected to the third node N3. The data write transistor T4 is configured to apply the data voltage Data to the third node N3 in response to a data scan signal GP.

[0084] In the pixel driving circuit illustrated in FIG2 , the pixel driving circuit further includes a pixel electrode reset transistor T7, which is a polysilicon transistor. The source of the pixel electrode reset transistor T7 is used to apply the second initialization voltage Vinit2. The drain of the pixel electrode reset transistor T7 is electrically connected to the fourth node N4. The pixel electrode reset transistor T7 is used to apply the second initialization voltage Vinit2 to the fourth node N4 in response to the pixel electrode reset signal RP, thereby resetting the pixel electrode of the sub-pixel. Of course, in other embodiments of the present disclosure, the pixel driving circuit may not include the pixel electrode reset transistor T7, or the pixel electrode reset transistor T7 may be a metal oxide thin film transistor.

[0085] In the display panel disclosed in the present invention, the pixel driving circuit can reduce the leakage of the first node N1 by setting the threshold compensation transistor T2 to a metal oxide transistor, thereby improving the voltage holding capability of the pixel driving circuit, reducing the risk of flickering of the display panel under low-frequency driving, and reducing the power consumption of the display panel. However, in actual tests, it was found that during the display process of some display panels, the threshold compensation transistor T2 is easily affected by the negative or positive bias of the threshold compensation voltage Vth, resulting in large fluctuations in the current of the organic light-emitting functional layer EL and deterioration of the display image quality of the display panel. The present invention optimizes the capacitance of the first node N1, thereby reducing the sensitivity of the voltage of the first node N1 to the change in the threshold voltage of the threshold compensation transistor T2, thereby improving the display quality of the display panel.

[0086] As shown in Figures 3 and 9 to 17, the top gate layer GT3 includes a top gate trace GT3L extending along the row direction DH. The top gate trace GT3L serves as the top gate of the threshold compensation transistor T2. The first source-drain metal layer SD1 includes a first conductive structure ML1. The first conductive structure ML1 is electrically connected to the drain of the threshold compensation transistor T2 via a first via VH1 and to the first electrode plate CP1 of the storage capacitor via a second via VH2. The first via VH1 and the second via VH2 are located on either side of the top gate trace GT3L. In other words, the first conductive structure ML1 can serve as part of the first node N1, electrically connecting the drain of the threshold compensation transistor T2 to the first electrode plate CP1 of the storage capacitor. Along the column direction DV, the orthographic projection of the first conductive structure ML1 on the substrate crosses the orthographic projection of the top gate trace GT3L on the substrate. In other words, a portion of the first conductive structure ML1 is located on one side of the top gate trace GT3L, and a portion of the first conductive structure ML1 is located on the other side of the top gate trace GT3L.

[0087] The top gate trace GT3L has a first protrusion SA1 on at least one side, and the first protrusion SA1 at least partially overlaps with the first conductive structure ML1; and / or, along the row direction DH, the first conductive structure ML1 has a second protrusion SA2 on at least one side, and the second protrusion SA2 at least partially overlaps with the top gate trace GT3L. In other words, the first protrusion SA1 can be provided on the top gate trace GT3L to increase the overlapping area between the top gate trace GT3L and the first conductive structure ML1. The second protrusion SA2 can also be provided on the first conductive structure ML1 to increase the overlapping area between the first conductive structure ML1 and the top gate trace GT3L. It is also possible to simultaneously provide the first protrusion SA1 on the top gate trace GT3L and the second protrusion SA2 on the first conductive structure ML1 to increase the overlapping area between the first conductive structure ML1 and the top gate trace GT3L.

[0088] The display panel provided by the present embodiment optimizes the capacitance of the first node N1 by increasing the overlapping area between the first conductive structure ML1 and the top gate trace GT3L, thereby reducing the sensitivity of the voltage of the first node N1 to the change in the threshold voltage of the threshold compensation transistor T2, thereby improving the display performance of the display panel.

[0089] FIG4 shows a schematic diagram of the partial structure of the metal light-shielding layer LS of the display panel of the example disclosed in the present invention. Referring to FIG4 , the metal light-shielding layer LS has a metal light-shielding portion LSP and a connecting trace LSL. The metal light-shielding portions LSP adjacent to each other in the same row and in the same column can be connected by the connecting trace LSL. In this way, the metal light-shielding layer LS is in a grid shape, which can play a role in shielding external signals and preventing signals outside the display panel from affecting the normal display of the display panel. The metal light-shielding portion LSP needs to have a large size to shield the light irradiating the channel region of the driving transistor T3 to ensure the stability of the characteristics of the driving transistor T3.

[0090] Figure 5 shows a partial structural diagram of the polysilicon semiconductor layer SEMI1 of a display panel according to an example of the present disclosure. As shown in Figures 3 and 5, the polysilicon semiconductor layer SEMI1 has polysilicon patterns corresponding to each pixel driver circuit. In the partial structural diagram shown in Figure 5, this polysilicon pattern forms the channel region T3Act of the driver transistor T3, which has semiconductor characteristics, as well as first, second, and third polysilicon strips PL1, PL2, and PL3, which are conductive. The first and second polysilicon strips PL1 and PL2 are located on either side of the channel region T3Act; the third polysilicon strip PL3 is located on one side of the channel region (not shown) of T1. The first polysilicon strip PL1 serves as part of the third node N3 and also serves as the drain of the data write transistor T4, the source of the driver transistor T3, and the drain of the first light emission control transistor T5. The second polysilicon strip PL2 serves as part of the second node N2 and also serves as the drain of the driver transistor T3 and the drain of the capacitor reset transistor T1.

[0091] Referring to Figure 5 , the channel region T3Act of the driving transistor T3 is bent so that the channel region T3Act of the driving transistor T3 has a longer length. Furthermore, the orthographic projection of the channel region T3Act of the driving transistor T3 on the metal light shielding layer LS can be completely located within the metal light shielding portion LSP. In this way, the metal light shielding portion LSP can shield the channel region T3Act of the driving transistor T3 from light. Figure 6 shows a schematic diagram of the partial structure of the first gate layer GT1 of the display panel of the example disclosed herein. Referring to Figure 6 and Figure 3 , the first gate layer GT1 is provided with a first electrode plate CP1 of the storage capacitor Cst and a data scan line GPL for carrying data scan signals GP and extending substantially along the row direction DH. The first electrode plate CP1 of the storage capacitor Cst completely covers the channel region T3Act of the driving transistor T3; that is, the orthographic projection of the channel region T3Act of the driving transistor T3 on the first gate layer GT1 is located within the range of the first electrode plate CP1 of the storage capacitor Cst. In this way, the first electrode plate CP1 of the storage capacitor Cst can serve as the gate of the driving transistor T3.

[0092] Figure 7 shows a schematic diagram of the partial structure of the second gate layer GT2 of the display panel of the example of the present disclosure. The second gate layer GT2 is provided with a second electrode plate CP2 of the storage capacitor Cst corresponding to each pixel driving circuit, and a capacitor reset line GN2L for loading the capacitor reset signal GN2 and extending substantially along the row direction DH. The second electrode plate CP2 overlaps with the first electrode plate CP1 of the storage capacitor Cst to form the storage capacitor Cst. The second electrode plate CP2 of the storage capacitor Cst has a notch CP2G, which exposes a portion of the first electrode plate CP1 of the storage capacitor Cst so that the first electrode plate CP1 of the storage capacitor Cst can be connected to the first source and drain metal layer SD1 through a via located in the notch CP2G.

[0093] Figure 8 illustrates a partial structural diagram of the metal oxide semiconductor layer SEMI2 of a display panel according to an example of the present disclosure. As shown in Figure 8 , the metal oxide semiconductor layer SEMI2 includes a metal oxide pattern corresponding to each pixel driver circuit. The orthographic projections of the metal oxide pattern of the pixel driver circuit and the polysilicon pattern on the substrate BP do not overlap. The metal oxide pattern includes a channel region T2Act of a threshold compensation transistor T2 that maintains semiconductor characteristics, and a first metal oxide portion OL1 and a second metal oxide portion OL2 that are conductive. The first metal oxide portion OL1 is electrically connected to the first conductive structure ML1 via a first via VH1 and serves as part of the first node N1. Referring to Figure 3 , the first source / drain metal layer SD1 also includes a second conductive structure ML2. The second conductive structure ML2 is electrically connected to the third polysilicon strip PL3 via a third via VH3, the second conductive structure ML2 is electrically connected to the second metal oxide portion OL2 via a fourth via VH4, and the second conductive structure ML2 is electrically connected to the second polysilicon strip PL2 of the polysilicon semiconductor layer SEMI1 via a fifth via VH5. Thus, the second conductive structure ML2 is electrically connected to the drain of the capacitor reset transistor T1 , the source of the threshold compensation transistor T2 , and the drain of the driving transistor T3 to serve as a portion of the second node N2 .

[0094] In one embodiment of the present disclosure, Figure 9 shows a schematic diagram of the partial stacking structure of the metal oxide semiconductor layer SEMI2, the top gate layer GT3, and the first source and drain metal layer SD1. The top gate layer GT3 includes a top gate trace GT3L extending substantially along the row direction DH. The top gate trace GT3L includes a trace body GT3LB and a first protrusion SA1 located on one side of the trace body GT3LB. The trace body GT3LB has a first dimension S1 along the column direction DV; the first conductive structure ML1 has a second dimension S2 along the row direction DH. The first protrusion SA1 is rectangular, with a third dimension H1 along the column direction DV and a dimension no less than the second dimension S2 along the row direction DH. As shown in Figure 9, the first protrusion SA1 is located on the side of the trace body GT3LB away from the first via VH1. In one example, the first protrusion SA1 can also be located on the side of the trace body GT3LB closer to the first via VH1. Exemplarily, in the top gate layer GT3, the distance between the side of the first protrusion SA1 away from the trace body GT3LB and the metal structure disposed on the same layer is not less than 2 μm. It is understood that the distance between the side of the first protrusion SA1 away from the trace body GT3LB and the first via VH1 or the second via VH2 is not less than 2 μm.

[0095] In the present disclosure, referring to FIG. 9 , the top gate trace GT3L has a trace body edge line 100 , and an extension line of a portion of the trace body edge line 100 close to the first protrusion SA1 is a first boundary line 200 between the trace body GT3LB and the first protrusion SA1 .

[0096] In one example, the orthographic projection of the side of the first protrusion SA1 away from the trace body GT3LB on the base substrate BP is a first projection line L1. Along the row direction DH, the first projection line L1 can cross the orthographic projection of the first conductive structure ML1 on the base substrate BP. In this way, while maintaining the same third dimension H1, the overlapping area between the first protrusion SA1 and the first conductive structure ML1 can be maximized, thereby optimizing the display performance of the display panel. Furthermore, the third dimension H1 is equal to the first dimension S1.

[0097] In one embodiment of the present disclosure, as shown in FIG10 , the top gate trace GT3L includes a trace body GT3LB and two first protrusions SA1 located on either side of the trace body GT3LB. The trace body GT3LB has a first dimension S1 along the column direction DV; the first conductive structure ML1 has a second dimension S2 along the row direction DH. The two first protrusions SA1 are rectangular; the sum of the dimensions of the two first protrusions SA1 along the column direction DV is a third dimension H1, and the dimension of any one of the first protrusions SA1 along the row direction DH is no less than the second dimension S2. That is, as shown in FIG10 , the third dimension H1 is the sum of the first sub-dimension H11 and the second sub-dimension H12. Exemplarily, in the top gate layer GT3, the distance between the side of the first protrusion SA1 away from the trace body GT3LB and the metal structure disposed on the same layer is no less than 2 μm.

[0098] In one example, referring to FIG10 , the orthographic projection of the side of either of the two first protrusions SA1 away from the trace body GT3LB on the substrate BP is a first projection line L1. Along the row direction DH, the first projection line L1 crosses the orthographic projection of the first conductive structure ML1 on the substrate BP. Thus, first protrusions SA1 are provided on both sides of the top gate trace GT3L, and given the same third dimension H1, both first protrusions SA1 maximize their overlap area with the first conductive structure ML1, thereby improving the image quality of the display panel. Furthermore, the third dimension H1 is equal to the first dimension S1.

[0099] In one embodiment of the present disclosure, as shown in FIG11 , the top gate trace GT3L includes a trace body GT3LB and a first protrusion SA1 located on one side of the trace body GT3LB. The trace body GT3LB has a first dimension S1 along the column direction DV; the first conductive structure ML1 has a second dimension S2 along the row direction DH. The first protrusion SA1 is trapezoidal, and the maximum dimension of the first protrusion SA1 along the column direction DV is a fourth dimension H2. The first protrusion SA1 includes a first long side and a first short side extending along the row direction DH. The first short side is located on the side of the first long side away from the trace body GT3LB. The dimension of the first long side is not less than the second dimension S2.

[0100] In one example, the orthographic projection of the first short side of the first protrusion SA1 on the base substrate BP is the second projection line L2. Along the row direction DH, the second projection line L2 crosses the orthographic projection of the first conductive structure ML1 on the base substrate BP. Thus, the overlapping portion of the first protrusion SA1 and the first conductive structure ML1 remains a rectangular structure, but the area in which the first protrusion SA1 is disposed in the top gate layer GT3 is reduced. Exemplarily, in the top gate layer GT3, the distance between the first short side and the metal structure disposed on the same layer is no less than 2 μm; that is, the distance between the first short side and the first via VH1 or the second via VH2 is no less than 2 μm.

[0101] In one example, the fourth size H2 is equal to the first size S1. Furthermore, the size of the first short side is half of the size of the first long side.

[0102] In one embodiment of the present disclosure, the top gate trace GT3L includes a trace body GT3LB and two first protrusions SA1 located on both sides of the trace body GT3LB. The dimension of the trace body GT3LB along the column direction DV is a first dimension S1; the dimension of the first conductive structure ML1 along the row direction DH is a second dimension S2. The two first protrusions SA1 are trapezoidal, and the sum of the maximum dimensions of the two first protrusions SA1 along the column direction DV is a fourth dimension H2. Any one of the first protrusions SA1 includes a first long side and a first short side extending along the row direction DH, and the first short side is arranged on the side of the first long side away from the trace body GT3LB; the dimension of any one of the first long sides is not less than the second dimension S2. Exemplarily, in the top gate layer GT3, the distance between the two first short sides and the metal structure arranged on the same layer is greater than 2μm.

[0103] Exemplarily, the two first protrusions SA1 may also have different shapes. For example, the first protrusion SA1 on the side of the wiring body GT3LB close to the first via VH1 may be set to a rectangle, and the first protrusion SA1 on the side of the wiring body GT3LB away from the first via VH1 may be set to a trapezoid.

[0104] In one example, the orthographic projection of the first short side of either of the two first protrusions SA1 onto the base substrate BP is a second projection line L2. Along the row direction DH, the second projection line L2 crosses the orthographic projection of the first conductive structure ML1 onto the base substrate BP. Thus, under the same fourth dimension H2, the first protrusions SA1 on both sides of the top gate trace GT3L maximize their overlap area with the first conductive structure ML1. In one example, the fourth dimension H2 is equal to the first dimension S1. Furthermore, the dimension of the first short side is half the dimension of the first long side.

[0105] It can be understood that the first protrusion SA1 can be set on one side or both sides of the top gate trace GT3L. The first protrusion SA1 can be rectangular, trapezoidal or other shapes, and is not limited to the shapes and combinations described in the above embodiments.

[0106] In one embodiment of the present disclosure, the first conductive structure ML1 includes a conductive structure body ML1B and a second protrusion SA2 located on one side of the conductive structure body ML1B. The top gate trace GT3L has a first size S1 along the column direction DV. The second protrusion SA2 is rectangular, has a fifth size W1 along the row direction DH, and has a size no less than the first size S1 along the column direction DV. Exemplarily, the second protrusion SA2 can be located on a side of the conductive structure body ML1B close to the second conductive structure ML2, with the side of the second protrusion SA2 away from the conductive structure body ML1B spaced no less than 2 μm from the second conductive structure ML2. Exemplarily, the second protrusion SA2 can also be located on a side of the conductive structure body ML1B away from the second conductive structure ML2.

[0107] In the present disclosure, referring to FIG. 12 , the first conductive structure ML1 has a conductive structure body edge line 300 , and an extension line of a portion of the conductive structure body edge line 300 close to the second protrusion SA2 is a second boundary line 400 between the first conductive structure ML1 and the second protrusion SA2 .

[0108] In one example, the orthographic projection of the side of the second protrusion SA2 away from the conductive structure body ML1B on the base substrate BP is a third projection line L3. Along the column direction DV, the third projection line L3 crosses the orthographic projection of the top gate trace GT3L on the base substrate BP. Thus, while maintaining the same fifth dimension W1, the overlapping area between the second protrusion SA2 and the top gate trace GT3L is maximized, thereby improving the image quality of the display panel.

[0109] In one embodiment of the present disclosure, as shown in FIG12 , the first conductive structure ML1 includes a conductive structure body ML1B and two second protrusions SA2 located on either side of the conductive structure body ML1B. The top gate trace GT3L has a first dimension S1 along the column direction DV, and the conductive structure body ML1B has a second dimension S2 along the row direction. The two second protrusions SA2 are rectangular, and the sum of their dimensions along the row direction is a fifth dimension W1. The dimension of the second protrusions SA2 along the column direction DV is no less than the first dimension S1. In other words, referring to FIG12 , the fifth dimension W1 is the sum of the third sub-dimension W11 and the fourth sub-dimension W12. Exemplarily, the second protrusion SA2, located on the side of the conductive structure body ML1B near the second conductive structure ML2, is spaced no less than 2 μm from the side of the conductive structure body ML1B away from the second conductive structure ML2.

[0110] In one example, the orthographic projection of the side of either of the two second protrusions SA2, away from the conductive structure body ML1B, on the base substrate BP is a third projection line L3. Along the column direction DV, the third projection line L3 crosses the orthographic projection of the top gate trace GT3L on the base substrate BP. Thus, while maintaining the same fifth dimension W1, the overlapping area between the two second protrusions SA2 and the top gate trace GT3L is maximized, thereby improving the image quality of the display panel.

[0111] In one embodiment of the present disclosure, as shown in FIG13 , the first conductive structure ML1 includes a conductive structure body ML1B and a second protrusion SA2 located on one side of the conductive structure body ML1B. The top gate trace GT3L has a first dimension S1 along the column direction DV. The second protrusion SA2 is trapezoidal, with a maximum dimension W2 along the row direction DH. The second protrusion SA2 includes a second long side and a second short side extending along the column direction DV, with the second short side disposed on a side of the second long side away from the conductive structure body. The dimension of the second long side is not less than the first dimension S1. Exemplarily, referring to FIG13 , the second protrusion SA2 may also be disposed on a side of the conductive structure body ML1B away from the second conductive structure ML2. Exemplarily, the second protrusion SA2 may be disposed on a side of the conductive structure body ML1B closer to the second conductive structure ML2, with the second short side of the second protrusion SA2 and the second conductive structure ML2 spaced at least 2 μm apart.

[0112] In one example, referring to FIG. 13 , the orthographic projection of the second short side of the second protrusion SA2 on the substrate BP is a fourth projection line L4. Along the column direction DV, the fourth projection line L4 crosses the orthographic projection of the top gate trace GT3L on the substrate BP. Thus, the overlapping portion of the second protrusion SA2 and the top gate trace still forms a rectangular structure, but the area of ​​the second protrusion SA2 in the first source / drain metal layer is reduced.

[0113] In one embodiment of the present disclosure, the first conductive structure ML1 includes a conductive structure body ML1B and two second protrusions SA2 located on either side of the conductive structure body ML1B. The top gate trace GT3L has a first dimension S1 along the column direction DV. The two second protrusions SA2 are trapezoidal, and the sum of their maximum dimensions along the row direction DH is a sixth dimension W2. Each of the second protrusions SA2 includes a second long side and a second short side extending along the column direction DV, with the second short side located on a side of the second long side away from the conductive structure body. The second long side is no less than the first dimension S1. Exemplarily, the second short side of the second protrusion SA2 located on the side of the conductive structure body ML1B closer to the second conductive structure ML2 is spaced no less than 2 μm from the second conductive structure ML2.

[0114] In one example, the orthographic projection of the second short side of either of the two second protrusions SA2 on the base substrate BP is a fourth projection line L4. Along the column direction DV, the fourth projection line L4 crosses the orthographic projection of the top gate trace GT3L on the base substrate BP. In this way, both second protrusions SA2 achieve a maximum overlap area with the top gate trace GT3L. In one example, the two second protrusions SA2 can be rectangular and trapezoidal, respectively.

[0115] In one example, as shown in FIG14 , the orthographic projection of the second short side of any one of the two second protrusions SA2 on the base substrate BP is a fourth projection line L4, and the fourth projection line L4 falls within the orthographic projection of the top gate trace GT3L on the base substrate BP. In other words, the fourth projection line L4 does not cross the orthographic projection of the top gate trace GT3L on the base substrate BP.

[0116] It is understandable that the second protrusion SA2 may be provided on one side or both sides of the first conductive structure ML1 , and the second protrusion SA2 may be rectangular, trapezoidal or in other shapes, and is not limited to the description and combination of the above embodiments.

[0117] In one embodiment of the present disclosure, as shown in Figures 15 to 17, the top gate trace GT3L includes a trace body GT3LB and a first protrusion SA1 located at least on one side of the trace body GT3LB, and the first conductive structure ML1 includes a conductive structure body ML1B and a second protrusion SA2 located at least on one side of the conductive structure body ML1B. Furthermore, the first protrusion SA1 is rectangular or trapezoidal, and the second protrusion SA2 is rectangular or trapezoidal. That is, the first protrusion SA1 is provided on the trace body GT3LB and the second protrusion SA2 is provided on the conductive structure body ML1B at the same time. The first protrusion SA1 can be provided on one side or on both sides, and the shape of the first protrusion SA1 can be rectangular, trapezoidal, or other shapes; the second protrusion SA2 can be provided on one side or on both sides, and the shape of the second protrusion SA2 can be rectangular, trapezoidal, or other shapes. Exemplarily, as shown in FIG15 , a trapezoidal first protrusion SA1 is provided on the side of the trace body GT3LB away from the first via VH1, and at the same time, a trapezoidal second protrusion SA2 is provided on both sides of the conductive structure body ML1B. Exemplarily, as shown in FIG16 , a trapezoidal first protrusion SA1 is provided on the side of the trace body GT3LB away from the first via VH1, and at the same time, a rectangular second protrusion SA2 is provided on both sides of the conductive structure body ML1B. Exemplarily, as shown in FIG17 , a rectangular first protrusion SA1 is provided on the side of the trace body GT3LB away from the first via VH1, and at the same time, a trapezoidal second protrusion SA2 is provided on the side of the conductive structure body ML1B away from the second conductive structure ML2. It will be understood that FIG15-FIG17 illustrate a combination of some of the first protrusion SA1 and the second protrusion SA2, but are not limited to the above combination. In this way, by simultaneously providing protruding structures on the wiring body GT3LB of the top gate wiring GT3L and the conductive structure body ML1B of the first conductive structure ML1, the overlapping area between the top gate wiring GT3L and the first conductive structure ML1 is further increased, thereby further improving the picture quality displayed by the display panel.

[0118] The present disclosure also provides a display device comprising any of the display panels described in the display panel embodiments above. The display device may be a smartphone screen, a smartwatch screen, or another type of display device. Because the display device comprises any of the display panels described in the display panel embodiments above, it exhibits the same beneficial effects, and the present disclosure will not elaborate further here.

[0119] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A display panel comprising a base substrate, a driving circuit layer, and a pixel layer stacked in sequence; the pixel layer being provided with sub-pixels; and the driving circuit layer being provided with a pixel driving circuit for driving the sub-pixels; The pixel driving circuit includes a threshold compensation transistor, a storage capacitor, and a driving transistor for generating a driving current; a source of the threshold compensation transistor and a drain of the driving transistor are electrically connected to a second node; the threshold compensation transistor is a metal oxide transistor, and is used to compensate for a threshold voltage of the driving transistor in response to a threshold compensation control signal; The driving circuit layer includes a metal oxide semiconductor layer, a top gate layer, an interlayer dielectric layer and a first source-drain metal layer stacked in sequence; The top gate layer includes a top gate trace extending in a row direction, the top gate trace being electrically connected to the gate of the threshold compensation transistor; the first source-drain metal layer includes a first conductive structure, the first conductive structure being electrically connected to the drain of the threshold compensation transistor through a first via, and being electrically connected to the first electrode plate of the storage capacitor through a second via; the first via and the second via are located on both sides of the top gate trace; At least one side of the top gate wiring has a first protrusion, and the first protrusion is at least partially overlapped with the first conductive structure; and / or, along the row direction, at least one side of the first conductive structure has a second protrusion, and the second protrusion is at least partially overlapped with the top gate wiring.

2. The display panel according to claim 1, wherein The top gate wiring includes a wiring body, the wiring body has a first size along the column direction; the first conductive structure has a second size along the row direction; The top gate trace further includes a first protrusion located on one side of the trace body, and a dimension of the first protrusion along the column direction is a third dimension, or the top gate trace further includes two first protrusions located on both sides of the trace body, and a sum of dimensions of the two first protrusions along the column direction is the third dimension; The first protrusion is rectangular; and a dimension of the first protrusion along the row direction is not smaller than the second dimension.

3. The display panel according to claim 2, wherein: The orthographic projection of the side of the first protrusion away from the wiring body on the substrate is a first projection line; Along the row direction, the first projection line crosses the orthographic projection of the first conductive structure on the substrate.

4. The display panel according to claim 2, wherein: The third size is equal to the first size.

5. The display panel according to claim 1, wherein: The top gate trace comprises a trace body; the trace body has a first size along the column direction; the first conductive structure has a second size along the row direction; The top gate trace further includes a first protrusion located on one side of the trace body, and the maximum dimension of the first protrusion along the column direction is a fourth dimension; or the top gate trace further includes two first protrusions located on both sides of the trace body, and the sum of the maximum dimensions of the two first protrusions along the column direction is the fourth dimension; The first protrusion is trapezoidal, and any one of the first protrusions includes a first long side and a first short side extending along the row direction, and the first short side is arranged on the side of the first long side away from the wiring body; the size of any one of the first long sides is not less than the second size. The display panel according to claim 5 , wherein: The orthographic projection of the first short side of the first protrusion on the base substrate is a second projection line; Along the row direction, the second projection line crosses the orthographic projection of the first conductive structure on the substrate.

7. The display panel according to claim 5, wherein: The fourth size is equal to the first size.

8. The display panel according to claim 5, wherein: The size of the first short side is half of the size of the first long side.

9. The display panel according to claim 1, wherein: The first conductive structure includes a conductive structure body, and further includes a second protrusion located on one side of the conductive structure body or two second protrusions located on both sides of the conductive structure body; The size of the top gate wiring along the column direction is a first size; the second protrusion is rectangular, and the size of the second protrusion along the column direction is not less than the first size.

10. The display panel according to claim 9, wherein: The orthographic projection of the side of the second protrusion away from the conductive structure body on the substrate is a third projection line; Along the column direction, the third projection line crosses the orthographic projection of the top gate trace on the substrate.

11. The display panel according to claim 1, wherein: The first conductive structure includes a conductive structure body, and further includes a second protrusion located on one side of the conductive structure body or two second protrusions located on both sides of the conductive structure body; The second protrusion is trapezoidal; any one of the second protrusions includes a second long side and a second short side extending along the column direction, and the second short side is arranged on a side of the second long side away from the conductive structure body; The size of the top gate wiring along the column direction is a first size; the size of the second long side is not less than the first size.

12. The display panel according to claim 11, wherein: The orthographic projection of the second short side of the second protrusion on the base substrate is a fourth projection line; Along the column direction, the fourth projection line crosses the orthographic projection of the top gate trace on the substrate.

13. The display panel according to claim 1, wherein: The top gate trace includes a trace body and a first protrusion located at least on one side of the trace body, and the first conductive structure includes a conductive structure body and a second protrusion located at least on one side of the conductive structure body.

14. The display panel according to claim 13, wherein: The first protrusion is rectangular or trapezoidal, and the second protrusion is rectangular or trapezoidal.

15. A display device comprising the display panel according to any one of claims 1 to 14.

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