Disconnection protection circuit and sensor

Abstract

The present invention relates to a disconnection protection circuit and a sensor. The disconnection protection circuit is used for protecting a device under test, and comprises a reverse inhibition drive circuit, a first reverse isolation circuit, and a second reverse isolation circuit. The reverse inhibition drive circuit outputs an inhibition drive signal when a power end or a ground end is disconnected. The first reverse isolation circuit blocks a current path from a high-side drive branch to a chip output end on the basis of the inhibition drive signal. The second reverse isolation circuit blocks a current path from a low-side drive branch to the chip output end on the basis of the inhibition drive signal. The sensor comprises the disconnection protection circuit. In this way, when the power end or the ground end is disconnected, the electrostatic current flowing to the chip output end is blocked to achieve a high-impedance state at the chip output end, and then the potential of the chip output end is determined by a pull-up resistor or a pull-down resistor. Compared with existing technical solutions of using charge pump circuits or other types of switching power supplies, the circuit of the present invention has high structural reliability, eliminates the effect of high-frequency interference, and has low costs.

Description

A line break protection circuit and sensor Technical Field

[0001] The present invention relates to the field of sensors, and in particular to a line break protection circuit and a sensor. Background Art

[0002] To ensure vehicle and personal safety, some automotive chips are required to report a power or ground line disconnection to the ECU (Electronic Control Unit). For sensors with analog outputs, fault alarms are typically implemented by connecting a pull-up or pull-down resistor to the output. When a pull-down resistor is connected to the output, the OUT terminal is pulled down to a low potential when the DUT (Device Under Test) power or ground line is disconnected. When a pull-up resistor is connected to the output, the OUT terminal is pulled up to a high potential when the DUT power or ground line is disconnected. Simply put, when the DUT power or ground line is disconnected, the OUT terminal must maintain a high impedance state, and the OUT terminal potential is determined by the external pull-up / pull-down resistor.

[0003] However, in actual circuit applications, the output stage transistors of the output op amp at the OUT terminal have parasitic diodes. If the power or ground line is disconnected, even if the output transistor channel at the OUT terminal is cut off, the DUT's quiescent current can still flow into or out of the OUT terminal through the parasitic diodes of the output stage transistors. This quiescent current flows through the external resistor, generating a voltage drop. Consequently, if the power line is disconnected, the OUT terminal cannot be pulled up to a high potential by the external pull-up resistor, as shown in Figure 1. Alternatively, if the ground line is disconnected, the OUT terminal cannot be pulled down to a low potential by the external pull-down resistor, as shown in Figure 2.

[0004] To address the aforementioned issues, a related art approach involves inserting a pair of back-to-back isolated NMOS transistors at the OUT terminal, with the gates of these transistors connected to and driven by a charge pump circuit. When the DUT supply voltage is sufficient, the charge pump activates, driving the gate potential of the back-to-back isolated NMOS transistors above the supply voltage, fully turning on the back-to-back isolated NMOS transistors. When the power or ground wires are disconnected, the charge pump shuts down, blocking the channels of the back-to-back isolated NMOS transistors. Simultaneously, the corresponding back-to-back parasitic diodes prevent the quiescent current output by the DUT from flowing through the parasitic diode branches, achieving a high-impedance state at the OUT terminal. However, the charge pump circuit structure employed in this solution is complex and expensive. Furthermore, the charge pump generates a voltage higher than the supply voltage, potentially exceeding the rated withstand voltage for some transistors or capacitors within the system circuit. This poses a reliability risk, particularly for automotive products that meet the high reliability requirements. Furthermore, the charge pump is a switching power supply, and during switching, it injects noise into the power supply, ground, and DUT substrate. This can introduce high-frequency interference to high-precision sensors, thereby impacting their performance. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a line break protection circuit and a sensor, which can solve the line break protection problem without using a charge pump or other types of switching power supplies, while reducing costs and improving reliability.

[0006] The present invention provides a technical solution to the above-mentioned technical problem as follows: a line break protection circuit for protecting a device under test, wherein the device under test includes a power supply terminal, a ground terminal, a high-side drive branch connected to the power supply terminal, a low-side drive branch connected to the ground terminal, and a chip output terminal connected between the high-side drive branch and the low-side drive branch, wherein the line break protection circuit includes:

[0007] A reverse suppression drive circuit for outputting a suppression drive signal when the power supply terminal or the ground terminal is disconnected;

[0008] a first reverse isolation circuit, connected to the reverse inhibition drive circuit and connected between the high-side drive branch and the chip output terminal, for blocking a current path from the high-side drive branch to the chip output terminal according to the inhibition drive signal;

[0009] A second reverse isolation circuit is connected to the reverse inhibition drive circuit and is connected between the low-side drive branch and the chip output end, and is used to block the current path from the low-side drive branch to the chip output end according to the inhibition drive signal.

[0010] On the basis of the above technical solution, the present invention can also be improved as follows.

[0011] Furthermore, the first reverse isolation circuit includes a first discharge path and a first reverse inhibition tube; wherein, the first discharge path connects the reverse inhibition drive circuit and the first reverse inhibition tube, and is used to generate a first discharge current signal according to the inhibition drive signal to block the first reverse inhibition tube from being turned on; the first reverse inhibition tube is connected in series with the high-side drive branch, and is used to block the current path from the high-side drive branch to the chip output end according to the inhibition drive signal and the first discharge current signal.

[0012] Furthermore, the first reverse suppression tube includes a first PMOS tube having a first parasitic diode; the first discharge path includes a first resistor; the high-side drive branch includes a second PMOS tube having a second parasitic diode;

[0013] The gate of the first PMOS transistor is connected to the reverse suppression drive circuit, the drain is connected to the second PMOS transistor, and the source is connected to the chip output terminal; the anode of the first parasitic diode is connected to the drain of the first PMOS transistor, and the cathode is connected to the source of the first PMOS transistor;

[0014] One end of the first resistor is connected between the reverse suppression driving circuit and the gate of the first PMOS transistor, and the other end is connected between the source of the first PMOS transistor and the chip output end.

[0015] Furthermore, the second reverse isolation circuit includes a second discharge path and a second reverse inhibition tube; wherein, the second discharge path connects the reverse inhibition drive circuit and the second reverse inhibition tube, and is used to generate a second discharge current signal according to the inhibition drive signal to block the conduction of the second reverse inhibition tube; the second reverse inhibition tube is connected in series with the low-side drive branch, and is used to block the current path from the low-side drive branch to the chip output end according to the inhibition drive signal and the second discharge current signal.

[0016] Furthermore, the second reverse suppression tube includes a first NMOS tube having a third parasitic diode; the second discharge path includes a second resistor; the low-side drive branch includes a second NMOS tube having a fourth parasitic diode;

[0017] The gate of the first NMOS transistor is connected to the reverse suppression drive circuit, the drain is connected to the second NMOS transistor, and the source is connected to the chip output terminal; the anode of the third parasitic diode is connected to the source of the first NMOS transistor, and the cathode is connected to the drain of the first NMOS transistor;

[0018] One end of the second resistor is connected between the reverse suppression drive circuit and the gate of the first NMOS transistor, and the other end is connected between the source of the first NMOS transistor and the chip output terminal.

[0019] Furthermore, it also includes:

[0020] An undervoltage protection circuit is preset with a reference voltage, and the undervoltage protection circuit is connected to the reverse inhibition drive circuit, and is used to output an enable invalid signal when the power supply terminal or the ground terminal is disconnected and the voltage difference between the power supply terminal and the ground terminal is lower than the reference voltage, or to output a valid enable signal when the power supply terminal and the ground terminal are not disconnected and the voltage difference between the power supply terminal and the ground terminal is equal to or higher than the reference voltage.

[0021] Furthermore, the suppression driving signal includes a first driving sub-signal and a second driving sub-signal; and the reverse suppression driving circuit includes:

[0022] a first tri-state gate, having an input end connected to the ground end, an output control end connected to the undervoltage protection circuit, and an output end connected to the first reverse isolation circuit, configured to output the first driving sub-signal according to the enable invalidation signal;

[0023] The second tri-state gate has an input end connected to the power supply end, an output control end connected to the undervoltage protection circuit, and an output end connected to the second reverse isolation circuit, and is used to output the second driving sub-signal according to the enable invalidation signal.

[0024] Furthermore, the high-side driving branch includes a second PMOS transistor having a second parasitic diode; the low-side driving branch includes a second NMOS transistor having a fourth parasitic diode; and the line break protection circuit further includes:

[0025] An output operational amplifier pre-stage drive circuit is connected to the undervoltage protection circuit, the gate of the second PMOS transistor, and the gate of the second NMOS transistor, and is used to drive the channel of the second PMOS transistor and the channel of the second NMOS transistor to be turned on according to the valid enable signal, or to drive the channel of the second PMOS transistor and the channel of the second NMOS transistor to be turned off according to the enable invalid signal.

[0026] Furthermore, the first reverse isolation circuit includes a first PMOS transistor having a first parasitic diode; the high-side drive branch includes a second PMOS transistor having a second parasitic diode; the current conduction direction of the second parasitic diode is opposite to the current conduction direction of the first parasitic diode; and / or

[0027] The second reverse isolation circuit includes a first NMOS transistor having a third parasitic diode; the low-side drive branch includes a second NMOS transistor having a fourth parasitic diode; the current conduction direction of the fourth parasitic diode is opposite to the current conduction direction of the third parasitic diode.

[0028] The present invention also provides a sensor, comprising a device under test, and a pull-up resistor or a pull-down resistor; and further comprising a line break protection circuit as described above, wherein the line break protection circuit connects the device under test and the pull-up resistor, or the line break protection circuit connects the device under test and the pull-down resistor.

[0029] The beneficial effect of the present invention is as follows: the present invention inserts a first reverse isolation circuit between the high-side drive branch of the device under test and the chip output terminal, and inserts a second reverse isolation circuit between the low-side drive branch and the chip output terminal. In this way, when the device under test is disconnected, the current path from the high-side drive branch to the chip output terminal is blocked, and the current path from the low-side drive branch to the chip output terminal is blocked, thereby achieving a high-impedance state of the chip output terminal, which can be further pulled up to a high potential by an external pull-up resistor, or pulled down to a low potential by an external pull-down resistor, thereby achieving disconnection protection. Compared with the existing technical solutions using charge pump circuits or other types of switching power supplies, the circuit structure of the present invention has high reliability, solves the influence of high-frequency interference, and has low cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] FIG1 is a schematic diagram showing that when a power supply terminal is disconnected, current flows out of an output terminal through a body diode of an output terminal transistor in the prior art;

[0031] FIG2 is a schematic diagram showing a case where a current flows into an output terminal through a body diode of an output terminal transistor when a ground terminal is disconnected in the prior art;

[0032] FIG3 is a structural block diagram of a sensor according to an embodiment of the present invention when the power supply terminal of the device under test is disconnected;

[0033] FIG4 is a structural block diagram of a sensor according to an embodiment of the present invention when the ground terminal of the device under test is disconnected;

[0034] FIG5 is a schematic structural diagram of a connection between a line break protection circuit and a device under test according to an embodiment of the present invention;

[0035] FIG6 is a specific circuit diagram of the connection between the line break protection circuit and the device under test according to an embodiment shown in FIG5 ;

[0036] 7 is another structural diagram of the connection between the line break protection circuit and the device under test according to an embodiment of the present invention;

[0037] 8 is a specific circuit diagram of the reverse suppression drive circuit of the line break protection circuit of an embodiment shown in FIG7 connected to the first reverse isolation circuit and the second reverse isolation circuit respectively;

[0038] FIG9 is another structural diagram of the connection between the line break protection circuit and the device under test according to an embodiment of the present invention;

[0039] FIG10 is a schematic structural diagram of a sensor under test device according to an embodiment of the present invention when the power supply terminal is disconnected;

[0040] FIG11 is a schematic structural diagram of a sensor according to an embodiment of the present invention when the ground terminal of the device under test is disconnected;

[0041] FIG12 is a specific circuit diagram of an output operational amplifier pre-stage driving circuit of the line break protection circuit shown in FIG9 according to an embodiment. DETAILED DESCRIPTION

[0042] The principles and features of the present invention are described below with reference to the accompanying drawings. The examples given are only used to explain the present invention and are not used to limit the scope of the present invention.

[0043] As shown in Figures 3 and 4, the present invention provides a sensor comprising a device under test 9, a pull-up resistor RPU or a pull-down resistor RPD, and a line break protection circuit 8. The device under test 9 may be a chip under test, specifically comprising a power supply terminal VCC, a ground terminal GND, a high-side drive branch 1 connected to the power supply terminal VCC, a low-side drive branch 2 connected to the ground terminal GND, and a chip output terminal OUT connected between the high-side drive branch 1 and the low-side drive branch 2. The line break protection circuit 8 is connected to the device under test 9, specifically between the high-side drive branch 1 and the low-side drive branch 2, and is connected to the pull-up resistor RPU via the chip output terminal OUT, or the line break protection circuit 8 is connected to the pull-down resistor RPD via the chip output terminal OUT, to protect the device under test 9.

[0044] As shown in FIG3 , when the power supply terminal VCC is disconnected, the pull-up resistor RPU is connected between the chip output terminal OUT and the preset power supply VCC1 to pull up the potential of the chip output terminal OUT to a high level.

[0045] Alternatively, as shown in FIG4 , when the ground terminal GND is disconnected, the pull-down resistor RPD is connected between the chip output terminal OUT and the ground GND1 to pull down the potential of the chip output terminal OUT to a low level.

[0046] As shown in Figure 5, the present invention provides a line break protection circuit. The line break protection circuit includes a reverse suppression drive circuit 3, a first reverse isolation circuit 4, and a second reverse isolation circuit 5. The reverse suppression drive circuit 3 is used to output a suppression drive signal when the power supply terminal VCC or the ground terminal GND is disconnected. The first reverse isolation circuit 4 is connected to the reverse suppression drive circuit 3 and is connected between the high-side drive branch 1 and the chip output terminal OUT, and is used to block the current path from the high-side drive branch 1 to the chip output terminal OUT according to the suppression drive signal. The second reverse isolation circuit 5 is connected to the reverse suppression drive circuit 3 and is connected between the low-side drive branch 2 and the chip output terminal OUT, and is used to block the current path from the low-side drive branch 2 to the chip output terminal OUT according to the suppression drive signal.

[0047] In this embodiment, when the power supply terminal VCC or the ground terminal GND is disconnected, the inhibition drive signal generated by the reverse inhibition drive circuit 3 is in a high-impedance state, which is also the state required by the chip output terminal OUT. Therefore, the potential of the chip output terminal OUT can be determined by the external pull-up resistor or pull-down resistor. However, when the power supply terminal VCC or the ground terminal GND is disconnected, static current will exist in the high-side drive branch 1 and the low-side drive branch 2 and flow to the chip output terminal OUT, resulting in the inhibition drive signal being unable to be input to the chip output terminal OUT, thereby causing the chip output terminal OUT to not be in a high-impedance state. Therefore, the chip output terminal OUT cannot be pulled up to a high potential by the external pull-up resistor, or cannot be pulled down to a low potential by the external pull-down resistor. Therefore, in order to block the static current of the high-side drive branch 1 and the low-side drive branch 2 from flowing to the chip output terminal OUT, the present application inserts a first reverse isolation circuit 4 between the high-side drive branch 1 and the chip output terminal OUT of the device under test 9, and inserts a second reverse isolation circuit 5 between the low-side drive branch 2 and the chip output terminal OUT. In this way, when the power supply terminal VCC of the device under test 9 is disconnected, the current path from the high-side drive branch 1 to the chip output terminal OUT is blocked, and when the ground terminal GND of the device under test is disconnected, the current path from the low-side drive branch 2 to the chip output terminal OUT is blocked, thereby achieving a high-impedance state of the chip output terminal OUT, which can be further pulled up to a high potential by an external pull-up resistor, or pulled down to a low potential by an external pull-down resistor. Compared with the existing technical solutions using charge pump circuits or other types of switching power supplies, the circuit structure of the present invention has high reliability, solves the influence of high-frequency interference, and has low cost.

[0048] In some embodiments, as shown in Figure 6, the first reverse isolation circuit 4 includes a first discharge path 41 and a first reverse inhibition tube 42; wherein, the first discharge path 41 connects the reverse inhibition drive circuit 3 and the first reverse inhibition tube 42, and is used to generate a first discharge current signal according to the inhibition drive signal to block the first reverse inhibition tube 42 from conducting; the first reverse inhibition tube 42 is connected in series with the high-side drive branch 1, and is used to block the current path from the high-side drive branch 1 to the chip output terminal OUT according to the inhibition drive signal and the first discharge current signal.

[0049] In this embodiment, the first bleeder path 41 is used to provide a bleeder path for the first reverse suppression transistor 42. When the suppression drive signal generated by the reverse suppression drive circuit 3 is in a high-impedance state, the first bleeder path 41 can provide a bleeder current to the first reverse suppression transistor 42, thereby turning off the first reverse suppression transistor 42. When the power supply terminal VCC of the device under test 9 is disconnected, the first reverse suppression transistor 42, under the combined action of the suppression drive signal and the first bleeder current signal, blocks the current path from the high-side drive branch 1 to the chip output terminal OUT, thereby achieving a high-impedance state at the chip output terminal OUT. Furthermore, the potential of the chip output terminal OUT can be pulled up to a high potential by an external pull-up resistor.

[0050] In some embodiments, the first reverse suppression transistor 42 includes, but is not limited to, a first PMOS transistor MBLK,HS having a first parasitic diode D1; the first discharge path 41 includes, but is not limited to, a first resistor RHS; and the high-side drive branch 1 includes a second PMOS transistor MDRV,HS having a second parasitic diode D2. When the power supply terminal VCC is disconnected, the aforementioned quiescent current is generated by the second parasitic diode D2. The gate of the first PMOS transistor MBLK,HS is connected to the reverse suppression drive circuit 3, the drain is connected to the second PMOS transistor MDRV,HS, and the source is connected to the chip output terminal OUT. The source of the second PMOS transistor MDRV,HS is connected to the power supply terminal VCC, and the drain is connected to the drain of the second PMOS transistor MDRV,HS. The anode of the second parasitic diode D2 is connected to the drain of the second PMOS transistor MDRV,HS, and the cathode is connected to the source of the second PMOS transistor MDRV,HS. The anode of the first parasitic diode D1 is connected to the drain of the first PMOS transistor MBLK,HS, and the cathode is connected to the source of the first PMOS transistor MBLK,HS. The current conduction direction of the second parasitic diode D2 is opposite to that of the first parasitic diode D1. Therefore, when the power supply terminal VCC is disconnected and the potential of the power supply terminal VCC is lower than the chip output terminal OUT, the second parasitic diode D2 is turned on, but the first parasitic diode D1 is reverse biased and cut off, thereby blocking the static current of the second PMOS transistor MDRV,HS from being transmitted to the chip output terminal OUT through the second parasitic diode D2.

[0051] Furthermore, one end of the first resistor RHS is connected between the reverse suppression drive circuit 3 and the gate of the first PMOS transistor MBLK, HS, and the other end is connected between the source of the first PMOS transistor MBLK, HS and the chip output terminal OUT. Thus, the first resistor RHS is connected across the gate and source of the first PMOS transistor MBLK, HS. When the suppression drive signal generated by the reverse suppression drive circuit 3 is in a high-impedance state, the first resistor RHS provides a discharge current to the gate and source of the first PMOS transistor MBLK, HS, causing the gate-source voltage VGS of the first PMOS transistor MBLK, HS to approach 0V, thereby blocking the channel of the first PMOS transistor MBLK, HS.

[0052] In this way, the channel of the first PMOS transistor MBLK, HS is cut off, and the first parasitic diode D1 of the first PMOS transistor MBLK, HS is reverse biased and cut off, so that the static current of the second PMOS transistor MDRV, HS cannot pass through the channel of the first PMOS transistor MBLK, HS. The static current of the second PMOS transistor MDRV, HS can be completely blocked from flowing to the chip output terminal OUT, thereby restoring the chip output terminal OUT to a high impedance state. Further, the potential of the chip output terminal OUT can be pulled up to a high potential by the external pull-up resistor.

[0053] In some embodiments, the connection positions of the first PMOS transistor MBLK, HS and the second PMOS transistor MDRV, HS can be interchanged to similarly block the flow of static current to the chip output terminal OUT. Specifically, the source of the first PMOS transistor MBLK, HS is connected to the power supply terminal VCC, and the source of the second PMOS transistor MDRV, HS is connected to the chip output terminal OUT. The other circuit structure connections remain unchanged.

[0054] In some embodiments, the second reverse isolation circuit 5 includes a second discharge path 51 and a second reverse inhibition tube 52; wherein, the second discharge path 51 connects the reverse inhibition drive circuit 3 and the second reverse inhibition tube 52, and is used to generate a second discharge current signal according to the inhibition drive signal to block the conduction of the second reverse inhibition tube 52; the second reverse inhibition tube 52 is connected in series with the low-side drive branch 2, and is used to block the current path from the low-side drive branch 2 to the chip output terminal OUT according to the inhibition drive signal and the second discharge current signal.

[0055] In this embodiment, the second discharge path 52 is used to provide a discharge path for the second reverse suppression tube 52. When the suppression drive signal generated by the reverse suppression drive circuit 3 is in a high-impedance state, a discharge current can be provided to the second reverse suppression tube 52 to put the second reverse suppression tube 52 into a cut-off state.

[0056] In some embodiments, the second reverse suppression transistor 52 includes, but is not limited to, a first NMOS transistor MBLK,LS having a third parasitic diode D3; the second discharge path 51 includes, but is not limited to, a second resistor RLS; and the low-side drive branch 2 includes a second NMOS transistor MDRV,LS having a fourth parasitic diode D4. When the ground terminal GND is disconnected, the aforementioned quiescent current is generated by the fourth parasitic diode D4. The gate of the first NMOS transistor MBLK,LS is connected to the reverse suppression drive circuit 3, the drain is connected to the second NMOS transistor MDRV,LS, and the source is connected to the chip output terminal OUT; the anode of the third parasitic diode D3 is connected to the source of the first NMOS transistor MBLK,LS, and the cathode is connected to the drain of the first NMOS transistor MBLK,LS; the current conduction direction of the fourth parasitic diode D4 is opposite to the current conduction direction of the third parasitic diode D3. In this way, when the ground terminal GND is disconnected and the potential of the ground terminal GND is higher than the chip output terminal OUT, the fourth parasitic diode D4 is turned on, but the third parasitic diode D3 is reverse biased and cut off, thereby blocking the static current of the second NMOS transistor MDRV,LS from being transmitted to the chip output terminal OUT through the fourth parasitic diode D4.

[0057] Furthermore, one end of the second resistor RLS is connected between the reverse suppression drive circuit 3 and the gate of the first NMOS transistor MBLK, LS, and the other end is connected between the source of the first NMOS transistor MBLK, LS and the chip output terminal OUT. Thus, the second resistor RLS is connected across the gate and source of the first NMOS transistor MBLK, LS. When the suppression drive signal generated by the reverse suppression drive circuit 3 is in a high-impedance state, the second resistor RLS provides a discharge current to the gate and source of the first NMOS transistor MBLK, LS, causing the gate-source voltage VGS of the first NMOS transistor MBLK, LS to approach 0V, thereby blocking the channel of the first NMOS transistor MBLK, LS.

[0058] In this way, the channel of the first NMOS transistor MBLK, LS is cut off, and the third parasitic diode D3 is reverse biased and cut off, so that the static current of the second NMOS transistor MDRV, LS cannot pass through the channel of the first NMOS transistor MBLK, LS. This can completely block the static current of the second NMOS transistor MDRV, LS from flowing to the chip output terminal OUT, thereby restoring the chip output terminal OUT to a high-impedance state. Further, the potential of the chip output terminal OUT can be pulled down to a low potential by the external pull-down resistor.

[0059] In some embodiments, the connection positions of the first NMOS transistor MBLK, LS and the second NMOS transistor MDRV, LS can be interchanged to similarly block static current from flowing to the chip output terminal OUT. Specifically, the source of the first NMOS transistor MBLK, LS is connected to the ground terminal GND, and the source of the second NMOS transistor MDRV, LS is connected to the chip output terminal OUT. The other circuit structure connections remain unchanged.

[0060] In some embodiments, as shown in Figure 7, the disconnection protection circuit of the present invention also includes an undervoltage protection circuit 6 with a preset reference voltage. The undervoltage protection circuit 6 is connected to the reverse inhibition drive circuit 3 and is used to output an enable invalid signal when the power supply terminal VCC or the ground terminal GND is disconnected and the voltage difference between the power supply terminal VCC and the ground terminal GND is lower than the reference voltage, or to output a valid enable signal when the power supply terminal VCC and the ground terminal GND are not disconnected and the voltage difference between the power supply terminal VCC and the ground terminal GND is equal to or higher than the reference voltage.

[0061] In this embodiment, as shown in Figures 6 and 7 , when the power supply terminal VCC or the ground terminal GND is disconnected, the voltage difference between the power supply terminal VCC and the ground terminal GND is lower than a preset reference voltage within the undervoltage protection circuit 6. When the power supply terminal VCC and the ground terminal GND are connected, the voltage difference between the power supply terminal VCC and the ground terminal GND is equal to or higher than the reference voltage. In the undervoltage protection circuit 6, the enable invalidation signal and the enable validation signal are collectively referred to as the enable signal EN. When the power supply terminal VCC or the ground terminal GND is disconnected, the enable signal EN output by the undervoltage protection circuit 6 is invalid, and the reverse suppression drive circuit 3 is in a high-impedance state. Accordingly, when the power supply terminal VCC is disconnected, the second parasitic diode D2 of the second PMOS transistor MDRV, HS is connected, and the first PMOS transistor MBLK, HS is completely turned off, thereby achieving a high-impedance state for the chip output terminal OUT. Alternatively, when the ground terminal GND is disconnected, the fourth parasitic diode D4 of the second NMOS transistor MDRV, LS is connected, and the first NMOS transistor MBLK, LS is completely turned off, thereby achieving a high-impedance state for the chip output terminal OUT. When both the power supply terminal VCC and the ground terminal GND are connected, the enable signal EN output by the undervoltage protection circuit 6 is valid. At this time, the reverse suppression drive circuit 3 is in a low-impedance state. Accordingly, the gate of the first PMOS transistor MBLK, HS is pulled low, and the gate of the first NMOS transistor MBLK, LS is pulled high. The channels of the first PMOS transistor MBLK, HS and the first NMOS transistor MBLK, LS are fully turned on, and the second PMOS transistor MDRV, HS and the second NMOS transistor MDRV, LS operate normally. In addition, it should be noted that the enable signal EN can be active at a high level or active at a low level, which can be reasonably selected according to specific examples.

[0062] In some embodiments, the suppression drive signal includes a first drive sub-signal and a second drive sub-signal. As shown in Figures 7 and 8 , the reverse suppression drive circuit 3 includes a first tri-state gate TS1 and a second tri-state gate TS2. The first tri-state gate TS1 has an input connected to the ground terminal GND, an output control terminal connected to the undervoltage protection circuit 6, and an output connected to the first reverse isolation circuit 4. The first tri-state gate TS1 is configured to output the first drive sub-signal based on the enable deactivation signal. The first drive sub-signal is configured to drive the channel of the first PMOS transistor MBLK, HS of the first reverse isolation circuit 4 to be turned off. The second tri-state gate TS2 has an input connected to the power supply terminal VCC, an output control terminal connected to the undervoltage protection circuit 6, and an output connected to the second reverse isolation circuit 5. The second drive sub-signal is configured to output the second drive sub-signal based on the enable deactivation signal. The second drive sub-signal is configured to drive the channel of the first NMOS transistor MBLK, LS of the second reverse isolation circuit 5 to be turned off.

[0063] Specifically, as shown in Figures 6 to 8, when the power supply terminal VCC or the ground terminal GND is disconnected, the enable signal EN output by the undervoltage protection circuit 6 is an enable invalid signal, and when the enable signal EN connected to the output control terminal of the first tri-state gate TS1 and the second tri-state gate TS2 is an enable invalid signal, the first drive sub-signal output by the first tri-state gate TS1 and the second drive sub-signal output by the second tri-state gate TS2 are both in a high-impedance state; at this time, the first PMOS transistor MBLK, HS and the first NMOS transistor MBLK, LS are both turned off.

[0064] In addition, in the present invention, the reverse suppression drive circuit 3 is further configured to output a normal drive signal when both the power supply terminal VCC and the ground terminal GND are connected. In this case, the first reverse isolation circuit is further configured to conduct under the action of the normal drive signal to enable the high-side drive branch to operate normally. The second reverse isolation circuit is further configured to conduct under the action of the normal drive signal to enable the low-side drive branch to operate normally. The normal drive signal includes a third drive sub-signal and a fourth drive sub-signal.

[0065] Specifically, the first tri-state gate TS1 is further configured to output the third driver sub-signal based on the valid enable signal; and the second tri-state gate TS2 is further configured to output the fourth driver sub-signal based on the valid enable signal. When the power supply terminal VCC and the ground terminal GND are both connected, the enable signal EN output by the undervoltage protection circuit 6 is a valid enable signal. When the enable signal EN connected to the output control terminals of the first tri-state gate TS1 and the second tri-state gate TS2 is a valid enable signal, the third driver sub-signal output by the first tri-state gate TS1 follows the input of the first tri-state gate TS1 as a low-level signal, and the fourth driver sub-signal output by the second tri-state gate TS2 follows the input of the second tri-state gate TS2 as a high-level signal. Since the first reverse inhibition tube in the first reverse isolation circuit is the first PMOS tube MBLK, HS, and the second reverse inhibition tube in the second reverse isolation circuit is the first NMOS tube MBLK, LS, and the PMOS tube is turned on when the gate is at a low level, and the NMOS tube is turned on when the gate is at a high level; therefore, when the enable signal EN connected to the output control terminal of the first tri-state gate TS1 and the second tri-state gate TS2 is a valid enable signal, the first PMOS tube MBLK, HS and the first NMOS tube MBLK, LS are both turned on, and at this time, the high-side drive branch 1 and the low-side drive branch 2 are not blocked, thereby ensuring the normal operation of the high and low-side drive branches.

[0066] In some embodiments, as shown in FIG9 , the disconnection protection circuit further includes an output op amp pre-stage driver circuit 7. The output op amp pre-stage driver circuit 7 is connected to the undervoltage protection circuit 6, the gate of the second PMOS transistor MDRV, HS, and the gate of the second NMOS transistor MDRV, LS, and is configured to drive the second PMOS transistor MDRV, HS and the second NMOS transistor MDRV, LS to turn on according to the valid enable signal, or to turn off the channel of the second PMOS transistor MDRV, HS and the channel of the second NMOS transistor MDRV, LS according to the invalid enable signal.

[0067] In the present invention, when the power supply terminal VCC and the ground terminal GND are properly connected, the voltage difference between the power supply terminal VCC and the ground terminal GND is equal to or greater than the reference voltage, the enable signal EN output by the undervoltage protection circuit 6 is valid, i.e., the effective enable signal. The first tri-state gate TS1 outputs the third drive sub-signal and follows the input of the first tri-state gate TS1 as a low-level signal, and the second tri-state gate TS2 outputs the fourth drive sub-signal and follows the input of the second tri-state gate TS2 as a high-level signal. As a result, the gate of the first PMOS transistor MBLK, HS is pulled low and turned on, and the gate of the first NMOS transistor MBLK, LS is pulled high and turned on. Furthermore, because the output op amp pre-stage driver circuit 7 drives the second PMOS transistor MDRV, HS and the second NMOS transistor MDRV, LS to turn on in response to the effective enable signal, the second PMOS transistor MDRV, HS and the second NMOS transistor MDRV, LS operate normally.

[0068] When the power supply terminal VCC or the ground terminal GND is disconnected, the voltage difference between the power supply terminal VCC and the ground terminal GND falls below a preset voltage. As shown in FIG10 , when the power supply terminal VCC is disconnected, the potential of the power supply terminal VCC is pulled down toward ground due to the quiescent current of the second PMOS transistor MDRV,HS. This triggers the undervoltage protection circuit 6, deactivating the enable signal EN output by the undervoltage protection circuit 6, thereby becoming the enable disable signal. Furthermore, the channels of the second PMOS transistor MDRV,H and the second NMOS transistor MDRV,LS are turned off, and the first driver sub-signal output by the first tri-state gate TS1 and the second driver sub-signal output by the second tri-state gate TS2 are both in a high-impedance state. When the potential of the power supply terminal VCC further decreases and becomes lower than the chip output terminal OUT, the second parasitic diode D2 of the second PMOS transistor MDRV,H is turned on. However, the conduction direction of the first parasitic diode D1 of the first PMOS transistor MBLK,HS is opposite to the conduction direction of the second parasitic diode D2. Therefore, the first parasitic diode D1 is reverse biased and cut off. Moreover, the channel of the first PMOS transistor MBLK,HS is turned off by the first discharge path 41. In this way, the current path from the second PMOS transistor MDRV,H to the chip output terminal OUT is blocked, that is, the static current is prevented from flowing to the chip output terminal OUT, thereby putting the chip output terminal OUT in a high-impedance state. As a result, the potential of the chip output terminal OUT can be pulled up to a high potential by the pull-up resistor.

[0069] As shown in Figure 11 , when ground terminal GND is disconnected, the potential of ground terminal GND is pulled higher toward the voltage of power supply terminal VCC due to the quiescent current of second NMOS transistor MDRV,LS. This triggers undervoltage protection circuit 6, deactivating the enable signal EN output by undervoltage protection circuit 6. Furthermore, the channels of second PMOS transistor MDRV,H and second NMOS transistor MDRV,LS are turned off, and the first driver sub-signal output by first tri-state gate TS1 and the second driver sub-signal output by second tri-state gate TS2 are both in a high-impedance state. When the potential of the ground terminal GND is further increased and exceeds the chip output terminal OUT, the fourth parasitic diode D4 of the second NMOS transistor MDRV, LS is turned on. However, the conduction direction of the third parasitic diode D3 of the first NMOS transistor MBLK, LS is opposite to that of the fourth parasitic diode D4. Therefore, the third parasitic diode D3 is reverse biased and cut off. Moreover, the channel of the first NMOS transistor MBLK, LS is turned off by the second discharge path 51. In this way, the current path from the second NMOS transistor MDRV, LS to the chip output terminal OUT is blocked, that is, the static current is prevented from flowing to the chip output terminal OUT, thereby putting the chip output terminal OUT in a high-impedance state. As a result, the potential of the chip output terminal OUT can be pulled down to a low potential by the pull-down resistor.

[0070] As shown in FIG12 , in some embodiments, the output operational amplifier pre-stage driving circuit 7 includes:

[0071] A first transistor M1 and a second transistor M2, wherein the gate of the first transistor M1 is connected to a first bias voltage VN, the gate of the second transistor M2 is connected to a second bias voltage VP, and the source of the first transistor M1 is connected to the source of the second transistor M2;

[0072] a third transistor M3 and a fourth transistor M4, wherein the drain of the third transistor M3 is connected to the drain of the first transistor M1, the drain of the fourth transistor M4 is connected to the drain of the second transistor M2, the gate of the third transistor M3 is connected to the gate of the fourth transistor M4 and is connected between the drain of the first transistor M1 and the drain of the third transistor M3, and the source of the third transistor M3 and the source of the fourth transistor M4 are both connected to a third bias voltage VDD;

[0073] a fifth transistor M5 , having a gate connected to the bias current I, a drain connected between the source of the first transistor M1 and the source of the second transistor M2 , and a source connected to a fourth bias voltage VSS;

[0074] a sixth transistor M6 and a seventh transistor M7, wherein the gate of the sixth transistor M6 is connected between the drain of the second transistor M2 and the drain of the fourth transistor M4, the source of the sixth transistor M6 is connected to the third bias voltage VDD, the drain of the sixth transistor M6 is connected to the drain of the seventh transistor M7, the gate of the seventh transistor M7 is connected to the gate of the fifth transistor M5 and is connected to the bias current I, and the source of the seventh transistor M7 is connected to the fourth bias voltage VSS;

[0075] an eighth transistor M8 , having a drain connected to the bias current I, a source connected to the fourth bias voltage VSS, and a gate connected to the gate of the fifth transistor M5 and connected to the bias current I;

[0076] a ninth transistor M9 and a tenth transistor M10, wherein the gates of the ninth transistor M9 and the tenth transistor M10 are both connected to the enable signal EN, the source of the ninth transistor M9 is connected to the third bias voltage VDD, the drain of the ninth transistor M9 is connected to the gate of the sixth transistor M6, the source of the tenth transistor M10 is connected to the fourth bias voltage VSS, and the drain of the tenth transistor M10 is connected to the gate of the seventh transistor;

[0077] A first driving signal VO for driving the second PMOS transistor MDRV, HS or the second NMOS transistor MDRV, LS to turn on is output between the drain of the sixth transistor M6 and the drain of the seventh transistor M7.

[0078] In addition, the output operational amplifier pre-stage driving circuit 7 further includes an inverting circuit (not shown in FIG12 ), which is connected between the drain of the sixth transistor M6 and the drain of the seventh transistor M7 and is configured to invert the first driving signal VO to obtain a second driving signal that is opposite to the first driving signal VO.

[0079] Specifically, when the first drive signal VO is used to drive the second PMOS transistor MDRV,HS, the gate of the second PMOS transistor MDRV,HS is connected between the drain of the sixth transistor M6 and the drain of the seventh transistor M7, and the gate of the second NMOS transistor MDRV,LS is connected to the reverse circuit. When the first drive signal VO is used to drive the second NMOS transistor MDRV,LS, the gate of the second NMOS transistor MDRV,LS is connected between the drain of the sixth transistor M6 and the drain of the seventh transistor M7, and the gate of the second PMOS transistor MDRV,HS is connected to the reverse circuit.

[0080] The present invention inserts a first reverse isolation circuit between the high-side drive branch of the device under test and the chip output terminal, and inserts a second reverse isolation circuit between the low-side drive branch and the chip output terminal. In this way, when the device under test is disconnected, the current path from the high-side drive branch to the chip output terminal is blocked, and the current path from the low-side drive branch to the chip output terminal is blocked, thereby achieving a high-impedance state of the chip output terminal, which can be further pulled up to a high potential by an external pull-up resistor, or pulled down to a low potential by an external pull-down resistor, thereby achieving disconnection protection. Compared with existing technical solutions using charge pump circuits or other types of switching power supplies, the circuit structure of the present invention has high reliability, solves the influence of high-frequency interference, and has low cost.

[0081] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A wire break protection circuit for protecting a device under test, the device under test including a power supply terminal, a ground terminal, a high-side drive branch connected to the power supply terminal, a low-side drive branch connected to the ground terminal, and a chip output terminal connected between the high-side drive branch and the low-side drive branch, characterized in that , The open - circuit protection circuit includes: A reverse - inhibition drive circuit, configured to output an inhibition drive signal when the power supply terminal or the ground terminal is open - circuited; A first reverse - isolation circuit, connected to the reverse - inhibition drive circuit and between the high - side drive branch and the chip output terminal, configured to block the current path from the high - side drive branch to the chip output terminal according to the inhibition drive signal; A second reverse - isolation circuit, connected to the reverse - inhibition drive circuit and between the low - side drive branch and the chip output terminal, configured to block the current path from the low - side drive branch to the chip output terminal according to the inhibition drive signal.

2. The disconnection protection circuit according to claim 1, wherein , The first reverse - isolation circuit includes a first discharge path and a first reverse - inhibition transistor; wherein, the first discharge path connects the reverse - inhibition drive circuit and the first reverse - inhibition transistor, and is configured to generate a first discharge current signal according to the inhibition drive signal to block the conduction of the first reverse - inhibition transistor; the first reverse - inhibition transistor is serially connected to the high - side drive branch and is configured to block the current path from the high - side drive branch to the chip output terminal according to the inhibition drive signal and the first discharge current signal.

3. The disconnection protection circuit according to claim 2, characterized in that , The first reverse - inhibition transistor includes a first PMOS transistor having a first parasitic diode; the first discharge path includes a first resistor; the high - side drive branch includes a second PMOS transistor having a second parasitic diode; The gate of the first PMOS transistor is connected to the reverse - inhibition drive circuit, the drain is connected to the second PMOS transistor, and the source is connected to the chip output terminal; the anode of the first parasitic diode is connected to the drain of the first PMOS transistor, and the cathode is connected to the source of the first PMOS transistor; One end of the first resistor is connected between the reverse - inhibition drive circuit and the gate of the first PMOS transistor, and the other end is connected between the source of the first PMOS transistor and the chip output terminal.

4. The disconnection protection circuit according to claim 1, characterized in that , The second reverse - isolation circuit includes a second discharge path and a second reverse - inhibition transistor; wherein, the second discharge path connects the reverse - inhibition drive circuit and the second reverse - inhibition transistor, and is configured to generate a second discharge current signal according to the inhibition drive signal to block the conduction of the second reverse - inhibition transistor; the second reverse - inhibition transistor is serially connected to the low - side drive branch and is configured to block the current path from the low - side drive branch to the chip output terminal according to the inhibition drive signal and the second discharge current signal.

5. The disconnection protection circuit according to claim 4, characterized in that , The second reverse - inhibition transistor includes a first NMOS transistor having a third parasitic diode; the second discharge path includes a second resistor; the low - side drive branch includes a second NMOS transistor having a fourth parasitic diode; The gate of the first NMOS transistor is connected to the reverse - inhibition drive circuit, the drain is connected to the second NMOS transistor, and the source is connected to the chip output terminal; the anode of the third parasitic diode is connected to the source of the first NMOS transistor, and the cathode is connected to the drain of the first NMOS transistor; One end of the second resistor is connected between the reverse suppression drive circuit and the gate of the first NMOS transistor, and the other end is connected between the source of the first NMOS transistor and the chip output terminal.

6. The disconnection protection circuit according to claim 1, characterized in that , further comprising: An undervoltage protection circuit with a preset reference voltage, the undervoltage protection circuit being connected to the reverse suppression drive circuit and configured to output an enable invalid signal when the power supply terminal or the ground terminal is disconnected and the voltage difference between the power supply terminal and the ground terminal is lower than the reference voltage, or to output a valid enable signal when the power supply terminal and the ground terminal are not disconnected and the voltage difference between the power supply terminal and the ground terminal is equal to or higher than the reference voltage.

7. The disconnection protection circuit according to claim 6, characterized in that , the suppression drive signal includes a first drive sub-signal and a second drive sub-signal; The reverse suppression drive circuit includes: A first tri-state gate, with an input terminal connected to the ground terminal, an output control terminal connected to the undervoltage protection circuit, and an output terminal connected to the first reverse isolation circuit, configured to output the first drive sub-signal according to the enable invalid signal; A second tri-state gate, with an input terminal connected to the power supply terminal, an output control terminal connected to the undervoltage protection circuit, and an output terminal connected to the second reverse isolation circuit, configured to output the second drive sub-signal according to the enable invalid signal.

8. The disconnection protection circuit according to claim 6, characterized in that , the high-side drive branch includes a second PMOS transistor having a second parasitic diode; the low-side drive branch includes a second NMOS transistor having a fourth parasitic diode; The open-circuit protection circuit further includes: An output operational amplifier pre-drive circuit, connected to the undervoltage protection circuit, the gate of the second PMOS transistor, and the gate of the second NMOS transistor, configured to drive the channels of the second PMOS transistor and the second NMOS transistor to conduct according to the valid enable signal, or to turn off the channels of the second PMOS transistor and the second NMOS transistor according to the enable invalid signal.

9. The disconnection protection circuit according to claim 1, wherein , the first reverse isolation circuit includes a first PMOS transistor having a first parasitic diode; the high-side drive branch includes a second PMOS transistor having a second parasitic diode; the current conduction direction of the second parasitic diode is opposite to the current conduction direction of the first parasitic diode; and / or The second reverse isolation circuit includes a first NMOS transistor having a third parasitic diode; The low-side drive branch includes a second NMOS transistor having a fourth parasitic diode; the current conduction direction of the fourth parasitic diode is opposite to the current conduction direction of the third parasitic diode.

10. A sensor includes a device under test, and a pull-up resistor or a pull-down resistor, characterized in that, It further includes the open-circuit protection circuit according to any one of claims 1 to 9, the open-circuit protection circuit being connected to the device under test and the pull-up resistor, or the open-circuit protection circuit being connected to the device under test and the pull-down resistor.

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