Processing-in-memory unit and operation method, processing-in-memory array and processing-in-memory circuit

Abstract

The present disclosure provides a processing-in-memory unit and an operation method, a processing-in-memory array and a processing-in-memory circuit. The processing-in-memory unit comprises four weight units, wherein each weight unit comprises a memristor element and a switch element, and the switch element is electrically connected to the memristor element; a switch element of a first weight unit is electrically connected to a switch element of a fourth weight unit to receive a first word line signal; a switch element of a second weight unit is electrically connected to a switch element of a third weight unit to receive a second word line signal; the switch element of the first weight unit is electrically connected to the switch element of the third weight unit to receive a first source line signal; the switch element of the second weight unit is electrically connected to the switch element of the fourth weight unit to receive a second source line signal; and the four switch elements are electrically connected to each other. According to the processing-in-memory unit, a differential structure is formed by using the four weight units, so that the calculated current varies in direct proportion to an input signal, and the additional overhead of a peripheral circuit is effectively reduced.

Description

Storage and computing integrated unit and operation method, storage and computing integrated array and storage and computing integrated circuit

[0001] This application claims priority to Chinese Patent Application No. 202410027072.9 filed on January 8, 2024, and the contents of the above-mentioned Chinese patent application disclosure are hereby incorporated by reference in their entirety as a part of this application. Technical Field

[0002] Embodiments of the present disclosure relate to a storage-computing integrated unit and an operation method, a storage-computing integrated array, and a storage-computing integrated circuit. Background Art

[0003] With the advent of the era of artificial intelligence, the "storage wall" problem of the traditional von Neumann architecture has seriously restricted the computing power and energy consumption of chips. The integrated storage and computing architecture based on memristors has become one of the key technologies to solve the problem.

[0004] Traditional memristor-based integrated memory and computing architectures mostly use arrays composed of 1T1R integrated memory and computing units. During the calculation process, the switching elements in the integrated memory and computing units operate in the linear region. In order to ensure the accuracy of the calculation current, high-precision peripheral drive circuits are required to support it, which increases the area and power consumption of the peripheral circuits. In addition, in order to reduce the impact of parasitic resistance and voltage drop (IR drop) in the array on the calculation current, larger integrated memory and computing units are usually required, which further increases the area of ​​the integrated memory and computing array.

[0005] Summary of the Invention

[0006] At least one embodiment of the present disclosure provides a storage-computing integrated unit, the storage-computing integrated unit includes four weight units, wherein each of the four weight units includes a memristor element and a switch element, the memristor element includes a first electrode and a second electrode, the switch element includes a control electrode, a first electrode and a second electrode, the first electrode of the switch element is electrically connected to the first electrode of the memristor element; the control electrode of the switch element of the first weight unit is electrically connected to the control electrode of the switch element of the fourth weight unit, serving as the first end of the storage-computing integrated unit for receiving a first word line signal; the control electrode of the switch element of the second weight unit is electrically connected to the control electrode of the switch element of the third weight unit The control electrode of the switching element of the weight unit is electrically connected to serve as the second end of the storage and computing unit, for receiving the second word line signal; the second electrode of the switching element of the first weight unit is electrically connected to the second electrode of the switching element of the third weight unit, as the third end of the storage and computing unit, for receiving the first source line signal; the second electrode of the switching element of the second weight unit is electrically connected to the second electrode of the switching element of the fourth weight unit, as the fourth end of the storage and computing unit, for receiving the second source line signal; the second electrodes of the four switching elements are electrically connected to each other, as the fifth end of the storage and computing unit, for receiving the bit line signal.

[0007] For example, in the storage and computing integrated unit provided in at least one embodiment of the present disclosure, the resistance value of the memristor element of the first weight unit is equal to the resistance value of the memristor element of the second weight unit; the resistance value of the memristor element of the third weight unit is equal to the resistance value of the memristor element of the fourth weight unit.

[0008] For example, in the storage and computing integrated unit provided in at least one embodiment of the present disclosure, the switching element of the first weight unit and the switching element of the second weight unit have the same switching current characteristics; the switching element of the third weight unit and the switching element of the fourth weight unit have the same switching current characteristics.

[0009] At least one embodiment of the present disclosure provides a storage-computing integrated array, the storage-computing integrated array comprising: a plurality of storage-computing integrated units as provided in at least one embodiment of the present disclosure, wherein the plurality of storage-computing integrated units are arranged into a plurality of storage-computing integrated unit rows and a plurality of storage-computing integrated unit columns along a first direction and a second direction; a plurality of first word lines extending along the first direction and connected one-to-one with the plurality of storage-computing integrated unit rows, wherein each of the plurality of first word lines is electrically connected to the first end of a corresponding storage-computing integrated unit row to provide the first word line signal; a plurality of second word lines extending along the first direction and connected one-to-one with the plurality of storage-computing integrated unit rows, wherein each of the plurality of second word lines is electrically connected to the second end of a corresponding storage-computing integrated unit row to provide providing the second word line signal; a plurality of first source lines extending along the second direction and connected one-to-one with the plurality of storage-computing integrated unit columns, wherein each of the plurality of first source lines is electrically connected to the third end of a corresponding storage-computing integrated unit column to provide the first source line signal; a plurality of second source lines extending along the second direction and connected one-to-one with the plurality of storage-computing integrated unit columns, wherein each of the plurality of second source lines is electrically connected to the fourth end of a corresponding storage-computing integrated unit column to provide the second source line signal; a plurality of bit lines extending along the first direction and connected one-to-one with the plurality of storage-computing integrated unit rows, wherein each of the plurality of bit lines is electrically connected to the fifth end of a corresponding storage-computing integrated unit row to provide the bit line signal.

[0010] At least one embodiment of the present disclosure provides a storage-computing integrated circuit, which includes: a storage-computing integrated array, a computing circuit module, and a programming circuit module as provided in at least one embodiment of the present disclosure; the computing circuit module is electrically connected to the storage-computing integrated array, and is configured to implement computing operations, including an input module and an output module; the programming circuit module is electrically connected to the storage-computing integrated array, and is configured to implement programming operations.

[0011] For example, in the storage and computing integrated circuit provided in at least one embodiment of the present disclosure, the input module includes: an input buffer, configured to store the input data of each row of the storage and computing integrated array; a digital-to-analog conversion circuit and a multiplexer, configured to perform digital-to-analog conversion on the input data of each row of the storage and computing integrated array to obtain corresponding first word line signals and second word line signals; a word line driving circuit, configured to enhance the driving capability of the first word line signal and the second word line signal, and electrically connected to the multiple first word lines and the multiple second word lines to provide enhanced first word line signals and second word line signals.

[0012] For example, in the storage and computing integrated circuit provided in at least one embodiment of the present disclosure, the output module includes: a source line driving circuit, electrically connected to the multiple first source lines and the multiple second source lines to provide the first source line signals and the second source line signals; an analog-to-digital conversion circuit, electrically connected to the multiple first source lines and the multiple second source lines, configured to convert the current signals on the multiple first source lines and the current signals on the multiple second source lines into digital signals; and an output buffer, configured to store and output the conversion results of the analog-to-digital conversion circuit.

[0013] For example, in the storage and computing integrated circuit provided in at least one embodiment of the present disclosure, the programming circuit module includes: a source line programming driving circuit, electrically connected to the multiple first source lines and the multiple second source lines to provide first source line programming signals and second source line programming signals; a word line programming driving circuit, electrically connected to the multiple first word lines and the multiple second word lines to provide first word line programming signals and second word line programming signals; and a bit line programming driving circuit, electrically connected to the multiple bit lines to provide bit line programming signals.

[0014] For example, in the storage and computing integrated circuit provided in at least one embodiment of the present disclosure, the analog-to-digital conversion circuit includes a plurality of differential analog-to-digital conversion circuits, and the plurality of differential analog-to-digital conversion circuits are electrically connected to the plurality of first source lines and the plurality of second source lines in a one-to-one correspondence. Each of the plurality of differential analog-to-digital conversion circuits includes: a first sampling circuit, configured to convert a current signal on the first source line corresponding to the column into a voltage signal; a second sampling circuit, configured to convert a current signal on the second source line corresponding to the column into a voltage signal; and a successive approximation analog-to-digital conversion circuit, configured to receive the voltage signals output by the first sampling circuit and the second sampling circuit, and convert them into digital signals.

[0015] For example, in the storage and computing integrated circuit provided in at least one embodiment of the present disclosure, the successive approximation analog-to-digital conversion circuit includes: a capacitive digital-to-analog converter, configured to be electrically connected to the output end of the first sampling circuit and the output end of the second sampling circuit; a comparator, electrically connected to the output end of the capacitive digital-to-analog converter, configured to compare the output voltage of the capacitive digital-to-analog converter and output a comparison result; a control logic circuit, configured to receive the comparison result output by the comparator, control the capacitive digital-to-analog converter according to the comparison result, perform conversion using a successive approximation method, and output the converted digital signal at the output end.

[0016] For example, in the storage-computation integrated circuit provided in at least one embodiment of the present disclosure, the first sampling circuit includes a first current source, a first switching element, and a first capacitor; the first switching element is electrically connected to the first current source and the first capacitor, respectively, and is configured to turn on or off the connection between the first current source and the first capacitor according to the control of a control signal; the first current source is electrically connected to the first voltage terminal and the first source line, respectively; the first capacitor is electrically connected to the second voltage terminal and the output terminal of the first sampling circuit, respectively; the second sampling circuit includes a second current source, a second switching element, and a second capacitor; the second switching element is electrically connected to the second current source and the second capacitor, respectively, and is configured to turn on or off the connection between the second current source and the second capacitor according to the control of a control signal; the second current source is electrically connected to the first voltage terminal and the second source line, respectively; the second capacitor is electrically connected to the second voltage terminal and the output terminal of the second sampling circuit, respectively.

[0017] At least one embodiment of the present disclosure provides an electronic device, including the storage and computing integrated circuit provided by at least one embodiment of the present disclosure.

[0018] At least one embodiment of the present disclosure provides an operating method for a storage-computing integrated unit as provided in at least one embodiment of the present disclosure, the operating method comprising: applying a first source line voltage and a second source line voltage to a target operating unit so that each switching element in the target operating unit operates in a saturation state; applying a first word line voltage and a second word line voltage to the target operating unit so that each memristor element in the target operating unit operates in a linear region.

[0019] For example, in the operating method provided in at least one embodiment of the present disclosure, it also includes: applying a programming voltage to each weight unit of the target operating unit one by one, so that the resistance value of the memristor element of the first weight unit is equal to the resistance value of the memristor element of the second weight unit, and the resistance value of the memristor element of the third weight unit is equal to the resistance value of the memristor element of the fourth weight unit.

[0020] For example, in the operating method provided in at least one embodiment of the present disclosure, it also includes: mapping multi-bit weight data into the slope of the calculated current of the target operating unit as the word line differential voltage changes, and applying a programming voltage to each weight unit of the target operating unit one by one, so that the resistance value of the memristor element of each weight unit is programmed to meet the slope.

[0021] For example, in the operating method provided in at least one embodiment of the present disclosure, applying the first word line voltage and the second word line voltage to the target operating unit includes: mapping multi-bit input data into a word line differential voltage, and applying the first word line voltage and the second word line voltage corresponding to the word line differential voltage to the target operating unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0023] FIG1A is a schematic diagram of a storage and computing integrated array based on 1T1R cells;

[0024] FIG1B is an actual current-word line voltage curve of a 1T1R memory-computing integrated unit;

[0025] FIG1C is an ideal current-word line voltage curve of a 1T1R memory-computing integrated unit;

[0026] FIG2A is a schematic diagram of a storage-computing integrated unit provided by at least one embodiment of the present disclosure;

[0027] FIG2B is a schematic diagram of a weight unit provided in at least one embodiment of the present disclosure;

[0028] FIG3A is a current-word line voltage curve of a memory-computing integrated unit according to at least one embodiment of the present disclosure;

[0029] FIG3B is a differential current-differential voltage curve of a storage-computing integrated unit provided by at least one embodiment of the present disclosure;

[0030] FIG4 is a schematic diagram of a storage-computing integrated array provided by at least one embodiment of the present disclosure;

[0031] FIG5 is a schematic diagram of a storage-computation-in-one circuit provided by at least one embodiment of the present disclosure;

[0032] FIG6 is a schematic diagram of a differential analog-to-digital conversion circuit provided by at least one embodiment of the present disclosure; and

[0033] FIG7 is a schematic diagram of a storage-computation-in-one unit implementing multi-bit multiplication calculations according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0035] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0036] A memristor element is a non-volatile device whose conductance state can be adjusted by applying external stimuli. As a two-terminal device, the memristor element has the characteristics of adjustable resistance and non-volatility, and is therefore widely used in storage and computing integration. The storage and computing integration involved in the storage and computing integration includes multiple rows and columns of weight units, and the weight units can be implemented in the form of memristor units. The memristor unit can be a 1T1R structure or a 2T2R structure, wherein the memristor unit of the 1T1R structure includes a switch element and a memristor element, and the first end of the memristor element is electrically connected to the first end of the switch element (such as the drain of the transistor), and the memristor unit of the 2T2R structure includes two switch elements and two memristor elements.

[0037] Memristor elements can perform operations directly in the analog domain. For example, they can perform multiplication operations based on Ohm's law and addition operations based on Kirchhoff's current law. For example, according to Kirchhoff's law, by setting the state (e.g., resistance) of the memristor elements and applying corresponding wordline and bitline signals to the wordline and bitline, the memristor array can perform multiplication and accumulation calculations in parallel, with both storage and calculation occurring in each element of the array.

[0038] The present disclosure does not limit the type, structure, etc. of the memristor element. The memristor element used in the embodiments of the present disclosure may be, for example, a resistive random access memory, a phase change memory, a conductive bridge memory, or other memristor elements with the same characteristics. The switching element used in the embodiments of the present disclosure may be, for example, a thin film transistor, a field effect transistor, or other switching element with the same characteristics. The source and drain of the transistor used here may be symmetrical in structure, so the source and drain may be structurally identical.

[0039] Writing to a memristor cell can be accomplished by performing set and reset operations on the memristor cell. For example, a set operation can be performed by applying a positive voltage pulse to the bit line while grounding the source line, which lowers the resistance of the memristor cell. A reset operation can be performed by applying a positive voltage pulse to the source line while grounding the bit line, which raises the resistance of the memristor cell. A single set or reset operation can be considered a single write operation.

[0040] A read operation on a memristor cell can include applying a read voltage to the memristor cell, obtaining the current value output by the memristor cell under the influence of the read voltage, and determining the current resistance / conductance value of the memristor cell based on the current value and the read voltage. For example, a read voltage can be applied to a source line, and the resistance / conductance value of the memristor cell can be determined using Ohm's law based on the current value output by a bit line.

[0041] After the memristor cell is manufactured, it needs to be initialized. For example, the initialization operation can be to apply a higher voltage to the memristor cell, that is, to apply a positive voltage pulse to the bit line while grounding the source line. The amplitude and duration of the positive voltage pulse should be higher than that of the set operation. This operation causes the resistance value of the memristor cell to change, giving it an initial resistance value. Because the resistance value of the memristor cell is random, even under the same initialization conditions, the resistance value of each memristor cell will be different.

[0042] The inventors of the present disclosure have noticed that the traditional 1T1R-based integrated storage and computing array will cause the computing accuracy to be seriously affected by the array IR drop, and will also lead to a large peripheral circuit overhead.

[0043] For example, Figure 1A is a schematic diagram of a memory-computing array based on 1T1R cells. As shown in Figure 1A, when current flows through the wires in the memory-computing array, the parasitic resistance of the wires generates an IR drop, which directly affects the computing voltage of the 1T1R memory-computing cell and thus the output computing current.

[0044] For another example, FIG1B is an actual curve of the current-word line voltage of a 1T1R memory-computing integrated unit. As shown in FIG1B , only when the word line voltage V WL Greater than V min In the range of , the current I of the 1T1R memory-computing integrated unit changes with the word line voltage V WL The change is linear, so take V min As the corresponding word line voltage of 0 input. However, when the word line voltage V WL V min When the current I is not 0, the positive weight current generated by the 1T1R storage and computing unit has an offset value I offset1 , the negative weight current has an offset value Ioffset2 . The current gathered by a column of 1T1R storage and computing units includes the sum of the offset currents of all the units in the column and the sum of the computing currents. Therefore, the sum of the offset currents of all the units in the column needs to be subtracted outside the array to meet the ideal current-word line voltage curve of the 1T1R storage and computing unit shown in Figure 1C. The offset current of each 1T1R storage and computing unit is related to the conductance value of the memristor element. Therefore, each column requires a column weight state storage circuit to store the conductance value of the storage and computing units involved in the calculation. However, this design requires that the conductance value of the storage and computing units involved in the calculation need to be determined before each calculation and stored in the column weight state storage circuit. This operation not only increases the circuit overhead, but also frequently involves external communication, thereby increasing the overall complexity and delay of the calculation.

[0045] At least one embodiment of the present disclosure provides a storage-computing integrated unit, which includes four weight units, wherein each of the four weight units includes a memristor element and a switch element, the memristor element includes a first electrode and a second electrode, the switch element includes a control electrode, a first electrode and a second electrode, and the first electrode of the switch element is electrically connected to the first electrode of the memristor element; the control electrode of the switch element of the first weight unit is electrically connected to the control electrode of the switch element of the fourth weight unit, serving as the first end of the storage-computing integrated unit for receiving a first word line signal; the control electrode of the switch element of the second weight unit is electrically connected to the control electrode of the switch element of the third weight unit, serving as the second end of the storage-computing integrated unit for receiving a second word line signal; the second electrode of the switch element of the first weight unit is electrically connected to the second electrode of the switch element of the third weight unit, serving as the third end of the storage-computing integrated unit for receiving a first source line signal; the second electrode of the switch element of the second weight unit is electrically connected to the second electrode of the switch element of the fourth weight unit, serving as the fourth end of the storage-computing integrated unit for receiving a second source line signal; the second electrodes of the four switch elements are electrically connected to each other, serving as the fifth end of the storage-computing integrated unit for receiving a bit line signal.

[0046] The storage and computing integrated unit provided by at least one embodiment of the present disclosure utilizes four weight units to form a differential structure, uses differential word line signals as input signals, and uses differential output currents as computing currents, thereby achieving a positive proportional change of computing current with the input signal in a single storage and computing integrated unit. There is no need to add circuits to compensate for the current offset value, thereby effectively reducing the additional overhead of peripheral circuits.

[0047] The following non-restrictive description of the storage and computing integrated unit provided according to the present disclosure is made through multiple embodiments and examples. As described below, different features in these specific examples or embodiments can be combined with each other without conflicting with each other to obtain new examples or embodiments, and these new examples or embodiments also fall within the scope of protection of the present disclosure.

[0048] Figure 2A is a schematic diagram of a storage-computing integrated unit according to at least one embodiment of the present disclosure. Figure 2B is a schematic diagram of a weighting unit according to at least one embodiment of the present disclosure.

[0049] For example, as shown in FIG2A , the storage-computing integrated unit 10 provided in an embodiment of the present disclosure includes four weight units, namely a first weight unit 110, a second weight unit 120, a third weight unit 130, and a fourth weight unit 140. The first weight unit 110 and the second weight unit 120 are used to implement positive weights, and the third weight unit 130 and the fourth weight unit 140 are used to implement negative weights.

[0050] For example, as shown in Figure 2B, each weight unit includes a memristor element 101 and a switching element 102, the memristor element 101 includes a first electrode 1011 and a second electrode 1012, the switching element 102 includes a control electrode 1023, a first electrode 1021 and a second electrode 1022, and the first electrode 1021 of the switching element 102 and the first electrode 1011 of the memristor element 1021 are electrically connected.

[0051] For example, as shown in Figure 2A, the control electrode of the switching element of the first weight unit 110 is electrically connected to the control electrode of the switching element of the fourth weight unit 140, serving as the first end of the storage and computing integrated unit 10, for receiving the first word line WL1 signal; the control electrode of the switching element of the second weight unit 120 is electrically connected to the control electrode of the switching element of the third weight unit 130, serving as the second end of the storage and computing integrated unit 10, for receiving the second word line WL2 signal; the second electrode of the switching element of the first weight unit 110 is electrically connected to the second electrode of the switching element of the third weight unit 130, serving as the third end of the storage and computing integrated unit 10, for receiving the first source line SL1 signal; the second electrode of the switching element of the second weight unit 120 is electrically connected to the second electrode of the switching element of the fourth weight unit 140, serving as the fourth end of the storage and computing integrated unit 10, for receiving the second source line SL2 signal; the second electrodes of the four switching elements are electrically connected to each other, serving as the fifth end of the storage and computing integrated unit 10, for receiving the bit line BL signal.

[0052] Figure 3A is a current-word line voltage curve of a storage and computing integrated unit according to at least one embodiment of the present disclosure. Figure 3B is a differential current-differential voltage curve of a storage and computing integrated unit according to at least one embodiment of the present disclosure.

[0053] During the calculation process, all the switching elements of the storage and calculation integrated unit 10 operate in the saturation region. + The current I1 of the first weight unit 110 + and the current I2 of the second weight unit 120 + Subtraction produces, that is, formula (1):

[0054] I + =I1 + -I2 + (1)

[0055] For example, the switch element of the first weight unit 110 and the switch element of the second weight unit 120 have the same switching current characteristics. During the calculation process, the first source line signal and the second source line signal are the same, so that the switch elements of the first weight unit 110 and the second weight unit 120 both operate in the saturation region, and the bit line signals are both grounded. For example, the resistance value of the memristor element of the first weight unit 110 is equal to the resistance value of the memristor element of the second weight unit 120, so the current I1 of the first weight unit 110 is equal to the current I2 of the second weight unit 120. + and the current I2 of the second weight unit 120 + Meet the same current-word line voltage (IV WL ) change relationship, see W in Figure 3A + .

[0056] As shown in FIG3A , the first word line signal is V WL1 , the second word line signal is V WL2 For example, V WL1 and V WL2 The common mode value is V ref , the differential mode value is ΔV WL . Set the word line voltage V WL The range of variation is V min To V max , in this range IV WL The curve shows a linear relationship. Therefore, the differential current between the first weight unit 110 and the second weight unit 120, that is, the positive weight current I + , will change with ΔV WL The change shows a positive proportional relationship, see W in Figure 3B + , positive weight current I + and ΔV WL Satisfy formula (2):

[0057] I + =s + ×ΔV WL (2)

[0058] Among them, the slope s + The memristor element resistance R of the first weight unit 110 and the second weight unit 120 generating the positive weight current + Decide.

[0059] Negative weight current I - The current I1 of the third weight unit 130 - and the current I2 of the fourth weight unit 140 -Subtraction produces formula (3):

[0060] I - =I1 - -I2 - (3)

[0061] For example, the switch element of the third weight unit 130 and the switch element of the fourth weight unit 140 have the same switching current characteristics. During the calculation process, the first source line signal and the second source line signal are the same, so that the switch elements of the third weight unit 130 and the fourth weight unit 140 both operate in the saturation region, and the bit line signals are both grounded. For example, the resistance value of the memristor element of the third weight unit 130 is equal to the resistance value of the memristor element of the fourth weight unit 140, so the current I1 of the third weight unit 130 is equal to the current I2 of the fourth weight unit 140. - and the current I2 of the fourth weight unit 140 - Meet the same current-word line voltage (IV WL ) change relationship, see W in Figure 3A - .

[0062] Consistent with the positive weight case, the differential current of the third weight unit 130 and the third weight unit 140, that is, the negative weight current I - , will change with ΔV WL The change shows a positive proportional relationship, see W in Figure 3B - , negative weight current I - and ΔV WL Satisfying formula (4):

[0063] I - =s - ×ΔV WL (4)

[0064] Among them, the slope s - The memristor element resistance R of the third weight unit 130 and the fourth weight unit 140 generating the negative weight current - Decide.

[0065] The calculation current ΔI of the storage and calculation integrated unit 10 satisfies formula (5):

[0066] ΔI=I + -I - =(s + -s - )×ΔV WL =s×ΔV WL (5)

[0067] The calculation current ΔI formula of the storage and computing integrated unit 10 can be further derived as formula (6):

[0068] ΔI=I+ -I - =I1 + -I2 + -(I1 - -I2 - )=(I1 + +I2 - )-(I2 + +I1 - )=I SL1 -I SL2 (6)

[0069] Therefore, the calculation current ΔI of the storage and calculation integrated unit 10 is the first source line current I SL1 and the second source line current I SL2 difference.

[0070] FIG4 is a schematic diagram of a memory-computation integrated array provided by at least one embodiment of the present disclosure. For example, as shown in FIG4 , the memory-computation integrated array provided by the embodiment of the present disclosure includes n first word lines WL1 (WL1[1] to WL1[n]), n second word lines WL2 (WL2[1] to WL2[n]), m first source lines SL1 (SL1[1] to SL1[m]), m second source lines SL2 (SL2[1] to SL2[m]), n bit lines BL (BL[1] to BL[n]), and a plurality of memory-computation integrated units 10 as shown in FIG2A , which are arranged into n memory-computation integrated unit rows and m memory-computation integrated unit columns along the first direction D1 and the second direction D2. It should be noted that m and n are positive integers, which will not be repeated in the following text.

[0071] For example, as shown in FIG4 , n first word lines WL1 extend along the first direction D1 and are connected one-to-one with n rows of storage-computing integrated units, and each first word line is electrically connected to the first end 11 of the corresponding row of storage-computing integrated units 10 to provide a first word line signal; n second word lines WL2 extend along the first direction D1 and are connected one-to-one with n rows of storage-computing integrated units, and each second word line is electrically connected to the second end 12 of the corresponding row of storage-computing integrated units 10 to provide a second word line signal; m first source lines SL1 extend along the second direction D2 and are connected one-to-one with m columns of storage-computing integrated units. One-to-one connection, each first source line is electrically connected to the third end 13 of the corresponding column of storage and computing units 10 to provide a first source line signal; m second source lines SL2 extend along the second direction D2 and are connected one-to-one with m columns of storage and computing units, each second source line is electrically connected to the fourth end 14 of the corresponding column of storage and computing units 10 to provide a second source line signal; n bit lines BL extend along the first direction D1 and are connected one-to-one with n rows of storage and computing units, each bit line is electrically connected to the fifth end 15 of the corresponding row of storage and computing units 10 to provide a bit line signal.

[0072] Matrix-vector multiplication refers to the process of multiplying an input vector by a matrix to obtain an output vector. An input vector of dimension n is multiplied by a matrix of dimension n×m to obtain an output vector of dimension m, as shown in formula (7):

[0073] Among them, x i is the i-th element of the input vector, w ij is the element in the i-th row and j-th column of the matrix, y j is the jth element of the output vector.

[0074] For example, as shown in Figure 4, the weight of the matrix w ij The data is stored in the storage-computing integrated unit 10 of the i-th row and j-th column of the storage-computing integrated array. The first terminal 11 and the second terminal 12 of the storage-computing integrated unit 10 of each row in the storage-computing integrated array are short-circuited respectively, and the third terminal 13 and the fourth terminal 14 of the storage-computing integrated unit 10 of each column in the storage-computing integrated array are short-circuited respectively. During the matrix-vector multiplication calculation, the elements in the input vector will be applied to the first word line WL1 and the second word line WL2 of the corresponding row of the storage-computing integrated array in the form of corresponding voltage differences. The elements of the output vector generated by the matrix-vector multiplication calculation will be output to the outside of the storage-computing integrated array in the form of the current difference on the first source line SL1 and the second source line SL2 of the corresponding column. Thus, an n×m-scale matrix-vector multiplication calculation is realized on the n×m-dimensional storage-computing integrated array.

[0075] In the storage and computing integrated array provided by the embodiment of the present disclosure, the influence of IR drop can be reduced in both the voltage input and current output links. In the voltage input link, the word line is connected to the control electrode of the switching element. Therefore, in the process of inputting voltage by the word line, no current is generated on the word line, thereby eliminating the IR drop on the voltage input line (word line). In the current output link, the characteristic of the switching element operating in the saturation region effectively alleviates the influence of the voltage fluctuation on the current output line (source line) on the output current (computing current), thereby reducing the influence of IR drop on the current output line on the output current. Furthermore, the area and power consumption of the driving circuit for driving the word line and source line are also effectively reduced.

[0076] Figure 5 is a schematic diagram of a memory-computation integrated circuit provided by at least one embodiment of the present disclosure. For example, as shown in Figure 5, the memory-computation integrated circuit provided by the embodiment of the present disclosure includes the memory-computation integrated array, programming circuit module, and calculation circuit module as shown in Figure 4.

[0077] For example, the programming circuit module is electrically connected to the storage and computing integrated array, and is configured to implement programming operations and provide voltage signals required for programming.

[0078] For example, as shown in FIG5 , the programming circuit module includes a source line programming driving circuit 21, a word line programming driving circuit 22, and a bit line programming driving circuit 23. The source line programming driving circuit 21 is electrically connected to the m first source lines SL1 (SL1[1] to SL1[m]) to provide a first source line programming signal and a second source line programming signal; the word line programming driving circuit 22 is electrically connected to the n first word lines WL1 (WL1[1] to WL1[n]) and the n second word lines WL2 (WL2[1] to WL2[n]) to provide a first word line programming signal and a second word line programming signal; and the bit line programming driving circuit 23 is electrically connected to the n bit lines BL (BL[1] to BL[n]) to provide a bit line programming signal.

[0079] For example, the computing circuit module is electrically connected to the storage and computing integrated array and is configured to implement computing operations, including an input module and an output module.

[0080] For example, as shown in FIG5 , the input module includes an input buffer 31, a digital-to-analog conversion circuit 32, a multiplexer 33, and a word line driver circuit 34. The input buffer 31 is configured to store the input data of each row of the storage and computing integrated array. The digital-to-analog conversion circuit 32 and the multiplexer 33 are configured to perform digital-to-analog conversion on the input data of each row of the storage and computing integrated array to obtain corresponding first word line signals and second word line signals. For example, taking the nth row as an example, based on the input data of the nth row stored in the input buffer 31, the multiplexer 33 selects two voltage signals from the multiple analog voltages provided by the digital-to-analog conversion circuit 32 as the first word line signals and second word line signals corresponding to the nth row. The word line driver circuit 34 is configured to enhance the driving capability of the first word line signals and the second word line signals, and is electrically connected to n first word lines WL1 (WL1[1] to WL1[n]) and n second word lines WL2 (WL2[1] to WL2[n]) to provide enhanced first word line signals and second word line signals. The word line driving circuit 34 includes a unity gain amplifier, for example, a Class-AB unity gain amplifier or other amplifiers with the same characteristics, which is not limited in the present disclosure.

[0081] For example, as shown in FIG5 , the output module includes a source line driver circuit 41, an analog-to-digital conversion circuit 42, and an output buffer 43. The source line driver circuit 41 is electrically connected to m first source lines SL1 (SL1[1] to SL1[m]) and m second source lines SL2 (SL2[1] to SL2[m]) to provide first source line signals and second source line signals for clamping the source line voltage during the calculation process. The analog-to-digital conversion circuit 42 is electrically connected to the m first source lines SL1 and the m second source lines SL2, and is configured to convert the current signals on the m first source lines SL1 and the current signals on the m second source lines SL2 into digital signals. For example, the differential current signal from the first source line and the second source line is converted from an analog signal to a digital signal. The output buffer 43 is configured to store the conversion result of the analog-to-digital conversion circuit 42 and output it.

[0082] For example, the analog-to-digital conversion circuit 42 includes a plurality of differential analog-to-digital conversion circuits, and the plurality of differential analog-to-digital conversion circuits are electrically connected to the m first source lines SL1 and the m second source lines SL2 in a one-to-one correspondence.

[0083] FIG6 is a schematic diagram of a differential analog-to-digital conversion circuit according to at least one embodiment of the present disclosure. For example, as shown in FIG6 , each differential analog-to-digital conversion circuit includes a first sampling circuit 51, a second sampling circuit 52, and a successive approximation analog-to-digital conversion circuit 53. For example, each differential analog-to-digital conversion circuit further includes a timing control circuit (not shown) configured to provide a timing signal to the successive approximation analog-to-digital conversion circuit 53.

[0084] For example, as shown in FIG6 , the first sampling circuit 51 is configured to convert the current signal I on the first source line corresponding to the column into + Converted into voltage signal V + The second sampling circuit 52 is configured to receive the current signal I on the second source line corresponding to the column - Converted into voltage signal V - The successive approximation analog-to-digital conversion circuit 53 is configured to receive the voltage signal V output by the first sampling circuit and the second sampling circuit + and V - , and converted into digital signals.

[0085] For example, as shown in Figure 6, the first sampling circuit 51 includes a first current source IB.1, a first switching element NC.1, and a first capacitor C.1. The first switching element NC.1 is electrically connected to the first current source IB.1 and the first capacitor C.1, respectively, and is configured to open or close the connection between the first current source IB.1 and the first capacitor C.1 according to a control signal. When the control signal is low, the current signal flowing into the first switching element NC.1 is converted into a voltage signal V across the first capacitor C.1. +, thereby realizing the voltage sampling process. For example, the control signal can be provided by the above-mentioned timing control circuit. The first current source IB.1 is electrically connected to the first voltage terminal and the first source line respectively to realize the current steering, that is, the current signal flowing into the first switching element NC.1 is the same as the current signal on the first source line I + The direction is opposite to that of the first voltage terminal. For example, the first voltage terminal is a power supply. The first capacitor C.1 is electrically connected to the second voltage terminal and the output terminal of the first sampling circuit 51, and the sampled voltage V + The output is used as the input of the successive approximation analog-to-digital conversion circuit 53. For example, the second voltage terminal is ground (GND).

[0086] For example, as shown in Figure 6, the second sampling circuit 52 includes a second current source IB.2, a second switch element NC.2, and a second capacitor C.2. The second switch element NC.2 is electrically connected to the second current source IB.2 and the second capacitor C.2, respectively, and is configured to open or close the connection between the second current source IB.2 and the second capacitor C.2 according to a control signal. When the control signal is low, the current signal flowing into the second switch element NC.2 is converted into a voltage signal V across the second capacitor C.2. - , thereby realizing the voltage sampling process. For example, the control signal can be provided by the above-mentioned timing control circuit. The second current source IB.2 is electrically connected to the first voltage terminal and the second source line respectively to realize the current diversion, that is, the current signal flowing into the second switching element NC.2 is the same as the current signal on the second source line I - The direction is opposite to that of the first voltage terminal. For example, the first voltage terminal is a power supply. The second capacitor C.2 is electrically connected to the second voltage terminal and the output terminal of the second sampling circuit 52, and the sampled voltage signal V - The output is used as the input of the successive approximation analog-to-digital conversion circuit 53. For example, the second voltage terminal is ground (GND).

[0087] For example, as shown in FIG6 , the successive approximation analog-to-digital conversion circuit 53 includes a capacitive digital-to-analog converter 531, a comparator 532, and a control logic circuit 533. The capacitive digital-to-analog converter 531 is configured to be electrically connected to the output terminal of the first sampling circuit 51 and the output terminal of the second sampling circuit 52 to generate a voltage signal V + and V -As a differential input, the capacitive digital-to-analog converter 531 includes two switched capacitor circuits for generating an adjustable voltage. Each capacitor in the switched capacitor circuit can store a digital bit and simulate the change of the digital signal by changing its charge. The comparator 532 is electrically connected to the output end of the capacitive digital-to-analog converter 531 and is configured to compare the output voltage of the capacitive digital-to-analog converter 531, that is, the output voltage of the two switched capacitor circuits, and output the comparison result. The control logic circuit 533 is configured to receive the comparison result output by the comparator 532, control the capacitive digital-to-analog converter 531 according to the comparison result, and convert it using a successive approximation register (SAR) method. Specifically, the control logic circuit 533 adjusts the output voltage of the capacitive digital-to-analog converter 531 by controlling the switched capacitors. The output voltage of the capacitive digital-to-analog converter 531 will gradually approach the input signal over time, and eventually reach a state equal to the input signal. Finally, the control logic circuit 533 outputs the converted digital signal at the output end, that is, the differential current I + and I - The analog-to-digital conversion result.

[0088] At least one embodiment of the present disclosure further provides an electronic device comprising the storage-computing integrated circuit provided by at least one embodiment above. The electronic device may be, for example, a server or terminal device, such as a server, a computer, or a controller.

[0089] At least one embodiment of the present disclosure further provides an operating method for the storage-computing integrated unit as described above, comprising step S1 and step S2.

[0090] S1: applying a first source line voltage and a second source line voltage to a target operation unit, so that each switching element in the target operation unit operates in a saturation state.

[0091] For example, the target operation unit is a storage and computing integrated unit involved in the calculation, and the same clamping voltage is applied to its corresponding first source line and second source line respectively, and the bit line voltage is grounded. The clamping voltage makes each switching element in the storage and computing integrated unit operate in a saturation state.

[0092] S2: applying a first word line voltage and a second word line voltage to the target operation unit, so that each memristor element in the target operation unit operates in a linear region.

[0093] For example, the target operation unit is a storage-computing integrated unit involved in the calculation, and voltages are applied to the corresponding first word line and second word line respectively, so that each memristor element in the storage-computing integrated unit operates in the linear region, and the differential mode value of the first word line voltage and the second word line voltage is the calculation voltage, which can be mapped to a multiplier for the multiplication calculation.

[0094] Before step S1 and step S2, the operating method provided in at least one embodiment of the present disclosure further includes step S3:

[0095] S3: Apply a programming voltage to each weight unit of the target operation unit one by one, so that the resistance value of the memristor element of the first weight unit is equal to the resistance value of the memristor element of the second weight unit, and the resistance value of the memristor element of the third weight unit is equal to the resistance value of the memristor element of the fourth weight unit.

[0096] For example, the target operation unit is a storage-computation integrated unit that participates in the calculation, and programming verification operations are performed on each weight unit in the storage-computation integrated unit one by one. The programming operation can be, for example, the write operation on the memristor unit mentioned above, which will not be described in detail here. During the verification process, each weight unit is connected in the form of a source follower, and the word line voltage, source line voltage and bit line voltage applied to the weight unit are fixed values. Therefore, the current of the weight unit is uniquely corresponding to the resistance of the memristor element of the weight unit. By observing the current of each weight unit respectively, it can be determined whether the resistance of the memristor element of the first weight unit is equal to the resistance of the memristor element of the second weight unit, and whether the resistance of the memristor element of the third weight unit is equal to the resistance of the memristor element of the fourth weight unit.

[0097] The storage-computation-in-one unit provided in an embodiment of the present disclosure can implement multi-bit multiplication calculations. FIG7 is a schematic diagram of the storage-computation-in-one unit provided in at least one embodiment of the present disclosure implementing multi-bit multiplication calculations.

[0098] In step S2 , the multi-bit input data is mapped into a word line differential voltage, and a first word line voltage and a second word line voltage corresponding to the word line differential voltage are applied to the target operation unit.

[0099] For example, as shown in FIG7 , taking the input data as a signed 2-bit multiplier as an example, a signed 2-bit multiplier corresponds to 7 possible values, namely (-11, -10, -01, 00, 01, 10, 11), and the 7 possible values ​​are mapped from -V max to V max The 7 word line differential voltages ΔV that change at equal intervals WL A voltage is applied to the first word line and the second word line corresponding to the storage and computing integrated unit participating in the calculation, so that the differential modulus value of the first word line voltage and the second word line voltage is equal to the voltage mapped by the signed 2-bit multiplier.

[0100] In step S3, the multi-bit weight data is mapped to the slope of the calculated current of the target operation unit as the word line differential voltage changes, and a programming voltage is applied to each weight unit of the target operation unit one by one, so that the resistance value of the memristor element of each weight unit is programmed to meet the slope.

[0101] For example, by adjusting the resistance R of the memristor element of the first and second weight units + and the resistance R of the memristor element of the third and fourth weight units - Programming to control the calculation current ΔI of the memory-calculation unit along with the word line differential voltage ΔV WL The slope s of the change changes from positive to negative at equal intervals, which can enable a single storage and calculation unit to realize the storage of signed multi-bit multipliers (i.e., weight data), where the number of slopes is related to the number of bits of the weight data. For example, as shown in Figure 7, the weight data corresponds to another signed 2-bit multiplier in the multiplication calculation, and its 7 possible values ​​(-11, -10, -01, 00, 01, 10, 11) are mapped to max to s max 7 slopes that change at equal intervals. Among them, s max Refers to programming R + and R - The maximum slope that can be generated. The calculated current ΔI of the storage and calculation unit is the multiplication result of the signed 2-bit multiplier.

[0102] For example, in a multi-bit multiplication calculation, the operation method of setting the resistance value of each weight unit memristor may specifically include steps S31-S32:

[0103] S31: Obtaining the current ΔI that is calculated to follow the word line differential voltage ΔV WL When the changing slope s is distributed at equal intervals, the first resistance value and the second resistance value at each slope can be obtained by simulating the calculation current ΔI of the storage and computing integrated unit.

[0104] S32: Obtain the slope obtained by mapping the multi-bit weight data, and perform programming and verification operations on each weight unit in the storage and computing integrated unit one by one according to the first resistance value and the second resistance value corresponding to the slope, so that the resistance value of the memristor element of the first weight unit and the resistance value of the memristor element of the second weight unit are equal and equal to the first resistance value, and the resistance value of the memristor element of the third weight unit and the resistance value of the memristor element of the fourth weight unit are equal and equal to the second resistance value.

[0105] The programming operation can be, for example, the write operation on the memristor unit mentioned above, which will not be described in detail here. During the verification process, each weight unit is connected in the form of a source follower, and the word line voltage, source line voltage and bit line voltage applied to the weight unit are constant. Therefore, the current of the weight unit is uniquely corresponding to the resistance of the memristor element of the weight unit. By observing the current of each weight unit respectively, it can be determined whether the resistance of the memristor element of the first weight unit is equal to the resistance of the memristor element of the second weight unit and equal to the first resistance, and whether the resistance of the memristor element of the third weight unit is equal to the resistance of the memristor element of the fourth weight unit and equal to the second resistance.

[0106] One or more embodiments of the present disclosure provide a storage-computing integrated unit and operating method, a storage-computing integrated array, a storage-computing integrated circuit, and an electronic device, which have one or more of the following beneficial effects:

[0107] (1) The integrated storage and computing unit provided by at least one embodiment of the present disclosure uses a differential word line signal as an input signal and a differential output current as a computing current, thereby realizing a positive proportional change of the computing current with the input signal in a single integrated storage and computing unit. There is no need to add a circuit to compensate for the current offset value, thereby effectively reducing the additional overhead of the peripheral circuit.

[0108] (2) In at least one embodiment of the present disclosure, the memory-computing integrated array provides a word line connected to the control electrode of the switching element. Therefore, when a voltage is input to the word line, no current is generated on the word line, thereby eliminating IR drop on the voltage input line and further reducing the area and power consumption of the corresponding driving circuit.

[0109] (3) In the storage and computing integrated array provided by at least one embodiment of the present disclosure, the characteristic of the switching elements operating in the saturation region effectively alleviates the impact of voltage fluctuations on the current output line on the output current, thereby reducing the impact of IR drop on the current output line on the output current, and further reducing the area and power consumption of the corresponding driving circuit.

[0110] Although the present disclosure has been described in detail above using general descriptions and specific embodiments, it will be apparent to those skilled in the art that modifications or improvements may be made based on the embodiments of the present disclosure. Therefore, such modifications or improvements, as long as they do not depart from the spirit of the present disclosure, are within the scope of protection claimed by the present disclosure.

[0111] Regarding this disclosure, the following points need to be explained:

[0112] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0113] (2) For the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness of layers or regions is exaggerated or reduced, that is, these drawings are not drawn according to the actual scale.

[0114] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0115] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A memory - in - computing unit, comprising: Four weight units, wherein each of the four weight units includes a memristor element and a switching element. The memristor element includes a first electrode and a second electrode, and the switching element includes a control electrode, a first pole, and a second pole. The first pole of the switching element is electrically connected to the first electrode of the memristor element; The control electrode of the switching element of the first weight unit is electrically connected to the control electrode of the switching element of the fourth weight unit, serving as the first end of the memory - in - computing unit for receiving a first word - line signal; The control electrode of the switching element of the second weight unit is electrically connected to the control electrode of the switching element of the third weight unit, serving as the second end of the memory - in - computing unit for receiving a second word - line signal; The second pole of the switching element of the first weight unit is electrically connected to the second pole of the switching element of the third weight unit, serving as the third end of the memory - in - computing unit for receiving a first source - line signal; The second pole of the switching element of the second weight unit is electrically connected to the second pole of the switching element of the fourth weight unit, serving as the fourth end of the memory - in - computing unit for receiving a second source - line signal; The second poles of the four switching elements are electrically connected to each other, serving as the fifth end of the memory - in - computing unit for receiving a bit - line signal.

2. The memory - in - computing unit according to claim 1, wherein, The resistance value of the memristor element of the first weight unit is equal to the resistance value of the memristor element of the second weight unit; The resistance value of the memristor element of the third weight unit is equal to the resistance value of the memristor element of the fourth weight unit.

3. The memory - in - computing unit according to claim 1 or 2, wherein, The switching element of the first weight unit and the switching element of the second weight unit have the same switching current characteristics; The switching element of the third weight unit and the switching element of the fourth weight unit have the same switching current characteristics.

4. A memory - in - computing array, comprising: A plurality of memory - in - computing units as described in any one of claims 1 - 3, wherein the plurality of memory - in - computing units are arranged in a plurality of memory - in - computing unit rows and a plurality of memory - in - computing unit columns along a first direction and a second direction; A plurality of first word - lines extending along the first direction and connected to the plurality of memory - in - computing unit rows in a one - to - one correspondence. Each of the plurality of first word - lines is electrically connected to the first end of a corresponding memory - in - computing unit row to provide the first word - line signal; A plurality of second word - lines extending along the first direction and connected to the plurality of memory - in - computing unit rows in a one - to - one correspondence. Each of the plurality of second word - lines is electrically connected to the second end of a corresponding memory - in - computing unit row to provide the second word - line signal; A plurality of first source - lines extending along the second direction and connected to the plurality of memory - in - computing unit columns in a one - to - one correspondence. Each of the plurality of first source - lines is electrically connected to the third end of a corresponding memory - in - computing unit column to provide the first source - line signal; A plurality of second source lines extending along the second direction and respectively connected to the plurality of in-memory computing unit columns in one-to-one correspondence, wherein each of the plurality of second source lines is electrically connected to the fourth end of a corresponding in-memory computing unit column to provide the second source line signal; A plurality of bit lines extending along the first direction and respectively connected to the plurality of in-memory computing unit rows in one-to-one correspondence, wherein each of the plurality of bit lines is electrically connected to the fifth end of a corresponding in-memory computing unit row to provide the bit line signal.

5. An in-memory computing circuit, comprising the in-memory computing array as claimed in claim 4, a computing circuit module, and a programming circuit module; The computing circuit module is electrically connected to the in-memory computing array and is configured to implement a computing operation, including an input module and an output module; The programming circuit module is electrically connected to the in-memory computing array and is configured to implement a programming operation.

6. The in-memory computing circuit according to claim 5, wherein, The input module includes: An input buffer configured to store the input data of each row of the in-memory computing array; A digital-to-analog conversion circuit and a multiplexer configured to perform digital-to-analog conversion on the input data of each row of the in-memory computing array to obtain corresponding first word line signals and second word line signals; A word line driving circuit configured to enhance the driving capabilities of the first word line signal and the second word line signal, and electrically connected to the plurality of first word lines and the plurality of second word lines to provide enhanced first word line signals and second word line signals.

7. The in-memory computing integrated circuit according to claim 5 or 6, wherein The output module includes: A source line driving circuit electrically connected to the plurality of first source lines and the plurality of second source lines to provide the first source line signal and the second source line signal; An analog-to-digital conversion circuit electrically connected to the plurality of first source lines and the plurality of second source lines and configured to convert the current signals on the plurality of first source lines and the current signals on the plurality of second source lines into digital signals; An output buffer configured to store the conversion result of the analog-to-digital conversion circuit and output it.

8. The in-memory computing integrated circuit according to any one of claims 5-7, wherein, The programming circuit module includes: A source line programming driving circuit electrically connected to the plurality of first source lines and the plurality of second source lines to provide first source line programming signals and second source line programming signals; A word line programming driving circuit electrically connected to the plurality of first word lines and the plurality of second word lines to provide first word line programming signals and second word line programming signals; A bit line programming driving circuit electrically connected to the plurality of bit lines to provide bit line programming signals.

9. The in-memory computing circuit according to claim 7, wherein, The analog-to-digital conversion circuit includes a plurality of differential analog-to-digital conversion circuits, the plurality of differential analog-to-digital conversion circuits are electrically connected to the plurality of first source lines and the plurality of second source lines in one-to-one correspondence, and each of the plurality of differential analog-to-digital conversion circuits includes: A first sampling circuit configured to convert the current signal on the first source line corresponding to the column where it is located into a voltage signal; A second sampling circuit configured to convert the current signal on the second source line corresponding to the column where it is located into a voltage signal; A successive approximation analog-to-digital conversion circuit configured to receive the voltage signals output by the first sampling circuit and the second sampling circuit and convert them into digital signals.

10. The in-memory computing circuit according to claim 9, wherein, The successive approximation analog-to-digital conversion circuit includes: A capacitive digital-to-analog converter, configured to be electrically connected to the output terminal of the first sampling circuit and the output terminal of the second sampling circuit; A comparator, electrically connected to the output terminal of the capacitive digital-to-analog converter, configured to compare the output voltage of the capacitive digital-to-analog converter and output a comparison result; A control logic circuit, configured to receive the comparison result output by the comparator, control the capacitive digital-to-analog converter according to the comparison result, perform conversion in a successive approximation manner and output a converted digital signal at the output terminal.

11. The memory and computing integrated circuit according to claim 9 or 10, wherein, The first sampling circuit includes a first current source, a first switching element, and a first capacitor; The first switching element is electrically connected to the first current source and the first capacitor respectively, and is configured to conduct or disconnect the connection between the first current source and the first capacitor according to the control of a control signal; The first current source is electrically connected to a first voltage terminal and the first source line respectively; The first capacitor is electrically connected to a second voltage terminal and the output terminal of the first sampling circuit respectively; The second sampling circuit includes a second current source, a second switching element, and a second capacitor; The second switching element is electrically connected to the second current source and the second capacitor respectively, and is configured to conduct or disconnect the connection between the second current source and the second capacitor according to the control of a control signal; The second current source is electrically connected to the first voltage terminal and the second source line respectively; The second capacitor is electrically connected to the second voltage terminal and the output terminal of the second sampling circuit respectively.

12. An operation method of a memory and computing integrated unit according to any one of claims 1-3, including: Applying a first source line voltage and a second source line voltage to a target operation unit to make each switching element in the target operation unit operate in a saturation state; Applying a first word line voltage and a second word line voltage to the target operation unit to make each memristor element in the target operation unit operate in a linear region.

13. According to the operation method of claim 12, it further includes: Applying a programming voltage to each weight unit of the target operation unit one by one, so that the resistance value of the memristor element of the first weight unit is equal to the resistance value of the memristor element of the second weight unit, and the resistance value of the memristor element of the third weight unit is equal to the resistance value of the memristor element of the fourth weight unit.

14. According to the operation method of claim 13, it further includes: Mapping multi-bit weight data to the slope of the calculation current of the target operation unit changing with the word line differential voltage Applying a programming voltage to each weight unit of the target operation unit one by one to program the resistance values of the memristor elements of each weight unit to meet the slope.

15. The operating method according to any one of claims 12-14, wherein The applying a first word line voltage and a second word line voltage to the target operation unit includes: Mapping multi-bit input data to a word line differential voltage, and applying the first word line voltage and the second word line voltage corresponding to the word line differential voltage to the target operation unit.

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