Circuit board, and semiconductor package comprising same

Abstract

The circuit board according to an embodiment may comprise: an insulating layer; a wiring layer disposed on the insulating layer; and metal oxide layers disposed on the lower and side surfaces of the wiring layer. The thickness of the metal oxide layer disposed on the lower surface of the wiring layer may vary in the horizontal direction.

Description

Circuit boards and semiconductor packages including the same

[0001] The present invention relates to a circuit board and a semiconductor package including the same.

[0002] As the performance of electrical and electronic products continues to improve, technologies are being proposed and researched to accommodate a greater number of semiconductor devices on circuit boards of limited size. However, conventional semiconductor packages typically consist of a single semiconductor device, limiting their ability to achieve desired performance.

[0003] Accordingly, semiconductor packages that utilize multiple substrates to accommodate multiple semiconductor devices have recently been developed. These semiconductor packages have a structure in which multiple semiconductor devices are connected horizontally and / or vertically on the substrate. Consequently, semiconductor packages offer the advantages of efficiently utilizing the mounting area of ​​semiconductor devices and enabling high-speed signal transmission through short signal transmission paths between semiconductor devices.

[0004] Due to these advantages, semiconductor packages such as these are widely used in mobile devices, etc.

[0005] In addition, semiconductor packages used in products that provide the Internet of Things (IoT), autonomous vehicles, and high-performance servers are demanding high-performance and high-reliability circuit boards in line with the trend toward high integration.

[0006] Meanwhile, in the prior art, a circuit board includes an insulating layer and a circuit layer disposed on the insulating layer. For example, in the prior art, a circuit board may mean a circuit layer disposed on an insulating layer, in which a mounting location for each semiconductor device is predetermined for mounting at least one semiconductor device, and a circuit layer connected to the semiconductor device is connected. The circuit layer may include a via electrode (or via) and a wiring layer (or circuit pattern layer). The semiconductor device is mounted on the circuit board and can transmit and receive signals through the circuit layer.

[0007] Meanwhile, with the recent advancement of portable electronic devices and other devices, the frequency of signals is increasing to enable high-speed processing of large amounts of information, and circuit boards suitable for high-frequency applications are in demand.

[0008] These circuit boards must satisfy conditions (e.g., adhesion, crack resistance, low stress, and low high-temperature gas generation) that can minimize various stresses and delamination occurring at the interface between the insulating layer and the wiring layer.

[0009] The technical problem of the present invention is to provide a circuit board having high reliability by improving the adhesion between a wiring layer and an insulating layer.

[0010] A circuit board according to an embodiment may include an insulating layer, a wiring layer disposed on the insulating layer, and a metal oxide layer disposed on a bottom surface and a side surface of the wiring layer.

[0011] Additionally, the thicknesses of the metal oxide layer disposed on the lower surface of the wiring layer may be different in the horizontal direction.

[0012] In addition, in the thickness of the metal oxide layer disposed on the lower surface of the wiring layer, the thickness of the metal oxide layer overlapping between the center and the upper and lower portions of the wiring layer may be different from the thickness of the metal oxide layer overlapping between the upper and lower portions of the outer portion of the wiring layer.

[0013] Additionally, the metal oxide layer may include a first metal oxide layer disposed between the insulating layer and the wiring layer and a second metal oxide layer surrounding a side surface of the wiring layer.

[0014] Additionally, the thickness of the first metal oxide layer may increase from the center of the wiring layer toward the outside.

[0015] Additionally, the insulating layer may include unevenness.

[0016] Additionally, the first metal oxide layer may be disposed between the unevenness of the insulating layer and the wiring layer.

[0017] Additionally, the insulating layer includes a filler, and the filler can be in contact with the first metal oxide layer.

[0018] Additionally, the filler may be horizontally overlapped with either the first metal oxide layer or the wiring layer.

[0019] Additionally, the thickness of the first metal oxide layer may be 30 to 100 nm.

[0020] Additionally, the insulating layer may include a roughness, and the roughness may include a filler.

[0021] Additionally, the metal oxide layer can be formed at a curing temperature of 150 to 300˚C.

[0022] According to the circuit board of the embodiment of the invention and the circuit board including the same, the adhesion between the wiring layer and the insulating layer can be improved by controlling the thickness of the metal oxide layer formed between the wiring layer and the insulating layer.

[0023] For example, referring to FIG. 2b, when a harmony (CZ) treatment process is performed after seed layer flash etching for forming a second wiring layer (120), there was an issue of an undercut (S) occurring between the second wiring layer and the second insulating layer (110).

[0024] To solve this problem, the embodiment has a technical effect of improving the adhesion between the metal oxide layer (180) and the second wiring layer (120) by performing a baking process in an oxygen (O2) atmosphere, as shown in FIG. 2d, so that the third metal oxide layer (183) fills the gap (S) between the second-first wiring layer (120a) and the second insulating layer (110).

[0025] Figure 1 is a drawing showing a circuit board according to an embodiment.

[0026] FIG. 2a illustrates a seed layer etching process for some areas, for example, a first area (A1), during a manufacturing process of a circuit board according to the embodiment illustrated in FIG. 1.

[0027] Fig. 2b illustrates a process for forming a metal oxide film for a first region (A1) during a manufacturing process of a circuit board according to an embodiment.

[0028] Figure 2c illustrates a CZ etching process for a first area (A1) during a manufacturing process of a circuit board according to an embodiment.

[0029] Fig. 2d illustrates a baking process for a first region (A1) during a manufacturing process of a circuit board according to an embodiment. Fig. 2e is an enlarged view of a second region (A2) in Fig. 2d.

[0030] Figure 3 shows an FIB photograph in a manufacturing process of a circuit board according to an embodiment.

[0031] Figure 4 shows the change in thickness of the metal oxide layer according to the curing temperature of the circuit board of the embodiment.

[0032] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the attached drawings.

[0033] However, the technical idea of ​​the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

[0034] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by those of ordinary skill in the technical field to which the present invention pertains, unless explicitly and specifically defined and described. Commonly used terms, such as terms defined in a dictionary, may have their meanings interpreted in consideration of the contextual meaning of the relevant technology. In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention.

[0035] In this specification, singular forms may also include plural forms unless specifically stated otherwise in the phrase, and when it is described as “A and / or at least one (or more) of B, C,” it may include one or more of all combinations that can be combined with A, B, and C. In addition, terms such as first, second, A, B, (a), (b), etc. may be used to describe components of embodiments of the present invention.

[0036] In this specification, for the convenience of explanation, components may be described in the horizontal direction and the vertical direction. The vertical direction means the top (above) or bottom (below) of each component, and the horizontal direction means the direction perpendicular to the vertical direction. In addition, the horizontal direction may include a first horizontal direction and a second horizontal direction. Here, when the horizontal direction follows a Cartesian coordinate system, the first horizontal direction may mean the X-axis, the second horizontal direction may mean the Y-axis, and the vertical direction may mean the Z-axis. When following a cylindrical coordinate system, the first horizontal direction may mean a direction along an azimuth, and the second horizontal direction may mean a direction toward a radius, and these may be selectively used in combination. In addition, the direction along an azimuth may be referred to as a circumferential direction, and the direction toward a radius may be referred to as a centrifugal direction.

[0037] These terms are only intended to distinguish the component from other components, and are not intended to limit the nature, order, or sequence of the component by the term. In addition, when a component is described as being "connected," "coupled," or "connected" to another component, it may include not only cases where the component is directly connected, coupled, or connected to the other component, but also cases where the component is "connected," "coupled," or "connected" by another component between the component and the other component.

[0038] Additionally, the statement that component A is exposed from component B should be understood to mean that component A is exposed from component B, not that component A is exposed from the entire product. That is, when it is stated that component A is exposed from component B, it should be understood to mean that component A is at least partially covered by component C.

[0039] Additionally, when it is described that a component A is in "contact" with a component B, it may include not only cases where that component is in "contact" with the other component directly, but also cases where that component is "contacted" by another component between that component and the other component. Thus, if a component A is to be understood to be in "direct contact" with a component B, it is described as being in "direct contact."

[0040] In addition, when it is written that configuration A is 'covered' by configuration B, it should be understood that configuration A is covered by configuration B, and that the part for the function and purpose to be solved is covered, and unless there are special circumstances, it should not be understood that the entire configuration A is covered by configuration B.

[0041] In addition, when it is described that configuration A is 'fixed' to configuration B, it should be understood that configuration A is not only directly coupled to configuration B and fixed, but also indirectly fixed to configuration B through configuration C and / or configuration D, etc., unless otherwise specified, taking into account the function and purpose to be solved, and when configuration A is only understood to be 'directly fixed' to configuration B, it is described as being 'directly fixed'.

[0042] Additionally, when it is described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Furthermore, when it is expressed as "above" or "below", it can include the meaning of the downward direction as well as the upward direction based on one component.

[0043] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0044]

[0045] Fig. 1 is a drawing showing a circuit board (100) according to an embodiment.

[0046] Referring to FIG. 1, a circuit board (100) according to an embodiment includes a build-up insulator (110N), a build-up wiring body (120C), and a protective layer (150), and the build-up wiring body (120C) includes a via electrode (130).

[0047] The build-up insulator (110N) includes a single or multiple insulating layers. For example, the build-up insulator (110N) may include, but is not limited to, a first insulating layer (105), a second insulating layer (110), and a third insulating layer (115), and the number of layers is not limited.

[0048] The first insulating layer (105), the second insulating layer (110), and the third insulating layer (115) may include the same insulating material, or at least one different insulating material, but is not limited thereto. In addition, the first insulating layer (105) may be the core layer (105), but is not limited thereto. In addition, the second insulating layer (110) may be an upper build-up insulator disposed on the first insulating layer (105), and the third insulating layer (115) may be a lower build-up insulator disposed under the first insulating layer (105).

[0049]

[0050]

[0051] For example, the build-up insulator (110N) of the circuit board (100) may be a photocurable material, and may include, for example, photosensitive polyimide, liquid photoimageable solder resist (LPI), photosensitive epoxy, and photosensitive acrylic.

[0052] As another example, the build-up insulator (110N) of the circuit board (100) may be a thermosetting material, and may include, for example, an epoxy resin, a polyimide, a phenolic resin, a bismaleimide-triazine (BT) resin, a silicone resin, or an Ajinomoto build-up film (ABF).

[0053] In addition, the insulating layer (110N) may include an optically isotropic film, for example, the first insulating layer (105) may include a cyclic olefin copolymer (COC), a cyclic olefin polymer (COP), an optically isotropic polycarbonate (PC), or an optically isotropic polymethyl methacrylate (PMMA). According to an embodiment, the build-up insulator (110N) may include a core layer (105). The core layer may function to secure the overall mechanical rigidity of the circuit board and suppress warpage. Since both warpage occurring during the process and warpage occurring during the operation of the product can be suppressed, the core layer (105) may improve the yield of the circuit board and improve the reliability of the circuit board.

[0054] The core layer (105) may include a reinforcing member such as glass fiber extending in the horizontal direction and a resin covering the same, and the mechanical rigidity may be adjusted according to the density of the reinforcing member. The reinforcing members of the core layer (105) may be provided in the resin layer by being laminated and spaced apart from each other in the vertical direction. According to another embodiment, the core layer (105) may be provided with glass. When provided with glass, the density of the via electrodes (130) penetrating the core layer (105) can be increased, and the gap between the via electrodes (130) can be easily controlled. In addition, the circuit board can be made thinner due to higher mechanical rigidity than a resin including glass fiber. The core layer (105) may be freely selected and used as long as it can secure mechanical rigidity without being limited to the above-described material in consideration of yield, price, etc.

[0055] The build-up insulator (110N) may include an upper build-up insulator (110) disposed on the upper surface of the core layer (105), and a lower build-up insulator (115) disposed on the lower surface of the core layer (105). The upper build-up insulator (110) and the lower build-up insulator (115) each have a function for disposing a circuit layer, a function for securing insulation between circuits, and a function for controlling impedance or insertion loss due to the circuit, and may be freely selected from among the thermosetting resin or photocurable resin described above in consideration of dielectric constant, mechanical rigidity, and processability.

[0056] In addition, the circuit board (100) may be a coreless board in which the build-up insulator (110N) does not include a core. For example, the circuit board (100) may include an organic material that does not include a reinforcing member that enables miniaturization of the build-up wiring body (120C). For example, the first insulating layer (105) may use ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., and FR-4, BT (Bismaleimide Triazine), PID (Photo Imagable Dielectric resin), BT, etc. may be used.

[0057]

[0058] Meanwhile, the circuit board (100) of the embodiment may include a first protective layer (151) disposed on the upper surface of the build-up insulator (110N) and a second protective layer (152) disposed on the lower surface of the build-up insulator (110N).

[0059] The first protective layer (151) and the second protective layer (152) can function to protect the upper and lower surfaces of the build-up insulator (110N).

[0060] The first protective layer (151) and the second protective layer (152) may be resist layers. Preferably, the first protective layer (151) and the second protective layer (152) may be solder resist layers containing an organic polymer material. For example, the first protective layer (151) and the second protective layer (152) may contain an epoxy acrylate series resin. In detail, the first protective layer (151) and the second protective layer (152) may contain a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic series monomer, etc. However, the embodiment is not limited thereto, and the first protective layer (151) and the second protective layer (152) may of course be any one of a photosolder resist layer, a cover-lay, and a polymer material.

[0061] Next, the circuit board (100) may include a build-up wiring body (120C). The build-up wiring body (120C) includes wiring layers (120, 122) arranged on the surface of each insulating layer, and via electrodes for vertically connecting each wiring layer. In addition, the wiring layers include pads for connecting to the circuit layers, via electrodes, and / or semiconductor devices and / or capacitors. The pads may refer to protrusions that are connected to the circuit layers, but whose horizontal widths are different from those of the circuit layers. The wiring layers of the build-up wiring body (120C) may be arranged on the surface of each insulating layer of the build-up insulator (110N). For example, when the build-up insulator (110N) has a five-layer structure, the wiring layers (120, 122) of the build-up wiring body (120C) may be arranged on the surfaces of the five insulating layers, respectively.

[0062] The build-up wiring body (120C) includes a second wiring layer (120) disposed on a core layer (105) or a second insulating layer (110) and a first wiring layer (122) disposed under the core layer (105) or a third insulating layer (115).

[0063] Additionally, the wiring layer (120, 122) of the build-up wiring body (120C) may include a reinforcing electrode (124) that is electrically and / or physically separated from the signal electrode (123). The reinforcing electrode (124) may mean a dummy electrode that is physically and / or electrically separated from the signal electrode (123). However, the embodiment is not limited thereto. The reinforcing electrode (124) may be electrically connected to the signal electrode (123), and for example, may be connected to a ground electrode included in the signal electrode (123).

[0064]

[0065] Next, the via electrode (130) can penetrate the build-up insulator (110N). The via electrode (130) can vertically connect build-up wiring bodies arranged on different layers. For example, the via electrode can connect each of the first wiring layers (122) or each of the second wiring layers (120). In addition, the first wiring layer (122) and the second wiring layer (120) can be connected.

[0066] The via electrode (130) can be formed by filling the inside of a through hole penetrating the build-up insulator (110N) with a conductive material.

[0067] Through-holes can be formed by any of the following processing methods: mechanical, laser, or chemical. When forming through-holes by mechanical processing, methods such as milling, drilling, and routing can be used. Furthermore, when forming through-holes by laser processing, UV or CO2 lasers can be used. Furthermore, when forming through-holes by chemical processing, chemicals such as aminosilanes and ketones can be used.

[0068] Once a through hole is formed, the inside of the through hole can be filled with a conductive material to form a via electrode (130). The metal material forming the via electrode can be any one material selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd). In addition, the filling of the conductive material can utilize any one of electroless plating, electrolytic plating, screen printing, sputtering, evaporation, inkjetting, and dispensing, or a combination thereof.

[0069] Meanwhile, in the circuit board (100) according to the embodiment, the via electrode (130) penetrating the core layer (105) may include an insulating member (140). The insulating member (140) may be provided to fill a portion of a through hole penetrating the core layer. The insulating member (140) may also be referred to as a hole plugging member. The insulating member (140) may include an insulating material provided in the through hole of the core layer. For example, the insulating member (140) may include a paste of an insulating ink material. For example, the insulating member (140) may include a plugging ink. However, the embodiment is not limited thereto. For example, the insulating member (140) may include a conductive material. Specifically, the insulating member (140) may include a conductive paste containing a conductive metal powder.

[0070]

[0071] Any one of the above-described build-up wiring bodies (120C) may have an ETS (Embedded Trace Substrate) structure. For example, the build-up wiring body arranged on the upper surface of the circuit board (100) may have an ETS structure. For example, the build-up wiring body arranged on the upper surface of the circuit board (100) may be arranged in a recess provided on the upper surface of the uppermost second insulating layer (110). The ETS structure may also be referred to as a buried structure. The ETS structure is advantageous for miniaturization compared to a build-up wiring body having a general protruding structure. Accordingly, the embodiment enables the formation of electrodes corresponding to the size and pitch of terminals provided in a semiconductor device. Through this, the embodiment can improve the circuit integration. Furthermore, the embodiment can minimize the transmission distance of a signal transmitted through a semiconductor device, thereby minimizing signal transmission loss.

[0072] In addition, the build-up wiring body (120C) may be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). In addition, the build-up wiring body (120C) may be formed of a paste or solder paste including at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn) having excellent bonding strength. Preferably, the build-up wiring body (120C) may be formed of copper (Cu) which has high electrical conductivity and is relatively inexpensive.

[0073]

[0074] Meanwhile, the circuit board (100) according to the embodiment may further include a protrusion (191). The protrusion (191) may be disposed on the signal electrode (123) of the build-up wiring body (120C). The protrusion (191) may be disposed to protrude upward on the signal electrode disposed at the uppermost side among the build-up wiring bodies (120C). However, the embodiment is not limited thereto. For example, the protrusion (191) may be disposed to protrude downward on the lower surface of the signal electrode disposed at the lowermost side among the build-up wiring bodies (120C). The protrusion (191) may be referred to as a bump, a post, or a pillar.

[0075]

[0076] FIGS. 2A to 2D may be manufacturing process diagrams of a portion of a circuit board according to the embodiment illustrated in FIG. 1, for example, a first portion (A1).

[0077] Specifically, FIG. 2a illustrates a seed layer etching process of a first region (A1) during a manufacturing process of a circuit board according to an embodiment, FIG. 2b illustrates a process of forming a metal oxide film of a first region (A1) during a manufacturing process of a circuit board according to an embodiment, FIG. 2c illustrates a CZ etching process of a first region (A1) during a manufacturing process of a circuit board according to an embodiment, and FIG. 2d illustrates a baking process of a first region (A1) during a manufacturing process of a circuit board according to an embodiment.

[0078] Referring to Fig. 2a, Fig. 2a illustrates a seed layer etching process of a first region (A1) among the manufacturing processes of a circuit board according to an embodiment. Accordingly, Fig. 2a may be in a state in which a lamination process, a via formation process, a desmear process, an electroless plating (chemical copper) process, a patterning process, an electroplating (electrolytic copper) process, a dry film (DFR) strip, and a seed flash etching process are performed.

[0079] The second insulating layer (110) of the circuit board (100) according to the embodiment may include ABF resin. In addition, the second insulating layer (110) may include a filler (111), and the upper surface of the second insulating layer (110) may include unevenness (110a) formed by a desmear process.

[0080] A second wiring layer (120) may be disposed on a second insulating layer (110). The second wiring layer (120) may include copper (Cu) metal. The second wiring layer (120) may include a 2-1 wiring layer (120a) in contact with the second insulating layer (110) and a 2-2 wiring layer (120b) disposed on the 2-1 wiring layer (120a). The 2-1 wiring layer (120a) may be chemical copper, and the 2-2 wiring layer (120b) may be electrolytic copper. The 2-1 wiring layer (120a) may be formed in an electroless plating process, and the 2-2 wiring layer (120b) may be formed in an electrolytic plating process. The circuit board illustrated in FIG. 2a may be formed immediately after a seed flash etching process has been performed, and may have an unnecessary portion of the metal seed layer removed.

[0081] The unevenness (110a) on the second insulating layer (110) can increase the surface area of ​​the second insulating layer (110) and the second wiring layer (120) to improve the adhesive strength.

[0082] Next, referring to FIG. 2b, a curing process of a circuit board according to an embodiment is performed. At this time, the curing process may be performed in an oxygen (O2) atmosphere.

[0083] In the curing process of the circuit board, a metal oxide layer (180) covering the second wiring layer (120) may be formed. The metal oxide layer (180) may include a first metal oxide layer (181) disposed between the second insulating layer (110) and the second wiring layer (120) and a second metal oxide layer (182) covering at least one of a side surface or an upper surface of the second wiring layer (120).

[0084] The metal oxide layer (180) can improve the adhesion with the second insulating layer (110) and strengthen the insulation between adjacent wires. The metal oxide layer (180) can include a Cu oxide component, for example, CuO, Cu2O. In addition, when the second wiring layer (120) uses an RCC (Resin coated copper) material, the metal oxide layer (180) can include a Cr oxide component, for example, Cr2O, due to the rust-preventing (SiH4) component of the RCC material.

[0085] In the conventional curing process, the circuit board was cured in a nitrogen (N2) atmosphere to form a thin metal oxide layer (180) formed around the second wiring layer (120).

[0086] On the other hand, in the curing process of the circuit board according to the embodiment, the thickness of the metal oxide layer (180) can be controlled according to the curing temperature by performing the curing process in oxygen (O2).

[0087] The curing process of the circuit board can be performed at a temperature of 180 to 300˚C. The thickness of the metal oxide layer (180) can be thickened depending on the curing temperature. For example, the thickness of the metal oxide layer (180) can be formed to be 30 to 100 nm. When the thickness of the metal oxide layer (180) is less than 30 nm, the adhesive strength with the second insulating layer (110) may be reduced, which may cause lift-off defects in the circuit wiring. In addition, when the thickness of the metal oxide layer (180) exceeds 100 nm, the brittleness of the metal oxide layer increases, so that when an external force is applied, the adhesive strength cannot be maintained, and instead, the adhesive strength with the second insulating layer (110) may be reduced. In addition, when the thickness of the initial metal oxide layer becomes thicker than 100 nm, the reactivity increases during Cu etching, which may cause a problem of lift-off of the circuit wiring.

[0088] In detail, the first metal oxide layer (181) can improve adhesion by filling the gap between the second insulating layer (110) and the second-first wiring layer (120a).

[0089] The first metal oxide layer (181) can be horizontally overlapped with the unevenness (110a). The first metal oxide layer (181) and the second metal oxide layer (182) can improve the adhesion between the first metal oxide layer (181) and the second metal oxide layer (182) by recrystallizing the interface through an annealing process.

[0090] Next, referring to FIG. 2c, a circuit board (100) according to an embodiment may undergo a harmonized (CZ) processing process.

[0091] Meanwhile, a portion of the second-first wiring layer (120a) and a portion of the first metal oxide layer (181) may be etched by the CZ treatment process. On the other hand, the second metal oxide layer (182) may be etched entirely or partially by the CZ treatment.

[0092] For example, a portion of the 2-1 wiring layer (120a) and a portion of the first metal oxide layer (181) are etched to create an undercut between the 2-1 wiring layer (120a) and the second insulating layer (110), thereby creating a gap (S) between the 2-1 wiring layer (120a) and the second insulating layer (110), thereby reducing the contact area between the two. In detail, the first metal oxide layer (181) may be etched so that only the central portion (181b) overlapping the central portion of the 2-1 wiring layer (120a) remains.

[0093] For example, the 2-1 wiring layer (120a) may have a 'U' shape that is curved in an outward direction from the center of the 2-1 wiring layer (120a).

[0094] Accordingly, in order to improve the adhesion between the 2-1 wiring layer (120a) and the second insulating layer (110), as shown in FIG. 2d, a baking process is performed in an oxygen (O2) atmosphere, and a third metal oxide layer (183) is formed on the bottom, side, and upper surface of the second wiring layer (120), thereby improving the adhesion between the metal oxide layer (180) and the second wiring layer (120).

[0095] For example, as the third metal oxide layer (183) is filled in the gap (S) between the second-first wiring layer (120a) and the second insulating layer (110), the adhesion between the metal oxide layer (180) and the second wiring layer (120) can be improved.

[0096] Figure 2e is an enlarged view of the second area (A2) in Figure 2d.

[0097] At this time, the thickness of the metal oxide layer (180) may increase in the outward direction from the central portion of the 2-1 wiring layer (120a).

[0098] For example, the second thickness (T2) of the third metal oxide layer (183) overlapping the outer portion of the 2-1 wiring layer (120a) may be thicker than the first thickness (T1) of the central portion (181b) of the first metal oxide layer (181) overlapping the central portion of the 2-1 wiring layer (120a).

[0099] According to internal technology, there was an issue in which an undercut occurred between the second wiring layer and the second insulating layer (110) due to the harmonic (CZ) treatment process after seed layer flash etching for forming the second wiring layer (120).

[0100] To solve this problem, the embodiment has a technical effect of improving the adhesion between the metal oxide layer (180) and the second wiring layer (120) by performing a baking process in an oxygen (O2) atmosphere, as shown in FIG. 2d, so that the third metal oxide layer (183) fills the gap (S) between the second-first wiring layer (120a) and the second insulating layer (110).

[0101] Figure 3 shows an FIB photograph in a manufacturing process of a circuit board according to an embodiment.

[0102] Figure 3(a) illustrates an interface between a 2-1 wiring layer (120a) and a 2nd insulating layer (110) in a curing process of a circuit board (100). A 1st metal oxide layer (181) may be formed between the 2-1 wiring layer (120a) and the 2nd insulating layer (110). The surface area in contact with the 2-1 wiring layer (120a) may increase due to the uneven shape of the 2nd insulating layer (110). The 1st metal oxide layer (181) may be in contact with the 2nd insulating layer (110) and may improve adhesion with the 2nd insulating layer (110).

[0103] Fig. 3(b) illustrates the interface between the 2-1 wiring layer (120a) and the 2nd insulating layer (110) during the CZ processing process of the circuit board. Undercuts may occur (area O) due to the CZ processing process. In the area where undercuts occur, the 1st metal oxide layer (181) may be etched away and may not exist. The more areas where undercuts occur, the lower the adhesion between the 2-1 wiring layer (120a) and the 2nd insulating layer (110).

[0104] Fig. 3(c) illustrates the interface between the second-first wiring layer (120a) and the second insulating layer (110) in the baking process of the circuit board. By performing the baking process at a temperature of about 150 to 300 degrees and in an oxygen (O2) atmosphere, the third metal oxide layer (183) can be filled in the area where undercuts occur. For example, the baking process temperature may be in the range of about 180 to 300 degrees, but is not limited thereto.

[0105] Accordingly, the embodiment has a technical effect of improving the adhesion between the metal oxide layer (180) and the second wiring layer (120) by filling the gap (S) between the 2-1 wiring layer (120a) and the second insulating layer (110) with the third metal oxide layer (183) by performing a baking process in an oxygen (O2) atmosphere.

[0106] In the processes of FIG. 3(a) to FIG. 3(c), at least one of the fillers (111) may overlap horizontally with the 2-1 wiring layer (120a) and the first metal oxide layer (181). The filler (111) may increase the mechanical strength of the second insulating layer (110). At least one of the fillers (111) may overlap horizontally at the interface between the first metal oxide layer (181) and the 2-1 wiring layer (120a). As a result, peeling due to a difference in thermal expansion coefficient between the first metal oxide layer (181) and the 2-1 wiring layer (120a) may be suppressed.

[0107] Additionally, at least a portion of the filler (111) may be included in the second insulating layer (110) and the unevenness of the second insulating layer. At least a portion of the filler (111) may be in contact with the first metal oxide layer (181) and may be in contact with the second-first wiring layer (120a). As a result, the filler (111) may improve adhesion with the first metal oxide layer (181) or the second-first wiring layer (120a).

[0108] Figure 4 shows the change in thickness of the metal oxide layer according to the curing temperature of the circuit board of the embodiment.

[0109] Fig. 4(a) shows the interface between the second wiring layer (120) and the second insulating layer (110) where the curing process is omitted as a comparative example. The comparative metal oxide layer (180R) may not exist between the second wiring layer (120) and the second insulating layer (110), or the thickness (d1) of the comparative metal oxide layer (180R) may be thin, less than 3.5 nm. When the comparative metal oxide layer (180R) does not exist or is thin, the adhesion between the second wiring layer (120) and the second metal oxide layer (180) may be weak.

[0110] On the other hand, according to the embodiment, Fig. 4(b) shows the interface between the second wiring layer (120) and the second insulating layer (110) that have undergone a curing process at a temperature of about 180˚C. A metal oxide layer (180) may be formed between the second wiring layer (120) and the second insulating layer (110). For example, the thickness (d2) of the metal oxide layer (180) of the circuit board cured at a temperature of 180˚C may be formed to be 10 to 30 nm.

[0111] Also, according to an embodiment, FIG. 4(c) shows the interface between the second wiring layer (120) and the second insulating layer (110) that have undergone a curing process at a temperature of about 200˚C. A metal oxide layer (180) may be formed between the second wiring layer (120) and the second insulating layer (110). For example, the thickness (d3) of the metal oxide layer (180) of the circuit board cured at a temperature of 200˚C may be formed to be about 30 to 90 nm.

[0112] According to the circuit board of the embodiment of the invention and the circuit board including the same, the adhesion between the wiring layer and the insulating layer can be improved by controlling the thickness of the metal oxide layer formed between the wiring layer and the insulating layer.

[0113] For example, when a harmony (CZ) treatment process is performed after seed layer flash etching to form a second wiring layer (120), there was an issue of an undercut (S) occurring between the second wiring layer and the second insulating layer (110).

[0114] To solve this problem, the embodiment has a technical effect of performing a baking process in an oxygen (O2) atmosphere so that a third metal oxide layer (183) fills the gap (S) between the second-first wiring layer (120a) and the second insulating layer (110), thereby improving the adhesion between the metal oxide layer (180) and the second wiring layer (120).

[0115]

[0116] The circuit board or package board according to the embodiment may be applied to any one of a CSP (Chip Scale Package), an FC-CSP (Flip Chip-Chip Scale Package), an FC-BGA (Flip Chip Ball Grid Array), a POP (Package On Package), and a SIP (System In Package).

[0117] Additionally, the circuit board or package board may be applied to, but is not limited to, smart phones, personal digital assistants, digital video cameras, digital still cameras, vehicles, high-performance servers, network systems, computers, monitors, tablets, laptops, netbooks, televisions, video games, smart watches, automotives, etc.

[0118]

[0119] Although the above description focuses on examples, these are merely examples and are not intended to limit the examples. Those skilled in the art will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present examples. For example, each component specifically shown in the examples can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

1. Insulating layer; A wiring layer disposed on the above insulating layer; and It includes a metal oxide layer arranged on the bottom and side surfaces of the above wiring layer; A circuit board in which the thicknesses of the metal oxide layer disposed on the lower surface of the wiring layer are different in the horizontal direction.

2. In paragraph 1, In the thickness of the metal oxide layer disposed on the lower surface of the wiring layer, The thickness of the metal oxide layer overlapping between the center and the upper and lower portions of the above wiring layer is A circuit board having a thickness different from that of the metal oxide layer overlapping vertically on the periphery of the wiring layer.

3. In paragraph 1, The above metal oxide layer is, A first metal oxide layer disposed between the insulating layer and the lower surface of the wiring layer; and A circuit board comprising a second metal oxide layer disposed on the side of the wiring layer.

4. In paragraph 3, A circuit board, wherein the thickness of the first metal oxide layer increases from the center of the wiring layer toward the outside.

5. In paragraph 1, The above insulating layer includes unevenness, A circuit board, wherein the first metal oxide layer is disposed between the unevenness of the insulating layer and the wiring layer.

6. In paragraph 3, The above insulating layer includes a filler, A circuit board, wherein at least some of said fillers are in contact with said first metal oxide layer.

7. In paragraph 6, A circuit board, wherein at least some of the fillers horizontally overlap one of the first metal oxide layer and the wiring layer.

8. In paragraph 3, A circuit board wherein the thickness of the first metal oxide layer is 30 to 100 nm.

9. In paragraph 6, The above insulating layer includes unevenness, The above-mentioned protrusion is a circuit board including the above-mentioned filler.

10. A package substrate including a circuit board according to any one of claims 1 to 9.

Images