Sidewall metal contact formation through incorporation of a replacement metal contact integration for semiconductor devices

Abstract

Aspects of the present disclosure provide a method of fabricating a semiconductor structure that includes a plurality of un-merged source-and-drain (S / D) contacts. For example, the method can include forming over a substrate a plurality of first channels that are stacked over each other and extend along a top surface of the substrate, forming on each of the first channels at one end thereof a first S / D contact, forming a first replacement dielectric material that covers the first S / D contacts, forming a first gate structure for each of the first channels; and replacing the first replacement dielectric material with a first interconnect that connects the first S / D contacts after the first gate structure is formed.

Description

SIDEWALL METAL CONTACT FORMATION THROUGH INCORPORATION OF A REPLACEMENT METAL CONTACT INTEGRATION FOR SEMICONDUCTOR DEVICESCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This present disclosure claims the benefit of U.S. Provisional Application No. 63 / 620,108, entitled “SIDEWALL METAL CONTACT FORMATION THROUGH INCORPORATION OF A REPLACEMENT METAL CONTACT INTEGRATION” filed on January 11, 2024, which is incorporated herein by reference in its entirety.FIELD OF THE INVENTION

[0002] The present disclosure relates to semiconductor processing, and, in particular, to formation of unmerged sidewall metal contacts of semiconductor devices.BACKGROUND

[0003] The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.

[0004] In the manufacture of a semiconductor device (especially on the microscopic scale), various fabrication processes are executed such as film -forming depositions, etch mask creation, patterning, material etching and removal, and dopingtreatments. These processes are performed repeatedly to form desired semiconductor device elements on a substrate. Historically, with microfabrication, transistors have been created in one plane, with wiring / metallization formed above the active device plane, and have thus been characterized as two-dimensional (2D) circuits or 2D fabrication. Scaling efforts have greatly increased the number of transistors per unit area in 2D circuits, yet scaling efforts are running into greater challenges as scaling enters single digit nanometer semiconductor device fabrication nodes. Semiconductor device fabricators have expressed a desire for three-dimensional (3D) semiconductor circuits in which transistors are stacked on top of each other.SUMMARY

[0005] Aspects of the present disclosure provide a method of fabricating a semiconductor structure that includes a plurality of un-merged source-and-drain (S / D) contacts. For example, the method can include forming over a substrate a plurality of first channels that are stacked over each other and extend along a top surface of the substrate, forming on each of the first channels at one end thereof a first S / D contact, forming a first replacement dielectric material that covers the first S / D contacts, forming a first gate structure for each of the first channels, and replacing the first replacement dielectric material with a first interconnect that connects the first S / D contacts after the first gate structure is formed.

[0006] In an embodiment, the method can further include forming a first silicidation layer on at least one of the first S / D contacts. For example, the first silicidation layer can be formed after the first gate structure is formed. In another embodiment, the method can further include forming a first contact etch-stop layer (CESL) to cap each of the first S / D contacts before the first gate structure is formed, and removing the first CESL after the first gate structure is formed. In some embodiments, the method can further include forming a first cladding material on at least one of the first S / D contacts, and removing the first cladding material after the first gate structure is formed. For example, the first cladding material can be formed before the first gate structure is formed. As another example, the first cladding material can include silicon.

[0007] In an embodiment, the method can further include forming a first epitaxy layer over at least one of the first S / D contact. For example, the first epitaxy layer can be formed after the first gate structure is formed. In another embodiment, the semiconductor structure can include an N-type metal oxide semiconductor (NMOS), and the first epitaxy layer can include phosphorous- or arsenic-doped silicon or silicon germanium. In some embodiments, the semiconductor structure can include a P-type metal oxide semiconductor (PMOS), and the first epitaxy layer can include boron-doped silicon or silicon germanium.

[0008] In an embodiment, the method can further include forming a first interconnect trench within which the first replacement dielectric material and the first interconnect are formed. In another embodiment, the first gate structure can wrap around each of the first channels. For example, forming the first gate structure can include forming a first replacement gate structure that wraps around each of the first channels, and performing a replacement metal gate (RMG) module to replace the first replacement gate structure with the first gate structure. In some embodiments, the first replacement dielectric material can be formed before the RMG module is performed.

[0009] In an embodiment, the method can further include forming a first etch-selective cap over the first channels, forming over the first etch-selective cap a plurality of second channels that are stacked over each other and extend along the top surface of the substrate, forming on each of the second channels at one end thereof a second S / D contact, forming a second gate structure for each of the second channels, and forming a second interconnect that connects the second S / D contacts and connects the first interconnect through an inter -tier via formed within the first etch-selective cap.

[0010] For example, forming the second interconnect can includes forming a second replacement dielectric material that covers the second S / D contacts before the second gate structure is formed, and replacing the second replacement dielectric material with the second interconnect after the second gate structure is formed. In an embodiment, the semiconductor structure can include a complementary field-effective transistor (CFET) structure.

[0011] In an embodiment, the method can further include forming a second etch-selective cap under the first interconnect. In another embodiment, the first etch-selective cap can be etched selectively with respect to the first replacement dielectric material.

[0012] Note that this summary section does not specify every embodiment and / or incrementally novel aspect of the present disclosure or claimed invention. Instead, this summary only provides a preliminary discussion of different embodiments and corresponding points of novelty. For additional details and / or possible perspectives of the invention and embodiments, the reader is directed to the Detailed Description section and corresponding figures of the present disclosure as further discussed below.BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Various embodiments of this disclosure that are proposed as examples will be described in detail with reference to the following figures, wherein like numerals reference like elements, and wherein:

[0014] FIGs. 1A and IB show cross-sectional views of two CFET device structures that include merged S / D contacts and sidewall metal contacts, respectively;

[0015] FIGs. 2-15 show a semiconductor structure fabricated at various intermediate steps that includes sidewall metal contacts formed through incorporation of replacement metal contact integration according to some embodiments of the present disclosure; and

[0016] FIG. 16 is a flow chart of an exemplary method of fabricating a semiconductor structure that includes unmerged sidewall metal contacts according to some embodiments of the present disclosure.DETAILED DESCRIPTION

[0017] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed. Further, spatially relative terms, such as “top,” “bottom,” “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature’s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0018] The order of discussion of the different steps as described herein has been presented for clarity sake. In general, these steps can be performed in any suitable order. Additionally, although each of the different features, techniques, configurations, etc. herein may be discussed in different places of this disclosure, it is intended that each of the concepts can be executed independently of each other or in combination with each other. Accordingly, the present disclosure can be embodied and viewed in many different ways.

[0019] Sidewall metal contact (SWMC) has been proposed as a design -technology -co- optimization (DTCO) solution to reduce parasitic contact resistance for both gate -all-around (GAA) and complimentary field -effective transistor (CFET) device structures. The sidewall metal contact replaces the conventional merged source-and-drain epitaxy contact with a small, un-merged source-and-drain (S / D) contact. This allows for parasitic resistance improvement through several mechanisms. For example, the merged doped silicon or silicon germanium epitaxy contact as the primary material filling the volume within an interconnect trench may be replaced with a highly conductive metal such as ruthenium (Ru), cobalt (Co),or tungsten (W) - thus providing a more highly conductive path from the signal wiring down through the collection of stacked nanosheets in a GAA or CFET device structure. An additional highly -doped, thin epitaxy may be grown overtop of the sidewall metal contact to further improve contact resistance as a substitution for implant doping of a merged source- and-drain contact, in which the implant would be limited to the top -most side of the source- and-drain contact. By having the more highly -doped epitaxy grown on top of the individual sidewall metal contact, this likewise ensures that all stacked nanosheets are more well- balanced and allows for the stacking of a greater number of nanosheets on top of one another in either GAA or CFET device structures which is important for future area scaling of the devices. An additional subtractive strain material may be grown or deposited overtop of the sidewall metal contact in which the strain can be more equally placed into each of the individual stacked nanosheets in a GAA or CFET device structure. This is in contrast to conventional merged source-and-drain processing in which the merging of the epitaxy across vertical-facing stacking faults can significantly reduce the strain being imposed into the channel. Even with the addition of a subtractive straining layer to the merged source-and- drain contact, the straining layer will be relegated to the outer most edges of the merged source-and-drain contact, thus reducing the overall efficiency of the straining layer to impose equal strain into all of the stacked nanosheets.

[0020] The sidewall metal contact was proposed by Wen -Li Sung in a publication, entitled “Characteristics of Stacked Gate-All-Around Si Nanosheet MOSFETs With Metal Sidewall Source / Drain and Their Impacts on CMOS Circuit Properties,” Transactions on Electron Devices; volume 68 number 6; June 2021, which is incorporated herein for reference in its entirety. The publication shows the parasitic resistance improvement captured as an increase in performance of a three-stage ring oscillator in which performance continues to increase even with the increase in the number of stacked nanosheets. Typically for GAA and CFET device structures, stacking nanosheets on top of one another provide for increased drive current through the devices; however, this also simultaneously increases the effective gate and interconnect metal heights, which adds a large parasitic capacitance component to the overall power / performance of the device. Additionally, having a large merged S / D contact also leads to larger parasitic resistance in the contact as the connection to the merged S / D contact is usually made at the very top of the merged contact structure.

[0021] For the case of the sidewall metal contact, the parasitic resistance is reduced through the primary material filling within the interconnect trench being a high conductive metal as opposed to a merged S / D contact doped semiconductor material. The improvement in theparasitic resistance is adequate to compensate for the higher parasitic capacitance associated with the increased metal heights of the gate and interconnect associated with the larger number of stacked nanosheets in the device.

[0022] Cross-sectional views of two CFET device structures 100 A and 100B that include merged S / D contacts 1 10A and sidewall metal contacts 1 10B, respectively, are shown in FIGs. 1 A and IB, respectively, which illustrate the primary differences between the two different S / D contact approaches. FIGs. 1 A and IB show this for the case of a CFET device structure in which NMOSs 120A and 120B are the lower-tier devices and PMOSs 130A and 13 OB are the upper-tier devices; as well as for the case of split power where VSSs 140 A and MOB are shown as the bottom copper back-side power rail and VDD is not shown in the cross-section, but will be a conventional top -side power rail within the M0 module. Any current supplied by the VDD for the case of the merged S / D contacts 110A will pass through the top-side of the wafer (i.e., the CFET device structure 100A) at the M0 power rail (not shown) and pass down to the top of the PMOS merged S / D contacts 110A where the silicide 150A is present; pass through the silicide 150A into the bulk boron-doped SiGe epitaxy contact (S / D contact 110A), and through the deep merged boron-doped SiGe epitaxy contacts (S / D contact 110A) before encountering the stacked silicon PMOS channels 160A of the PMOS 130A. The path length of the current through the merged eSiGe:B contact (S / D contact 110A) is quite large before encountering the bottom-most PMOS channel 160A. Comparatively, FIG. IB shows the case of the sidewall metal contact 110B in which the current from the VDD power rail (not shown) will pass into a bulk PMOS interconnect 170B such as ruthenium (Ru) and be allowed to pass all the way down the depth of the PMOS interconnect 170B to then pass through a local silicide 150B grown at the end of the much smaller, un-merged boron-doped SiGe contacts (sidewall metal contacts HOB), and thus have much less path-length through this lower conductive medium before encountering the silicon PMOS channel 160B of the PMOS 130B.

[0023] The sidewall metal contact process is a more challenging integration compared to the merged S / D contact process, simply because the merged S / D contact 110A presents as a fixed structure in which the merged S / D contact 110A can be formed and covered up by a dielectric material such as a silicon oxide during the replacement metal gate module; and then subsequently re-opened either where only the top of the merged S / D contact 110A needs to be exposed to make connection to the interconnect metal, or for the case of wrap -around contact, where the oxide surrounding the merged S / D contact 110A can be opened on either side of the merged S / D contact 110A in order to make a wrap-around connection to theinterconnect metal. For the case of the sidewall metal contact 110B, the protruding ends of the sidewall metal contacts 11 OB prevent anisotropic etching of the silicon oxide dielectric as the upper sidewall metal contacts HOB will “shadow” the dielectric etch to the sidewall metal contacts underneath. In order to integrate a sidewall metal contact process, a replacement metal contact integration is typically required. U.S. Patent No. 11,264, 274-B2, entitled “Reverse contact and silicide process for three -dimensional logic devices,” describes such an integration method which can be adopted to enable a manufacturing process for the sidewall metal contact HOB, and is thus incorporated herein for reference in its entirety.

[0024] The replacement metal contact integration was initially designed to: enable to form a S / D contact on a lower-tier device for CFET device structures in which the silicide can be formed on the bottom contact well after the replacement metal gate processing in order to maintain thermal processing consistency; allow for the placement of wrap-around interconnect metal around a non-straight S / D contact; and enable the inclusion of a direct backside contact to directly connect the S / D to a back-side power rail to eliminate any fringe capacitance associated with having the connections to the wafer backside from having to extend well beyond the sides of the S / D contact

[0025] However, the replacement metal contact integration can be used to also enable the sidewall metal contact integration in which S / D contacts need to be formed and the interconnect trench memorized with an alternate etch -selective dielectric relative to the surrounding oxide, in which the interconnect trench can be re-opened following replacement metal gate processing to form the silicide and interconnect metallization without causing any degradation to the surrounding oxide field.

[0026] There is an economic push to simplify the sidewall metal contact integration flow in order to reduce the total number of processing steps as well as the overall process complexity. In this case, alternate integrations of the sidewall metal contact integration are proposed in which this can be realized. In an embodiment, the sidewall metal contact 1 10B can be formed by the use of the replacement metal contact (RMC) integration. The RMC integration can be employed to have a fully self -aligned backside contact to the backside power connections and / or power distribution network. In the RMC integration, the S / D contact can be memorized by the doped epitaxy which is captured within the protection of the inner spacer, and will have a lateral dimension equal to the lateral recess of the silicon nanosheet in the S / D formation module. The additional space the RMC integration provides will allow for additional contacted poly pitch (CPP) reduction as well as allowing additional space to haveadditional low-temperature / extremely high doping epitaxy grown overtop of the sidewall metal contact in order to further reduce contact resistance of the device.

[0027] The fundamental challenge with adopting an un -merged sidewall metal contact (e.g., the sidewall metal contact 1 10B) is with the intermediate steps between the formation of the contacts, which is typically done much earlier in the front-end-of-the-line (FEOL) processing, and the silicidation and metallization of the contacts, which is done following the replacement metal gate (RMG) module, after the reliability anneals have been done on the device. With a conventional merged source -and-drain (S / D) contact (e.g., the merged S / D contact 110A), the contact can be created and the area surrounding the contact can be easily re-filled with a dielectric material such as silicon oxide; in the subsequent interconnect trench opening process, the silicon oxide can be opened where the merged S / D contact can provide some level of continuity where either a partial amount or the full amount of contact can be exposed to what will eventually become the interface to which the silicide can be formed over the contact and the interface between the silicide and the interconnect metal.

[0028] For a stacked nanosheet type of device, as what exists for gate -all-around (GAA) and complimentary field effective transistors (CFET) devices, the merged S / D contact allows for connection from the uppermost portion of the contact making connection to the interconnect metal down across all nanosheets in the stacked nanosheet device, where the electrical connectivity between the interconnect metal and the nanosheets is accomplished through the S / D contact itself.

[0029] The sidewall metal contact (SWMC) allows for each nanosheet to have a small volume of S / D contact at each terminal of the transistor which is directly connected to the interconnect metal which wraps around each of the S / D contacts and extends down to the bottom-most nanosheet, thus providing a much higher conductive medium in which signal to travel from the S / D contact to the metal signal wires, and vice-versa.

[0030] The sidewall metal contact, being un-merged, actually makes the standard integration process of forming the S / D contacts and re-filling with a dielectric such as silicon oxide before the RMG module more challenging. The challenge comes in the interconnect trench open process in which the silicon oxide needs to be etched to make connection to each individual S / D terminal of the group of sidewall metal contacts, as the protruding un-merged S / D contacts will block the silicon oxide transfer etch from reaching the un-merged S / D contacts directly underneath the uppermost S / D contact which is encountered by the etch process.

[0031] Applying some measure of anisotropicity and isotropicity to the trench etch process, where the initial trench is opened with the S / D contact being blocked or shadowed by the uppermost S / D contact, and then including an isotropic etch to ensure wrap-around of the trench etch to the underlying S / D contacts can be considered an option; however, the challenge with applying this approach as a solution is that the isotropic etch will extend the effective trench “heights” (with height meaning the north-south dimension of the interconnect trench in terms of the logic standard cell) which will likewise lead to higher parasitic capacitance and either slower overall device performance or greater device power consumption.

[0032] One potential solution to the formation of the sidewall metal contact may be an application of US Patent No. 11,264,274-B2 from Tokyo Electron in which a replacement metal contact integration flow is provided in which a replacement dielectric with etch selectivity to silicon oxides and other dielectric materials present in the device during the FEOL and middle-of-the-line (MOL) processing modules is used as a means to memorize the interconnect morphology such that in the sequence where the interconnect trench would normally be opened, instead of etching into the silicon oxide dielectric, the trench is simply “re-formed” from its memorized morphology through the isotropic etching of the replacement dielectric gap-fill material which will have selectivity to the silicon oxide surrounding the memorized interconnect trench.

[0033] The replacement metal contact process outlined in the referenced Tokyo Electron patent was initially intended to allow for the thermal processing of the contact and interconnect modules in a CFET device where the bottom -most device would need to have the silicidation and metallization of the interconnect done after the RMG module proc essing. This was accomplished in the present disclosure through memorizing the interconnect shape with the replacement dielectric material; when the wafer would be flipped over to process the bottom-most device, the replacement dielectric could be removed in an isotropic manner with selectivity to the silicon oxide in order to perform the silicide and metallization of the bottom device through the backside of the wafer well after the RMG processing was finished. The application of the replacement metal contact was later adopted to allow for the inclusion of a self-aligned direct backside contact which would allow for a direct metal connection between the bottom-most device and any backside power lines or backside signal lines.

[0034] The concept herein is to adopt the replacement metal contact integration to allow for the formation of the sidewall metal contact, which otherwise could not be done through conventional interconnect integration processes.

[0035] An example of how such an integration would be done is shown below using a monolithic CFET device, which adds greater complexity over standard gate -all-around (GAA) device structures given that there needs to be consideration for the tier-to-tier connections which will be needed in some instances to merge the input and / or output of the NMOS and PMOS devices together without doing so utilizing a signal track in the BEOL metal stack.

[0036] For the monolithic CFET reference, a number of assumptions are used, including: (1) split power where VDD is supplied by a top-side power rail and VSS is connected through a backside power rail; (2) the connection of a NMOS device to VSS power is done through an integrated self-aligned backside direct contact (BSC) which also adds complexity to the integration at the benefit of significant reduction in fringe capacitance (and hence improvement in either cell -level performance and / or power consumption); (3) configuration of the monolithic CFET device in which a PMOS is the uppermost device, and a NMOS is the bottom -most device; where the PMOS being separated from the substrate would require additional processing in the integration to provide some measure of strain into the channel ; (4) for this example a silicon-on-insulator (SOI) type of substrate wafer is used where a buried oxide layer exists under the silicon / silicon germanium active stack - it is realized that this integration can be adopted for standard silicon substrates without any buried oxide and other types of starting wafers such as sequentially processed wafers which could be used in a sequential CFET device structure; and (5) other assumptions include 4 stacked NMOS sheets (e.g., nanosheets) with four stacked PMOS sheets (e.g., nanosheets) overtop, with the nanosheet width being 21nm with a lOnm vertical spacing between silicon nanosheets; an physical gate length of 15nm, and a contacted poly pitch of 42nm.

[0037] It is stressed that the present disclosure would equally apply to any configuration of a CFET device where power can both be either top -side or back-side and even a combination of the two; and the device orientations can be swapped to where a NMOS is the uppermost device. It is also stressed that the present disclosure can equally pertain to gate-all-around (GAA) devices and is not limited to CFET device structures. Only the case of the monolithic CFET device is shown in this example as it provides the more challenging of the device structures to effectively demonstrate the present disclosure.

[0038] FIGs. 2-15 show a semiconductor structure 200 fabricated at various intermediate steps that includes sidewall metal contacts formed through incorporation of replacement metal contact integration according to some embodiments of the present disclosure. In an embodiment, the semiconductor structure 200 can include a monolithic CFET device(semiconductor structure 200). FIG. 2 shows an INVD4 standard logic cell in the monolithic CFET device (semiconductor structure 200) starting at an inner spacer formation step proceeding to a patterning step in which a self-aligned direct backside contact (BSC) is formed and then transferred through aburied oxide layer230 formed on a substrate 240 (e.g., a SOI substrate) and then gap -filled and etch-recessed with a replacement dielectric material 210. The choice of the replacement dielectric material 210 will be co-optimized with the other surrounding dielectric materials (e.g., the buried oxide layer 230) in orderto achieve the required etch selectivity - both in the selective etch recesses of the replacement dielectric material 210, but also for the eventual selective removal of the replacement dielectric material 210 selective to the surrounding dielectric materials. A number of potential materials can be used for the replacement dielectric material 210, ranging from silicon oxide - assuming that the surrounding dielectric materials will either be heavily doped with carbon or lined with some type of carbon film to provide etch -selectivity; or the replacement dielectric material 210 can be composed of materials such as boron nitride or similar dielectric materials which can be removed with high degrees of selectivity with respect to silicon oxides and silicon nitrides. The replacement dielectric material 210 will possess good gap-filling capability and good etch selectivity to other dielectric materials including, but not limited to, silicon oxides, silicon nitrides, and carbon -doped silicon oxides and silicon nitrides. The BSC contact here is fully self-aligned to a source / drain (S / D) contact region 220 which is critical for the eventual metal connection between a backside power (e.g., VSS) and / or backside signal wires to the BSC contact without shorting to the adjacent metal gate which will be created adjacent to the BSC contact. In an embodiment, the semiconductor structure 200 can be a CFET device structure in which a NMOS 200N is the lower-tier device nanosheets and a PMOS 200P is the upper-tier device nanosheets.

[0039] FIG. 3 carries the integration on through the formation of a cover spacer 310 which will cover the upper-tier device nanosheets (PMOS 200P) (i.e., the PMOS in this example) from the exposed lower-tier device nanosheets (NMOS 200N) (i.e., the NMOS in this example), followed by an oxide deposition to fill spaces between the nanosheets with an oxide material (e.g., silicon oxide) 320 and patterning of a NMOS interconnect trench 330 and sub sequent transfer of the NMOS interconnect trench 330 through the oxide material 320, followed by the lateral recess etch of the nanosheets in a NMOS region (where the NMOS 200N is to be formed) to form the desired gate extension lengths of NMOS channels 340 of the NMOS 200N. As stated earlier, for the sidewall metal contact integration (e.g., the sidewall metal contact 110B), the individual S / D contacts need to be grown within a pre-defined interconnect trench structure which will later be memorized. The lateral recess etch of the nanosheets in the NMOS region can be anywhere to set a zero -extension for the metal gate to where the nanosheet is preserved to be flush with the inner spacer.

[0040] FIG. 4 shows the formation of un-merged NMOS sidewall metal contacts 410 from the ends (e.g., the NMOS channels 340) of the lower-tier device nanosheets (NMOS 200N) (i.e., the NMOS), followed by a deposition of a NMOS contact etch-stop layer (CESL) 420 to cap (or line) the NMOS sidewall metal contacts 410, and gap-filling and subsequent recess etching of the replacement dielectric material 210. For the NMOS 200N, the NMOS sidewall metal contacts 410 can be composed of epitaxy silicon which is in -situ doped with phosphorous (P) or arsenic (As) in order to improve the conductance of the NMOS sidewall metal contacts 410. The NMOS CESL 420 can be composed of a high quality silicon nitride film and its role is to protect the NMOS sidewall metal contacts 410 from subsequent etch processes as well as to prevent any contamination of the NMOS sidewall metal contacts 410 during subsequent processing steps. The NMOS CESL 420 may also protect the silicon epitaxy surface of NMOS sidewall metal contacts 410 from oxidation as well as to provide an etch-stopping layer to prevent damage to the source-and-drain (S / D) region of the NMOS 200N. As discussed previously, the replacement dielectric material 210 has etch selectivity to both the silicon oxide and carbon-doped silicon oxide shown in the damage-free etch recess step where the replacement dielectric material 210 is recessed down in between the NMOS and PMOS intended regions.

[0041] FIG. 5 shows the formation of an etch-selective cap (dielectric) 510 overtop of the recessed replacement dielectric material 210, followed by refilling of the upper portion of the NMOS interconnect trench 330 (shown in FIG. 3) with a dielectric material (e.g., silicon oxide), and subsequent patterning and etching of a PMOS (i.e., upper-tier) interconnect trench 530, where the etching will endpoint and stop once the etch -selective cap 510 overtop the (NMOS) replacement dielectric material 210 is exposed.

[0042] FIG. 6 shows the selective removal of the cover spacer 310 (shown in FIG. 3) to reveal the upper-tier device nanosheets (i.e., the PMOS) 200P, followed by the lateral recess of the upper-tier PMOS device nanosheets 200P to form the PMOS gate extensions, and followed by un-merged PMOS sidewall metal contacts 610 (e.g., epitaxially grown within S / D regions). The lateral recess of the upper-tier PMOS device nanosheets 200P follows the same rationale as what was described for the formation of the NMOS sidewall metal contacts 410. In an embodiment, the PMOS sidewall metal contacts 610 will be composed of silicon germanium with in-situ doping of boron (B) or similar species. For the PMOS 200P, thePMOS sidewall metal contacts 610 can be composed of multiple layers of silicon germanium of different compositions of germanium in order to provide some level of additional strain to PMOS channels 620 of the PMOS 200P, and to also provide some etch selectivity between the silicon germanium within the PMOS sidewall metal contacts 610 and the silicon germanium comprised in a silicon / silicon germanium fin structure within a gate region.

[0043] FIG. 7 shows additional processing of the PMOS sidewall metal contacts 610 in which, optionally, a semiconductor cladding material 720 such as silicon can be epitaxially grown over the PMOS sidewall metal contacts 610 in order to provide additional strain into the PMOS channels 620. Such contact cladding methodologies may be able to provide more strain into the PMOS channels 620 for the PMOS sidewall metal contacts 610 compared to a merged S / D contact (e.g., the merged S / D contact 110A) in which the cladding material is less equally distributed with respect to all of the stacked nanaosheets as well as being positioned farther away from the effective channels.

[0044] In an embodiment, the silicon cladding material can be optional as there are other mechanisms to provide strain into the PMOS channels 620, including but not limited to, direct channel cladding of silicon germanium over silicon channels, or utilizing either a CESL liner (e.g., the NMOS contact etch-stop layer (CESL) 420) or a replacement dielectric material (e.g., the replacement dielectric material 210) to be able to impart some strain into the PMOS channels 620 through the interface of the PMOS sidewall metal contacts 610.

[0045] Following any contact cladding processing, a PMOS CESL 710 can be likewise deposited onto the PMOS sidewall metal contacts 610 and a similar replacement dielectric material (e.g., the replacement dielectric material 210) can be gap-filled into the PMOS (i.e., upper-tier) interconnect trenches 530 (shown in FIG. 5) in order to memorize the morphology of upper-tier PMOS interconnect to be formed within the PMOS interconnect trenches 530.

[0046] The etch-selective cap 510, which was formed overtop the replacement dielectric material 210 of the lower-tier NMOS 200N, will likewise serve as an etch-stop between the two interconnects (i.e., NMOS and PMOS interconnects) during the isotropic opening processes of both interconnects which will prevent these two interconnects from forming a common interconnect structure during said isotropic etching processes.

[0047] FIG. 8 follows the integration where after the gap -filling of the replacement dielectric material 210 for the upper-tier device nanosheets (PMOS 200P), the semiconductor structure 200 is then polished down to reveal the amorphous silicon 730 of a replacement gate structure (shown in FIG. 7) of the PMOS 200P, followed by a replacement metal gate (RMG) module in which the amorphous silicon 730 is selectively removed, followed byremoval of the silicon germanium in the active fin stack, growth of an interface oxide layer (e.g., SiO2, HfO2, etc.) 811 over the silicon nanosheets (e.g., including the upper-tier device nanosheets (PMOS 200P)) and the lower-tier device nanosheets (NMOS 200N)), deposition of a high-k dielectric 812, depositions of work function metals (and liners) 813 to achieve required threshold voltage targets, and filling of a high conductive metal 814 such a tungsten (W) into the gate, to form a PMOS gate structure 810 of the PMOS 200P. During the RMG module, the single diffusion breaks are formed in a self -aligned manner and gap-filled with dielectric, any gate cuts are implemented and likewise filled with dielectric materials, and the final replacement metal gate is vertically recessed and then subsequently capped with a dielectric such as silicon nitride.

[0048] Following the RMG module processing, the upper-tier PMOS replacement dielectric material 210 is exposed and is able to be isotropically removed through a wet-etch or vapor-phase etch with very high selectivity to the surrounding dielectric films (or layers) in order to reveal the memorized upper-tier PMOS interconnect trench 530 (shown in FIG. 5). As the replacement dielectric material 210 can be removed selectively with an isotropic removal process, the entire PMOS interconnect trench 530 can be opened without any shadowing of the PMOS interconnect trench 530 underneath the uppermost protruding uppertier PMOS sidewall metal contacts 610.

[0049] FIG. 9 shows the case where it is necessary to create shorting between PMOS and NMOS interconnects for a monolithic CFET (e.g., the semiconductor structure 200), as would exist in the case of the output of an inverter. For GAA device structures, the merging of the outputs between NMOS and PMOS would be done by the lateral merging of the NMOS and PMOS interconnects; however, for the case of monolithic CFET device structures where NMOS and PMOS (e.g., the NMOS 200N and the PMOS 200P) are stacked on top of one another, the merging of the PMOS and NMOS interconnects must be done vertically and bypassing the etch-selective cap 510 which is placed to electrically isolated one from the other.

[0050] This can be done through a variety of methods. In an embodiment, the opened upper-tier PMOS interconnect trench 530 can be filled with a carbon spin-on material 910 followed by the patterning of a tier-to-tier (or inter-tier) via 920 which will electrically connect the PMOS and NMOS interconnects together. The PMOS CESL 710 (shown in FIGs. 7 and 8) can provide some etch protection to the PMOS sidewall metal contacts 610 (shown in FIGs. 6-8), or the dimension of the PMOS interconnect trench 530 can be extend out such that the inter-tier via 920 would be formed well away from any sidewall metalcontacts. Then, the etch-selective cap 510 can be opened, and the carbon spin -on material 910 can be removed.

[0051] Another approach is to forego the patterning of the inter-tier via 920 completely, and to pattern a “keep” mask (not shown) which will isolate the interconnects which will be electrically merged from those which will not, and to develop an isotropic etch process which will only remove the etch-selective cap 510 over the lower interconnect structure entirely, thus providing significant parasitic resistance improvement.

[0052] FIG. 10 shows the continuation of the processing where the silicon cladding material and the PMOS CESL 710 are etched away selective to the PMOS sidewall metal contacts 610. At this point, a low-temperature, very high boron-doped (or phosphorous- doped or arsenic-doped for a NMOS) silicon germanium (or silicon) second layer of the sidewall metal contact 610 (or called a secondary epitaxy layer) can be epitaxially grown over the existing sidewall metal contact 610 in order to further improve the contact resistance of the sidewall metal contact 610. Such epitaxy deposition is typically extremely slow; however, for the case of a sidewall metal contact (e.g., the PMOS sidewall metal contact 610), only a very small additional layer of highly doped epitaxy is required to achieve the contact resistance improvement. The benefit of having the secondary high -doped layer of the sidewall metal contact 610 grown on top of the existing sidewall metal contact 610 is that: (1) the additional low-temp erature / highly doped second layer would be grown very close to the PMOS channel 620 compared to the case of a merged S / D (e.g., the merged S / D contact 110A) where the proximity of the high-doped region would be considerably farther away from the bottom-most nanosheet; (2) the additional low-temperature / highly doped second layer would have a larger effective surface area for the case of the sidewall metal contacts 610, where it would be grown equally across all the sidewall metal contacts 610 as opposed to just the upper-face of the merged S / D contact 110A; and (3) the additional low- temperature / highly doped second layer would be a good substitute for any implant processing on the merged S / D contact 110A as this would likewise be limited to the upper face of the merged S / D contact 110A which would be considerable distance away from the bottom -most nanosheet. Additionally, the sidewall metal contact 610 would make implant more challenging as a straight top-down implant would only encounter the uppermost sidewall metal contact 610 and have no mechanism to transfer down to the sidewall metal contacts 610 underneath which are shadowed by the uppermost sidewall metal contact 610. Thus, this secondary epitaxy layer is seen as a good proxy for a more consistent doping process for un - merged sidewall metal contacts.

[0053] Following any secondary epitaxy layer generation, the sidewall metal contact 610 can then be subjected to a silicidation process where a metal such as titanium (Ti)— but not limited to titanium - can be deposited into the PMOS interconnect trench 530 (shown in FIG. 5), reacted with the silicon germanium sidewall metal contact (PMOS sidewall metal contacts 610) to form a silicidation layer 1010 (e.g., titanium silicon germanium), and where the unreacted titanium is removed from the PMOS interconnect trench 530. Following the silicidation process, the PMOS interconnect trench 530 can then be filled with a high conductive metal such as ruthenium (Ru), cobalt (Co), tungsten (W), etc. and then polished using the silicon nitride cap of an RMG 1020 as an CMP-stop to form an upper-tier PMOS interconnect 1030.

[0054] FIG. 11 continues the integration where the upper-tier PMOS interconnect 1030 (e.g., highly conductive metal) in the PMOS interconnect trench 530 (shown in FIG. 5) is recessed down and then subsequently filled with an etch -selective cap (dielectric) 1120 which has etch selectivity to the silicon nitride gate cap, the silicon oxide field dielectric, and the carbon-doped silicon oxide film which typically comprises the low-k gate spacer. Such dielectrics can be composed of carbon -rich silicon nitride films, or even films composed of silicon carbide or SiCN.

[0055] The etch selectivity is important for the self-aligned gate contact (SAGC) or contact-over-active-gate (COAG) integrations in which etch -selectivity is used to be able to assign via-to-gate and via-to-contact connections through a self -aligned method to signal wires.

[0056] Afterthe upper-tier PMOS interconnect metallization and capping (i.e., the uppertier PMOS interconnect 1030 and the etch-selective cap 1120), the entire back-end-of-the-line (BEOL) module is completed where all of the signal layers are created along with any of the power distribution network metal layers, and any passivation and padding layers.

[0057] Typically, this would be the end of the chip processing; however, for monolithic CFET as well as for device structures which incorporate any backside metal routing or power layers, the semiconductor structure 200 will need to be placed onto a carrier wafer and flipped over in order to continue the lower-tier NMOS interconnect metallization as well as any backside metal processing.

[0058] FIG. 12 continues the wafer processing after the semiconductor structure 200 is bonded to a carrier wafer 1210 and flipped over in which the initial substrate 240 (shown in FIG. 11) is removed through a combination of a grinding process followed by optional CMP and etch removal processes to expose the buried oxide layer 230. Again, the assumption forthis example is that a buried oxide layer 1220 is used; for other integrations where no SOI wafer is used, the stop would be done on the shallow trench isolation dielectric instead.

[0059] In this approach, the buried oxide layer 230 is revealed as well as the replacement dielectric material 210 (shown in FIG. 11) from the lower-tier NMOS 200N. In an embodiment, the replacement dielectric material 210 can be isotropically removed with etch selectivity the buried oxide / shallow trench isolation dielectric as well as the field silicon oxide and the carbon-doped silicon oxide comprised in the inner spacer.

[0060] It is at this point where the inter-tier via 920 merging the PMOS interconnect 1030 and the NMOS interconnect 1320 (shown in FIG. 13) is exposed along with the metal. After the removal of the NMOS CESL 420 (shown in FIG. 10) from the NMOS sidewall metal contact 410, the NMOS sidewall metal contact 410 will be cleaned which will likewise clean the exposed metal (e.g., the upper-tier PMOS interconnect 1030) from the upper-tier PMOS device 200P.

[0061] Alternately, an additional step can be added to the integration which is not shown where some carbon gap-fill material can be gap-filled into the opened PMOS interconnect trench 530 prior to the removal of the NMOS CESL 420 and then recessed down to allow for full exposure of all of the NMOS sidewall metal contacts 410, but to maintain some level of protection over the exposed metal from the PMOS interconnect 1030, if desired.

[0062] FIG. 13 continues the processing of the semiconductor structure 200 where the NMOS CESL 420 is removed from the NMOS sidewall metal contact 410 and the silicide formation and interconnect metallization is completed to form a silicidation layer 1310 on top of the NMOS sidewall metal contact 410 and a NMOS interconnect 1320, respectively, similar to what was done for the PMOS interconnect 1030 described earlier. In the metallization of the NMOS interconnect 1320, the backside direct contact will be metallized as well as will the inter-tier via 920 connecting any NMOS and PMOS interconnects (e.g., the NMOS interconnect 1320 and the PMOS interconnect 1030) together.

[0063] FIG. 14 illustrates the process by which direct backside contacts which are to connect to backside power (e.g., VDD or VSS) or signal lines are “kept” through the patterning of a masking layer 1410 and the subsequent vertical recess of the metal 1420 and re-fill with a filler material (e.g., silicon oxide) 1430 and CMP to remove the masking layer 1410 and isolate the NMOS sidewall metal contacts 410 not making any connection to the wafer backside. In some embodiments, these steps can be removed from the integration flow if the initial self-aligned backside contact patterning illustrated in FIG. 2 is limited to just formingthe BSC where there is to be a direct contact made. In this example, this additionalprocessing step was maintaining in the flow in order to enable multiple types of backside connections. The patterning and etch transfer of a backside power (e.g., VSS) rail which will make direct contact to the NMOS sidewall metal contacts 410.

[0064] FIG. 15 shows the completion of the backside metallization 1510. Optionally, the carrier wafer 1210 (shown in FIG. 12) and the semiconductor structure 200 can be re-flipped if it is desired to have the top-side of the semiconductor structure 200 connect to a top-side power distribution network.

[0065] FIG. 16 is a flow chart of an exemplary method 1600 of fabricating a semiconductor structure (e.g., the semiconductor structure 200) according to some embodiments of the present disclosure. In various embodiments, some of the steps of the method 1600 shown can be performed concurrently or in a different order than shown, can be substituted by other method steps, or can be omitted. Additional method steps can also be performed as desired. The method 1600 can start with step S1610S, at which formed over a substrate can be a plurality of first channels that are stacked over each other and extend along a top surface of the substrate. For example, the PMOS channels 620 can be formed over the substrate 240, as shown in FIG. 9. The method 1600 can proceed to step S1620.

[0066] At step SI 620, a first S / D contact (or a first sidewall metal contact) can be formed on each of the first channels at one end thereof. For example, the PMOS sidewall metal contact 610 can be formed on each ofthe PMOS channels 620 at one end thereof, as shown in FIG. 6. In an embodiment, a first contact etch-stop layer (CESL) can be formed to cap each of the first S / D contacts. For example, a PMOS CESL 710 can be formed on the PMOS sidewall metal contacts 610, as shown in FIG. 7. In another embodiment, a first cladding material can be formed on at least one of the first S / D contacts. For example, the cladding material 720 can be formed on the PMOS sidewall metal contacts 610, as shown in FIG. 7. The method 1600 can proceed to step SI 630.

[0067] At step SI 630, a first replacement dielectric material can be formed that covers the first S / D contacts. For example, the replacement dielectric material 210 can be formed that covers the PMOS sidewall metal contacts 610, as shown in FIG. 7. The method 1600 can proceed to step SI 640.

[0068] At step S1640, a first gate structure can be formed for each of the first channels. For example, the PMOS gate structure 810 can be formed for each of the PMOS channels 620, as shown in FIG. 8. The method 1600 can proceed to step S1650.

[0069] At step SI 650, the first replacement dielectric material can be replaced with a first interconnect that connects the first S / D contacts after the first gate structure is formed. Forexample, the replacement dielectric material 210 can be replaced with the PMOS interconnect 1030 that connects the PMOS sidewall metal contacts 610 after the PMOS gate structure 810 is formed, as shown in FIG. 10. In an embodiment, a first silicidation layer can be formed on at least one of the first S / D contacts after the first gate structure is formed. For example, the silicidation layer 1010 can be formed on the PMOS sidewall metal contact 610 after the PMOS gate structure 810 is formed, as shown in FIG. 10. As the first interconnect and the first silicidation layer are formed after the first gate structure is formed, the first interconnect and the first silicidation layer will not be impacted by the thermal process during which the first gate structure is formed. In another embodiment, the first CESL and the first cladding material can be removed after the first gate structure is formed. For example, the PMOS CESL 710 and the cladding material 720 can be removed after the PMOS gate structure 810 is formed, as shown in FIG. 9.

[0070] In some embodiments, a first etch-selective cap can be formed over the first channels, a plurality of second channels can be formed over the first etch -selective cap that are stacked over each other and extend along the top surface of the substrate, a second S / D contact can be formed on each of the second channels at one end thereof, a second gate structure can be formed for each of the second channels, and a second interconnect can be formed that connects the second S / D contacts and connects the first interconnect through an inter-tier via formed within the first etch-selective cap. For example, the etch-selective cap 510 can be formed over the NMOS channels 340, the PMOS channels 620 can be formed over the etch-selective cap 510 that are stacked over each other and extend along the top surface of the substrate 240, the PMOS sidewall metal contact 610 can be formed on each of the PMOS channels 620 at one end thereof, the PMOS gate structure 810 can b e formed for each of the PMOS channels 620, and the PMOS interconnect 1030 can be formed that connects the PMOS sidewall metal contacts 610 and connects the NMOS interconnect 1320 through the inter-tier via 920 formed within the etch-selective cap 510, as shown in FIGs. 3, 4, 8 and 11-13. In some embodiments, the second interconnect can be formed by forming a second replacement dielectric material that covers the second S / D contacts before the second gate structure is formed, and replacing the second replacement dielectric material with the second interconnect after the second gate structure is formed. For example, the PMOS interconnect 1030 can be formed by forming the replacement dielectric material 210 that covers the PMOS sidewall metal contacts 610 before the PMOS gate structure 810 is formed, and replacing the replacement dielectric material 210 with the PMOS interconnect 1030 after the PMOS gate structure 810 is formed, as shown in FIGs. 4, 12 and 13.

[0071] In the preceding description, specific details have been set forth, such as a particular geometry of a processing system and descriptions of various components and processes used therein. It should be understood, however, that techniques herein may be practiced in other embodiments that depart from these specific details, and that such details are for purposes of explanation and not limitation. Embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, for purposes of explanation, specific numbers, materials, and configurations have been set forth in order to provide a thorough understanding. Nevertheless, embodiments may be practiced without such specific details. Components having substantially the same functional constructions are denoted by like reference characters, and thus any redundant descriptions may be omitted.

[0072] Various techniques have been described as multiple discrete operations to assist in understanding the various embodiments. The order of description should not be construed as to imply that these operations are necessarily order dependent. Indeed, these operations need not be performed in the order of presentation. Operations described may be performed in a different order than the described embodiment. Various additional operations may be performed and / or described operations may be omitted in additional embodiments.

[0073] “ Substrate” or “target substrate” as used herein generically refers to an object being processed in accordance with the present disclosure. The substrate may include any material portion or structure of a device, particularly a semiconductor or other electronics device, and may, for example, be a base substrate structure, such as a semiconductor wafer, reticle, or a dielectric layer on or overlying a base substrate structure such as a thin film. Thus, substrate is not limited to any particular base structure, underlying dielectric layer or overlying dielectric layer, patterned or un-pattemed, but rather, is contemplated to include any such dielectric layer or base structure, and any combination of dielectric layers and / or base structures. The description may reference particular types of substrates, but this is for illustrative purposes only.

[0074] Those skilled in the art will also understand that there can be many variations made to the operations of the techniques explained above while still achieving the same objectives of the present disclosure. Such variations are intended to be covered by the scope of this disclosure. As such, the foregoing descriptions of embodiments of the invention are not intended to be limiting. Rather, any limitations to embodiments of the invention are presented in the following claims.

Claims

WHAT IS CLAIMED IS:

1. A method of fabricating a semiconductor structure, the method comprising: forming over a substrate a plurality of first channels that are stacked over each other and extend along a top surface of the substrate; forming on each of the first channels at one end thereof a first S / D contact; forming a first replacement dielectric material that covers the first S / D contacts; forming a first gate structure for each of the first channels; and replacing the first replacement dielectric material with a first interconnect that connects the first S / D contacts after the first gate structure is formed.

2. The method of claim 1, further comprising: forming a first silicidation layer on at least one of the first S / D contacts.

3. The method of claim 2, wherein the first silicidation layer is formed after the first gate structure is formed.

4. The method of claim 1, further comprising: forming a first contact etch-stop layer (CESL) to cap each of the first S / D contacts before the first gate structure is formed; and removing the first CESL after the first gate structure is formed.

5. The method of claim 1, further comprising: forming a first cladding material on at least one of the first S / D contacts; and removing the first cladding material after the first gate structure is formed.

6. The method of claim 5, wherein the first cladding material is formed before the first gate structure is formed.

7. The method of claim 5, wherein the first cladding material includes silicon.

8. The method of claim 1, further comprising: forming a first epitaxy layer over at least one of the first S / D contact.

9. The method of claim 8, wherein the first epitaxy layer is formed after the first gate structure is formed.

10. The method of claim 8, wherein the semiconductor structure includes an N-type metal oxide semiconductor (NMOS), and the first epitaxy layer includes phosphorous- or arsenic-doped silicon or silicon germanium.11 . The method of claim 8, wherein the semiconductor structure includes a P-type metal oxide semiconductor (PMOS), and the first epitaxy layer includes boron -doped silicon or silicon germanium.

12. The method of claim 1, further comprising: forming a first interconnect trench within which the first replacement dielectric material and the first interconnect are formed.

13. The method of claim 1, wherein the first gate structure wraps around each of the first channels.

14. The method of claim 13, wherein forming the first gate structure includes: forming a first replacement gate structure that wraps around each of the first channels; and performing a replacement metal gate (RMG) module to replace the first replacement gate structure with the first gate structure.

15. The method of claim 14, wherein the first replacement dielectric material is formed before the RMG module is performed.

16. The method of claim 1, further comprising: forming a first etch-selective cap over the first channels; forming over the first etch-selective cap a plurality of second channels that are stacked over each other and extend along the top surface of the substrate; forming on each of the second channels at one end thereof a second S / D contact; forming a second gate structure for each of the second channels; andforming a second interconnect that connects the second S / D contacts and connects the first interconnect through an inter-tier via formed within the first etch-selective cap.

17. The method of claim 16, wherein forming the second interconnect includes: forming a second replacement dielectric material that covers the second S / D contacts before the second gate structure is formed; and replacing the second replacement dielectric material with the second interconnect after the second gate structure is formed.

18. The method of claim 16, wherein the semiconductor structure includes a complementary field-effective transistor (CFET) structure.

19. The method of claim 16, further comprising: forming a second etch-selective cap under the first interconnect.

20. The method of claim 16, wherein the first etch -selective cap is etched selectively with respect to the first replacement dielectric material.

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