Array substrate and display apparatus

Abstract

An array substrate and a display apparatus. The array substrate comprises a substrate (20), the substrate (20) comprising a display area (AA) and a non-display area (BB) located on at least one side of the display area (AA). The array substrate further comprises at least one first transistor (21) and at least one second transistor (22) arranged on the same side of the substrate (20), the at least one first transistor (21) comprising a first gate (19) and a first active layer (23), and the at least one second transistor (22) comprising a second gate (18) and a second active layer (17). In a direction perpendicular to the substrate (20), the minimum distance between the first active layer (23) and the substrate (20) is greater than the minimum distance between the second active layer (17) and the substrate (20), and the first active layer (23) and the second active layer (17) are located on opposite sides of the first gate (19).

Description

Array substrate and display device Technical Field

[0001] This article relates to but is not limited to the field of display technology, and in particular to an array substrate and a display device. Background Art

[0002] Liquid crystal displays (LCDs) are a common type of display. LCDs use two polarized materials with a liquid crystal solution (liquid crystal) between them. Applying a voltage across the two polarized materials causes the liquid crystal to deflect. The degree of deflection can be controlled by controlling the applied voltage. Currently, LCDs are being developed to be lightweight, thin, short, and compact.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] Embodiments of the present disclosure provide an array substrate and a display device.

[0006] In one aspect, embodiments of the present disclosure provide an array substrate. The array substrate includes a substrate, the substrate including a display area and a non-display area located on at least one side of the display area; the array substrate also includes at least one first transistor and at least one second transistor disposed on the same side of the substrate, the at least one first transistor including a first gate and a first active layer, and the at least one second transistor including a second gate and a second active layer; along a direction perpendicular to the substrate, the minimum spacing between the first active layer and the substrate is greater than the minimum spacing between the second active layer and the substrate, and the first active layer and the second active layer are located on opposite sides of the first gate.

[0007] In an exemplary embodiment, the first gate and the second gate are arranged in the same layer, the first active layer is located on a side of the first gate away from the substrate, and the second active layer is located on a side of the second gate close to the substrate.

[0008] In one exemplary embodiment, the display area includes the at least one first transistor, and the non-display area includes the at least one second transistor.

[0009] In an exemplary embodiment, the display area includes at least one data line, and the at least one data line is electrically connected to the first electrode of the at least one first transistor;

[0010] The first active layer includes a bottom surface, a top surface and a first side surface connecting the bottom surface and the top surface, and the bottom surface is closer to the substrate than the top surface; the partial surface of the at least one data line close to the substrate side is in contact and connected with the partial surface of the top surface, and part of the data line is in contact and connected with the first side surface.

[0011] In an exemplary embodiment, a first slope angle is formed between the first side surface and the bottom surface, and the first slope angle ranges from 45 degrees to 90 degrees.

[0012] In an exemplary embodiment, the at least one data line includes a contact portion, a portion of the surface of the contact portion close to the substrate is in contact with a portion of the surface of the top surface, and other portions of the data line except the contact portion are closer to the substrate than the contact portion.

[0013] In an exemplary embodiment, the first transistor includes a first electrode and a second electrode that are opposite to each other, and a material of the first electrode and a material of the second electrode are the same or different.

[0014] In an exemplary embodiment, the material of the first electrode is different from the material of the second electrode, and the material of the first electrode includes at least one of indium gallium zinc oxide, indium gallium tin oxide, indium tin zinc oxide, indium gallium zinc tin oxide, indium-free metal oxide and rare earth-doped oxide, and the material of the second electrode includes at least one of indium gallium zinc oxide, indium gallium tin oxide, indium tin zinc oxide, indium gallium zinc tin oxide, indium-free metal oxide and rare earth-doped oxide.

[0015] In an exemplary embodiment, a material of the second active layer includes at least one of indium gallium zinc oxide, indium gallium tin oxide, indium tin zinc oxide, indium gallium zinc tin oxide, indium-free metal oxide, and rare earth doped oxide.

[0016] In an exemplary embodiment, the display area further includes at least one first electrode, at least one data line and at least one pixel connection electrode, the at least one pixel connection electrode is located between the first electrode and the second electrode of the first transistor, and the first electrode and the second electrode of the first transistor are electrically connected via the pixel connection electrode.

[0017] In an exemplary embodiment, the pixel connection electrode and the data line are in the same layer structure.

[0018] In an exemplary embodiment, the first active layer includes a bottom surface, a top surface, and a first side surface and a second side surface connecting the bottom surface and the top surface; the bottom surface is closer to the substrate than the top surface; a portion of the surface of the at least one data line close to the substrate is in contact and connected with a portion of the surface of the top surface, and a portion of the data line is in contact and connected with the first side surface, and at least a portion of the surface of the pixel connection electrode close to the substrate is in contact and connected with a portion of the surface of the top surface.

[0019] In an exemplary embodiment, a portion of the pixel connection electrode is in contact with the second side surface.

[0020] In an exemplary embodiment, the display area further includes at least one first electrode, and the first electrode and the first active layer are connected to each other as an integral structure;

[0021] The display area further includes a second electrode, which is located on a side of the first electrode away from the substrate, and orthographic projections of the first electrode and the second electrode on a plane where the substrate is located at least partially overlap.

[0022] On the other hand, an embodiment of the present disclosure provides a display device, comprising the array substrate, opposing substrate and liquid crystal layer described in any of the aforementioned embodiments; the array substrate and the opposing substrate are arranged opposite to each other, and the liquid crystal layer is located between the array substrate and the opposing substrate.

[0023] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0024] Summary of the Figures

[0025] The accompanying drawings are intended to provide a further understanding of the technical solutions of the present disclosure and constitute part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of one or more components in the accompanying drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0026] FIG1A is a schematic cross-sectional view of an array substrate;

[0027] FIG1B is a partial cross-sectional schematic diagram of a display area of ​​an array substrate;

[0028] FIG2 is a schematic front view of an array substrate according to an embodiment of the present disclosure;

[0029] FIG3 is a partial cross-sectional schematic diagram of an array substrate according to an embodiment of the present disclosure;

[0030] 4A is a schematic plan view of an array substrate after a first conductive layer pattern is formed in the display region according to an embodiment of the present disclosure;

[0031] 4B is a cross-sectional schematic diagram of an array substrate after a first conductive layer pattern is formed in the display region according to an embodiment of the present disclosure;

[0032] 5A is a schematic plan view of an array substrate after a second semiconductor layer pattern is formed in the display region according to an embodiment of the present disclosure;

[0033] 5B is a schematic cross-sectional view of an array substrate after a second semiconductor layer pattern is formed in the display region according to an embodiment of the present disclosure;

[0034] 6A is a plan view schematically showing a second conductive layer pattern formed on the display region of an array substrate according to an embodiment of the present disclosure;

[0035] 6B is a schematic cross-sectional view of the array substrate after forming a second conductive layer pattern in the display region according to an embodiment of the present disclosure;

[0036] 7A is a plan view schematically showing a display region of an array substrate after a fourth insulating layer pattern is formed thereon according to an embodiment of the present disclosure;

[0037] 7B is a cross-sectional schematic diagram of an array substrate after a fourth insulating layer pattern is formed in the display region according to an embodiment of the present disclosure;

[0038] 8A is a plan view of an array substrate after a third conductive layer pattern is formed in the display region according to an embodiment of the present disclosure;

[0039] 8B is a schematic cross-sectional view of the array substrate after a third conductive layer pattern is formed in the display region according to an embodiment of the present disclosure;

[0040] 9A is a plan view of an array substrate after a fifth insulating layer pattern is formed in the display region according to an embodiment of the present disclosure;

[0041] 9B is a schematic cross-sectional view of the array substrate after a fifth insulating layer pattern is formed in the display region according to an embodiment of the present disclosure;

[0042] 10A is a plan view schematically showing a display region of an array substrate after a fourth conductive layer pattern is formed thereon according to an embodiment of the present disclosure;

[0043] 10B is a schematic cross-sectional view of an array substrate after a fourth conductive layer pattern is formed in the display region according to an embodiment of the present disclosure;

[0044] FIG11A is a plan view of an array substrate after a fifth conductive layer pattern is formed in the display region according to an embodiment of the present disclosure;

[0045] 11B is a schematic cross-sectional view of the array substrate after a fifth conductive layer pattern is formed in the display region according to an embodiment of the present disclosure;

[0046] FIG12A is a plan view of an array substrate after a sixth conductive layer pattern is formed in the display region according to an embodiment of the present disclosure;

[0047] 12B is a schematic cross-sectional view of the array substrate after a sixth conductive layer pattern is formed in the display region according to an embodiment of the present disclosure;

[0048] FIG13 is a cross-sectional schematic diagram of an array substrate according to another embodiment of the present disclosure;

[0049] 14A is a plan view of an array substrate after forming a second conductive layer pattern in the display region according to another embodiment of the present disclosure;

[0050] 14B is a cross-sectional schematic diagram of another embodiment of the present disclosure after a second conductive layer pattern is formed in the display region of the array substrate;

[0051] 15A is a plan view of an array substrate after a fifth insulating layer pattern is formed in the display region according to another embodiment of the present disclosure;

[0052] 15B is a schematic cross-sectional view of an array substrate after a fifth insulating layer pattern is formed in the display region according to another embodiment of the present disclosure;

[0053] 16A is a plan view of an array substrate after a sixth conductive layer pattern is formed in the display region according to another embodiment of the present disclosure;

[0054] 16B is a schematic cross-sectional view of an array substrate after a sixth conductive layer pattern is formed in the display region according to another embodiment of the present disclosure;

[0055] FIG17 is a cross-sectional schematic diagram of an array substrate according to another embodiment of the present disclosure;

[0056] 18A is a plan view of an array substrate after a fifth insulating layer pattern is formed in the display region according to another embodiment of the present disclosure;

[0057] 18B is a schematic cross-sectional view of an array substrate after a fifth insulating layer pattern is formed in the display region according to another embodiment of the present disclosure;

[0058] 19A is a plan view of an array substrate after a sixth conductive layer pattern is formed in the display region according to another embodiment of the present disclosure;

[0059] 19B is a cross-sectional schematic diagram of another embodiment of the present disclosure after a sixth conductive layer pattern is formed in the display region of the array substrate;

[0060] FIG20 is a schematic cross-sectional view of an array substrate according to yet another embodiment of the present disclosure;

[0061] FIG21 is a cross-sectional schematic diagram of an array substrate according to another embodiment of the present disclosure;

[0062] FIG22 is a schematic cross-sectional view of a display device according to an embodiment of the present disclosure.

[0063] Reference numerals: 100-data line, 200-active layer, 300-light-shielding structure; 10-pixel electrode, 21-first transistor, 22-second transistor, DL-data line, DL-1-inclined surface, DL-2-contact portion, GL-gate line, 20-substrate, 11-first insulating layer, 12-second insulating layer, 13-third insulating layer, 14-fourth insulating layer, 15-fifth insulating layer, 16-sixth insulating layer, 17-second active layer, 17-1-second channel region, 17-2-third region, 17-3-fourth region, 18-second gate, 19-first gate, 23-first active layer, 23-1-first region, 23-2-second region, 23-3-first channel region, 23-4-straight extension section, 23-5-oblique extension section, 23a-bottom surface, 23b-top surface, 23c-first side surface, 23d-second side surface, 24-first connecting electrode, 25-second connecting electrode, 26-pixel connecting electrode, 27-common electrode, 27-1-connecting portion, 27-2-comb tooth portion, 28-common electrode line; 1-opposing substrate, 2-liquid crystal layer, 3-black matrix, 4-color filter layer, 5-array substrate.

[0064] Details

[0065] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the method and content can be transformed into one or more forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other in any way.

[0066] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of one or more components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0067] The ordinal numbers such as "first," "second," and "third" in this disclosure are provided to avoid confusion among constituent elements, and are not intended to limit the number. The "plurality" in this disclosure includes two or more.

[0068] In this disclosure, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it should not be understood as a limitation of this disclosure. The positional relationships of constituent elements are appropriately changed according to the direction in which the constituent elements are described. Therefore, the words and phrases are not limited to those described in the specification and can be appropriately replaced according to the circumstances.

[0069] In this disclosure, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this disclosure based on the specific circumstances.

[0070] In this disclosure, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having one or more functions.

[0071] In this disclosure, a transistor refers to a device comprising at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0072] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in the present disclosure, "source electrode" and "drain electrode" may be interchanged.

[0073] In this disclosure, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus includes a state where the angle is greater than 85° and less than 95°.

[0074] In this disclosure, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0075] In the present disclosure, “about” and “approximately” refer to values ​​that are not strictly defined but allow for process and measurement errors.

[0076] The triangles, rectangles, trapezoids, pentagons or hexagons in the present disclosure are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0077] In recent years, near-eye display technology and head-mounted display devices, such as virtual reality (VR) technology, augmented reality (AR) and mixed reality (MR) technology, have attracted more and more attention. Many technology companies have increased their research and development efforts, hoping to develop related products for consumer terminals as soon as possible. VR / AR / MR products have increasingly higher requirements for the pixel density (pixels per inch, PPI) of display devices. With the continuous improvement of PPI, the problem of light leakage in local areas of the display area has become a bottleneck restricting the development of VR / AR / MR products using liquid crystal displays. As shown in Figure 1A, in the design structure of the existing array substrate, the data line 100 is connected to the active layer 200 of the transistor through the via D. The data line 100 is distorted at the climbing position of the via D. The distortion is shown in the dotted area in Figure 1B, which causes the light to be depolarized in this area, resulting in light leakage in local areas of the display area. Currently, a common solution to localized light leakage in the display area is to add a light-shielding structure 300 to the array substrate. As shown in Figure 1A, this structure blocks light leakage from via D. However, as VR / AR / MR products continue to increase their PPI requirements, for example, when the PPI exceeds 1500ppi, the adverse effect of the light-shielding structure 300 on the aperture ratio of the display area becomes increasingly apparent. Furthermore, the wide width of the data lines 100 in existing array substrates hinders improving the aperture ratio of the display area.

[0078] An embodiment of the present disclosure provides an array substrate, which includes a substrate, the substrate including a display area and a non-display area located on at least one side of the display area; the array substrate also includes at least one first transistor and at least one second transistor arranged on the same side of the substrate, the at least one first transistor including a first gate and a first active layer, and the at least one second transistor including a second gate and a second active layer; along a direction perpendicular to the substrate, the minimum spacing between the first active layer and the substrate is greater than the minimum spacing between the second active layer and the substrate, and the first active layer and the second active layer are located on opposite sides of the first gate.

[0079] The array substrate provided in the embodiment of the present disclosure can simplify the layout of the array substrate by setting the structure of the first transistor and the second transistor. The first transistor and the second transistor are set to a combination of a top gate structure and a bottom gate structure, which can improve the contrast of the display device and improve the display quality.

[0080] Figure 2 is a schematic front view of an array substrate according to one embodiment of the present disclosure. As shown in Figure 2, the array substrate may include a display area AA and a non-display area BB located on at least one side of the display area AA. The non-display area BB may include a first non-display area B1 located on one side of the display area AA and a second non-display area B2 located on the remaining sides of the display area AA. For example, the first non-display area B1 may include the bottom frame of the array substrate, and the second non-display area B2 may include the top, left, and right frames of the array substrate.

[0081] In one exemplary embodiment, as shown in FIG2 , the display area AA may include: a plurality of data lines DL and a plurality of gate lines GL disposed on a substrate. The plurality of gate lines GL may extend along a first direction X and be sequentially arranged along a second direction Y different from the first direction X. The plurality of data lines DL may extend along the second direction Y and be sequentially arranged along the first direction X. The first direction X and the second direction Y may intersect; for example, the first direction X may be perpendicular to the second direction Y. The plurality of data lines DL and the plurality of gate lines GL may be located in different film layers; for example, the plurality of data lines DL may be located on a side of the plurality of gate lines GL away from the substrate.

[0082] In an exemplary embodiment, as shown in FIG2 , a plurality of data lines DL and a plurality of gate lines GL may intersect to form a plurality of sub-pixel areas. The area defined by the intersection of adjacent data lines DL and adjacent gate lines GL may be a sub-pixel area. A sub-pixel may be provided in a corresponding sub-pixel area. The sub-pixel area may include an opening area and a non-opening area surrounding the opening area. The non-opening area may be an area blocked by the black matrix of the opposing substrate of the array substrate, and the opening area may be an area not blocked by the black matrix of the opposing substrate. Adjacent gate lines GL and data lines DL may both be located within the non-opening area. The array substrate of the disclosed embodiment may be used to implement a display function, and the opening area of ​​each sub-pixel area may be configured for display. The non-opening area surrounds the opening area and does not display. However, the disclosed embodiment is not limited to this. In some examples, the array substrate may be used to implement other functions.

[0083] In one exemplary embodiment, the display area AA may include: a plurality of pixel units disposed on a substrate. At least one pixel unit may include: three sub-pixels (e.g., a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged sequentially along a first direction X). The three sub-pixels of the pixel unit may be, for example, a blue sub-pixel, a red sub-pixel, and a green sub-pixel, and the three sub-pixels may be arranged sequentially in the order of blue sub-pixel, red sub-pixel, and green sub-pixel. As shown in FIG2 , at least one sub-pixel may include: a pixel electrode 10 and a common electrode (not shown in FIG2 ), and the orthographic projections of the pixel electrode 10 and the common electrode of the sub-pixel on the substrate may overlap. The common electrode of the plurality of sub-pixels in the display area AA may be a single-piece structure. For example, the common electrode may be located on a side of the pixel electrode 10 away from the substrate. The sub-pixel may also include a first transistor 21. The first transistor 21 may be located adjacent to the intersection of a data line DL and a gate line GL. The first transistor 21 may include a first gate, a first electrode, and a second electrode. The first gate may be electrically connected to the gate line GL, the first electrode of the first transistor 21 may be electrically connected to the data line DL, and the second electrode may be electrically connected to the pixel electrode 10 of the sub-pixel. The first transistor 21 may be configured to provide a data signal transmitted by the data line DL to the pixel electrode 10 of the sub-pixel under the control of the gate line GL.

[0084] In an exemplary embodiment, the second non-display area B2 may include at least a gate drive circuit (e.g., including a plurality of cascaded shift registers), and the plurality of shift registers may be electrically connected to the plurality of gate lines GL in the display area AA. The gate drive circuit may further include a second transistor. The second transistor may include a second gate, a first electrode, and a second electrode. In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.

[0085] Liquid crystal display devices have various display modes, such as ADS (Advanced Super Dimension Switch) mode, TN (twisted nematic) mode, and VA (Vertical Alignment) mode. In the ADS mode, the pixel electrode and common electrode are both located on one side of the array substrate. In the TN and VA modes, the pixel electrode and common electrode are respectively arranged on opposite sides of the liquid crystal layer, with the pixel electrode located on one side of the array substrate and the common electrode on the opposite substrate.

[0086] The ADS mode operates on the principle that liquid crystal molecules lie in a plane parallel to the glass substrate. When no voltage is applied, light passing through the lower polarizer becomes linearly polarized, parallel to the short axis of the liquid crystal molecules. This polarization cannot be rotated, and is therefore absorbed by the upper polarizer and prevented from exiting. When voltage is applied, a transverse electric field forms on the liquid crystal, aligning the liquid crystal molecules along the direction of the electric field. After passing through the lower polarizer and the liquid crystal layer, the light becomes elliptically polarized, allowing it to pass through the upper polarizer and exit.

[0087] The TN mode operates under the principle that in the absence of voltage, the liquid crystal molecules are twisted into a 90° alignment by the alignment films. Light passes through the lower polarizer and the liquid crystal molecules before exiting through the upper polarizer. When voltage is applied, most of the liquid crystal molecules, except for those near the upper and lower polarizers, align vertically. Light passing through the lower polarizer passes through the liquid crystal layer without deflection. However, since its polarization axis is parallel to the upper polarizer, the light is absorbed and cannot be emitted.

[0088] The VA mode operates on the principle that liquid crystal molecules are aligned perpendicular to the glass substrate. When no voltage is applied, light passing through the lower polarizer forms linear polarization parallel to the short axis of the liquid crystal molecules. This polarization cannot be rotated, and is therefore absorbed by the upper polarizer and prevented from being emitted. When voltage is applied, the liquid crystal molecules are deflected in the direction of the electric field. Light passing through the lower polarizer and liquid crystal layer becomes elliptically polarized, allowing it to pass through the upper polarizer and be emitted.

[0089] The structure of the array substrate is described below by taking the ADS mode array substrate structure as an example.

[0090] FIG3 is a partial cross-sectional schematic diagram of an array substrate according to an embodiment of the present disclosure. As shown in FIG3 , the array substrate may include a substrate 20 and a first semiconductor layer, a first conductive layer, a second semiconductor layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer sequentially arranged on one side of the substrate 20. The array substrate may further include a first insulating layer 11 located between the first semiconductor layer and the substrate 20, a second insulating layer 12 located between the first semiconductor layer and the first conductive layer, a third insulating layer 13 located between the first conductive layer and the second semiconductor layer, a fourth insulating layer 14 located between the second conductive layer and the third conductive layer, a fifth insulating layer 15 located between the third conductive layer and the fourth conductive layer, and a sixth insulating layer 16 located between the fourth conductive layer and the fifth conductive layer. In the embodiment of the present disclosure, the first insulating layer may also be referred to as a buffer layer, the second insulating layer may also be referred to as a gate insulating (GI) layer, the third insulating layer may also be referred to as an interlayer insulating (ILD) layer, the fourth insulating layer may also be referred to as a first passivation (PVX1) layer, the fifth insulating layer may also be referred to as a planarization (PLN) layer, and the sixth insulating layer may also be referred to as a second passivation (PVX2) layer.

[0091] As shown in FIG3 , the array substrate includes a display area AA and a non-display area BB. The display area AA may include multiple first transistors 21, and the non-display area BB may include multiple second transistors 22. FIG3 illustrates only one first transistor 21 and one second transistor 22 as an example. The first semiconductor layer may include the second active layer 17 of the second transistor 22. The first conductive layer may include the second gate 18 of the second transistor 22, the first gate 19 of the first transistor 21, and the gate line GL. The second semiconductor layer may include the first active layer 23 of the first transistor 21. The second conductive layer may include a first connection electrode 24, a second connection electrode 25, and a data line DL. As shown in FIG3 , the orthographic projection of the first connection electrode 24 on the array substrate at least partially overlaps with the orthographic projection of the second active layer 17 on the array substrate, and the orthographic projection of the second connection electrode 25 on the array substrate at least partially overlaps with the orthographic projection of the second active layer 17 on the array substrate. Both the first connection electrode 24 and the second connection electrode 25 are electrically connected to the second active layer 17. The portion of the surface of the data line DL on the side close to the substrate 20 contacts the portion of the surface of the first active layer 23 on the side away from the substrate 20. The third conductive layer may include a pixel connection electrode 26, the orthographic projection of the pixel connection electrode 26 on the array substrate at least partially overlaps with the orthographic projection of the first active layer 23 on the array substrate, and the pixel connection electrode 26 is electrically connected to the first active layer 23. The fourth conductive layer may include a pixel electrode 10, the orthographic projection of the pixel electrode 10 on the array substrate may at least partially overlap with the orthographic projection of the pixel connection electrode 26 on the array substrate, and the pixel electrode 10 is electrically connected to the first active layer 23 of the first transistor 21 via the pixel connection electrode 26. The sixth conductive layer may include a common electrode 27, the orthographic projection of the common electrode 27 on the array substrate may at least partially overlap with the orthographic projection of the pixel electrode 10 on the array substrate. In the embodiment of the present disclosure, the pixel electrode 10 may also be referred to as the first electrode of a sub-pixel, and the common electrode 27 may also be referred to as the second electrode of a sub-pixel. Alternatively, the pixel electrode 10 may also be referred to as the second electrode of a sub-pixel, and the common electrode 27 may also be referred to as the first electrode of a sub-pixel.

[0092] As shown in Figure 3, the fifth conductive layer may include at least one common electrode line 28. The orthographic projection of the common electrode line 28 on the array substrate may at least partially overlap with the orthographic projection of the data line DL on the array substrate. For example, the orthographic projection of the common electrode line 28 on the array substrate may be located within the orthographic projection of the data line DL on the array substrate, thereby avoiding the influence of the common electrode line on the aperture ratio of the display area. The common electrodes of multiple sub-pixels may all be electrically connected to the same common electrode line. A portion of the surface of the common electrode line 28 away from the substrate 20 may be in contact with a portion of the surface of the common electrode 27 close to the substrate 20, so that the connection between the common electrode and the common electrode line does not require the provision of a via, thereby reducing the resistance of the common electrode and improving the uniformity of the common electrode voltage.

[0093] In one exemplary embodiment, as shown in FIG3 , along a direction perpendicular to the substrate 20, the minimum spacing between the first active layer 23 and the substrate 20 is d1, and the minimum spacing between the second active layer 17 and the substrate 20 is d2, where d1 is greater than d2. The first active layer 23 and the second active layer 17 are located on opposite sides of the first gate 19. For example, the first active layer 23 is located on a side of the first gate 19 away from the substrate 20, and the second active layer 17 is located on a side of the first gate 19 closer to the substrate 20. In the disclosed embodiment, the first active layer 23 and the second active layer 17 are located on opposite sides of the first gate 19. Opposite sides refer to being located on opposite sides of the first gate along a direction perpendicular to the substrate. The direction perpendicular to the substrate may also be referred to as the thickness direction of the array substrate.

[0094] In an exemplary embodiment, the substrate 20 may be a transparent substrate. For example, the substrate 20 may be a rigid substrate or a flexible substrate. For example, the material of the rigid substrate may include, but is not limited to, one or more of glass and quartz. The material of the flexible substrate may include, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. However, the present disclosure is not limited to this.

[0095] In an exemplary embodiment, the materials of the first conductive layer, the second conductive layer, and the fifth conductive layer can be metal materials, such as any one or more of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti). Alternatively, the materials of the first conductive layer, the second conductive layer, and the fifth conductive layer can be alloy materials of metal materials such as molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), such as aluminum-neodymium alloy (AlNd), molybdenum-niobium alloy (MoNb), and molybdenum-nickel-titanium alloy (MoNiTi). The first conductive layer, the second conductive layer, and the fifth conductive layer can be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti, Mo / Nb / Cu, MoNiTi / Cu, MoNb / Cu / MoNiTi, or MoNiTi / Cu / MoNiTi, etc.

[0096] In one exemplary embodiment, the thickness of the first conductive layer may range from 1000 angstroms to 8000 angstroms.

[0097] In one exemplary embodiment, the second conductive layer may have a thickness ranging from 1000 angstroms to 8000 angstroms.

[0098] In one exemplary embodiment, the third conductive layer, the fourth conductive layer, and the sixth conductive layer may be made of a transparent conductive oxide material, which may include indium tin oxide (ITO) or indium zinc oxide (IZO). For example, the third conductive layer, the fourth conductive layer, and the sixth conductive layer may be a single layer structure or a multilayer composite structure, such as ITO / Al / ITO.

[0099] In an exemplary embodiment, the first insulating layer 11, the second insulating layer 12, the third insulating layer 13, the fourth insulating layer 14 and the sixth insulating layer 16 may be made of inorganic materials. For example, silicon oxynitride (SiO x N y ) or silicon nitride (SiN x ) or silicon oxide (SiO x ) and the like. The first insulating layer 11, the second insulating layer 12, the third insulating layer 13, the fourth insulating layer 14, and the sixth insulating layer 16 can be a single layer, a multilayer, or a composite layer structure. For example, the first insulating layer 11 can be a composite layer structure of a silicon nitride (SiN) layer and a silicon dioxide (SiO2) layer, the thickness of the silicon nitride layer can range from 300 angstroms to 2000 angstroms, and the thickness of the silicon dioxide layer can range from 1000 angstroms to 5000 angstroms. For example, the thickness of the second insulating layer 12 can range from 500 angstroms to 3000 angstroms. The thickness of the third insulating layer 13 can range from 1000 angstroms to 8000 angstroms.

[0100] In one exemplary embodiment, the third insulating layer 13 may include at least one silicon dioxide layer and at least one silicon nitride layer, and the silicon dioxide layer may be in contact with the second semiconductor layer. For example, the third insulating layer 13 may be a composite layer structure of a silicon dioxide layer, a silicon nitride layer, and a silicon dioxide layer, with the silicon nitride layer located between the two silicon dioxide layers.

[0101] In one exemplary embodiment, the insulating layer in contact with the second semiconductor layer may be an inorganic oxide layer. For example, the inorganic oxide layer may be a silicon oxide layer, an aluminum oxide layer, or a zirconium oxide layer. The inorganic oxide layer can prevent conductivity issues in the second semiconductor layer and improve the performance of the first transistor. For example, the insulating layer in contact with the side of the second semiconductor layer away from the substrate is an inorganic oxide layer, or the insulating layer in contact with both sides of the second semiconductor layer along its thickness direction is an inorganic oxide layer.

[0102] In one exemplary embodiment, the insulating layer in contact with the first semiconductor layer may be an inorganic oxide layer. For example, the inorganic oxide layer may be a silicon oxide layer, an aluminum oxide layer, or a zirconium oxide layer. The inorganic oxide layer can prevent conductivity issues in the first semiconductor layer and improve the performance of the second transistor. For example, the insulating layer in contact with the side of the first semiconductor layer away from the substrate is an inorganic oxide layer, or the insulating layer in contact with both sides of the first semiconductor layer along its thickness direction is an inorganic oxide layer.

[0103] In one exemplary embodiment, the fifth insulating layer 15 can be made of an organic material. Examples of such organic materials include any one or more of epoxy resin, phenolic resin, urea-formaldehyde resin, melamine-formaldehyde resin, furan resin, silicone resin, polyester resin, polyamide resin, acrylic resin, polyurethane, vinyl resin, hydrocarbon resin, and polyether resin. The fifth insulating layer 15 can be a single layer, a multilayer structure, or a composite layer structure. In the disclosed embodiment, providing an organic insulating layer can reduce crosstalk from the first gate to the common electrode.

[0104] In an exemplary embodiment, the materials of the first semiconductor layer and the second semiconductor layer may include one or more materials selected from the group consisting of indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), zinc tin oxide (ZTO), indium-free metal oxide (In-free OS), and rare earth doped oxide (Ln-OS). The materials of the first semiconductor layer and the second semiconductor layer may be amorphous, partially crystalline, single crystal, or polycrystalline, and may also be a single layer or multilayer structure. In an example, the materials of the first semiconductor layer and the second semiconductor layer may be various materials such as amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, and polythiophene. The array substrate provided in the embodiment of the present disclosure is suitable for transistors manufactured based on oxide technology, silicon technology, and organic technology.

[0105] In one exemplary embodiment, the thickness of the first semiconductor layer may be in a range of 100 angstroms to 1000 angstroms.

[0106] In one exemplary embodiment, as shown in FIG3 , the orthographic projection of the first active layer 23 on the array substrate may at least partially overlap with the orthographic projection of the first gate 19 on the array substrate. The first active layer 23 may include a first channel region 23-3, a first region 23-1 located on opposite sides of the first channel region 23-3, and a second region 23-2 located on opposite sides of the first channel region 23-3. The orthographic projection of the first gate 19 on the array substrate may at least partially overlap with the orthographic projection of the first channel region 23-3 on the array substrate. The first gate may block at least some light from affecting the first channel region, thereby improving the performance of the first transistor.

[0107] For example, during the preparation of the array substrate, a portion of the first active layer 23 can be subjected to a conductorization treatment so that the portions of the first active layer 23 form a first region 23-1 and a second region 23-2, respectively. The first region 23-1 of the first active layer 23 can be used as the first electrode of the first transistor, and the second region 23-2 of the first active layer 23 can be used as the second electrode of the first transistor. By conducting a conductorization treatment on a portion of the first active layer to form the first electrode and the second electrode of the first transistor, compared to a solution in which the first gate is energized to achieve conduction in the first channel region, the array substrate solution provided in the embodiment of the present disclosure can reduce the area of ​​the first gate, thereby avoiding the impact of the first gate on the aperture ratio of the display area, and facilitating the application of the array substrate to small-sized, high-resolution products such as near-eye displays.

[0108] In an exemplary embodiment, the first active layer 23 may include two or more sub-active layers. For example, the first active layer 23 may include two sub-active layers, or the first active layer 23 may include three sub-active layers, etc. The materials of each of the two or more sub-active layers may be the same or different.

[0109] In one exemplary embodiment, as shown in FIG3 , the orthographic projection of the second active layer 17 on the array substrate may at least partially overlap with the orthographic projection of the second gate electrode 18 on the array substrate. The second active layer 17 may include a second channel region 17-1, and a third region 17-2 and a fourth region 17-3 located on opposite sides of the second channel region 17-1. The orthographic projection of the second gate electrode 18 on the array substrate may at least partially overlap with the orthographic projection of the second channel region 17-1 on the array substrate.

[0110] For example, during the process of preparing the array substrate, a portion of the second active layer 17 can be subjected to a conductorization process so that portions of the second active layer 17 form a third region 17-2 and a fourth region 17-3, respectively. The third region 17-2 of the second active layer 17 can be used as the first electrode of the second transistor, and the fourth region 17-3 of the second active layer 17 can be used as the second electrode of the second transistor. The present embodiment does not limit the conductorization process for the semiconductor layer. As shown in Figure 3, the first connection electrode 24 is electrically connected to the third region 17-2, and the second connection electrode 25 is electrically connected to the fourth region 17-3.

[0111] In an exemplary embodiment, the first transistor includes a first electrode and a second electrode that are opposite to each other, and a material of the first electrode and a material of the second electrode are the same or different.

[0112] In an exemplary embodiment, the material of the first electrode is different from the material of the second electrode, and the material of the first electrode includes at least one of indium gallium zinc oxide, indium gallium tin oxide, indium tin zinc oxide, indium gallium zinc tin oxide, indium-free metal oxide and rare earth-doped oxide, and the material of the second electrode includes at least one of indium gallium zinc oxide, indium gallium tin oxide, indium tin zinc oxide, indium gallium zinc tin oxide, indium-free metal oxide and rare earth-doped oxide.

[0113] In an exemplary embodiment, the material of the second active layer includes at least one of indium gallium zinc oxide, indium gallium tin oxide, indium tin zinc oxide, indium gallium zinc tin oxide, indium-free metal oxide, and rare earth doped oxide.

[0114] The structure of the array substrate is described below using an example of its fabrication process. The "patterning process" referred to in the embodiments of this disclosure includes processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping for metal, inorganic, or transparent conductive materials. For organic materials, it includes processes such as organic material coating, mask exposure, and development. The deposition process can be any one or more of sputtering, evaporation, and chemical vapor deposition; the coating process can be any one or more of spray coating, spin coating, and inkjet printing; and the etching process can be any one or more of dry etching and wet etching, although this disclosure does not limit this. A "thin film" refers to a thin layer of a material formed on a substrate using deposition, coating, or other processes. If a "thin film" does not require a patterning process during the entire fabrication process, it can also be referred to as a "layer." If a "thin film" requires a patterning process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process. A "layer" after the patterning process contains at least one "pattern." The term "A and B in the same layer" as used in this disclosure means that A and B are formed through the same patterning process.

[0115] The preparation process of the array substrate may include the following steps:

[0116] (11) Forming a first semiconductor layer pattern. Forming the first semiconductor layer pattern may include: sequentially depositing a first insulating film and a first semiconductor film on one side of the substrate, patterning the first semiconductor film through a patterning process to form a first insulating layer located on one side of the substrate, and a first semiconductor layer pattern located on a side of the first insulating layer away from the substrate, wherein the first semiconductor layer may include a second active layer of the second transistor.

[0117] (12) Forming a first conductive layer pattern. Forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on one side of the substrate 20 on which the aforementioned pattern is formed, and patterning the first conductive film through a patterning process to form a second insulating layer pattern located on a side of the first semiconductor layer away from the substrate 20, and a first conductive layer pattern located on a side of the second insulating layer 12 away from the substrate 20. The first conductive layer may include a second gate of the second transistor, a first gate 19 of the first transistor 21, and a gate line GL, as shown in FIG4A and FIG4B , with FIG4B being a cross-sectional view taken along line AA in FIG4A .

[0118] 4A , the gate line GL may be in the shape of a line extending along the first direction X. The first gate electrode 19 and the gate line GL may be an integrated structure connected to each other.

[0119] (13) Forming a second semiconductor layer pattern. Forming the second semiconductor layer pattern may include: sequentially depositing a third insulating film and a second semiconductor film on one side of the substrate 20 on which the aforementioned pattern is formed, patterning the second semiconductor film through a patterning process to form a third insulating layer pattern located on a side of the first conductive layer away from the substrate 20 and a second semiconductor layer pattern located on a side of the third insulating layer 13 away from the substrate 20. The second semiconductor layer may include the first active layer 23 of the first transistor 21, as shown in FIG5A and FIG5B. FIG5B is a cross-sectional view taken along the AA line in FIG5A. In FIG5B, the first active layer 23 is not graphically filled to facilitate parameter identification.

[0120] As shown in FIG5A , the first active layer 23 may include a connected straight extension segment 23-4 and an oblique extension segment 23-5. The straight extension segment 23-4 may include a first end and a second end disposed opposite each other, and the second end may extend along a first direction X. The first end of the oblique extension segment 23-5 is connected to the second end of the straight extension segment 23-4, and the second end of the oblique extension segment 23-5 extends along a direction different from the first direction X and the second direction Y. For example, the second end of the oblique extension segment 23-5 extends along a diagonal direction opposite to the first direction X and the second direction Y. For example, the orthographic projection of the oblique extension segment 23-5 on the array substrate partially overlaps with the orthographic projection of the gate line GL on the array substrate.

[0121] As shown in FIG5B , forming the second semiconductor layer pattern may further include performing a conductor treatment on a portion of the first active layer 23, so that the first active layer 23 forms a first region 23-1 and a second region 23-2. The first region 23-1 of the first active layer 23 may be used as a first electrode of the first transistor, and the second region 23-2 of the first active layer 23 may be used as a second electrode of the first transistor.

[0122] As shown in FIG5B , the first active layer 23 may include a bottom surface 23a and a top surface 23b disposed opposite each other, and a first side surface 23c connecting the bottom surface 23a and the top surface 23b. The bottom surface 23a is closer to the substrate 20 than the top surface 23b. A first slope angle α1 is formed between the first side surface 23c and the bottom surface 23a. The first slope angle α1 can range from 45 degrees to 90 degrees. For example, the first slope angle α1 can be 70 degrees. Portions of subsequently formed data lines can contact and mate with the first side surface 23c and the top surface 23b of the first active layer 23. This increases the contact area between the data lines and the first active layer 23, ensuring the reliability of the electrical connection between the data lines and the first active layer 23. In the disclosed embodiments, by limiting the range of the first slope angle α1, distortion of the data lines during the ramping process can be prevented, ensuring the contact yield between the data lines and the first active layer, and, to a certain extent, avoiding light leakage.

[0123] As shown in FIG5B , the first active layer 23 may further include a second side surface 23d, which connects the bottom surface 23a and the top surface 23b. A second slope angle α2 is formed between the second side surface 23d and the bottom surface 23a. The second slope angle α2 may range from 45 degrees to 90 degrees. For example, the second slope angle α2 may be 70 degrees. In one example, the first slope angle α1 and the second slope angle α2 may be the same or different.

[0124] (14) Forming a second conductive layer pattern. Forming the second conductive layer pattern may include: depositing a second conductive film on one side of the substrate 20 on which the aforementioned pattern is formed, and patterning the second conductive film through a patterning process to form a second conductive layer pattern located on a side of the second semiconductor layer away from the substrate 20. The second conductive layer may include a first connecting electrode, a second connecting electrode, and a data line DL, as shown in FIG6A and FIG6B , with FIG6B being a cross-sectional view taken along line AA in FIG6A .

[0125] As shown in FIG. 6A , the data line DL may be in a line shape extending along the second direction Y. As shown in FIG.

[0126] As shown in Figure 6B, the data line DL and the first active layer 23 are not filled with patterns to facilitate parameter identification. The data line DL has an inclined surface DL-1, which contacts the first side surface 23c of the first active layer 23. The inclined surface DL-1 and the first side surface 23c can have the same slope angle, which can improve the bonding performance between the data line DL and the first active layer 23. The inclined surface DL-1 has a slope angle β with the bottom surface 23a. The slope angle β can range from 45 degrees to 90 degrees. For example, the slope angle β can be 70 degrees.

[0127] As shown in Figure 6B, the data line DL may further include a contact portion DL-2, wherein a portion of the surface of the contact portion DL-2 close to the substrate 20 is in contact and connected with a portion of the surface of the top surface 23b, and other portions of the data line DL except the contact portion DL-2 are closer to the substrate 20 than the contact portion DL-2, thereby avoiding the need to set a via for data line connection on the insulating layer, and avoiding problems such as light leakage.

[0128] (15) Forming a fourth insulating layer pattern. Forming the fourth insulating layer pattern may include: depositing a fourth insulating film on one side of the substrate 20 on which the aforementioned pattern is formed, patterning the fourth insulating film through a patterning process to form a fourth insulating layer pattern located on the side of the second conductive layer away from the substrate 20, the fourth insulating layer 14 may include at least one first via K1, the fourth insulating film in the first via K1 is etched away, and the first via K1 exposes a portion of the surface of the first active layer 23 away from the substrate 20, the first via K1 is configured so that a subsequently formed pixel connection electrode is electrically connected to the first active layer 23 via the via, as shown in FIG7A and FIG7B, FIG7B is a cross-sectional view taken along line AA in FIG7A.

[0129] As shown in FIG7A , the orthographic projection of the first via hole K1 on the array substrate at least partially overlaps with the orthographic projection of the first active layer 23 on the array substrate. For example, the orthographic projection of the first via hole K1 on the array substrate may be located within the orthographic projection of the first active layer 23 on the array substrate.

[0130] In some exemplary embodiments, the first via hole K1 may be a circular hole, a rectangular hole, an elliptical hole, a hexagonal hole, or the like.

[0131] (16) Forming a third conductive layer pattern. Forming the third conductive layer pattern may include: depositing a third conductive film on one side of the substrate 20 on which the aforementioned pattern is formed, and patterning the third conductive film through a patterning process to form a third conductive layer pattern located on a side of the fourth insulating layer 14 away from the substrate 20. The third conductive layer may include a pixel connection electrode 26, as shown in FIG8A and FIG8B, with FIG8B being a cross-sectional view taken along line AA in FIG8A.

[0132] As shown in FIG8A , the pixel connection electrode 26 may be rectangular, and the orthographic projection of the pixel connection electrode 26 on the array substrate may at least partially overlap with the orthographic projection of the first active layer 23 on the array substrate. The pixel connection electrode 26 may be electrically connected to the first active layer 23 via a first via K1. In the disclosed embodiment, the provision of the pixel connection electrode can reduce the depth of the via hole that electrically connects the pixel electrode to the first transistor, thereby ensuring the reliability of the connection between the pixel electrode and the first transistor.

[0133] As shown in FIG. 8A , the pixel connection electrode 26 may be located between two adjacent data lines DL.

[0134] (17) Forming a fifth insulating layer pattern. Forming the fifth insulating layer pattern may include: depositing a fifth insulating film on one side of the substrate 20 on which the aforementioned pattern is formed, patterning the fifth insulating film through a patterning process to form a fifth insulating layer pattern located on the side of the third conductive layer away from the substrate 20, the fifth insulating layer 15 may include at least one second via hole K2, the fifth insulating film in the second via hole K2 is etched away, and the second via hole K2 exposes a portion of the surface of the pixel connection electrode 26 away from the substrate 20, and the second via hole K2 is configured so that a subsequently formed pixel electrode is electrically connected to the pixel connection electrode 26 via the via hole, as shown in FIG9A and FIG9B, FIG9B is a cross-sectional view taken along line AA in FIG9A.

[0135] As shown in FIG9A , the orthographic projection of the second via hole K2 on the array substrate may at least partially overlap with the orthographic projection of the pixel connection electrode 26 on the array substrate. For example, the orthographic projection of the second via hole K2 on the array substrate may be located within the orthographic projection of the pixel connection electrode 26 on the array substrate.

[0136] In some exemplary embodiments, the second via hole K2 may be a circular hole, a rectangular hole, an elliptical hole, a hexagonal hole, etc. The shape and size of the second via hole K2 may be the same as or different from that of the first via hole K1.

[0137] (18) Forming a fourth conductive layer pattern. Forming the fourth conductive layer pattern may include: depositing a fourth conductive film on one side of the substrate 20 on which the aforementioned pattern is formed, and patterning the fourth conductive film through a patterning process to form a fourth conductive layer pattern located on a side of the fifth insulating layer 15 away from the substrate 20. The fourth conductive layer may include the pixel electrode 10, as shown in FIG10A and FIG10B, with FIG10B being a cross-sectional view taken along line AA in FIG10A.

[0138] As shown in FIG10A , the orthographic projection of the pixel electrode 10 on the array substrate may be an irregular rectangular shape. The orthographic projection of the pixel electrode 10 on the array substrate may at least partially overlap with the orthographic projection of the pixel connection electrode 26 on the array substrate. For example, the orthographic projection of the pixel electrode 10 on the array substrate may include the orthographic projection of the pixel connection electrode 26 on the array substrate. The pixel electrode 10 may be connected to the pixel connection electrode 26 via the second via K2 to achieve connection with the first active layer of the first transistor.

[0139] (19) Forming a fifth conductive layer pattern. Forming the fifth conductive layer pattern may include: sequentially depositing a sixth insulating film and a fifth conductive film on one side of the substrate 20 on which the aforementioned pattern is formed, patterning the fifth conductive film through a patterning process to form a sixth insulating layer pattern located on a side of the fourth conductive layer away from the substrate 20, and a fifth conductive layer pattern located on a side of the sixth insulating layer 16 away from the substrate 20. The fifth conductive layer may include at least one common electrode line 28, as shown in FIG11A and FIG11B, FIG11B being a cross-sectional view taken along line AA in FIG11A.

[0140] As shown in FIG11A , the common electrode line 28 may be linear and extend along the second direction Y. A plurality of common electrode lines 28 may be arranged at intervals along the first direction X. The orthographic projection of the common electrode line 28 on the array substrate may at least partially overlap with the orthographic projection of the data line DL on the array substrate. For example, the orthographic projection of the common electrode line 28 on the array substrate may be within the orthographic projection of the data line DL on the array substrate, thereby preventing the common electrode line from affecting the aperture ratio of the display area.

[0141] (20) Forming a sixth conductive layer pattern. Forming the sixth conductive layer pattern may include: depositing a sixth conductive film on one side of the substrate 20 on which the aforementioned pattern is formed, and patterning the sixth conductive film through a patterning process to form a sixth conductive layer pattern located on a side of the fifth conductive layer away from the substrate 20. The sixth conductive layer may include a common electrode 27, as shown in FIG12A and FIG12B, with FIG12B being a cross-sectional view taken along line AA in FIG12A.

[0142] As shown in FIG12A , the common electrode 27 may include a connecting portion 27 - 1 and a plurality of comb-tooth portions 27 - 2 connected to each other. The connecting portion 27 - 1 may be rectangular and extend along the first direction X. The first ends of the plurality of comb-tooth portions 27 - 2 may be connected to the connecting portion 27 - 1, and the second ends of the plurality of comb-tooth portions 27 - 2 may extend in a direction opposite to the second direction Y. For example, the plurality of comb-tooth portions 27 - 2 may be arranged at equal intervals along the first direction X.

[0143] As shown in Figure 12A, part of the surface of the common electrode 27 close to the substrate 20 is in contact with part of the surface of the common electrode line 28 away from the substrate 20, which can avoid the need to set up vias for electrically connecting the common electrode and the common electrode line, simplify the film layer structure of the array substrate, reduce the resistance of the common electrode, and improve the uniformity of the common electrode voltage.

[0144] Figure 13 is a schematic cross-sectional view of an array substrate according to another embodiment of the present disclosure. As shown in Figure 13, the array substrate may include a substrate 20, and a first semiconductor layer, a first conductive layer, a second semiconductor layer, a second conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer sequentially arranged on one side of the substrate 20. The array substrate may further include a first insulating layer 11 located between the first semiconductor layer and the substrate 20, a second insulating layer 12 located between the first semiconductor layer and the first conductive layer, a third insulating layer 13 located between the first conductive layer and the second semiconductor layer, a fourth insulating layer 14 and a fifth insulating layer 15 located between the second conductive layer and the fourth conductive layer, and a sixth insulating layer 16 located between the fourth conductive layer and the fifth conductive layer.

[0145] As shown in Figure 13, the array substrate includes a display area AA and a second non-display area B2. The display area AA may include multiple first transistors 21, and the second non-display area B2 may include multiple second transistors 22. Figure 13 illustrates only one first transistor 21 and one second transistor 22. The first semiconductor layer may include the second active layer 17 of the second transistor 22. The first conductive layer may include the second gate electrode 18 of the second transistor 22, the first gate electrode 19 of the first transistor 21, and the gate line GL. The second semiconductor layer may include the first active layer 23 of the first transistor 21. The second conductive layer may include a first connection electrode 24, a second connection electrode 25, a data line DL, and a pixel connection electrode 26. As shown in Figure 13, a portion of the surface of the data line DL near the substrate 20 contacts a portion of the surface of the first active layer 23 away from the substrate 20. A portion of the surface of the pixel connection electrode 26 near the substrate 20 contacts a portion of the surface of the first active layer 23 away from the substrate 20. In this exemplary embodiment, disposing the pixel connection electrode in the second conductive layer reduces the number of conductive layers, simplifies the array substrate manufacturing process, and reduces the manufacturing cost of the array substrate.

[0146] As shown in FIG13 , the fourth conductive layer may include a pixel electrode 10. The orthographic projection of the pixel electrode 10 on the array substrate may at least partially overlap with the orthographic projection of the pixel connection electrode 26 on the array substrate. The pixel electrode 10 is electrically connected to the first active layer 23 of the first transistor 21 via the pixel connection electrode 26. The sixth conductive layer may include a common electrode 27. The orthographic projection of the common electrode 27 on the array substrate may at least partially overlap with the orthographic projection of the pixel electrode 10 on the array substrate.

[0147] As shown in Figure 13, the fifth conductive layer may include at least one common electrode line 28. The orthographic projection of the common electrode line 28 on the array substrate may at least partially overlap with the orthographic projection of the data line DL on the array substrate. For example, the orthographic projection of the common electrode line 28 on the array substrate may be located within the orthographic projection of the data line DL on the array substrate, thereby avoiding the influence of the common electrode line on the aperture ratio of the display area. The common electrodes of multiple sub-pixels may all be electrically connected to the same common electrode line. A portion of the surface of the common electrode line 28 away from the substrate 20 may be in contact with a portion of the surface of the common electrode 27 close to the substrate 20, so that the connection between the common electrode and the common electrode line does not require the provision of a via, which can reduce the resistance of the common electrode and improve the uniformity of the common electrode voltage.

[0148] The preparation process of the array substrate may include the following steps:

[0149] (21) The first semiconductor layer, the first conductive layer, and the second semiconductor layer are formed in sequence. The preparation process of the aforementioned array substrate can be referred to and will not be elaborated here.

[0150] (22) Forming a second conductive layer pattern. Forming the second conductive layer pattern may include: depositing a second conductive film on one side of the substrate 20 on which the aforementioned pattern is formed, and patterning the second conductive film through a patterning process to form a second conductive layer pattern located on the side of the second semiconductor layer away from the substrate 20. The second conductive layer may include a first connecting electrode, a second connecting electrode, a data line DL, and a pixel connecting electrode 26, as shown in FIG14A and FIG14B. FIG14B is a cross-sectional view taken along line BB in FIG14A. In FIG14B, the first active layer 23 is not pattern-filled to facilitate parameter identification.

[0151] As shown in FIG14A , the data line DL may be in the shape of a line extending along the second direction Y. As shown in FIG14A , the orthographic projection of the pixel connection electrode 26 on the array substrate may be rectangular, and the orthographic projection of the pixel connection electrode 26 on the array substrate at least partially overlaps with the orthographic projection of the first active layer 23 on the array substrate. The pixel connection electrode 26 may be located between two adjacent data lines DL.

[0152] As shown in FIG14B , the first active layer 23 may include a bottom surface 23a and a top surface 23b disposed opposite each other, and a first side surface 23c connecting the bottom surface 23a and the top surface 23b. The bottom surface 23a is closer to the substrate 20 than the top surface 23b. A first slope angle α1 is defined between the first side surface 23c and the bottom surface 23a. The first slope angle α1 may range from 45 degrees to 90 degrees. Portions of the data line DL may contact and mate with the first side surface 23c and the top surface 23b of the first active layer 23. This increases the contact area between the data line DL and the first active layer 23, ensuring the reliability of the electrical connection between the data line DL and the first active layer 23. In the disclosed embodiment, by limiting the range of the first slope angle α1, distortion of the data line during the ramping process can be prevented, ensuring the bonding performance between the data line DL and the first active layer.

[0153] As shown in FIG14B , the first active layer 23 may further include a second side surface 23 d, the second side surface 23 d connecting the bottom surface 23 a and the top surface 23 b. A second slope angle α2 is formed between the second side surface 23 d and the bottom surface 23 a. The second slope angle α2 may range from 45 degrees to 90 degrees. In one example, the first slope angle α1 and the second slope angle α2 may be the same or different. For example, the first slope angle α1 and the second slope angle α2 may both be 70 degrees.

[0154] As shown in Figure 14B, the pixel connection electrode 26 contacts both the top surface 23b and the second side surface 23d, thereby ensuring the reliability of the electrical connection between the pixel connection electrode 26 and the first active layer 23. In the embodiment of the present disclosure, by limiting the range of the second slope angle α2, the bonding performance between the pixel connection electrode and the first active layer can be guaranteed.

[0155] (23) Forming a fifth insulating layer pattern. Forming the fifth insulating layer pattern may include: sequentially depositing a fourth insulating film and a fifth insulating film on one side of the substrate 20 on which the aforementioned pattern is formed, and patterning the fifth insulating film through a patterning process to form a fourth insulating layer pattern and a fifth insulating layer pattern located on the side of the second conductive layer away from the substrate 20, as shown in Figures 15A and 15B. Figure 15B is a cross-sectional view taken along line BB in Figure 15A. The fifth insulating layer 15 may include at least one third via hole K3. The fourth insulating film and the fifth insulating film located in the third via hole K3 are both etched away, exposing a portion of the surface of the pixel connection electrode 26 on the side away from the substrate 20. The third via hole K3 is configured so that a subsequently formed pixel electrode is electrically connected to the pixel connection electrode 26 via the via hole.

[0156] In some exemplary embodiments, as shown in FIG15A , the orthographic projection of the third via hole K3 on the array substrate at least partially overlaps with the orthographic projection of the pixel connecting electrode 26 on the array substrate. For example, the orthographic projection of the third via hole K3 on the array substrate may be located within the orthographic projection of the pixel connecting electrode 26 on the array substrate.

[0157] In some exemplary embodiments, the third via hole K3 may be a circular hole, a rectangular hole, an elliptical hole, a hexagonal hole, or the like.

[0158] (24) The fourth conductive layer, the fifth conductive layer and the sixth conductive layer are formed in sequence, as shown in FIG16A and FIG16B . FIG16B is a cross-sectional view taken along the line BB in FIG16A . For reference, the aforementioned embodiment may be used and no further details will be given here.

[0159] Figure 17 is a schematic cross-sectional view of an array substrate according to another embodiment of the present disclosure. As shown in Figure 17, the array substrate may include a substrate 20, and a first semiconductor layer, a first conductive layer, a second semiconductor layer, a second conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer sequentially arranged on one side of the substrate 20. The array substrate may further include a first insulating layer 11 located between the first semiconductor layer and the substrate 20, a second insulating layer 12 located between the first semiconductor layer and the first conductive layer, a third insulating layer 13 located between the first conductive layer and the second semiconductor layer, a fourth insulating layer 14 and a fifth insulating layer 15 located between the second conductive layer and the fourth conductive layer, and a sixth insulating layer 16 located between the fourth conductive layer and the fifth conductive layer.

[0160] As shown in Figure 17, the array substrate includes a display area AA and a second non-display area B2. The display area AA may include multiple first transistors 21, and the second non-display area B2 may include multiple second transistors 22. Figure 17 illustrates only one first transistor 21 and one second transistor 22 as an example. The first semiconductor layer may include a second active layer 17 of the second transistor 22. The first conductive layer may include a second gate electrode 18 of the second transistor 22, a first gate electrode 19 of the first transistor 21, and a gate line GL. The second semiconductor layer may include a first active layer 23 of the first transistor 21. The second conductive layer may include a first connection electrode 24, a second connection electrode 25, and a data line DL. As shown in Figure 17, a portion of the surface of the data line DL on the side closest to the substrate 20 contacts a portion of the surface of the first active layer 23 on the side away from the substrate 20. In this exemplary embodiment, no pixel connection electrode is required, which reduces the number of conductive layers, simplifies the array substrate manufacturing process, and reduces the manufacturing cost of the array substrate.

[0161] As shown in Figure 17, the fourth conductive layer may include a pixel electrode 10. The orthographic projection of the pixel electrode 10 on the array substrate may at least partially overlap with the orthographic projection of the first active layer 23 on the array substrate. The pixel electrode 10 is electrically connected to the first active layer 23 of the first transistor 21 via a fourth via K4. The sixth conductive layer may include a common electrode 27. The orthographic projection of the common electrode 27 on the array substrate may at least partially overlap with the orthographic projection of the pixel electrode 10 on the array substrate.

[0162] As shown in Figure 17, the fifth conductive layer may include at least one common electrode line 28. The orthographic projection of the common electrode line 28 on the array substrate may at least partially overlap with the orthographic projection of the data line DL on the array substrate. For example, the orthographic projection of the common electrode line 28 on the array substrate may be located within the orthographic projection of the data line DL on the array substrate, thereby avoiding the influence of the common electrode line on the aperture ratio of the display area. The common electrodes of multiple sub-pixels may all be electrically connected to the same common electrode line. A portion of the surface of the common electrode line 28 away from the substrate 20 may be in contact with a portion of the surface of the common electrode 27 close to the substrate 20, so that the connection between the common electrode and the common electrode line does not require the provision of a via, thereby reducing the resistance of the common electrode and improving the uniformity of the common electrode voltage.

[0163] The preparation process of the array substrate may include the following steps:

[0164] (31) The first semiconductor layer, the first conductive layer, the second semiconductor layer, and the second conductive layer are formed in sequence. The preparation process of the aforementioned array substrate can be referred to and will not be elaborated here.

[0165] (32) Forming a fifth insulating layer pattern. Forming the fifth insulating layer pattern may include: sequentially depositing a fourth insulating film and a fifth insulating film on one side of the substrate 20 on which the aforementioned pattern is formed, patterning the fifth insulating film through a patterning process to form a fourth insulating layer pattern and a fifth insulating layer pattern located on the side of the second conductive layer away from the substrate 20, as shown in Figures 18A and 18B, Figure 18B is a cross-sectional view taken along the CC direction in Figure 18A, the fifth insulating layer 15 may include at least one fourth via K4, the fourth insulating film and the fifth insulating film located in the fourth via K4 are both etched away, and a portion of the surface of the first active layer 23 on the side away from the substrate 20 is exposed. The fourth via K4 is configured so that the pixel electrode formed subsequently is electrically connected to the first active layer of the first transistor via the via.

[0166] In some exemplary embodiments, as shown in FIG18A , the orthographic projection of the fourth via hole K4 on the array substrate may at least partially overlap with the orthographic projection of the first active layer 23 on the array substrate. For example, the orthographic projection of the fourth via hole K4 on the array substrate may be located within the orthographic projection of the first active layer 23 on the array substrate.

[0167] In some exemplary embodiments, the fourth via hole K4 may be a circular hole, a rectangular hole, an elliptical hole, a hexagonal hole, or the like.

[0168] (33) The fourth conductive layer, the fifth conductive layer and the sixth conductive layer are formed in sequence, as shown in FIG19A and FIG19B . FIG19B is a cross-sectional view taken along the CC direction in FIG19A . For reference, the aforementioned embodiment may be used and no further details will be given here.

[0169] Figure 20 is a schematic cross-sectional view of an array substrate according to another embodiment of the present disclosure. As shown in Figure 20, the array substrate may include a substrate 20, and a first semiconductor layer, a first conductive layer, a second semiconductor layer, a second conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer, sequentially arranged on one side of the substrate 20. The array substrate may further include a first insulating layer 11 located between the first semiconductor layer and the substrate 20, a second insulating layer 12 located between the first semiconductor layer and the first conductive layer, a third insulating layer 13 located between the first conductive layer and the second semiconductor layer, a fourth insulating layer 14 located between the second conductive layer and the fourth conductive layer, and a sixth insulating layer 16 located between the fourth conductive layer and the fifth conductive layer. In this embodiment of the present disclosure, the fifth insulating layer can be omitted, thereby reducing the impact of the vias provided in the fifth insulating layer on the liquid crystal layer and preventing disturbances in the liquid crystal layer.

[0170] As shown in Figure 20, the array substrate includes a display area AA and a second non-display area B2. The display area AA may include multiple first transistors 21, and the second non-display area B2 may include multiple second transistors 22. Figure 20 illustrates only one first transistor 21 and one second transistor 22 as an example. The first semiconductor layer may include the second active layer 17 of the second transistor 22. The first conductive layer may include the second gate electrode 18 of the second transistor 22, the first gate electrode 19 of the first transistor 21, and the gate line GL. The second semiconductor layer may include the first active layer 23 of the first transistor 21. The second conductive layer may include a first connection electrode 24, a second connection electrode 25, and a data line DL. As shown in Figure 20, a portion of the surface of the data line DL on the side closest to the substrate 20 contacts a portion of the surface of the first active layer 23 on the side away from the substrate 20. In this exemplary embodiment, no pixel connection electrode is required, which reduces the number of conductive layers, simplifies the array substrate manufacturing process, and reduces the manufacturing cost of the array substrate.

[0171] As shown in Figure 20, the fourth conductive layer may include a pixel electrode 10. The orthographic projection of the pixel electrode 10 on the array substrate may at least partially overlap with the orthographic projection of the first active layer 23 on the array substrate. The pixel electrode 10 is electrically connected to the first active layer 23 of the first transistor 21 via a fifth via K5. The sixth conductive layer may include a common electrode 27. The orthographic projection of the common electrode 27 on the array substrate may at least partially overlap with the orthographic projection of the pixel electrode 10 on the array substrate.

[0172] As shown in Figure 20, the fifth conductive layer may include at least one common electrode line 28, and the orthographic projection of the common electrode line 28 on the array substrate may at least partially overlap with the orthographic projection of the data line DL on the array substrate. For example, the orthographic projection of the common electrode line 28 on the array substrate may be located within the orthographic projection of the data line DL on the array substrate, thereby avoiding the influence of the common electrode line on the aperture ratio of the display area.

[0173] Figure 21 is a schematic cross-sectional view of an array substrate according to another embodiment of the present disclosure. As shown in Figure 21, the array substrate may include a substrate 20, and a first semiconductor layer, a first conductive layer, a second semiconductor layer, a second conductive layer, a fifth conductive layer, and a sixth conductive layer, sequentially arranged on one side of the substrate 20. The array substrate may also include a first insulating layer 11 located between the first semiconductor layer and the substrate 20, a second insulating layer 12 located between the first semiconductor layer and the first conductive layer, a third insulating layer 13 located between the first conductive layer and the second semiconductor layer, and a fourth insulating layer 14 located between the second conductive layer and the fifth conductive layer.

[0174] As shown in Figure 21, the array substrate includes a display area AA and a second non-display area B2. The display area AA may include multiple first transistors 21, and the second non-display area B2 may include multiple second transistors 22. The first semiconductor layer may include the second active layer 17 of the second transistor 22. The first conductive layer may include the second gate electrode 18 of the second transistor 22, the first gate electrode 19 of the first transistor 21, and the gate line GL. The second semiconductor layer may include the first active layer 23 of the first transistor 21. As shown in Figure 21, the pixel electrode 10 and the first active layer 23 may be an integrated structure connected to each other. This simplifies the film structure of the array substrate, avoids the need for vias electrically connecting the pixel electrode 10 to the first transistor 21, and simplifies the manufacturing method of the array substrate. The second conductive layer may include a first connecting electrode 24, a second connecting electrode 25, and a data line DL. As shown in Figure 21, a portion of the surface of the data line DL on the side close to the substrate 20 contacts a portion of the surface of the first active layer 23 on the side away from the substrate 20.

[0175] As shown in FIG21 , the sixth conductive layer may include a common electrode 27, and the orthographic projection of the common electrode 27 on the array substrate may at least partially overlap with the orthographic projection of the pixel electrode 10 on the array substrate. The fifth conductive layer may include at least one common electrode line 28, and the orthographic projection of the common electrode line 28 on the array substrate may at least partially overlap with the orthographic projection of the data line DL on the array substrate. For example, the orthographic projection of the common electrode line 28 on the array substrate may be located within the orthographic projection of the data line DL on the array substrate, thereby preventing the common electrode line from affecting the aperture ratio of the display area.

[0176] Figure 22 is a schematic cross-sectional view of a display device according to an embodiment of the present disclosure. As shown in Figure 22 , an embodiment of the present disclosure further provides a display device. For example, a display device capable of implementing an Advanced Super Dimension Switch (ADS) mode may include an array substrate 5 , which may be any of the array substrates provided in the aforementioned embodiments.

[0177] The display device may further include an opposing substrate 1 and a liquid crystal layer 2 disposed between an array substrate 5 and the opposing substrate 1. The pixel electrodes and common electrodes included in the array substrate 5 may be configured to generate an electric field that controls the deflection of liquid crystal molecules in the liquid crystal layer 2. As shown in FIG22 , the liquid crystal molecules in the liquid crystal layer 2 may be horizontally aligned on the array substrate 5. In the disclosed embodiment, the horizontal direction is parallel to the plane of the array substrate 5.

[0178] In an exemplary embodiment, as shown in Figure 22 , the counter substrate 1 may include a base substrate, and a black matrix 3 and a color filter layer 4 disposed on the base substrate. However, the present disclosure is not limited thereto.

[0179] The present disclosure also provides a display device. The display device includes the array substrate described in any of the preceding embodiments. The display device can be any product or component with a display function, such as a liquid crystal panel, electronic paper, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigation system. The present disclosure is not limited thereto.

[0180] Although the embodiments disclosed herein are as described above, the contents described are merely embodiments for facilitating understanding of the present invention and are not intended to limit the present invention. It should be noted that the above embodiments or implementations are merely illustrative and not restrictive. Therefore, the present disclosure is not limited to the contents specifically shown and described herein. Various modifications, substitutions, or omissions may be made to the forms and details of the implementations without departing from the scope of the present disclosure.

Claims

1. An array substrate, comprising a substrate, the substrate comprising a display area and a non-display area located on at least one side of the display area; the array substrate further comprising at least one first transistor and at least one second transistor disposed on the same side of the substrate, the at least one first transistor comprising a first gate and a first active layer, and the at least one second transistor comprising a second gate and a second active layer; along a direction perpendicular to the substrate, a minimum spacing between the first active layer and the substrate is greater than a minimum spacing between the second active layer and the substrate, and the first active layer and the second active layer are located on opposite sides of the first gate.

2. The array substrate according to claim 1, wherein: The first gate and the second gate are arranged in the same layer, the first active layer is located on a side of the first gate away from the substrate, and the second active layer is located on a side of the second gate close to the substrate.

3. The array substrate according to claim 2, wherein: The display area includes the at least one first transistor, and the non-display area includes the at least one second transistor.

4. The array substrate according to claim 1, wherein: The display area includes at least one data line, and the at least one data line is electrically connected to the first electrode of the at least one first transistor; The first active layer includes a bottom surface, a top surface and a first side surface connecting the bottom surface and the top surface, and the bottom surface is closer to the substrate than the top surface; the partial surface of the at least one data line close to the substrate side is in contact and connected with the partial surface of the top surface, and part of the data line is in contact and connected with the first side surface.

5. The array substrate according to claim 4, wherein: A first slope angle is formed between the first side surface and the bottom surface, and the first slope angle ranges from 45 degrees to 90 degrees.

6. The array substrate according to claim 4, wherein: The at least one data line includes a contact portion, a surface portion of the contact portion close to the substrate is in contact with a surface portion of the top surface, and other portions of the data line except the contact portion are closer to the substrate than the contact portion.

7. The array substrate according to claim 1, wherein: The first transistor includes a first electrode and a second electrode that are opposite to each other. The material of the first electrode is the same as or different from the material of the second electrode.

8. The array substrate according to claim 7, wherein: The material of the first pole is different from the material of the second pole. The material of the first pole includes at least one of indium gallium zinc oxide, indium gallium tin oxide, indium tin zinc oxide, indium gallium zinc tin oxide, indium-free metal oxide and rare earth-doped oxide. The material of the second pole includes at least one of indium gallium zinc oxide, indium gallium tin oxide, indium tin zinc oxide, indium gallium zinc tin oxide, indium-free metal oxide and rare earth-doped oxide.

9. The array substrate according to claim 1, wherein: The material of the second active layer includes at least one of indium gallium zinc oxide, indium gallium tin oxide, indium tin zinc oxide, indium gallium zinc tin oxide, indium-free metal oxide and rare earth doped oxide.

10. The array substrate according to any one of claims 1 to 9, wherein: The display area also includes at least one first electrode, at least one data line and at least one pixel connecting electrode, wherein the at least one pixel connecting electrode is located between the first electrode and the second electrode of the first transistor, and the first electrode and the second electrode of the first transistor are electrically connected via the pixel connecting electrode.

11. The array substrate according to claim 10, wherein: The pixel connection electrode and the data line are in the same layer structure.

12. The array substrate according to claim 11, wherein: The first active layer includes a bottom surface, a top surface, and a first side surface and a second side surface connecting the bottom surface and the top surface; the bottom surface is closer to the substrate than the top surface; a portion of the surface of the at least one data line close to the substrate is in contact and connected with a portion of the surface of the top surface, and a portion of the data line is in contact and connected with the first side surface, and at least a portion of the surface of the pixel connection electrode close to the substrate is in contact and connected with a portion of the surface of the top surface.

13. The array substrate according to claim 12, wherein: A portion of the pixel connection electrode is in contact with the second side surface.

14. The array substrate according to any one of claims 1 to 9, wherein: The display area further includes at least one first electrode, wherein the first electrode and the first active layer are connected to each other as an integral structure; The display area further includes a second electrode, which is located on a side of the first electrode away from the substrate, and orthographic projections of the first electrode and the second electrode on a plane where the substrate is located at least partially overlap.

15. A display device comprising the array substrate, an opposing substrate, and a liquid crystal layer according to any one of claims 1 to 14; the array substrate and the opposing substrate are arranged opposite to each other, and the liquid crystal layer is located between the array substrate and the opposing substrate.

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