Storage circuit, storage device, and electronic apparatus

Abstract

Provided is a storage circuit capable of holding data for a long period of time. The storage circuit includes: first to sixth transistors; and first and second capacitive elements. A first terminal of the first transistor is electrically connected to a gate of the second transistor, a gate of the fifth transistor, and a first terminal of the first capacitive element. A second terminal of the first transistor is electrically connected to a first terminal of the fourth transistor, a first terminal of the fifth transistor, a first terminal of the sixth transistor, and a first terminal of the second capacitive element. A first terminal of the second transistor is electrically connected to a first terminal of the third transistor. A second terminal of the source or the drain of the second transistor is electrically connected to a second terminal of the first capacitive element. A gate of the first transistor is electrically connected to first wiring. A gate of the fourth transistor is electrically connected to the first wiring.

Description

Memory circuit, memory device and electronic device

[0001] One embodiment of the present invention relates to a memory circuit, a memory device, and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an object, an operating method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, specific examples of the technical field of one embodiment of the present invention disclosed in this specification include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, memory devices, signal processing devices, sensors, processors, electronic devices, systems, driving methods thereof, manufacturing methods thereof, and inspection methods thereof.

[0003] In recent years, with the increase in the amount of data handled, there has been a demand for memory devices with larger storage capacities. Meanwhile, there is also a demand for smaller electronic devices, and development is also underway to reduce the circuit area of ​​memory devices provided in electronic devices. One possible means for reducing the circuit area of ​​a memory device is to promote integration or miniaturization of transistors and capacitive elements provided in memory circuits (which can also be referred to as memory cells, memory cells, etc.). For example, Patent Document 1 discloses a configuration in which multiple memory cells are stacked above a drive circuit in order to increase the memory capacity per unit area.

[0004] International Publication No. 2022 / 238798

[0005] In addition, the storage capacity of a storage device can be increased by increasing the number of memory cells (storage circuits). However, when the number of memory cells (storage circuits) is increased by miniaturizing transistors and capacitors to increase the storage density, the leakage current of the transistors may increase. Furthermore, the capacitance value of the capacitors may also decrease, which may result in a decrease in data retention characteristics.

[0006] An object of one embodiment of the present invention is to provide a memory circuit that can retain data for a long period of time.An object of one embodiment of the present invention is to provide a memory circuit that can reduce the number of times data is refreshed.An object of one embodiment of the present invention is to provide a memory device including the memory circuit.An object of one embodiment of the present invention is to provide an electronic device including the memory device.An object of one embodiment of the present invention is to provide a novel memory circuit, a novel memory device, or a novel electronic device.

[0007] Note that the problem of one embodiment of the present invention is not limited to the above problem. The above problem does not preclude the existence of other problems. Note that the other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification, drawings, etc., and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the above problem and other problems, and does not necessarily solve all of the above problem and other problems.

[0008] One aspect of the present invention, which has been made in consideration of the above-described problems, is a memory circuit including a source follower. The source follower acquires the potential of a first retention node as an input potential and outputs an output potential equal to the potential of the first retention node to a second retention node. Note that when a write transistor of the memory circuit is turned on, conduction occurs between the first retention node and the second retention node. With this configuration, even if the write transistor is turned off and a leakage current occurs between the source and drain, causing a drop in the potential of the second retention node, the source follower compensates for the charge, thereby raising the potential of the second retention node to the potential of the first retention node.

[0009] Below, examples of an amplifier circuit, a memory circuit, and an electronic device for solving the above problems will be described.

[0010] (1) One embodiment of the present invention is a memory circuit including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first capacitor, and a second capacitor. One of a source or a drain of the first transistor is electrically connected to a gate of the second transistor, a gate of the fifth transistor, and a first terminal of the first capacitor. The other of the source or the drain of the first transistor is electrically connected to one of a source or a drain of the fourth transistor, one of a source or a drain of the fifth transistor, one of a source or a drain of the sixth transistor, and a first terminal of the second capacitor. The one of the source or the drain of the second transistor is electrically connected to one of a source or a drain of the third transistor. The other of the source or the drain of the second transistor is electrically connected to the second terminal of the first capacitor. The gate of the first transistor is electrically connected to the gate of the fourth transistor.

[0011] (2) Another embodiment of the present invention is a memory circuit different from the memory circuit described in (1) above, including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first capacitor, and a second capacitor. One of a source or a drain of the first transistor is electrically connected to a gate of the second transistor, a gate of the fifth transistor, and a first terminal of the first capacitor. The other of the source or the drain of the first transistor is electrically connected to one of a source or a drain of the fourth transistor, one of a source or a drain of the fifth transistor, one of a source or a drain of the sixth transistor, and a first terminal of the second capacitor. The one of the source or the drain of the second transistor is electrically connected to one of a source or a drain of the third transistor. The other of the source or the drain of the second transistor is electrically connected to a second terminal of the first capacitor and a second terminal of the second capacitor. The gate of the first transistor is electrically connected to a gate of the fourth transistor.

[0012] (3) Another embodiment of the present invention is a memory circuit including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a first capacitor. One of a source or a drain of the first transistor is electrically connected to a gate of the second transistor, a gate of the fifth transistor, and a first terminal of the first capacitor. The other of the source or the drain of the first transistor is electrically connected to one of a source or a drain of the fourth transistor, one of a source or a drain of the fifth transistor, and one of a source or a drain of the sixth transistor. The one of the source or the drain of the second transistor is electrically connected to one of a source or a drain of the third transistor. The other of the source or the drain of the second transistor is electrically connected to a second terminal of the first capacitor. The gate of the first transistor is electrically connected to the gate of the fourth transistor.

[0013] (4) In another embodiment of the present invention, in any one of (1) to (3), each of the first to sixth transistors may include an oxide semiconductor in a channel formation region. The oxide semiconductor preferably includes one or more elements selected from the group consisting of indium, zinc, and an element M.

[0014] The element M is one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony.

[0015] (5) Another embodiment of the present invention is a memory device including the memory circuit described in (4) above and a driver circuit, where the memory circuit is located above the driver circuit, and the driver circuit includes a transistor including silicon in a channel formation region.

[0016] (6) Another embodiment of the present invention is an electronic device including the storage device according to (5) above and a housing.

[0017] The memory circuit according to any one of (1) to (4) above can prevent fluctuations in the potentials held at the first and second storage nodes due to leakage currents. Furthermore, because the potential fluctuations can be prevented, the number of times data written in the memory circuit is refreshed can be reduced.

[0018] According to one embodiment of the present invention, a memory circuit capable of retaining data for a long period of time can be provided. Alternatively, according to one embodiment of the present invention, a memory circuit capable of reducing the number of times data is refreshed can be provided. Alternatively, according to one embodiment of the present invention, a memory device including the memory circuit can be provided. Alternatively, according to one embodiment of the present invention, an electronic device including the memory device can be provided. Alternatively, according to one embodiment of the present invention, a novel memory circuit, a novel memory device, or a novel electronic device can be provided.

[0019] Note that the effects of one embodiment of the present invention are not limited to the above-described effects. The above-described effects do not preclude the existence of other effects. Furthermore, the other effects are effects not mentioned in this section, which will be described below. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification, drawings, etc., and can be extracted as appropriate from these descriptions. Note that one embodiment of the present invention has at least one of the above-described effects and other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases.

[0020] FIG. 1 is a circuit diagram showing a configuration example of a memory circuit. FIGS. 2A to 2C are circuit diagrams showing a configuration example of a memory circuit. FIG. 3 is a timing chart showing an operation example of a memory circuit. FIG. 4 is a schematic plan view showing an example of a memory circuit. FIGS. 5A and 5B are circuit diagrams showing a configuration example of a memory circuit. FIG. 6 is a circuit diagram showing a configuration example of a memory circuit. FIG. 7A is a perspective view illustrating a configuration example of a memory device, and FIG. 7B is a block diagram illustrating a configuration example of a memory device. FIG. 8 is a block diagram showing a configuration example of a memory device. FIG. 9 is a schematic cross-sectional view showing a configuration example of a memory device. FIGS. 10A and 10B are schematic cross-sectional views showing a configuration example of a transistor. FIG. 11 is a schematic cross-sectional view showing a configuration example of a memory device. FIG. 12A is a schematic plan view showing a configuration example of a transistor, and FIGS. 12B to 12D are schematic cross-sectional views showing a configuration example of a transistor. FIGS. 13A to 13C are schematic cross-sectional views showing a configuration example of a transistor. FIG. 14 is a schematic cross-sectional view showing a configuration example of a memory device. FIG. 15A is a schematic plan view showing an example of the configuration of a memory device, and FIG. 15B is a schematic cross-sectional view showing an example of the configuration of a memory device. FIGS. 16A and 16B are diagrams showing various memory devices by layer. FIGS. 17A to 17D are diagrams showing an example of an electronic component. FIGS. 18A and 18B are diagrams showing an example of an electronic device, and FIG. 18C is a diagram showing an example of a mainframe computer. FIG. 19 is a diagram showing an example of space equipment. FIG. 20 is a diagram showing an example of a storage system applicable to a data center. FIGS. 21A to 21C are diagrams showing the configuration of a memory circuit used in a simulation in the examples. FIGS. 22A to 22C are graphs showing the retention characteristics of a memory circuit as a result of the simulation in the examples. FIGS. 23A1 to 23A7 and 23B1 to 23B6 are circuit diagrams for explaining electrical connections.

[0021] (Additional Notes Related to This Specification) In this specification, etc., a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (for example, a transistor, a diode, and a photodiode), or a device having such a circuit. Also, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. An example of a semiconductor device is an integrated circuit. Another example of a semiconductor device is a chip equipped with an integrated circuit. Another example of a semiconductor device is an electronic component that houses a chip in a package. Also, for example, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be a semiconductor device, or may include a semiconductor device.

[0022] In this specification, "connection" includes, for example, "electrical connection."

[0023] When the term "electrical connection" is used to define the connection relationship between circuit elements as an object, it includes, for example, "direct connection" and "indirect connection." For example, "A and B are directly connected" refers to a connection between A and B without the intervention of a circuit element (e.g., a transistor or a switch; wiring is not considered a circuit element). On the other hand, for example, "A and B are indirectly connected" refers to a connection between A and B via one or more circuit elements. Note that A, B, and C, which will be described later, represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0024] Here, when "A and B are indirectly connected," it refers to the following connection relationship, for example. That is, assuming that a circuit is operating, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, such a circuit can be defined as an entity, and "A and B are indirectly connected." Note that even if there is a time when electrical signal transmission or potential interaction does not occur between A and B, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, it can be defined as "A and B are indirectly connected." Note that "A and B are indirectly connected" is a definition of the connection relationship between circuit elements as an entity. Therefore, for example, even when a power supply voltage is not supplied to a circuit and the circuit is not operating, the circuit can be defined as an entity, and "A and B are indirectly connected" (however, for example, this is limited to the case where electrical signal transmission or potential interaction occurs between A and B during the operation of the circuit when a power supply voltage is supplied to the circuit and the circuit is operating).

[0025] Specific examples of "indirect connection" are shown below. First, an example of "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors, as shown in FIGS. 23A1 and 23A2. Another example of "A and B are indirectly connected" is when A and B are connected via one or more switches. When "A and B are indirectly connected," it is assumed that, assuming the circuit is operating, there is at least one time when one transistor between A and B is in an on state, a conductive state, or a state in which current can flow. Note that "A and B are indirectly connected" also includes cases where one transistor between A and B is in an off state or a non-conductive state. When "A and B are indirectly connected," if multiple transistors are connected between A and B, it is assumed that, assuming the circuit is operating, each of the multiple transistors between A and B is in an on state, a conductive state, or a state in which current can flow. In other words, when "A and B are indirectly connected," it is not necessary for all of the multiple transistors to be in an on state, a conductive state, or a state in which current can flow simultaneously. Therefore, when "A and B are indirectly connected," it also includes cases where multiple transistors between A and B are in an off state or a non-conductive state at the same time or at different times. As another example, as shown in FIG. 23A3, when A and C are connected via the source and drain of transistor TrP and B and C are connected via the source and drain of transistor TrQ, it can be defined as "A and C are indirectly connected," "B and C are indirectly connected," or "A and B are indirectly connected." However, as will be described later, when a constant potential V is supplied to C from a power supply, GND, or the like, it can be said that "A and C are indirectly connected" or "B and C are indirectly connected," but it cannot be said that "A and B are indirectly connected."

[0026] While we have provided examples of cases where an "indirect connection" can and cannot be established, we will now present another example of a case where an "indirect connection" cannot be established. Even if an electrical signal exchange or potential interaction occurs between A and B during the operation of the circuit, there are exceptional cases where it cannot be said that "A and B are indirectly connected." An example of such an exceptional case is when A and B are connected via an insulator. In other words, when A and B are connected via an insulator, it cannot be said that "A and B are indirectly connected." A specific example of a case where A and B are connected via an insulator is when a capacitive element is connected between A and B, as shown in FIG. 23A4. Another example of a case where A and B are connected via an insulator is when a gate insulating film of a transistor is interposed between A and B, as shown in FIG. 23A5. In this case, it cannot be said that "A (the gate of the transistor) and B (the source or drain of the transistor) are indirectly connected."

[0027] Another example of a case where it cannot be said that "A and B are indirectly connected" is a case where there is no timing when an electrical signal is exchanged or when potential interaction occurs between A and B. An example of this is when, as shown in Figures 23A6 and 23A7, multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between the transistors from a power supply, GND, or the like. In this case, it cannot be said that "A and B are indirectly connected," but it is possible to say that "A and V are indirectly connected" or "B and V are indirectly connected." In addition, in Figure 23A3, if A and C are connected via the source and drain of transistor TrP, and B and C are connected via the source and drain of transistor TrQ, and a constant potential V is supplied to C from a power supply or GND, etc., the relationship will be the same as in Figures 23A6 and 23A7, so it cannot be said that "A and B are indirectly connected," but it can be said that "A and C are indirectly connected," or "B and C are indirectly connected."

[0028] Although an example of "indirect connection" has been given above, as an example, the definition of "indirect connection" is included in the definition of "electrical connection," so if "A and B are indirectly connected," it can also be said that "A and B are electrically connected."

[0029] Next, specific examples of "direct connection" are shown. Examples of "A and B are directly connected" include cases where A and B are connected without any circuit element between them, as shown in FIGS. 23B1, 23B2, and 23B3. When A and B are connected to a power supply that supplies a constant potential V or to GND without any circuit element between them, as shown in FIGS. 23B4 and 23B5, it can be said that "A and B are directly connected," "A and V are directly connected," or "B and V are directly connected." Even when A (or B) is connected to a constant potential V via the source and drain of a transistor, as shown in FIG. 23B6, it can also be said that "A and B are directly connected." Because A and V or B and V are connected via the source and drain of a transistor, they cannot be said to be directly connected, but rather that "A and V are indirectly connected" or "B and V are indirectly connected."

[0030] Although an example of "direct connection" has been given above, as an example, the definition of "direct connection" is included in the definition of "electrical connection," so when "A and B are directly connected," it can also be said that "A and B are electrically connected."

[0031] Note that even when independent components are shown as being connected to each other in a circuit diagram, one component may have the functions of multiple components. For example, if part of a wiring also functions as an electrode, one conductive film has the functions of both a wiring and an electrode. Therefore, in this specification, the term "connection" also includes such cases where one conductive film has the functions of multiple components.

[0032] Furthermore, in this specification, a "resistance element" can be, for example, a circuit element having a resistance value higher than 0Ω, or a wiring having a resistance value higher than 0Ω. Therefore, in this specification, a "resistance element" includes a wiring having a resistance value, a transistor in which a current flows between a source and a drain, a diode, or a coil. Therefore, the term "resistance element" can sometimes be replaced with the terms "resistance," "load," or "region having a resistance value." Conversely, the terms "resistance," "load," or "region having a resistance value" can sometimes be replaced with the term "resistance element." The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. Furthermore, for example, a resistance value can be, for example, 1 Ω or more and 1×10 ９ It can be made smaller than Ω.

[0033] Furthermore, in this specification, a "capacitive element" can refer to, for example, a circuit element having a capacitance value higher than 0 F, a wiring region having a capacitance value higher than 0 F, a parasitic capacitance, or a gate capacitance of a transistor. The terms "capacitive element," "parasitic capacitance," or "gate capacitance" can sometimes be replaced with the term "capacitance." Conversely, the term "capacitance" can sometimes be replaced with the terms "capacitive element," "parasitic capacitance," or "gate capacitance." A "capacitive element" (including a "capacitive element" with three or more terminals) includes an insulator and a pair of conductors sandwiching the insulator. Therefore, the term "pair of conductors" in "capacitance" can be replaced with "pair of electrodes," "pair of conductive regions," "pair of regions," or "pair of terminals." The terms "one of the pair of terminals" and "the other of the pair of terminals" may be referred to as a first terminal and a second terminal, respectively. The capacitance value can be, for example, 0.05 fF to 10 pF. It can also be, for example, 1 pF to 10 μF.

[0034] In this specification, a switch refers to a device that can be turned on or off and has the function of controlling whether or not a current flows, or a device that can select and switch a path through which a current flows.

[0035] In this specification, a "conductive state" refers to a state in which a current can flow between two input / output terminals, and a "non-conductive state" refers to a state in which the two input / output terminals are considered to be electrically disconnected. In this specification, the on state of a switch falls under the category of a "conductive state," and the off state of a switch falls under the category of a "non-conductive state." Therefore, in this specification, the "conductive state" and the "on state" of a switch are interchangeable, and the "non-conductive state" and the "off state" are interchangeable.

[0036] Furthermore, the switch may have two or more terminals for passing current in addition to the control terminal. For example, an electrical switch, a mechanical switch, or the like may be used. In other words, the switch is not limited to a specific type as long as it has the function of controlling current.

[0037] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, and diode-connected transistors), or logic circuits combining these. When a transistor is used as a switch, the "conductive state" or "on state" of the transistor refers to a state in which a current can flow between the source electrode and the drain electrode of the transistor. The "non-conductive state" or "off state" of the transistor refers to a state in which the source electrode and the drain electrode of the transistor can be considered to be electrically disconnected. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0038] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical systems) technology. This switch has a mechanically movable electrode, and the movement of the electrode controls the conductive and non-conductive states.

[0039] In this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls switching between a conductive state and a non-conductive state of the transistor. The two terminals that function as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals serves as a source and the other as a drain depending on the conductivity type (n-channel or p-channel) of the transistor and the level of the potential applied to the three terminals of the transistor. Therefore, in this specification, the terms "source" and "drain" may be interchangeable. In addition, in this specification, when describing the connection relationship of a transistor, the terms "one of the source and the drain" and "the other of the source and the drain" are used. In this specification, one of the source and the drain may be referred to as a "first electrode of the transistor" or a "first terminal of the transistor," and the other of the source and the drain may be referred to as a "second electrode of the transistor" or a "second terminal of the transistor." Note that, depending on the structure of a transistor, a backgate may be provided in addition to the three terminals described above. In this case, in this specification, one of the gate or back gate of the transistor may be referred to as a first gate, and the other of the gate or back gate of the transistor may be referred to as a second gate. Furthermore, for the same transistor, the terms "gate" and "back gate" may be interchangeable. Furthermore, when a transistor has three or more gates, in this specification, the respective gates may be referred to as a first gate, a second gate, a third gate, etc.

[0040] For example, in this specification, a transistor having a multi-gate structure with two or more gate electrodes can be used as an example of a transistor. With a multi-gate structure, the channel formation regions are connected in series, resulting in a structure in which multiple transistors are connected in series. Therefore, the multi-gate structure can reduce the off-state current and improve the breakdown voltage (reliability) of the transistor. Alternatively, when operating in the saturation region, the multi-gate structure can provide voltage-current characteristics with a flat slope, such that the current between the drain and source does not change significantly even when the voltage between the drain and source changes. By utilizing voltage-current characteristics with a flat slope, an ideal current source circuit or an active load with a very high resistance value can be realized. As a result, a differential circuit or a current mirror circuit with excellent characteristics can be realized.

[0041] Furthermore, even when a single circuit element is shown on a circuit diagram, the circuit element may include multiple circuit elements. For example, when a circuit diagram shows one resistor, this includes two or more resistors connected in series. For example, when a circuit diagram shows one capacitance element, this includes two or more capacitance elements connected in parallel. For example, when a circuit diagram shows one transistor, this includes two or more transistors connected in series, with the gates of the transistors connected to each other. Similarly, when a circuit diagram shows one switch, this includes two or more transistors connected in series or in parallel, with the gates of the transistors connected to each other.

[0042] Furthermore, in this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on the circuit configuration and device structure. Furthermore, a terminal, a wiring, etc. can be referred to as a node.

[0043] Furthermore, in this specification and the like, a selector may refer to, for example, a circuit having multiple input terminals and one output terminal, selecting one of the multiple input terminals, and establishing a conductive state between the selected input terminal and the one output terminal. In other words, a selector may refer to a circuit that selects one of the input signals input to each of the multiple input terminals and outputs the selected input signal to the output terminal. Alternatively, a selector may refer to, for example, a circuit having multiple output terminals and one input terminal, selecting one of the multiple output terminals, and establishing a conductive state between the selected output terminal and the one input terminal. In other words, a selector may refer to a circuit that selects one of the multiple output terminals and outputs an input signal input to the input terminal to the selected output terminal. In other words, a selector may refer to a multiplexer or a demultiplexer. In particular, when inputting or outputting an analog potential or an analog current, a selector may refer to an analog multiplexer or an analog demultiplexer.

[0044] Furthermore, in this specification and the like, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also changes.

[0045] Furthermore, in this specification and the like, the terms "high-level potential" and "low-level potential" do not mean specific potentials. For example, when two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials applied to the two wirings may be different from each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials applied to the two wirings may be different from each other.

[0046] Furthermore, "current" refers to the phenomenon of charge transfer (electrical conduction). For example, the statement "electrical conduction of a positively charged body is occurring" can be rephrased as "electrical conduction of a negatively charged body is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) associated with the movement of carriers. Examples of carriers here include electrons, holes, anions, cations, and complex ions, and the carriers differ depending on the system through which the current flows (e.g., semiconductor, metal, electrolyte, and vacuum). Furthermore, the "direction of current" in wiring, etc., refers to the direction in which positively charged carriers move and is expressed as a positive current amount. In other words, the direction in which negatively charged carriers move is opposite to the direction of current and is expressed as a negative current amount. Therefore, in this specification, unless otherwise specified regarding the positive / negative sign of the current (or the direction of current), the statement "current flows from element A to element B" can be rephrased as "current flows from element B to element A." Furthermore, the statement "current is input to element A" can be rephrased as "current is output from element A."

[0047] Furthermore, in this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. Furthermore, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0048] Furthermore, in this specification, terms indicating position, such as "above" and "below," may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each configuration is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing by 180 degrees.

[0049] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B. Similarly, the expression "electrode B above insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B. Similarly, the expression "electrode B below insulating layer A" does not require that electrode B be formed in direct contact below insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0050] Furthermore, in this specification, terms such as "row" and "column" may be used to describe components arranged in a matrix and their positional relationships. Furthermore, the positional relationships between components change as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those used in the specification, and may be rephrased appropriately depending on the situation. For example, the expression "row direction" may be rephrased as "column direction" by rotating the orientation of the drawing by 90 degrees.

[0051] Furthermore, in this specification and the like, the terms "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be changed to the term "conductive film." Or, for example, the term "insulating film" may be changed to the term "insulating layer." Or, in some cases or depending on the situation, the terms "film" and "layer" may not be used and may be replaced with other terms. For example, the term "conductive layer" or "conductive film" may be changed to the term "conductor." Or, for example, the term "insulating layer" or "insulating film" may be changed to the term "insulator."

[0052] Furthermore, in this specification and the like, terms such as "electrode," "wiring," and "terminal" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, terms such as "electrode" or "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where one or more selected from "electrode," "wiring," and "terminal" are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, the terms "electrode," "wiring," and "terminal" may be replaced with the term "region" in some cases.

[0053] Furthermore, in this specification and the like, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." For example, the term "wiring" may be changed to the term "power line." Vice versa, terms such as "signal line" or "power line" may be changed to the term "wiring." A term such as "power line" may be changed to the term "signal line." Vice versa, a term such as "signal line" may be changed to the term "power line." Furthermore, a term such as "potential" applied to a wiring may be changed to the term "signal" depending on the circumstances. Vice versa, a term such as "signal" may be changed to the term "potential."

[0054] In addition, timing charts may be used in this specification and the like to explain an operation method of a semiconductor device. The timing charts used in this specification and the like illustrate ideal operation examples, and the periods, magnitudes, and timings of signals (e.g., potentials or currents) described in the timing charts are not limited unless otherwise specified. The magnitudes and timings of signals (e.g., potentials or currents) input to each wiring (including a node) in the timing charts described in this specification and the like can be changed depending on the situation. For example, even if two periods are shown at equal intervals in a timing chart, the lengths of the two periods may be different. For example, even if one period is shown as being long and the other period is shown as being short, the lengths of the two periods may be equal, or one period may be short and the other period may be long.

[0055] Furthermore, in this specification and the like, flowcharts may be used to explain the operation method of a semiconductor device. Furthermore, in this specification and the like, the processes shown in the flowcharts are classified by operation and shown as mutually independent steps. However, in actual processing, it is difficult to separate the processes shown in the flowcharts by operation, and there are cases where one step involves multiple steps, or where one step involves multiple steps. Therefore, the processes shown in the flowcharts are not limited to the steps described in the specification, and can be appropriately rearranged depending on the situation. Specifically, the order of steps can be rearranged, steps can be added, and steps can be deleted depending on the situation.

[0056] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OSs), and the like. For example, when a metal oxide is contained in a channel formation region of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, when a metal oxide can form a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. Furthermore, an OS transistor can be referred to as a transistor including a metal oxide or an oxide semiconductor.

[0057] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0058] In this specification and the like, the term "impurities" in a semiconductor refers to, for example, elements other than the main component constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic % is an impurity. The presence of impurities may cause one or more of the following: an increase in the defect level density of the semiconductor, a decrease in carrier mobility, and a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main component, particularly, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen.

[0059] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0060] In this specification and the like, the configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be appropriately combined with each other.

[0061] In addition, the content described in one embodiment can be applied, combined, or replaced with another content described in that embodiment and at least one of the content described in another embodiment.

[0062] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0063] Furthermore, a figure described in one embodiment can be combined with another portion of that figure and at least one figure described in one or more other embodiments to form even more figures.

[0064] The embodiments described in this specification are described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that various changes in form and details can be made without departing from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments. Note that in the configuration of the invention of the embodiments, the same reference numerals are used in different drawings for the same parts or parts having similar functions, and repeated description thereof may be omitted. Also, in perspective views and the like, the description of some components may be omitted to ensure clarity of the drawings.

[0065] In this specification, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "[n]", "[m, n]" may be added to the reference numeral. Also, when an identification symbol such as "_1", "[n]", "[m, n]" is added to the reference numeral in the drawings, etc., the identification symbol may not be added if it is not necessary to distinguish between them in this specification.

[0066] In addition, in the drawings of this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences may be included.

[0067] Embodiment 1 In this embodiment, a memory circuit which is one embodiment of the present invention will be described.

[0068] 2A shows a circuit diagram of a conventional memory circuit, specifically, a memory circuit MCt1 of a 3T1C (3 transistors and 1 capacitor) gain cell type.

[0069] The memory circuit MCt1 includes three transistors, that is, a transistor MO1, a transistor MO2, and a transistor MO3, and one capacitive element, that is, a capacitive element CD1.

[0070] A first terminal of the transistor MO1 is connected to a first terminal of the capacitor CD1 and a gate of the transistor MO2. A second terminal of the transistor MO1 is connected to a wiring WBL, and a gate of the transistor MO1 is connected to a wiring WWL. A first terminal of the transistor MO2 is connected to a first terminal of the transistor MO3, and a second terminal of the transistor MO2 is connected to a second terminal of the capacitor CD1 and a wiring SL. A second terminal of the transistor MO3 is connected to a wiring RBL, and a gate of the transistor MO3 is connected to a wiring RWL.

[0071] In FIG. 2A, the connection point between the first terminal of the transistor MO1, the gate of the transistor MO2, and the first terminal of the capacitance element CD1 is shown as a node N1.

[0072] The wiring WWL has a function as a wiring that transmits a selection signal for writing in order to select the memory circuit MCt1 that is the write destination, for example. For this reason, the wiring WWL may be called a write word line.

[0073] The wiring RWL has a function as a wiring that transmits a selection signal for reading in order to select the memory circuit MCt1 that is the read source, for example. For this reason, the wiring RWL may be referred to as a read word line.

[0074] For example, the wiring WBL functions as a wiring for transmitting data to be written to the memory circuit MCt1, and is therefore sometimes referred to as a write bit line.

[0075] For example, the wiring RBL functions as a wiring for transmitting data read from the memory circuit MCt1, and is therefore sometimes referred to as a read bit line.

[0076] For example, the wiring SL functions as a wiring for supplying a fixed potential required when reading data from the memory circuit MCt1. For this reason, the wiring SL may be referred to as a source line. Note that the fixed potential may be, for example, a low-level potential, a ground potential, a negative potential, or the like.

[0077] In the memory circuit MCt1, the transistor MO1 is turned on, electrical continuity is established between the gate of the transistor MO2 and the wiring WBL, a write potential corresponding to write data is applied from the wiring WBL to the gate of the transistor MO1, and then the transistor MO1 is turned off, thereby enabling the write data to be held at the node N1. At this time, a fixed potential is always applied to the wiring SL, and thus a potential difference between the potential corresponding to the write data and the fixed potential is held in the capacitor CD1.

[0078] Furthermore, by applying a high-level potential, for example, as a fixed potential, to the wiring RBL and turning on the transistor MO3 to establish electrical continuity between the wiring RBL and the first terminal of the transistor MO2, a current corresponding to the gate-source voltage of the transistor MO2 (the potential difference between the first terminal and the second terminal of the capacitor CD1) flows between the wiring SL and the wiring RBL. By measuring the current flowing through the wiring SL or the wiring RBL, the write potential held in the memory circuit MCt1 can be read.

[0079] Furthermore, for example, by precharging the wiring RBL with a high-level potential to put the wiring RBL in a floating state, the transistor MO3 is turned on to establish electrical continuity between the wiring RBL and the first terminal of the transistor MO2, and the potential of the wiring RBL fluctuates depending on the gate-source voltage of the transistor MO2 (the potential difference between the first terminal and the second terminal of the capacitor CD1).The write potential held in the memory circuit MCt1 can also be read by measuring the fluctuating potential of the wiring RBL.

[0080] 2A holds a write potential at the node N1, the potential may fluctuate due to a leakage current (off-state current) of the transistor MO1. Therefore, the memory circuit MCt1 is preferably configured so that the potential of the node N1 does not fluctuate due to the leakage current.

[0081] An example of a configuration that prevents the potential of node N1 from fluctuating due to leakage current is the memory circuit MCt2 shown in Fig. 2B. The memory circuit MCt2 shown in Fig. 2B is a modified example of the memory circuit MCt1 shown in Fig. 2A, and differs from the memory circuit MCt1 in that it includes a transistor MO4 and a capacitance element CD2.

[0082] 2B, the second terminal of the transistor MO1 is connected to the first terminal of the transistor MO4 and the first terminal of the capacitance element CD2, not to the wiring WBL. The second terminal of the transistor MO4 is connected to the wiring WBL, and the gate of the transistor MO4 is connected to the wiring WWL. The second terminal of the capacitance element CD2 is connected to the wiring VGE.

[0083] In FIG. 2B, the connection point between the second terminal of the transistor MO1, the first terminal of the transistor MO4, and the first terminal of the capacitive element CD2 is shown as a node N2.

[0084] For example, the wiring VGE functions as a wiring that applies a fixed potential, which may be, for example, a low-level potential, a ground potential, or a negative potential.

[0085] In the memory circuit MCt2 of Figure 2B, the transistors MO1 and MO4 are connected in series, and the same wiring WWL is connected to the gates of the transistors MO1 and MO4. By connecting the transistors MO1 and MO4 in series in this way, the channel length of the transistor MO1 in Figure 2A can be considered to be substantially longer. By increasing the channel length, the leakage current flowing through the transistors MO1 and MO4 can be reduced, and the potential held at the node N1 of the memory circuit MCt2 can be maintained for a long period of time.

[0086] As described above, the capacitance element CD2 is connected to the second terminal of the transistor MO1 and the first terminal of the transistor MO4. When the transistors MO1 and MO4 are both on and the threshold voltages of the transistors MO1 and MO4 are appropriate, the potentials of the nodes N1 and N2 are equal. By turning off the transistors MO1 and MO4 after equalizing the potentials of the nodes N1 and N2, it is possible to prevent fluctuations in the potential of the node N1 even if, for example, the leakage current of the transistor MO1 increases due to a malfunction.

[0087] 2B, the number of each of the transistor MO4 and the capacitance element CD2 can be more than one. The memory circuit MCt3 of Fig. 2C is a modified example of the memory circuit MCt2 of Fig. 2B, and differs from the memory circuit MCt2 of Fig. 2B in that K (K is an integer of 2 or more) pieces of each of the transistor MO4 and the capacitance element CD2 are provided.

[0088] 2C shows only the transistor MO4[1], the transistor MO4[2], and the transistor MO4[K] out of the K transistors MO4, and also shows only the capacitance element CD2[1] and the capacitance element CD2[K] out of the K capacitance elements CD2.

[0089] The first terminal of the transistor MO4[K] is connected to the second terminal of the transistor MO1 and the capacitor CD2[K]. The second terminal of the transistor MO4[k+1] (k is an integer greater than or equal to 1 and less than or equal to K-1) is connected to the first terminal of the transistor MO4[k] and the first terminal of the capacitor CD2[k]. The second terminal of the transistor MO4[1] is connected to the wiring WBL. The gates of the transistors MO4[1] to MO4[K] are connected to the wiring WWL. The second terminals of the capacitors CD2[1] to CD2[K] are connected to the wiring VGE.

[0090] 2C, the connection point between the first terminal of the transistor MO4[1], the second terminal of the transistor MO4[2], and the capacitance element CD2[1] is shown as node N2[1], and the connection point between the first terminal of the transistor MO4[K], the second terminal of the transistor MO1, and the capacitance element CD2[K] is shown as node N2[K].

[0091] 2C , by providing multiple transistors between the node N1 and the wiring WBL, the channel length of the transistor MO1 can be effectively increased. This reduces the leakage current of each transistor flowing between the node N1 and the wiring WBL. Furthermore, by providing the capacitance element CD2 between each transistor, a sudden change in the potential of each node N2 can be prevented even if the leakage current of some of the transistors increases.

[0092] For example, a leakage current may occur between the source and drain of a transistor when a potential difference occurs between the source and drain in the off state. Specifically, in FIG. 2A, a leakage current may occur in transistor MO1 when a potential difference occurs between node N1 and wiring WBL. In FIG. 2B, a leakage current may occur in transistor MO4 when a potential difference occurs between node N2 and wiring WBL. In FIG. 2C, a leakage current may occur in transistor MO4[1] when a potential difference occurs between node N2[1] and wiring WBL.

[0093] 2A to 2C, when data is to be retained for a long period of time, even if the leakage current between the retention nodes (node ​​N1 in FIG. 2A, nodes N1 and N2 in FIG. 2B, and nodes N1 and N2[1] to N2[K] in FIG. 2C) and the wiring WBL is small, the potential change of the retention nodes gradually increases over time. For this reason, the data in the memory circuits MCt1 to MCt3 also needs to be periodically refreshed.

[0094] <Memory Circuit 1 of One Embodiment of the Present Invention> A memory circuit of one embodiment of the present invention has been developed in consideration of the above-described problems and has a configuration in which a source follower configuration is added to the above-described memory circuit. FIG. 1 shows an example of a circuit configuration of a memory circuit of one embodiment of the present invention. The memory circuit MC1 in FIG. 1 is a modified example of the memory circuit MCt1 in FIG. 2A and has a configuration in which transistors MS1 and MS2 are added to the memory circuit MCt1 in FIG. 2A. Therefore, description of parts of the memory circuit MC1 that are common to the memory circuit MCt1 will be omitted.

[0095] The gate of transistor MS1 is connected to the first terminal of transistor MO1, the gate of transistor MO2, and the first terminal of capacitor CD1. The first terminal of transistor MS1 is connected to the first terminal of transistor MS2, and the second terminal of transistor MS1 is connected to wiring VDE. The gate of transistor MS2 is connected to wiring VRE, and the second terminal of transistor MS2 is connected to wiring VSE.

[0096] 1, the transistors MO1 to MO4, the transistor MS1, and the transistor MS2 are preferably OS transistors, for example. In particular, examples of metal oxides in the channel formation regions of OS transistors include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably includes one or more elements selected from the group consisting of indium, an element M, and zinc. The element M is preferably one or more elements selected from the group consisting of aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony. In particular, the element M is preferably one or more elements selected from the group consisting of aluminum, gallium, yttrium, and tin.

[0097] In particular, as the metal oxide used for the semiconductor layer, an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also referred to as IGZO) is preferably used. Alternatively, an oxide containing indium, tin, and zinc (also referred to as ITZO (registered trademark)) is preferably used. Alternatively, an oxide containing indium, gallium, tin, and zinc is preferably used. Alternatively, an oxide containing indium (In), aluminum (Al), and zinc (Zn) (also referred to as IAZO) is preferably used. Alternatively, an oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) (also referred to as IAGZO) is preferably used. Note that OS transistors will be described in detail in Embodiments 2 and 3.

[0098] Furthermore, the metal oxide included in the channel formation region of the OS transistor preferably has a stacked structure of multiple oxide layers with different chemical compositions. For example, consider a two-layer oxide layer structure consisting of a first layer and a second layer located immediately above the first layer. The atomic ratio of the element M to the main metal element in the metal oxide used for the first layer is preferably larger than the atomic ratio of the element M to the main metal element in the metal oxide used for the second layer. Furthermore, the atomic ratio of the element M to In in the metal oxide used for the first layer is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the second layer. This structure can suppress diffusion of impurities and oxygen from structures formed below the first layer into the second layer.

[0099] In the metal oxide used for the second layer, the atomic ratio of In to the element M is preferably larger than that of In to the element M in the metal oxide used for the first layer. With this structure, the OS transistor can have large on-state current and high frequency characteristics.

[0100] Specifically, for example, the metal oxide used in the first layer may have a composition of In:M:Zn = 1:3:2 (atomic ratio) or a composition thereabout, In:M:Zn = 1:3:4 (atomic ratio) or a composition thereabout, or In:M:Zn = 1:1:0.5 (atomic ratio) or a composition thereabout. Furthermore, the metal oxide used in the second layer may have a composition of In:M:Zn = 1:1:1 (atomic ratio) or a composition thereabout, In:M:Zn = 1:1:1.2 (atomic ratio) or a composition thereabout, In:M:Zn = 1:1:2 (atomic ratio) or a composition thereabout, or In:M:Zn = 4:2:3 (atomic ratio) or a composition thereabout. Note that a composition thereabout includes a range of ±30% of the desired atomic ratio.

[0101] Incidentally, in order to reduce the off-state current of a transistor, it is preferable to use, for example, an oxide containing indium (In), gallium (Ga), and zinc (Zn) as the metal oxide used in the semiconductor layer of the transistor. When the semiconductor layer of the transistor contains an oxide containing indium (In), gallium (Ga), and zinc (Zn), the amount of current flowing between the source and drain of the transistor when the gate-source voltage is 0 V is 1×10 per 1 μm of channel width at room temperature (e.g., 25° C.). −２０ A or less, 1 x 10 at 85°C −１８ A or less, or 1 x 10 at 125°C −１６ A or less. In this specification, as described above, the term "normally off" refers to a state in which the amount of current flowing between the source and drain of a transistor is extremely small when the gate-source voltage of the transistor is 0 V. In particular, by using transistors including the oxide in semiconductor layers as the transistors MO1, MO4, MS1, and MS2, the off-state current of each of the transistors MO1, MO4, MS1, and MS2 can be extremely small.

[0102] Furthermore, each of the transistors MO1 to MO4, the transistor MS1, and the transistor MS2 can be a transistor containing silicon in a channel formation region (hereinafter referred to as a Si transistor) other than an OS transistor. Si transistors have a higher on-state current than OS transistors and are therefore suitable for passing a large current. In particular, by using a Si transistor as the transistor MO2, a read current flowing between the source and drain of the transistor MO2 can be increased, thereby enabling a faster read operation.

[0103] Further, for each of the transistors MO1 to MO4, the transistor MS1, and the transistor MS2, in addition to OS transistors and Si transistors, a transistor including germanium in a channel formation region, a transistor including a compound semiconductor such as zinc selenide, cadmium sulfide, gallium arsenide, indium phosphide, gallium nitride, or silicon germanium in a channel formation region, a transistor including a carbon nanotube in a channel formation region, or a transistor including an organic semiconductor in a channel formation region can be used.

[0104] For example, the wiring VDE functions as a wiring that applies a fixed potential. The fixed potential can be, for example, a high-level potential.

[0105] For example, the wiring VSE functions as a wiring that applies a fixed potential. The fixed potential can be, for example, a low-level potential, a ground potential, or a negative potential that is lower than the high-level potential applied by the wiring VDE.

[0106] For example, the wiring VRE functions as a wiring that applies a fixed potential. The fixed potential is preferably a potential that allows the transistor MS2 to function as a current source. For example, when the wiring VSE functions as a wiring that applies a ground potential, applying a high-level potential to the wiring VRE makes the gate-source voltage of the transistor MS2 constant. Therefore, applying a voltage between the source and drain of the transistor MS2 causes a constant current to flow between the source and drain of the transistor MS2.

[0107] The transistors MS1 and MS2 have a source follower configuration. Specifically, the circuit configuration of the transistors MS1 and MS2 has a function of outputting a potential corresponding to the potential of the node N1 to the first terminal of the transistor MS1 and the first terminal of the transistor MS2 (node ​​N2). In particular, in one embodiment of the present invention, the gain between the potential of the node N1 (which is the input) and the potential of the node N2 (which is the output) is preferably 1:1. To achieve this, it is preferable to adjust the gain by changing the potential applied by the wiring VRE.

[0108] By setting the gain between the potential of node N1 (the input) and the potential of node N2 (the output) at 1:1, the potential of node N2 can be set to the potential of node N1. Furthermore, by making the current flowing from the wiring VDE via transistor MS1 or the current flowing to the wiring VSE via transistor MS2 larger than the leakage current of transistor MO4, the charge lost at node N2 due to the leakage current can be compensated for by the source followers of transistors MS1 and MS2. This allows the potential of node N2 to be maintained at the potential of node N1.

[0109] <<Example of Operation Method>> Next, an example of the operation method of the memory circuit MC1 in FIG. 1 will be described.

[0110] 3 is a timing chart illustrating an operation example of the memory circuit MC1. The timing chart in FIG. 3 illustrates changes in the potentials of the wirings WWL, RWL, WBL, and RBL, the node N1, and the node N2 during the periods T1 to T8. In the timing chart in FIG. 3, a high-level potential is represented as "High," and a low-level potential is represented as "Low."

[0111] In the timing chart of FIG. 3, data is written to the memory circuit MC1 in the periods T1 to T4, and data is read from the memory circuit MC1 in the periods T6 to T8.

[0112] Before the period T1, the wirings WWL, RWL, and RBL are supplied with a low-level potential, and the gates of the transistors MO1, MO3, and MO4 are supplied with a low-level potential, turning off the transistors MO1, MO3, and MO4.

[0113] In addition, for example, the wiring WBL is Ｍ is given. Ｍ is a potential higher than the low level potential and lower than the high level potential.

[0114] Before the period T1, the potential of the node N1 is V ＵＫ In addition, V ＵＫ The potential of the node N2 is set to V, which is the same as the potential of the node N1, by the source follower formed by the transistors MS1 and MS2. ＵＫ It is assumed that the following is true.

[0115] Note that a low-level potential is always applied to the wiring SL.

[0116] [Period T1] During the period T1, a potential corresponding to data written to the memory circuit MC1 is applied to the wiring WBL. For example, when the data corresponds to a logic "1," a high-level potential corresponding to the data is applied to the wiring WBL. When the data corresponds to a logic "0," a low-level potential corresponding to the data is applied to the wiring WBL.

[0117] In the timing chart of FIG. 3, the potential changes of the wiring WBL and the nodes N1 and N2 are indicated by dashed lines for data corresponding to the logic of "1" and by dashed lines for data corresponding to the logic of "0".

[0118] [Period T2] During period T2, a high-level potential is applied to the wiring WWL. Therefore, a high-level potential is applied to the gates of the transistors MO1 and MO4, turning on the transistors MO1 and MO4. As a result, the wiring WBL, the node N1, and the node N2 are mutually conductive and at the same potential.

[0119] For example, when a high-level potential corresponding to logic "1" is applied to the wiring WBL, the potentials of the nodes N1 and N2 become high. On the other hand, when a low-level potential corresponding to logic "0" is applied to the wiring WBL, the potentials of the nodes N1 and N2 become low.

[0120] [Period T3] During period T3, a low-level potential is applied to the wiring WWL. As a result, a low-level potential is applied to the gates of the transistors MO1 and MO4, turning off the transistors MO1 and MO4. This causes the wiring WBL to be electrically disconnected from the nodes N1 and N2.

[0121] At this time, the nodes N1 and N2 are each in a floating state. Furthermore, the source follower formed by the transistors MS1 and MS2 applies a potential equal to the potential of the node N1 to the node N2. This prevents fluctuations in the potential of the node N2 due to leakage currents in the transistors MO1, MO4, and the capacitance element CD2.

[0122] [Period T4] During period T4, for example, V Ｍ is given.

[0123] [Period T5] During period T5, no signals are input to the wirings WWL, RWL, WBL, and RBL. Therefore, the potentials of nodes N1 and N2 of memory circuit MC1 do not fluctuate according to the data written thereto. Even if the potential of node N2 fluctuates due to leakage current from transistor MO4, capacitor CD2, and the like, the source follower formed by transistors MS1 and MS2 maintains the potential of node N2 at the same potential as node N1. Therefore, period T5 may be referred to as a retention period, for example.

[0124] [Period T6] In the period T6, for example, a high-level potential is applied to the wiring RBL.

[0125] [Period T7] During period T7, a high-level potential is applied to the wiring RWL. Therefore, a high-level potential is applied to the gate of the transistor MO3, turning the transistor MO3 on. As a result, a high-level potential is applied from the wiring RBL to the first terminal of the transistor MO2.

[0126] At this time, the gate-source voltage of transistor MO2 is the potential difference between the high-level potential and the low-level potential, so that transistor MO2 is turned on. Furthermore, the source-drain voltage of transistor MO2 is the potential difference between the high-level potential and the low-level potential, so that a drain current flows between the source and drain of transistor MO2. Note that the amount of this drain current is determined by the gate-source voltage of transistor MO2 when transistor MO2 operates in the saturation region. Therefore, the amount of this drain current is determined by the potential corresponding to the logic of the data written to the gate (node ​​N1) of transistor MO2.

[0127] Therefore, by measuring the current flowing from the wiring RBL to the wiring SL through the transistors MO2 and MO3, data written in the memory circuit MC1 can be read.

[0128] [Period T8] During the period T8, a low-level potential is applied to the wiring RWL. Therefore, a low-level potential is applied to the gate of the transistor MO3, turning off the transistor MO3. Also, during the period T8, a low-level potential is applied to the wiring RBL. Therefore, during the period T8, no current flows from the wiring RBL to the wiring SL through the transistors MO2 and MO3.

[0129] As described above, data can be written to the memory circuit MC1 by performing the periods T1 to T4, and the data can be read from the memory circuit MC1 by performing the periods T5 to T8.

[0130] In the periods T5 to T8, data is read from the memory circuit MC1 based on the amount of current flowing from the wiring RBL to the wiring SL through the transistors MO2 and MO3. However, for example, data can also be read from the memory circuit MC1 by precharging the wiring RBL to a high-level potential in the period T6 to bring it into a floating state, and then turning on the transistor MO3 in the period T7 to measure the potential that has changed in the wiring RBL.

[0131] Since the memory circuit MC1 has a source follower consisting of transistors MS1 and MS2, the memory circuit MC1 can write and read not only digital value (binary) data as shown in the timing chart of Figure 3, but also analog potential (multiple-valued) data.

[0132] <<Example of Layout of Memory Circuit>> Next, an example of the layout of the above-described memory circuit MC1 will be described.

[0133] Fig. 4 is a layout (also referred to as a plan view schematic diagram) showing an example of the memory circuit MC1 shown in Fig. 1. In Fig. 4, the memory circuit MC1 has, as an example, a conductive layer GEM, a conductive layer SDM, a conductive layer WIR, a semiconductor layer SMC, and a conductive layer PLG. Note that, to clearly show the layout, Fig. 4 does not show the insulating layers included in the memory circuit MC1.

[0134] As an example, the semiconductor layer SMC is located below the conductive layers SDM and GEM. Also, as an example, the conductive layer PLG is located above the conductive layers SDM and GEM. Also, as an example, the conductive layer WIR is located above the conductive layer PLG. The order of formation can be as follows: first, the semiconductor layer SMC, second, one of the conductive layers SDM and GEM, third, the other of the conductive layers SDM and GEM, fourth, the conductive layer PLG, and fifth, the conductive layer WIR.

[0135] For example, parts of the conductive layer GEM function as gates of the transistors MO1 to MO4, the transistor MS1, and the transistor MS2, and for example, parts of the conductive layer GEM function as one of a pair of electrodes of the capacitors CD1 and CD2.

[0136] Furthermore, a part of the conductive layer GEM can be a wiring extending around the memory circuit MC1. For example, in FIG. 4, each of the wiring WWL, wiring SL, wiring VRE, wiring VSE, wiring VDE, and wiring RWL extending around the memory circuit MC1 can be formed as a part of the conductive layer GEM.

[0137] Part of the conductive layer SDM functions as the source or drain of each of the transistors MO1 to MO4, the transistor MS1, and the transistor MS2, for example.

[0138] For example, a part of the conductive layer WIR functions as the other of the pair of electrodes of each of the capacitor elements CD1 and CD2.

[0139] Furthermore, a part of the conductive layer WIR can be a wiring extending around the memory circuit MC1. For example, in FIG. 4, each of the wiring VGE, wiring WBL, and wiring RBL extending around the memory circuit MC1 can be formed as a part of the conductive layer WIR.

[0140] The conductive layer GEM, the conductive layer SDM, the conductive layer WIR, and the semiconductor layer SMC can each be formed using, for example, a lithography method. Specifically, for example, when forming the conductive layer GEM, a conductive material to be the conductive layer GEM can be formed using one or more methods selected from a sputtering method, a CVD (Chemical Vapor Deposition) method, a PLD (Pulsed Laser Deposition) method, and an ALD (Atomic Layer Deposition) method, and then a desired pattern can be formed using a lithography method. In addition, the conductive layer SDM, the conductive layer WIR, the semiconductor layer SMC, and the conductive layer PLG can also be formed using the same method as above.

[0141] Furthermore, insulating layers may be provided between the semiconductor layer SMC and the conductive layer GEM, between the conductive layer GEM and the conductive layer SDM, and between the conductive layer WIR and the conductive layer GEM. In particular, the insulating layer provided between the semiconductor layer SMC and the conductive layer GEM may function as a gate insulating film (sometimes referred to as a front gate insulating film, etc.). Furthermore, in the region where the capacitive element CD1 or the capacitive element CD2 is provided, an insulating layer that functions as a dielectric of the capacitive element CD1 or the capacitive element CD2 is preferably provided between the conductive layer WIR and the conductive layer GEM.

[0142] Furthermore, an opening is provided in the region where a portion of the conductive layer SDM overlaps a portion of the conductive layer WIR, and a conductive layer PLG is embedded in the opening. This allows charge to move between a portion of the conductive layer SDM and a portion of the conductive layer WIR via the conductive layer PLG. Similarly, an opening is provided in the region where a portion of the conductive layer GEM overlaps a portion of the conductive layer WIR, and another conductive layer PLG is embedded in the opening. This allows charge to move between a portion of the conductive layer GEM and a portion of the conductive layer WIR via the conductive layer PLG.

[0143] Furthermore, since the memory circuit MC1 of FIG. 1 has six transistors, the transistors can be arranged in a matrix of two rows and three columns, as shown in FIG. 4. Specifically, it is preferable to arrange the transistors MO4, MO1, and MO2 in order from the upper left to the upper right of FIG. 4, and the transistors MS2, MS1, and MO3 in order from the lower left to the lower right of FIG. 4. This allows the capacitance element CD1 to be arranged between the transistors MO1 and MS1 and the transistors MO2 and MO3, and the capacitance element CD2 to be arranged between the transistors MO4 and MO1 and the transistors MS1 and MS2. By designing the memory circuit MC1 of FIG. 1 according to the layout of FIG. 4, a memory circuit MC1 with a reduced circuit area can be configured.

[0144] Note that the layout of the memory circuit of one embodiment of the present invention is not limited to that shown in FIG. 4. The layout of the memory circuit of one embodiment of the present invention may be modified as appropriate to that shown in FIG.

[0145] <Memory Circuit 2 of One Embodiment of the Present Invention> Here, a configuration of a memory circuit of one embodiment of the present invention, which is different from the configuration of the memory circuit MC1 shown in FIG. 1, will be described.

[0146] The memory circuit MC2 shown in Figure 5A is a modified example of the memory circuit MC1 of Figure 1, and differs from the memory circuit MC1 in that the second terminal of the capacitance element CD2 is connected to the second terminal of the transistor MO2, the second terminal of the capacitance element CD1, and the wiring SL, rather than to the wiring VGE.

[0147] Unlike the configuration of the memory circuit MC1 in Fig. 1, the memory circuit MC2 in Fig. 5A does not need to have a wiring VGE, and therefore the circuit area can be reduced more than that of the memory circuit MC1 in Fig. 1. This allows the storage density per circuit area to be increased in a memory device including the memory circuit MC2.

[0148] <Memory Circuit 3 of One Embodiment of the Present Invention> A configuration of a memory circuit of one embodiment of the present invention, which is different from the configurations of the memory circuit MC1 in FIG. 1 and the memory circuit MC2 in FIG. 5A, will be described.

[0149] The memory circuit MC3 in FIG. 5B is a modification of the memory circuit MC1 in FIG. 1, and differs from the memory circuit MC1 in that it does not include the capacitive element CD2.

[0150] The memory circuit MC3 in FIG. 5B does not include the capacitive element CD2, and therefore the potential of the node N2 can be maintained by constantly operating the source follower formed by the transistor MS1 and the transistor MS2.

[0151] Furthermore, since the memory circuit MC3 in Fig. 5B does not include the capacitive element CD2, the circuit area can be reduced compared to the memory circuit MC1 in Fig. 1. This allows the recording density per circuit area to be increased in a memory device including the memory circuit MC2.

[0152] <Memory Circuit 4 of One Embodiment of the Present Invention> A configuration of a memory circuit of one embodiment of the present invention, which is different from the configurations of the memory circuit MC1 in FIG. 1, the memory circuit MC2 in FIG. 5A, and the memory circuit MC3 in FIG. 5B, will be described.

[0153] 6 is a memory circuit configured to amplify the potentials of the nodes N2[1] to N2[K] by source followers that receive the potential of the node N1 as an input in the memory circuit MCt3 in FIG. 2C. Therefore, the memory circuit MC4 has a circuit configuration in which K source followers are added to the circuit configuration of the memory circuit MCt3.

[0154] Specifically, the memory circuit MC4 has a configuration in which transistors MS1[1] to MS1[K] and transistors MS2[1] to MS2[K] are added to the circuit configuration of the memory circuit MCt3.

[0155] The gates of the transistors MS1[1] to MS1[K] are connected to the first terminal of the transistor MO1, the gate of the transistor MO2, and the first terminal of the capacitor CD1. The second terminals of the transistors MS1[1] to MS1[K] are connected to the wiring VDE. The second terminals of the transistors MS2[1] to MS2[K] are connected to the wiring VSE.

[0156] The first terminal of the transistor MS1[K] is connected to the first terminal of the transistor MS2[K], the first terminal of the transistor MO4[K], the second terminal of the transistor MO1, and the first terminal of the capacitive element CD2[K]. The first terminal of the transistor MS1[k] is connected to the first terminal of the transistor MS2[k], the first terminal of the transistor MO4[k], the second terminal of the transistor MO4[k+1], and the first terminal of the capacitive element CD2[k].

[0157] 2C includes K source followers, the potentials of the nodes N2[1] to N2[K] can be amplified to the potential of the node N1. This can prevent a decrease in the potentials of the nodes N2[1] to N2[K] due to leakage current that may occur in the transistors MO4[1] to MO4[K], the transistor MO1, the capacitors CD2[1] to CD2[K], and the like.

[0158] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0159] Embodiment 2 In this embodiment, a memory device including the memory circuit described in the above embodiment will be described.

[0160] Fig. 7A shows a schematic perspective view illustrating an example of the configuration of the memory device MDV. Fig. 7B shows a block diagram illustrating an example of the configuration of the memory device MDV. The memory device MDV has a layer SS1 including a substrate 311 and a drive circuit region 50 formed on the substrate 311, and a layer SS2 including memory cells 10. Also, as shown in Fig. 7A, the layer SS2 can be provided above the layer SS1.

[0161] The substrate 311 may be, for example, a semiconductor substrate (e.g., a single-crystal substrate made of silicon or germanium). Other than semiconductor substrates, examples of materials that may be used include an SOI (Silicon-On-Insulator) substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate having stainless steel foil, a tungsten substrate, a substrate having tungsten foil, a flexible substrate, a laminated film, paper containing a fibrous material, or a base film. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, and soda-lime glass. Examples of flexible substrates, laminated films, and base films include plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Another example is a synthetic resin such as acrylic. Other examples include polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride. Other examples include polyamide, polyimide, aramid, epoxy resin, inorganic vapor deposition film, and paper. If the manufacturing process of the memory device MDV includes heat treatment, it is preferable to select a material with high heat resistance for the substrate.

[0162] In this embodiment, the substrate 311 is described as a semiconductor substrate containing silicon.

[0163] The memory circuit MC1 described in the first embodiment can be applied to the memory cell 10 shown in FIG. 7A . The memory device MDV includes a memory cell array MCA, which includes a plurality of memory cells 10. In FIG. 7A , the memory cell array MCA includes a plurality of memory cells 10 arranged in a matrix. In FIG. 7B , the memory cell array MCA includes a memory cell 10[1,1], a memory cell 10[m,1] (where m is an integer equal to or greater than 1), a memory cell 10[1,n] (where n is an integer equal to or greater than 1), a memory cell 10[m,n], and a memory cell 10[i,j] (where i is an integer equal to or greater than 1 and m, and j is an integer equal to or greater than 1 and n) arranged in the memory cell array MCA.

[0164] 7B, the drive circuit region 50 shown in Fig. 7A has a PSW 22 (power switch), a PSW 23, and a peripheral circuit 31. The peripheral circuit 31 has a peripheral circuit 41, a control circuit 32, and a voltage generation circuit 33.

[0165] In the memory device MDV, each circuit, each signal, and each voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or other signals can be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0166] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Signals PON1 and PON2 can be generated by the control circuit 32.

[0167] The control circuit 32 is a logic circuit that has the function of controlling the overall operation of the memory device MDV. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation or read operation) of the memory device MDV. Alternatively, the control circuit 32 generates a control signal for the peripheral circuit 41 so that this operation mode is executed.

[0168] For example, the voltage generating circuit 33 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 33. For example, when a high-level signal is applied to the signal WAKE, the signal CLK is input to the voltage generating circuit 33, and the voltage generating circuit 33 generates a negative voltage.

[0169] The peripheral circuit 41 is a circuit for writing and reading data to and from the memory cell 10. The peripheral circuit 41 includes a row decoder , a column decoder 44, a row driver 43, a column driver 45, an input circuit 47, and an output circuit .

[0170] The row decoder 42 and the column decoder 44 have the function of decoding the signal ADDR. The row decoder 42 is a circuit for specifying the row to be accessed, and the column decoder 44 is a circuit for specifying the column to be accessed. In other words, the row decoder 42 and the column decoder 44 are sometimes called selection circuits that select the memory cell 10 to be written to or read from.

[0171] The row driver 43 has a function of selecting the write and read word lines designated by the row decoder 42 .

[0172] Specifically, for example, the write word line corresponds to the wiring WWL described in the first embodiment, and the read word line corresponds to the wiring RWL described in the first embodiment. Therefore, by selecting one of the plurality of wirings WWL by the row decoder 42, the write transistors (corresponding to the transistors MO1 and MO4 in FIG. 1 ) of the memory cells 10 arranged in the row to which data is written can be turned on. Also, by selecting one of the plurality of wirings RWL by the row decoder 42, the read transistors (corresponding to the transistor MO3 in FIG. 1 ) of the memory cells 10 arranged in the row from which data is read can be turned on.

[0173] The column driver 45 has the function of writing data to the memory cells 10, the function of reading data from the memory cells 10, and the function of holding the read data.

[0174] The column driver 45 also has a function of selecting the write and read bit lines specified by the column decoder 44. This allows the column decoder 44 to select a column including a memory cell 10 to be written to or read from. Specifically, for example, the write bit line corresponds to the wiring WBL described in the first embodiment, and the read bit line corresponds to the wiring RBL described in the first embodiment. Therefore, by selecting the wiring WBL using the column decoder 44, write data can be transmitted to the memory cell 10 to be written to via the wiring WBL. Furthermore, by selecting the wiring RBL using the column decoder 44, read data can be received from the memory cell 10 to be read from via the wiring RBL.

[0175] As described above, the column driver 45 contributes to the write operation on the memory cell 10, and therefore may be referred to as a write circuit that transmits write data to the memory cell 10. Similarly, the column driver 45 contributes to the read operation on the memory cell 10, and therefore may be referred to as a read circuit that reads read data from the memory cell 10.

[0176] The input circuit 47 has a function of holding a signal WDA. The data held by the input circuit 47 is output to the column driver 45. The output data of the input circuit 47 is data (Din) to be written to the memory cell 10. The data (Dout) read from the memory cell 10 is amplified by an amplifier circuit included in the column driver 45 and output to the output circuit 48. The output circuit 48 has a function of holding Dout. The output circuit 48 also has a function of outputting Dout to the outside of the memory device MDV. The data output from the output circuit 48 is a signal RDA.

[0177] PSW22 has a function of controlling the supply of VDD to the peripheral circuit 31. PSW23 has a function of controlling the supply of VHM to the row driver 43. In this example, the high power supply voltage of the memory device MDV is VDD, and the low power supply voltage is GND (ground potential). VHM is a high power supply voltage used to set the word line to a high level and is higher than VDD. Signal PON1 switches PSW22 between the ON and OFF states, and signal PON2 switches PSW23 between the ON and OFF states. In FIG. 7B, the number of power domains to which VDD is supplied in the peripheral circuit 31 is one, but multiple domains may also be used. In this case, it is preferable to provide a power switch for each power domain.

[0178] 8 is a block diagram showing an example of the configuration of the peripheral circuit 41 and the memory cell array MCA. In Fig. 8, a row decoder 42 and a row driver 43 are connected to the wirings WWL[1] to WWL[m] and the wirings RWL[1] to RWL[m], respectively, and a column decoder 44, a column driver 45, and a sense amplifier 46 are connected to the wirings WBL[1] to WBL[n] and the wirings RBL[1] to RBL[n], respectively.

[0179] Note that the wirings WWL[1] to WWL[m] correspond to the wiring WWL described in Embodiment 1, and the wirings RWL[1] to RWL[m] correspond to the wiring RWL described in Embodiment 1. The wirings WBL[1] to WBL[n] correspond to the wiring WBL described in Embodiment 1, and the wirings RBL[1] to RBL[n] correspond to the wiring RBL described in Embodiment 1.

[0180] The memory cell 10[i,j] arranged in the i-th row and j-th column is connected to the wiring WWL[i], the wiring RWL[i], the wiring WBL[j], and the wiring RBL[j].

[0181] As shown in FIG. 8, by connecting the memory cell array MCA and the peripheral circuit 41 to each other, data can be written to the memory cell array MCA and data can be read from the memory cell array MCA.

[0182] <Cross-sectional configuration example 1 of memory device> Next, a specific configuration example of the memory device MDV shown in Figures 7A and 7B will be described. Figure 9 is a schematic cross-sectional view of one example of the memory device MDV shown in Figures 7A and 7B.

[0183] 9 shows a schematic cross-sectional view of the layer SS1 and the memory layer SS2. Note that the memory device MDV shown in FIG. 9 has a configuration in which the layer SS1 is formed directly on the layer SS1.

[0184] 9 illustrates a transistor 400 included in the layer SS1. The transistor 400 is provided over a substrate 311 and includes a conductive layer 316 functioning as a gate, insulating layers 315 and 317 functioning as gate insulating films, a semiconductor region 313 including part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions including part of the substrate. A p-channel transistor or an n-channel transistor can be used as the transistor 400.

[0185] In the transistor 400 shown in FIG. 9 , a semiconductor region 313 (a part of a substrate 311) where a channel is formed has a convex shape. A conductive layer 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulating layer 315 interposed therebetween. Note that the conductive layer 316 can be formed using a material that adjusts the work function. Such a transistor 400 is also called a fin-type transistor because it utilizes the convex portion of the semiconductor substrate. Note that one method for forming the convex portion is to form an insulating layer on the semiconductor substrate, which functions as a mask for forming the convex portion. While the case where the convex portion is formed by processing a part of the semiconductor substrate has been described, a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

[0186] Note that the transistor 400 illustrated in FIG. 9 is an example and is not limited to this structure. An appropriate transistor can be used depending on the circuit configuration or driving method.

[0187] The transistor 400 may be, for example, a transistor included in the drive circuit region 50 shown in FIGS. 7A and 7B.

[0188] Furthermore, one or both of the layer SS1 and the layer SS2 may include a wiring layer provided with an interlayer film, wiring, and plugs. Furthermore, multiple wiring layers may be provided depending on the design. Furthermore, in this specification and the like, wiring and a plug connected to the wiring may be integrated. That is, there are cases where a part of a conductive layer functions as wiring, and cases where a part of a conductive layer functions as a plug.

[0189] For example, an insulating layer 320, an insulating layer 324, and an insulating layer 326 are stacked in this order as an interlayer film over the transistor 400. A conductive layer 328 and the like are embedded in the insulating layer 320. A conductive layer 330 and the like are embedded in the insulating layer 324 and the insulating layer 326. The conductive layer 328 and the conductive layer 330 function as contact plugs or wirings.

[0190] The insulating layer functioning as an interlayer film can also be used as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulating layer 320 can be planarized by a planarization process using a chemical mechanical polishing (CMP) method to improve the planarity.

[0191] 9, an insulating layer 350, an insulating layer 357, an insulating layer 352, and an insulating layer 354 are stacked in this order over the insulating layer 326 and the conductive layer 330. A conductive layer 356 is formed in the insulating layer 350, the insulating layer 357, and the insulating layer 352. The conductive layer 356 functions as a contact plug or a wiring.

[0192] An insulating layer 354 is provided on the insulating layer 352 and the conductive layer 356. Contact plugs or wiring can be embedded in the insulating layer 354 to connect to an upper circuit (e.g., a circuit included in layer SS2).

[0193] 9 also illustrates a portion of the memory cell 10 included in the layer SS2. Specifically, FIG. 9 illustrates transistors MO1 to MO4 and capacitors CD1 and CD2 included in the memory cell 10. Note that the memory cell 10 can be the memory circuits MC1 to MC4 described in the embodiment. Therefore, although the transistors MS1 and MS2 are not illustrated in FIG. 9, the transistors MS1 and MS2 can be provided in the layer SS2. Although the transistors MO1 to MO4 are described below, the description of the transistors MO1 to MO4 can be referred to for the transistors MS1 and MS2.

[0194] Each of the transistors MO1 to MO4 is a transistor with a GL (Gate Last) structure, in which a gate insulating film is formed so as to cover the top and side surfaces of an island-shaped semiconductor layer, and a gate electrode is formed on the gate insulating film.

[0195] In the layer SS2 of the memory device MDV in Figure 9, the transistors MO2, MO3, and the capacitor CD1 are formed on the insulating layer STJ1. The transistors MO1, MO4, and the capacitor CD2 are formed on the insulating layer STJ2. The insulating layer STJ2 is located above the insulating layer STJ1. Therefore, the transistors MO1, MO4, and the capacitor CD2 are located above the transistors MO2, MO3, and the capacitor CD1.

[0196] 9, the transistors MO2 and MO3 are provided so as to share one island-shaped semiconductor layer. Specifically, a gate insulating film and a gate electrode of the transistor MO2 are formed in one of two regions of the island-shaped semiconductor layer, and a gate insulating film and a gate electrode of the transistor MO3 are formed in the other of the two regions of the island-shaped semiconductor layer.

[0197] 9, as an example, transistors each having a back gate are used as the transistors MO2 and MO3. In particular, the back gate of the transistor MO2 is located in a region overlapping the gate insulating film and gate electrode of the transistor MO2 below the one island-shaped semiconductor layer described above, and the back gate of the transistor MO3 is located in a region overlapping the gate insulating film and gate electrode of the transistor MO3 below the one island-shaped semiconductor layer described above.

[0198] A conductive layer corresponding to the wiring SL is electrically connected to one of the source electrode or drain electrode of the transistor MO2. A conductive layer corresponding to the wiring RBL is connected to one of the source electrode or drain electrode of the transistor MO3. The wiring SL and the wiring RBL extend in the channel width direction of the transistor MO2 or the transistor MO3, for example.

[0199] The conductive layer serving as the gate electrode of the transistor MO3 extends in the direction of the channel width and corresponds to the wiring RWL.

[0200] An insulating layer functioning as an interlayer film is formed between the transistors MO2 and MO3 and between the transistors MO1 and MO4. The insulating layer has openings in a region overlapping the gate electrode of the transistor MO2 and a region overlapping the capacitor CD1, and conductive layers are embedded in each of the openings. Both conductive layers are connected to one of the source electrode and drain electrode of the transistor MO1.

[0201] As described above, the transistors MO1 and MO4 are located above the transistors MO2 and MO3. A dielectric for the capacitor CD2 is formed between the transistors MO1 and MO4 so as to cover the ends of the island-shaped semiconductor layers of each transistor, and a conductive layer functioning as the second terminal of the capacitor CD2 is formed on the dielectric. The conductive layer also functions as the wiring VGE.

[0202] The gate insulating film and gate electrode of the transistor MO1 are formed in the island-shaped semiconductor layer region of the transistor MO1. In particular, the conductor serving as the gate electrode of the transistor MO1 extends in the channel width direction. This conductive layer also functions as the wiring WWL.

[0203] Similarly, a gate insulating film and a gate electrode of the transistor MO4 are formed in the island-shaped semiconductor layer region of the transistor MO4. In particular, the conductor serving as the gate electrode of the transistor MO4 extends in the channel width direction. This conductive layer also functions as a wiring WWL.

[0204] Similarly to the transistors MO3 and MO4, each of the transistors MO1 and MO4 may be a transistor having a back gate. In particular, the back gate of the transistor MO1 is located in a region that overlaps the gate insulating film and gate electrode of the transistor MO1 below the island-shaped semiconductor layer. Similarly, the back gate of the transistor MO4 is located in a region that overlaps the gate insulating film and gate electrode of the transistor MO4 below the island-shaped semiconductor layer.

[0205] As described above, in the transistors MO1 to MO4, the gate and the back gate are arranged to sandwich a semiconductor channel formation region between them. The gate and the back gate are formed of conductors. The back gate can function similarly to the gate. The threshold voltage of the transistor can be changed by changing the potential of the back gate. For example, the back gate can be connected to the gate to make the potentials of the gate and the back gate uniform. Alternatively, for example, the back gate can be connected to an external power supply circuit or the like to apply a ground potential or any other potential generated by the power supply circuit or the like to the back gate.

[0206] Furthermore, since the gate and back gate are made of conductors, they also have the function of preventing an electric field generated outside the transistor from acting on the semiconductor in which the channel is formed (particularly, an electrostatic shielding function against static electricity). That is, it is possible to prevent the electrical characteristics of the transistor from fluctuating due to the influence of an external electric field such as static electricity. Furthermore, the provision of a back gate can reduce the amount of change in the threshold voltage of the transistor before and after a bias thermal stress test (sometimes called a BT test).

[0207] For example, by using a transistor having a back gate as the transistor MO1, the influence of an external electric field can be reduced and the transistor can be stably maintained in an off state. Therefore, data written to the first terminal of the capacitive element CD1 can be stably held. By providing a back gate, the operation of the memory cell 10 can be stabilized, and the reliability of the memory cell array MCA including the memory cell 10 can be improved.

[0208] For the semiconductor layers in which the channels of the transistors MO1 to MO4 are formed, a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used alone or in combination. Examples of the semiconductor material include silicon and germanium. As another example, a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenide, an oxide semiconductor, or a nitride semiconductor can also be used.

[0209] Note that the transistors MO1 to MO4 are preferably transistors (OS transistors) that use an oxide semiconductor, which is a type of metal oxide, in a semiconductor layer in which a channel is formed. The band gap of an oxide semiconductor is 2 eV or more, and therefore the off-state current is significantly small. Therefore, the power consumption of the memory cell 10 can be reduced. Therefore, the power consumption of the memory device MDV including the memory cell 10 can be reduced.

[0210] Furthermore, the OS transistor operates stably even in a high-temperature environment and exhibits little fluctuation in characteristics. For example, the off-state current hardly increases even in a high-temperature environment. Specifically, the off-state current hardly increases even in an environment of room temperature or higher and 200° C. or lower. Furthermore, the on-state current is unlikely to decrease even in a high-temperature environment. Therefore, the memory cell 10 operates stably even in a high-temperature environment and exhibits high reliability.

[0211] Next, a specific example of a GL transistor that can be applied to the transistors MO1 to MO4 in Fig. 9 will be described. The transistor MO shown in Fig. 10A and Fig. 10B is an example of a GL transistor that can be applied to the transistors MO1 to MO4 in Fig. 9. Unlike the transistors MO2 and MO3 shown in Fig. 9, the transistor MO has a structure in which two or more transistors do not share the same semiconductor layer. Furthermore, unlike the transistors MO1 and MO4 shown in Fig. 9, the transistor MO does not have a conductive layer that functions as a wiring VGE above the side surface of the island-shaped semiconductor layer.

[0212] In particular, FIG. 10A shows a schematic cross-sectional view of the transistor MO in the channel length direction, and FIG. 10B shows a schematic cross-sectional view of the transistor MO in the channel width direction.

[0213] 10A and 10B , for example, the transistor MO includes a semiconductor layer 531a, a semiconductor layer 531b, a conductive layer 505, a conductive layer 542a, a conductive layer 542b, an insulating layer 580, a conductive layer 560, an insulating layer 514, an insulating layer 516, an insulating layer 520, an insulating layer 522, an insulating layer 524, an insulating layer 550, an insulating layer 554, an insulating layer 574, an insulating layer 580, and an insulating layer 581. Note that the transistor MO may not include all of the above-described components. For example, the conductive layer 505 functions as a backgate electrode of the transistor MO, but the transistor MO may not include the conductive layer 505.

[0214] Materials that can be used for the conductive layer, insulating layer, and semiconductor layer will be described later.

[0215] The conductive layer 505 (conductive layer 505a and conductive layer 505b) and the insulating layer 516 are disposed above a substrate (not shown). In particular, the conductive layer 505 is preferably provided so as to be embedded in the insulating layer 516. Specifically, the conductive layer 505a is preferably provided in contact with the bottom surface and sidewall of an opening provided in the insulating layer 516. The conductive layer 505b is preferably provided so as to be embedded in a recess formed in the conductive layer 505a. Note that in the transistor MO shown in FIGS. 10A and 10B , the height of the top surface of the conductive layer 505b is approximately the same as the height of the top surface of the conductive layer 505a and the height of the top surface of the insulating layer 516.

[0216] The semiconductor layer 531 and the conductive layer 560 are disposed in a region overlapping with the conductive layer 505. The semiconductor layer 531b is disposed on the semiconductor layer 531a. The conductive layers 542a and 542b are disposed on the semiconductor layer 531b and spaced apart from each other. The insulating layer 580 is disposed on the conductive layers 542a and 542b. In particular, an opening is formed in the insulating layer 580 in a region between the conductive layers 542a and 542b. The conductive layer 560 is disposed in the opening. The insulating layer 550 is disposed between the semiconductor layer 531b, the conductive layers 542a and 542b, and the insulating layer 580 and the conductive layer 560. Here, as shown in FIGS. 10A and 10B , it is preferable that the top surface of the conductive layer 560 be substantially flush with the top surfaces of the insulating layers 550 and 580. Note that hereinafter, the conductive layers 505a and 505b may be collectively referred to as conductive layers 505. The semiconductor layers 531a and 531b may be collectively referred to as semiconductor layers 531. The conductive layers 542a and 542b may be collectively referred to as conductive layers 542.

[0217] 10A , a region 543a may be formed as a low-resistance region at the interface between the semiconductor layer 531b and the conductive layer 542a and in its vicinity. Similarly, a region 543b may be formed as a low-resistance region at the interface between the semiconductor layer 531b and the conductive layer 542b and in its vicinity. In this case, the region 543a functions as one of a source region and a drain region, and the region 543b functions as the other of the source region and the drain region. A channel formation region is formed in a region sandwiched between the regions 543a and 543b.

[0218] By providing the conductive layer 542a (conductive layer 542b) so as to be in contact with the semiconductor layer 531, the oxygen concentration in the region 543a (region 543b) may be reduced. Furthermore, a metal compound layer containing a metal contained in the conductive layer 542a (conductive layer 542b) and a component of the semiconductor layer 531 may be formed in the region 543a (region 543b). In such a case, the carrier concentration in the region 543a (region 543b) increases, and the region 543a (region 543b) becomes a low-resistance region.

[0219] 10A and 10B , the side surfaces of the conductive layers 542a and 542b facing the conductive layer 560 have a substantially perpendicular shape. Note that the transistor MO shown in FIGS. 10A and 10B is not limited thereto, and the angle formed between the side surface and the bottom surface of the conductive layers 542a and 542b may be 10° to 80°, preferably 30° to 60°. Furthermore, the opposing side surfaces of the conductive layers 542a and 542b may have a plurality of surfaces.

[0220] Note that the transistor MO has a two-layer structure in which the semiconductor layer 531a and the semiconductor layer 531b are stacked in the region where a channel is formed (hereinafter also referred to as the channel formation region) and in the vicinity thereof, but the present invention is not limited to this. For example, the semiconductor layer 531b may have a single-layer structure or a stacked structure of three or more layers. Furthermore, each of the semiconductor layer 531a and the semiconductor layer 531b may have a stacked structure of two or more layers.

[0221] Here, the conductive layer 560 functions as a first gate electrode (sometimes referred to as a top gate electrode or a front gate electrode) of the transistor, and the conductive layers 542a and 542b function as a source electrode and a drain electrode, respectively. As described above, the conductive layer 560 is formed so as to be embedded in the opening of the insulating layer 580 and in a region sandwiched between the conductive layers 542a and 542b. Here, the conductive layers 560, 542a, and 542b are formed in a self-aligned manner with respect to the opening of the insulating layer 580. That is, in the transistor MO, the first gate electrode can be disposed between the source electrode and the drain electrode in a self-aligned manner. Therefore, the conductive layer 560 can be formed without providing a margin for alignment, thereby reducing the area occupied by the transistor MO. This enables a high-definition display device. Furthermore, the display device can have a narrow frame.

[0222] The conductive layer 505 may function as a second gate electrode (also referred to as a bottom gate electrode or a back gate electrode). In this case, the potential applied to the conductive layer 505 may be changed independently of the potential applied to the conductive layer 560, thereby reducing the threshold voltage V ｔｈ In particular, by applying a negative potential to the conductive layer 505, the V ｔｈ Therefore, when a negative potential is applied to the conductive layer 505, the drain current when the potential applied to the conductive layer 560 is 0 V can be made smaller than when no negative potential is applied.

[0223] The conductive layer 505 is preferably provided to be larger than the channel formation region of the semiconductor layer 531. In particular, as shown in Fig. 10B, the conductive layer 505 preferably extends as a wiring also in a region outside the end portion intersecting with the channel width direction of the semiconductor layer 531. That is, outside the side surface of the semiconductor layer 531 in the channel width direction, the conductive layer 505 and the conductive layer 560 preferably overlap with each other with an insulating layer interposed therebetween.

[0224] 10A, the conductive layer 560 preferably includes a conductive layer 560a provided inside the insulating layer 550 and a conductive layer 560b provided so as to be embedded inside the conductive layer 560a. Although the conductive layer 560 is shown as having a two-layer stacked structure in FIGS. 10A and 10B, the present invention is not limited to this. For example, the conductive layer 560 may have a single-layer structure or a stacked structure of three or more layers.

[0225] 10A and 10B , the transistor MO preferably includes an insulating layer 512 disposed on a substrate (not shown), an insulating layer 514 disposed on the insulating layer 512, an insulating layer 516 disposed on the insulating layer 514, a conductive layer 505 disposed so as to be embedded in the insulating layer 516, an insulating layer 520 disposed on the insulating layer 516 and the conductive layer 505, an insulating layer 522 disposed on the insulating layer 520, and an insulating layer 524 disposed on the insulating layer 522. A semiconductor layer 531 a is preferably disposed on the insulating layer 524.

[0226] 10A and 10B, an insulating layer 554 is preferably disposed between the insulating layer 522, the insulating layer 524, the semiconductor layer 531a, the semiconductor layer 531b, the conductive layer 542a, the conductive layer 542b, and the insulating layer 580. Here, the insulating layer 554 is preferably in contact with the side surface of the insulating layer 550, the top and side surfaces of the conductive layer 542a, the top and side surfaces of the conductive layer 542b, the side surfaces and top surfaces of the semiconductor layer 531a, the semiconductor layer 531b, and the insulating layer 524, and the top surface of the insulating layer 522, as shown in FIG.

[0227] An insulating layer 574 and an insulating layer 581 functioning as interlayer films are preferably provided over the transistor MO. Here, the insulating layer 574 is preferably provided in contact with top surfaces of the conductive layer 560, the insulating layer 550, and the insulating layer 580. In this case, the top surface of the insulating layer 580 is preferably planarized.

[0228] It is preferable to provide a conductive layer 540 (conductive layer 540a and conductive layer 540b) that is connected to the transistor MO and functions as a plug. Therefore, the conductive layer 540 is provided in contact with the inner walls of the openings of the insulating layer 554, the insulating layer 580, the insulating layer 574, and the insulating layer 581. In particular, a first conductive layer of the conductive layer 540 may be provided in contact with the inner walls, and a second conductive layer of the conductive layer 540 may be provided on a side surface of the first conductive layer. Here, the height of the top surface of the conductive layer 540 and the height of the top surface of the insulating layer 581 can be made approximately the same.

[0229] Specifically, for example, a first conductive layer of the conductive layer 540a is provided in contact with the inner wall of one of the two openings of the insulating layer 581, the insulating layer 574, the insulating layer 580, and the insulating layer 554, and a second conductive layer of the conductive layer 540a is formed in contact with the side surface thereof. Note that a conductive layer 542a is located in part of the bottom of the opening, and the conductive layer 540a is in contact with the conductive layer 542a. Similarly, for example, a first conductive layer of the conductive layer 540b is provided in contact with the inner wall of the other of the two openings of the insulating layer 581, the insulating layer 574, the insulating layer 580, and the insulating layer 554, and a second conductive layer of the conductive layer 540b is formed in contact with the side surface thereof. Note that the conductive layer 542b is located in part of the bottom of the opening, and the conductive layer 540b is in contact with the conductive layer 542b.

[0230] Note that although the transistor MO has a structure in which the first conductive layer of the conductive layer 540 and the second conductive layer of the conductive layer 540 are stacked, the present invention is not limited to this. For example, the conductive layer 540 may have a single layer structure or a stacked structure of three or more layers. When the structure has a stacked structure, the structures may be distinguished by assigning ordinal numbers to the order of formation.

[0231] 10B , in a region of the semiconductor layer 531b that does not overlap with the conductive layer 542, in other words, in the channel formation region of the semiconductor layer 531, the side surface of the semiconductor layer 531 is arranged to be covered with the conductive layer 560. This makes it easier for the electric field of the conductive layer 560, which functions as the first gate electrode, to act on the side surface of the semiconductor layer 531, and as a result, the channel formation region of the semiconductor layer 531 can be electrically surrounded by the electric field of the conductive layer 560. This increases the on-state current of the transistor MO, and improves its frequency characteristics.

[0232] <<Constituent Materials of Transistors>> Next, the constituent materials of the transistors MO1 to MO4 will be described.

[0233] [Metal Oxide (Oxide Semiconductor)] The transistors MO1 to MO4 preferably include a metal oxide that functions as an oxide semiconductor, including a channel formation region. For example, the metal oxide that forms the channel formation region preferably has a band gap of 2 eV or more, preferably 2.5 eV or more, and more preferably 3.0 eV or more. Specifically, for example, in the case of the transistor MO in FIGS. 10A and 10B, the semiconductor layer 531 preferably includes a metal oxide that functions as an oxide semiconductor.

[0234] Note that metal oxide structures are divided into single-crystal structures and other structures (non-single-crystal structures). Examples of non-single-crystal structures include a c-axis aligned crystalline (CAAC) structure, a polycrystalline (polycrystalline) structure, a nanocrystalline (nc) structure, a pseudo-amorphous (a-like) structure, and an amorphous structure. The structure of the metal oxide according to one embodiment of the present invention is not particularly limited, and any of the above structures may be used. However, the use of a crystalline metal oxide, such as a CAAC structure or an nc structure, is preferable because it enables a highly reliable semiconductor device to be obtained.

[0235] As described in the above embodiment, the metal oxide preferably contains at least indium or zinc. In particular, it is preferable that the metal oxide contains indium and zinc. Furthermore, it is preferable that the metal oxide further contains element M. As element M, one or more elements selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony can be used. In particular, it is preferable that element M is one or more elements selected from aluminum, gallium, yttrium, and tin.

[0236] Specifically, for example, the metal oxide may be In-Ga-Zn oxide (indium-gallium-zinc oxide), Ga-Zn oxide, gallium oxide, or indium oxide.

[0237] The metal oxide may have an atomic ratio of In:Ga:Zn=1:3:4, 1:3:2, 1:1:0.5, 1:1:1, 4:2:3, or 3:1:2. Alternatively, a metal oxide having an atomic ratio of In:Zn=4:1 may be used.

[0238] The metal oxide can be preferably formed by sputtering or ALD. When the metal oxide is formed by sputtering, a film with high crystallinity or high film density can be formed. Furthermore, when the metal oxide is formed by ALD, atoms can be deposited layer by layer, which has the advantages of enabling film formation with fewer defects such as pinholes, film formation with excellent coverage, and film formation at low temperatures. After the metal oxide is formed, it is preferable to perform an impurity removal treatment to remove impurities (typically, impurities such as water, hydrogen, carbon, and nitrogen) from the metal oxide film. Examples of impurity removal treatments include plasma treatment, microwave treatment, microwave plasma treatment, and heat treatment.

[0239] [Conductive Layer] For the conductive layers included in the transistors MO1 to MO4, for example, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy containing two or more selected from the above metal elements, or an alloy combining two or more selected from the above metal elements, is preferably used. For the conductive layers, for example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel is preferably used. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferable because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen. In addition, the conductive layer may be made of a semiconductor with high electrical conductivity, typified by polycrystalline silicon containing an impurity element (e.g., phosphorus), or a silicide (e.g., nickel silicide).

[0240] A plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may also be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may also be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0241] The conductive layer functioning as the second gate electrode, for example, the conductive layer 505 shown in FIGS. 10A and 10B, contains hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (for example, N ２ O, NO or NO ２It is preferable to use a conductive material that has the function of suppressing the diffusion of impurities such as copper atoms and copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (e.g., oxygen atoms and / or oxygen molecules). In particular, examples of conductive materials that have the function of suppressing the diffusion of oxygen include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide.

[0242] In addition to the above, it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component.

[0243] 10A and 10B, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy containing two or more of the above metal elements, or an alloy combining two or more of the above metal elements. For example, the conductive layer preferably includes tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when they absorb oxygen.

[0244] The conductive layer functioning as the first gate electrode, for example, the conductive layer 560 shown in FIGS. 10A and 10B, is preferably a conductive layer having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Alternatively, it is preferably a conductive material having a function of suppressing the diffusion of oxygen. Examples of conductive materials having a function of suppressing the diffusion of oxygen include tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, and ruthenium oxide. Furthermore, by providing a conductive material containing oxygen as the conductive layer, oxygen released from the conductive material is more easily supplied to the channel formation region.

[0245] The conductive layer functioning as the first gate electrode is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Since the conductive layer also functions as a wiring, it is preferable to use a conductive layer with high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. The conductive layer may have a stacked structure, for example, a stacked structure of titanium or titanium nitride and the above-mentioned conductive material.

[0246] The conductive layer may be formed using, for example, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide doped with silicon. The conductive layer may be formed using, for example, indium gallium zinc oxide containing nitrogen. The use of such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an outer insulating layer or the like may be captured.

[0247] [Insulating Layer] Examples of insulating layers included in the transistors MO1 to MO4 include oxide, nitride, oxynitride, nitride oxide, metal oxide, metal oxynitride, and metal nitride oxide, all of which have insulating properties.

[0248] The insulating layer that can be provided in the transistors preferably functions as a barrier insulating film that prevents impurities such as water and hydrogen from entering the semiconductor layers of the transistors MO1 to MO4 from the substrate side. Therefore, the insulating layer is preferably made of an insulating material that has a function of preventing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms (i.e., through which the impurities are less likely to permeate). Alternatively, the insulating layer is preferably made of an insulating material that has a function of preventing the diffusion of oxygen (i.e., through which the oxygen is less likely to permeate).

[0249] Examples of insulating layers that suppress the permeation of impurities such as water and hydrogen and oxygen include, for example, single-layer or multi-layer insulating layers containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, examples of insulating layers that suppress the permeation of impurities such as water and hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Examples of insulating layers that suppress the permeation of impurities such as water and hydrogen and oxygen include oxides containing aluminum and hafnium (hafnium aluminate). Examples of insulating layers that suppress the permeation of impurities such as water and hydrogen and oxygen include nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0250] The second gate insulating film in contact with the metal oxide contained in the channel formation region, for example, the insulating layer 522 and the insulating layer 524 shown in FIGS. 10A and 10B, preferably has oxygen released by heating. In this specification and the like, oxygen released by heating is sometimes referred to as excess oxygen. For example, silicon oxide or silicon oxynitride may be used as the second gate insulating film as appropriate. By providing an insulating layer containing oxygen in contact with the metal oxide, oxygen vacancies in the metal oxide can be reduced, and the reliability of the transistor can be improved.

[0251] Specifically, it is preferable to use an oxide material from which part of oxygen is released by heating as the insulating layer. The oxide material from which oxygen is released by heating is an oxide material from which the amount of released oxygen converted into oxygen atoms by thermal desorption spectrometry (TDS) is 1.0×10 １８ atoms / cm ３ or more, preferably 1.0 × 10 １９ atoms / cm ３ More preferably, 2.0×10 １９ atoms / cm ３ or more, or 3.0 x 10 ２０ atoms / cm ３ The surface temperature of the film during the TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0252] Furthermore, the insulating layer included in the transistor may preferably contain an oxide of one or both of aluminum and hafnium, which are insulating materials. Examples of insulating layers containing an oxide of one or both of aluminum and hafnium include aluminum oxide and hafnium oxide. Another example is an oxide containing aluminum and hafnium (hafnium aluminate). When such a material is used to form an insulating layer around a transistor, the insulating layer can function as a layer that suppresses oxygen release and the intrusion of impurities such as hydrogen from the periphery of the transistor into the metal oxide.

[0253] Furthermore, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to an insulating layer included in a transistor. Alternatively, these insulating layers may be nitrided. Furthermore, silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulating layer.

[0254] The insulating layer included in the transistor may be made of, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ３ ) or (Ba,Sr)TiO ３ An insulating layer containing a so-called high-k material such as (BST) may be used as a single layer or a laminate.

[0255] 10A and 10B, an insulating layer serving as a first gate insulating film, for example, the insulating layer 550 shown in FIG. 10A and FIG. 10B, is preferably disposed in contact with the upper surface of the metal oxide. For the insulating layer, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having vacancies can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

[0256] <Second Cross-Sectional Configuration Example of Storage Device> Next, a cross-sectional configuration example of the storage device MDV, which is different from that shown in FIG. 9, will be described.

[0257] 11 , the transistors MO2 and MO3 are provided to share a single fin-shaped semiconductor layer SC1, and the transistors MO1 and MO4 are provided to share a single fin-shaped semiconductor layer SC2. Specifically, the gate insulating film and gate electrode of the transistor MO2 are formed to overlap a portion of another region of the single fin-shaped semiconductor layer SC1, and the gate insulating film and gate electrode of the transistor MO3 are formed to overlap a portion of another region of the single fin-shaped semiconductor layer SC1. Similarly, the gate insulating film and gate electrode of the transistor MO1 are formed to overlap a portion of a region of the single fin-shaped semiconductor layer SC2, and the gate insulating film and gate electrode of the transistor MO4 are formed to overlap a portion of another region of the single fin-shaped semiconductor layer SC2.

[0258] A conductive layer functioning as a wiring SL is connected to one of the source electrode or drain electrode of the transistor MO2. A conductive layer functioning as a wiring RBL is connected to one of the source electrode or drain electrode of the transistor MO3. The wirings RWL and RBL extend in the channel width direction of the transistors MO2 and MO3, for example. Note that the conductive layer functioning as the wiring SL is formed so as not to overlap with the fin-shaped semiconductor layer SC1, for example, and the conductive layer functioning as the wiring RBL is formed so as to overlap with the fin-shaped semiconductor layer SC1, for example.

[0259] The transistor MO2 is also provided with a conductive layer MEG that functions as a gate electrode. In particular, the conductive layer MEG is provided so as to overlap the fin-shaped semiconductor layer SC1. Similarly, the transistor MO3 is also provided with a conductive layer that functions as a gate electrode. In particular, the conductive layer can be part of the wiring RWL. In addition, the conductive layer is provided so as to overlap the fin-shaped semiconductor layer SC1.

[0260] An insulating layer functioning as an interlayer film is formed between the transistors MO2 and MO3 and the transistors MO1 and MO4. An opening is provided in the insulating layer in a region overlapping with the conductive layer MEG of the transistor MO2, and a conductive layer is embedded in the opening. The conductive layer is connected to one of the source electrode and the drain electrode of the transistor MO1. The conductive layer MEG can be part of the node N1 shown in FIG. 1 and described in Embodiment 1.

[0261] A partial region of the conductive layer that functions as the other of the source electrode or drain electrode of the transistor MO2 functions as one of a pair of electrodes of the capacitor CD1. A region of an insulating layer that functions as the dielectric of the capacitor CD1 is formed so as to overlap with a partial region of the conductive layer that functions as the other of the source electrode or drain electrode of the transistor MO2. A conductive layer that functions as the other of the pair of electrodes of the capacitor CD1 is formed in the insulating layer region. The conductive layer that functions as the other of the pair of electrodes of the capacitor CD1 is formed so as to be connected to one of the source electrode or drain electrode of the transistor MO1 located in the upper layer.

[0262] As described above, the transistors MO1 and MO4 are located above the transistors MO2 and MO3. The transistors MO1 and MO3 also have partial regions of the fin-shaped semiconductor layer SC2. A partial region of the conductive layer that functions as the other of the source and drain electrodes of the transistor MO1 and one of the source and drain electrodes of the transistor MO4 functions as one of a pair of electrodes of the capacitor CD2. A region of the insulating layer that functions as the dielectric of the capacitor CD2 is formed so as to overlap with a partial region of the conductive layer that functions as the other of the source and drain electrodes of the transistor MO1 and one of the source and drain electrodes of the transistor MO4. A conductive layer that functions as the other of the pair of electrodes of the capacitor CD2 is also formed in the insulating layer region.

[0263] The gate insulating film and gate electrode of transistor MO1 are formed so as to overlap a partial region of the fin-shaped semiconductor layer SC2. In particular, the conductive layer that is the gate electrode of transistor MO1 extends in the channel width direction. This conductive layer also functions as a wiring WWL. In addition, the gate insulating film and gate electrode of transistor MO4 are formed so as to overlap another partial region of the fin-shaped semiconductor layer SC2. In particular, the conductive layer that is the gate electrode of transistor MO4 extends in the channel width direction. This conductive layer also functions as a wiring WWL.

[0264] 9, a conductive layer functioning as a back gate can be provided below the insulating layer STJ1 in the transistors MO2 and MO3. Similarly, a conductive layer functioning as a back gate can be provided below the insulating layer STJ2 in the transistors MO1 and MO4. By providing a back gate in each transistor and changing the potential of the back gate, the threshold voltage of the transistor can be changed.

[0265] For example, by using a transistor having a back gate as the transistor MO1, the influence of an external electric field can be reduced and the transistor can be stably maintained in an off state. Therefore, data written to the first terminal of the capacitive element CD1 can be stably held. By providing a back gate, the operation of the memory cell 10 can be stabilized, and the reliability of the memory cell array MCA including the memory cell 10 can be improved.

[0266] The semiconductor layers in which the channels of the transistors MO1 to MO4 are formed can be formed using a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or a combination of two or more thereof. Examples of the semiconductor material include silicon and germanium. Other examples include compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, oxide semiconductors, and nitride semiconductors.

[0267] Note that the transistors MO1 to MO4 are preferably transistors (OS transistors) that use an oxide semiconductor, which is a type of metal oxide, in a semiconductor layer in which a channel is formed. The band gap of an oxide semiconductor is 2 eV or more, and therefore the off-state current is significantly small. Therefore, the power consumption of the memory cell 10 can be reduced. Therefore, the power consumption of the memory device MDV including the memory cell 10 can be reduced.

[0268] A memory cell including an OS transistor can be called an “OS memory.” A memory device MDV including the memory cell can also be called an “OS memory.”

[0269] Furthermore, the OS transistor operates stably even in a high-temperature environment, and its characteristics fluctuate little. For example, the off-state current hardly increases even in a high-temperature environment. Specifically, the off-state current hardly increases even in an environment of room temperature or higher and 200° C. or lower. Furthermore, the on-state current hardly decreases even in a high-temperature environment. Therefore, the OS memory operates stably even in a high-temperature environment, and high reliability is achieved.

[0270] <<Configuration Example of Transistor>> Next, the structures of the transistors MO1, MO2, MO3, and MO4 used in the schematic cross-sectional view of FIG. 11 will be described.

[0271] 12A to 12D are schematic plan views and cross-sectional views, respectively, illustrating the structure of a transistor 500mf that includes two fin-shaped, circumferentially shaped semiconductor layers, similar to the above-described transistors. Note that, unlike the above-described transistors, the transistor 500mf in FIGS. 12A to 12D has a structure in which two or more transistors do not share the same semiconductor layer.

[0272] Fig. 12A is a schematic plan view of a transistor 500mf applicable to each of transistors MO1, MO2, MO3, and MO4 of the memory device MDV of Fig. 11, and Figs. 12B to 12D are schematic cross-sectional views of the transistor 500mf. In particular, Fig. 12B is a schematic cross-sectional view of the portion indicated by dashed-dotted line A1-A2 in Fig. 12A, and is also a schematic cross-sectional view of the transistor 500mf in the channel width direction. Fig. 12C is a schematic cross-sectional view of the portion indicated by dashed-dotted line A3-A4 in Fig. 12A, and is also a schematic cross-sectional view of the transistor 500mf in the channel width direction. Fig. 12D is a schematic cross-sectional view of the portion indicated by dashed-dotted line A5-A6 in Fig. 12A, and is also a schematic cross-sectional view of the transistor 500mf in the channel length direction. Here, the dashed-dotted line A5-A6 is perpendicular to the dashed-dotted line A1-A2 and the dashed-dotted line A3-A4, and the dashed-dotted line A1-A2 and the dashed-dotted line A3-A4 are parallel to each other. Note that in the schematic plan view of FIG. 12A, some elements are omitted for clarity, and some elements are shown transparently. FIG. 13A shows an enlarged view of the vicinity of the conductive layer 560 in FIG. 12D. FIG. 13B shows an enlarged view of the vicinity of the semiconductor layer 530 in FIG. 12B. FIG. 13C shows an enlarged view of the vicinity of the semiconductor layer 530 in FIG. 12C.

[0273] The transistor 500mf includes an insulating layer 516 over the insulating layer 514, an insulating layer 521 over the insulating layer 516, an insulating layer 522 over the insulating layer 521, a semiconductor layer 530 over the insulating layer 522, conductive layers 542a and 542b over the semiconductor layer 530 and the insulating layer 522, an insulating layer 550 over the semiconductor layer 530, and a conductive layer 560 (conductive layer 560a and conductive layer 560b) over the insulating layer 550. Note that hereinafter, the conductive layer 542a and the conductive layer 542b may be collectively referred to as the conductive layer 542.

[0274] An insulating layer 575 is provided over the conductive layer 542, and an insulating layer 580 is provided over the insulating layer 575. The insulating layer 550 and the conductive layer 560 are disposed inside openings provided in the insulating layer 580 and the insulating layer 575. The openings reach the semiconductor layer 530, and the insulating layer 550 is in contact with the semiconductor layer 530 within the openings. An insulating layer 582 is provided over the insulating layer 580 and the conductive layer 560. An insulating layer 583 is provided over the insulating layer 582.

[0275] An insulating layer 541a is provided in contact with the inner wall of an opening of the insulating layer 580 or the like, and a conductive layer 540a is provided in contact with the side surface of the insulating layer 541a. The bottom surface of the conductive layer 540a is in contact with the top surface of the conductive layer 542a. An insulating layer 541b is provided in contact with the inner wall of an opening of the insulating layer 580 or the like, and a conductive layer 540b is provided in contact with the side surface of the insulating layer 541b. The bottom surface of the conductive layer 540b is in contact with the top surface of the conductive layer 542b. Note that hereinafter, the conductive layers 540a and 540b may be collectively referred to as the conductive layer 540. The insulating layers 541a and 541b may be collectively referred to as the insulating layer 541.

[0276] For the insulating layers 541 a and 541 b, an insulating film having a function of suppressing oxygen permeation is preferably used to prevent a decrease in conductivity due to oxidation of the conductive layers 542 a and 542 b. For example, a silicon nitride film is preferably formed by a PEALD method.

[0277] The insulating layer 516 functions as a planarizing film that flattens steps caused by plugs or the like, similar to the insulating layer 320. Therefore, the insulating layer 516 can be made of a material that functions as a planarizing film, similar to the insulating layer 320. Furthermore, by using a material with a low dielectric constant for the insulating layer 516, the parasitic capacitance between wirings can be reduced.

[0278] For this reason, the insulating layer 516 can be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride. Alternatively, the insulating layer 516 can be made of, for example, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, or silicon oxide having vacancies. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, or silicon oxide having vacancies are preferable because they can easily form a region containing oxygen that is released by heating. Alternatively, the insulating layer 516 can be made of, for example, a resin. The material used for the insulating layer 516 may be an appropriate combination of the above-mentioned insulating materials.

[0279] For the insulating layers 521 and 522, it is preferable to use an insulating layer having a barrier property against one or more selected from hydrogen, oxygen, and water, similar to the insulating layers 324 and 350. Therefore, for the insulating layers 521 and 522, it is preferable to use an insulating layer having a barrier property against one or more selected from hydrogen, oxygen, and water, similar to the insulating layers 324 and 350.

[0280] The semiconductor layer 530 has a region that functions as a channel formation region of the transistor 500mf. The conductive layer 560 has a region that functions as a first gate electrode (upper gate electrode) of the transistor 500mf. The insulating layer 550 has a region that functions as a first gate insulating film of the transistor 500mf.

[0281] In particular, a metal oxide that functions as an oxide semiconductor can be used for the semiconductor layer 530. In this case, the transistor 500mf is an OS transistor. Note that the semiconductor layer 530 can be any of the above metal oxides.

[0282] In particular, an oxide semiconductor that is an axial growth CAAC (AG CAAC) can be used as a metal oxide for the semiconductor layer 530. The AG CAAC refers to an oxide semiconductor having a CAAC structure, which is produced by solid-phase growth of a metal oxide included in an oxide semiconductor layer including a first layer and a second layer having higher crystallinity than the first layer, using the second layer as a nucleus or seed.

[0283] For example, the first layer is preferably formed by atomic layer deposition (ALD) or chemical vapor deposition (CVD). Examples of CVD include plasma enhanced CVD (PECVD), thermal CVD, photo-assisted CVD, and metal organic CVD (MOCVD). The first layer may also be formed by a wet process. Furthermore, molecular beam epitaxy (MBE), which is a film formation method for growing a thin film having a crystal structure that reflects the crystal system of the substrate, may also be used. These film formation methods can cause less damage to the surface to be formed than sputtering.

[0284] Next, the second layer is preferably formed by sputtering or pulsed laser deposition (PLD). By forming the second layer after the first layer, in particular, it is possible to prevent a mixed layer from being formed at the interface between the first and second layers. Furthermore, it is possible to prevent impurities contained in the surface on which the second layer is formed from being mixed into the second layer. These factors further enhance the crystallinity of the second layer.

[0285] In addition, methods for solid-phase growth of the metal oxide contained in the first layer using the second layer as a nucleus or seed include, for example, heat treatment, plasma treatment, microwave (typically 2.45 GHz) treatment, microwave plasma treatment, and light (e.g., ultraviolet light) irradiation treatment. Note that a plurality of these treatments may be performed simultaneously or sequentially. For example, heat treatment and microwave plasma treatment may be performed simultaneously. Alternatively, microwave plasma treatment may be performed after heat treatment.

[0286] In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz to 300 GHz. Microwave plasma treatment refers to treatment using a device with a power source that generates high-density plasma using microwaves. Microwave plasma treatment can also be called microwave-excited high-density plasma treatment.

[0287] Furthermore, it is more preferable to perform the treatment for increasing the crystallinity of the oxide semiconductor layer multiple times during the formation of the oxide semiconductor layer. For example, when the oxide semiconductor layer is formed by an ALD method, it is preferable to perform microwave plasma treatment every time an atomic layer is formed. Alternatively, it is preferable to perform the treatment for increasing the crystallinity every time an oxide semiconductor layer having a thickness within a predetermined range is formed, in order to increase productivity. Specifically, it is preferable to form a first oxide semiconductor layer having a thickness of 1 nm to 10 nm, perform the first microwave plasma treatment, and then form a second oxide semiconductor layer having a thickness of 1 nm to 10 nm, and perform the second microwave plasma treatment. Note that the method for forming the first oxide semiconductor layer and the second oxide semiconductor layer is not particularly limited, and ALD or sputtering may be used, respectively. In particular, forming the first oxide semiconductor layer by the ALD method is preferable because it can prevent elements of the layers constituting the formation surface from being mixed (also referred to as mixing) into the first oxide semiconductor layer and the second oxide semiconductor layer. This is particularly suitable when the element contained in the layer constituting the formation surface inhibits crystallization of the oxide semiconductor (for example, when silicon, carbon, or the like is contained). The first oxide semiconductor layer and the second oxide semiconductor layer may have different compositions. Although a stacked structure of the first oxide semiconductor layer and the second oxide semiconductor layer is illustrated here, the present invention is not limited to this. The same treatment can be applied to a single oxide semiconductor layer or a stacked structure of three or more layers.

[0288] Treatment for increasing the crystallinity of the oxide semiconductor layer may be performed after the oxide semiconductor layer is formed. Specifically, the treatment may be performed directly on the formed oxide semiconductor layer, or may be performed through another film such as an insulating film formed on the oxide semiconductor layer. For example, microwave plasma treatment may be performed after the oxide semiconductor layer is formed, or an insulating film (e.g., a silicon nitride film, a silicon oxide film, or an aluminum oxide film) may be formed after the oxide semiconductor layer is formed, and then heat treatment or microwave plasma treatment may be performed on the oxide semiconductor layer through the insulating film.

[0289] Note that the treatment for increasing the crystallinity of the oxide semiconductor layer can also serve as treatment for removing impurities contained in the oxide semiconductor layer. For example, carbon, hydrogen, nitrogen, and the like contained in the oxide semiconductor layer can be preferably removed. Alternatively, by performing the treatment for increasing the crystallinity of the oxide semiconductor layer in an oxygen gas atmosphere, oxygen vacancies in the oxide semiconductor layer can be reduced.

[0290] When the treatment for increasing the crystallinity of the oxide semiconductor layer is performed, the temperature of the substrate is preferably room temperature or higher, 100° C. or higher and 600° C. or lower, or 300° C. or higher and 450° C. The temperature of the heat treatment is preferably 100° C. or higher and 700° C. or lower, or 300° C. or higher and 450° C.

[0291] In addition to the above-described method for forming an oxide semiconductor layer, treatment for increasing the crystallinity of the oxide semiconductor layer can be performed, whereby a highly reliable transistor can be provided.

[0292] 13B, the semiconductor layer 530 can have a structure including a semiconductor layer 530a, a semiconductor layer 530b in contact with the semiconductor layer 530a, and a semiconductor layer 530c in contact with the semiconductor layer 530b. In addition, the side surfaces of the semiconductor layer 530 (the semiconductor layers 530a to 530c) are preferably perpendicular or approximately perpendicular to the substrate surface.

[0293] As described above, in the cross section of the semiconductor layer 530 (semiconductor layers 530a to 530c) observed using a TEM image, it is confirmed that metal atoms are arranged in layers in a direction parallel to or substantially parallel to the formation surface. In other words, in the cross section of the semiconductor layer 530 (semiconductor layers 530a to 530c) observed using a TEM image, it is confirmed that metal atoms are arranged in layers in a direction perpendicular to or substantially perpendicular to the substrate surface. It can also be said that the c-axis of AG CAAC is substantially parallel to the normal direction to the side surface of the semiconductor layer 530.

[0294] In this way, by using the semiconductor layer 530 made of AG CAAC in the channel formation region of the transistor 500mf, a transistor with large on-state current, high field-effect mobility, a good S value, high frequency characteristics, and good reliability can be provided. Note that the S value is a subthreshold swing value, which indicates the amount of change in gate voltage in the subthreshold region required to change the drain current by one order of magnitude at a constant drain voltage. The smaller the S value, the steeper the slope of the drain current with respect to the gate voltage, resulting in better switching characteristics.

[0295] The semiconductor layers 530a to 530c can be formed, for example, by providing a pillar that functions as a sacrificial layer on the insulating layer 522, depositing a first semiconductor film that will become the semiconductor layer 530a, a second semiconductor film that will become the semiconductor layer 530b, and a third semiconductor film that will become the semiconductor layer 530c on the side surfaces of the pillar in this order, removing the first to third semiconductor films located on the top surfaces of the insulating layer 522 and the pillars, and then removing the pillars.

[0296] Furthermore, when the semiconductor layer 530 has a three-layer structure of semiconductor layers 530a to 530c as described above, the semiconductor layer 530 is formed in the order of semiconductor layer 530a, semiconductor layer 530b, and semiconductor layer 530c, with the region where the pillars were formed at the center. In other words, as shown in Fig. 12A, the semiconductor layer 530 has a structure that surrounds the region where the pillars were formed in plan view.

[0297] A channel formation region and a source region and a drain region sandwiching the channel formation region are formed in the semiconductor layer 530. At least a part of the channel formation region overlaps with the conductive layer 560. The source region overlaps with the conductive layer 542a, and the drain region overlaps with the conductive layer 542b. Note that the source region and the drain region can be interchanged.

[0298] The channel formation region has fewer oxygen vacancies or a lower impurity concentration than the source and drain regions, and is therefore a high-resistance region with a low carrier concentration. Therefore, the channel formation region can be said to be i-type (intrinsic) or substantially i-type.

[0299] The source and drain regions are low-resistance regions with high carrier concentrations due to a large number of oxygen vacancies or high concentrations of impurities such as hydrogen, nitrogen, and metal elements. That is, the source and drain regions are n-type regions (low-resistance regions) with a higher carrier concentration than the channel formation region.

[0300] The carrier concentration in the channel formation region is 1×10 １８ cm −３ Below, 1 x 10 １７ cm −３ Less than 1 x 10 １６ cm −３ Less than 1 x 10 １５ cm −３ Less than 1 x 10 １４ cm −３ Less than 1 x 10 １３ cm −３ Less than 1 x 10 １２ cm −３ Less than 1 x 10 １１ cm −３ Less than or 1 x 10 １０ cm −３ The lower limit of the carrier concentration in the channel formation region is not particularly limited, but is preferably less than 1×10 −９ cm −３ It can be said that:

[0301] Note that when the carrier concentration of the semiconductor layer 530 is reduced, the impurity concentration in the semiconductor layer 530 is reduced to reduce the density of defect states. In this specification and the like, a low impurity concentration and a low density of defect states are referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor (or metal oxide). Note that an oxide semiconductor (or metal oxide) with a low carrier concentration may be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor (or metal oxide).

[0302] In order to stabilize the electrical characteristics of the transistor 500mf, it is effective to reduce the impurity concentration in the channel formation region in the semiconductor layer 530. Furthermore, in order to reduce the impurity concentration in the semiconductor layer 530, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. Note that the impurities in the semiconductor layer 530 refer to, for example, elements other than the main components constituting the semiconductor layer 530. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0303] Furthermore, it may be difficult to clearly detect the boundaries between regions in the semiconductor layer 530. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region may vary continuously within each region, rather than varying stepwise from region to region. That is, the concentrations of metal elements and impurity elements such as hydrogen and nitrogen may decrease in regions closer to the channel formation region.

[0304] In a transistor using an oxide semiconductor for the semiconductor layer 530, impurities and oxygen vacancies are present in a region where a channel is formed in the oxide semiconductor, and the transistor's electrical characteristics are likely to fluctuate, which may result in poor reliability. Ｏ H) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor, the transistor is likely to be normally on. Therefore, in the channel formation region of the oxide semiconductor, impurities, oxygen vacancies, and V Ｏ It is preferable that H be reduced as much as possible. In other words, it is preferable that the carrier concentration of a channel formation region in the oxide semiconductor be reduced and that the channel formation region be i-type (intrinsic) or substantially i-type.

[0305] In response to this problem, an insulating layer containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen) is provided near the oxide semiconductor, and heat treatment is performed. This allows oxygen to be supplied from the insulating layer to the oxide semiconductor, thereby eliminating oxygen vacancies and V ＯH can be reduced. However, if an excessive amount of oxygen is supplied to the source region or drain region, the on-state current or field-effect mobility of the transistor 500 mf may decrease. Furthermore, variations in the amount of oxygen supplied to the source region or drain region within the substrate surface may cause variations in the characteristics of a semiconductor device including the transistor. Furthermore, if oxygen supplied from the insulating layer to the oxide semiconductor diffuses into a conductive layer such as a gate electrode, a source electrode, or a drain electrode, the conductive layer may be oxidized, resulting in a loss of conductivity, which may adversely affect the electrical characteristics and reliability of the transistor.

[0306] Therefore, in the oxide semiconductor, the channel formation region preferably has a reduced carrier concentration and is i-type or substantially i-type, and the source and drain regions preferably have a high carrier concentration and are n-type. Ｏ It is also preferable to prevent an excessive amount of oxygen from being supplied to the source and drain regions, and to reduce V Ｏ It is preferable to prevent the amount of H from being excessively reduced. Furthermore, it is preferable to have a structure that suppresses a decrease in the conductivity of the conductive layer 560, the conductive layer 542a, the conductive layer 542b, and the like. For example, it is preferable to have a structure that suppresses oxidation of the conductive layer 560, the conductive layer 542a, the conductive layer 542b, and the like. Note that hydrogen in the oxide semiconductor is converted into V Ｏ H can be formed, so V Ｏ To reduce the amount of H, it is necessary to reduce the hydrogen concentration.

[0307] 13B , the insulating layer 550 includes an insulating layer 550a, an insulating layer 550b, an insulating layer 550c, and an insulating layer 550d. The insulating layers 550a to 550d function as part of a first gate insulating film. The insulating layers 550a to 550d are provided in an opening formed in the insulating layer 580, similar to the conductive layer 560 described later. To miniaturize the transistor 500mf, the insulating layers 550a to 550d are preferably thin. The thicknesses of the insulating layers 550a to 550d are preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5.0 nm, more preferably 0.5 nm to 5.0 nm, still more preferably 1.0 nm to 5.0 nm, and even more preferably 1.0 nm to 3.0 nm. Note that it is only necessary that at least a part of each of the insulating layers 550a to 550d has a region with the above-described thickness.

[0308] The thickness of the silicon oxide film used as the insulating layer 550 is preferably 0.7 nm to 3 nm.

[0309] In order to thin the insulating layers 550a to 550d as described above, it is preferable to form the insulating layers 550a to 550d by an ALD method. Furthermore, it is preferable to form the insulating layers 550a to 550d in openings in the insulating layer 580 or the like by an ALD method. Examples of the ALD method include a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, and a PEALD method in which a plasma-excited reactant is used. The PEALD method may be preferable because it enables film formation at a lower temperature by using plasma.

[0310] The ALD method can deposit atoms layer by layer, and therefore has the following advantages: it is possible to form an extremely thin film, it is possible to form a film on a structure with a high aspect ratio, it is possible to form a film with few defects such as pinholes, it is possible to form a film with excellent coverage, it is possible to form a film at a low temperature, etc. Therefore, the insulating layer 550 can be formed with good coverage on the side surface of the opening formed in the insulating layer 580 and with the thin film thickness as described above.

[0311] Note that some precursors used in the ALD method contain carbon and the like. Therefore, films formed by the ALD method may contain more impurities such as carbon than films formed by other film formation methods. Note that the quantity of impurities can be determined using secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), or Auger electron spectroscopy (AES).

[0312] Although the insulating layer 550 has been described above as having a four-layer structure of insulating layers 550a to 550d, the present invention is not limited to this. The insulating layer 550 may have a structure including at least one of the insulating layers 550a to 550d. By forming the insulating layer 550 using one, two, or three of the insulating layers 550a to 550d, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0313] For example, the insulating layer 550 may have a three-layer structure. In this case, it is preferable that the insulating layer 550 has a laminated structure of an insulating layer 550a, an insulating layer 550b on the insulating layer 550a, and an insulating layer 550c on the insulating layer 550b. In other words, this is a structure obtained by removing the insulating layer 550d from the structure shown in FIG. 13A.

[0314] It is preferable to use the ALD process two or more times in forming the insulating layer 550. For example, the insulating layer 550 preferably has a stacked structure of a plurality of insulating films, and it is preferable that two or more of the plurality of insulating films are formed using the ALD process. By forming at least two or more insulating films using the ALD process, it is possible to improve the coverage and film thickness uniformity of the insulating layer 550. Furthermore, it is possible to increase productivity by successively forming two or more different films, for example, two or more insulating films, using the ALD process.

[0315] For example, the insulating layer 550a is preferably made of aluminum oxide, which has a high ability to capture or fix hydrogen. The insulating layer 550b is preferably made of silicon oxide, which has a high dielectric strength. The insulating layer 550c is preferably made of hafnium oxide, which has a high ability to capture or fix hydrogen. The insulating layer 550d is preferably made of silicon nitride, which has a high hydrogen barrier property.

[0316] 12D and other figures, the conductive layer 560 is shown as having a two-layer structure. Here, the conductive layer 560 preferably includes a conductive layer 560a and a conductive layer 560b disposed on the conductive layer 560a. For example, the conductive layer 560a is preferably disposed so as to surround the bottom and side surfaces of the conductive layer 560b. In this case, the conductive layer 560a is preferably made of a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion.

[0317] The conductive layer 560a is preferably made of a conductive material that has a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms, or a conductive material that has a function of suppressing diffusion of oxygen.

[0318] Furthermore, since the conductive layer 560a has a function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of the conductive layer 560b caused by oxygen contained in the insulating layer 580, etc. As a conductive material having a function of suppressing oxygen diffusion, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used.

[0319] The conductive layer 560b is preferably a conductive layer with high conductivity. For example, the conductive layer 560b can be formed using a conductive material containing tungsten, copper, or aluminum as a main component. The conductive layer 560b may have a layered structure, for example, a layered structure of titanium or titanium nitride and the above-mentioned conductive material.

[0320] The conductive layers 560a and 560b can each be made of the above-mentioned conductive materials. The conductive layers 560a and 560b are preferably made of a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy containing two or more of the above metal elements, or an alloy combining two or more of the above metal elements. The conductive layer 560a is preferably made of, for example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel. Tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen. Furthermore, the conductor may be a semiconductor with high electrical conductivity, typified by polycrystalline silicon containing an impurity element (e.g., phosphorus or arsenic), or a silicide (e.g., nickel silicide).

[0321] In the transistor 500mf, the conductive layer 560 is formed in a self-aligned manner to fill an opening formed in the insulating layer 580 or the like. Here, the side surfaces of the insulating layer 580 in the openings coincide or substantially coincide with the side surfaces of the conductive layers 542a and 542b. Therefore, the conductive layer 560 can be arranged to overlap the region between the conductive layers 542a and 542b without alignment.

[0322] The conductive layer 542a has a region functioning as one of the source electrode and drain electrode of the transistor 500mf. The conductive layer 540a functions as a plug connected to the conductive layer 542a. The conductive layer 542b has a region functioning as the other of the source electrode and drain electrode of the transistor 500mf. The conductive layer 540b functions as a plug connected to the conductive layer 542b.

[0323] For the conductive layers 542a and 542b, it is preferable to use, for example, a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion. Examples of such conductive materials include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layers 542a and 542b. When a conductive material containing metal and nitrogen is used for the conductive layers 542a and 542b, the conductive layers 542a and 542b become conductive layers containing at least metal and nitrogen. For example, a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion can be selected from the materials that can be used for the conductive layers 560a and 560b.

[0324] The conductive layers 540a and 540b are preferably made of a conductive material containing, for example, tungsten, copper, or aluminum as a main component. The conductive layer 540 may have a layered structure in which a first conductive layer is provided in contact with the side surface of the insulating layer 541 and a second conductive layer is provided further inside. In this case, the above-described conductive material may be used as the second conductive layer. The conductive layers 540a and 540b may also be made of materials that can be used for the conductive layers 560a and 560b. Here, the first conductive layer corresponds to the conductive layer 540a1 shown in FIG. 13A , and the second conductive layer corresponds to the conductive layer 540a2 shown in FIG. 13A .

[0325] Furthermore, when the conductive layer 540 has a stacked structure, a first conductive layer disposed near the insulating layer 583, the insulating layer 582, the insulating layer 580, and the insulating layer 575 is preferably made of a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like is preferably used. Furthermore, a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a stacked layer. With such a structure, impurities such as water and hydrogen contained in layers above the insulating layer 583 can be prevented from entering the semiconductor layer 530 through the conductive layer 540a and the conductive layer 540b.

[0326] For example, the insulating layer 575 is preferably a barrier insulating film against oxygen. Examples of the barrier insulating film against oxygen include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate).

[0327] For example, the insulating layer 580 preferably has a lower dielectric constant than the insulating layer 522. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance occurring between wirings can be reduced. For this reason, the insulating layer 580 preferably uses, as a material with a low dielectric constant, one or more of silicon oxide, silicon oxynitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, and silicon oxide having vacancies.

[0328] In particular, silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are preferred because they can easily form regions containing oxygen that is desorbed by heating.

[0329] The upper surfaces of the insulating layers 580 may be planarized, so that the insulating layers 580 also function as planarizing films.

[0330] As described above, the insulating layer 580 can be formed using a material similar to that of the insulating layer 516 .

[0331] One or both of the insulating layers 582 and 583 preferably function as a barrier insulating layer that suppresses diffusion of impurities from above the insulating layers 582 and 583 to the transistor 500mf or the like. Therefore, one or both of the insulating layers 582 and 583 preferably include an insulating material that has a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms (through which the impurities are less likely to permeate). Alternatively, one or both of the insulating layers 582 and 583 preferably includes an insulating material that has a function of suppressing diffusion of oxygen (through which the oxygen is less likely to permeate).

[0332] The insulating layers 582 and 583 preferably have an insulating layer that has a function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen, and can be made of, for example, aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and zirconium (hafnium zirconium oxide), gallium oxide, silicon nitride, or silicon nitride oxide. For example, the insulating layer 583 is preferably made of silicon nitride, which has a higher hydrogen barrier property. For example, the insulating layer 582 is preferably made of aluminum oxide, which has a high ability to capture or fix hydrogen.

[0333] The semiconductor layer 530 is formed on and in contact with the insulating layer 522. As shown in Figures 13B and 13C, the semiconductor layer 530 has a shape with a high aspect ratio when viewed cross-sectionally in the channel width direction. For this reason, the semiconductor layer 530 can also be said to have a fin-like shape.

[0334] Here, the aspect ratio of the semiconductor layer 530 in a cross-sectional view in the channel width direction refers to the ratio of the length L of the semiconductor layer 530 in the direction of the dashed dotted line A1-A2 (which can also be referred to as the width L of the semiconductor layer 530) to the length H of the semiconductor layer 530 in a direction perpendicular to the surface on which the semiconductor layer 530 is formed (for example, the insulating layer 522) (which can also be referred to as the height H of the semiconductor layer 530). The aspect ratio of the semiconductor layer 530 is preferably as large as possible within a range in which the semiconductor layer 530 does not collapse during the manufacturing process of the transistor 500mf. In the semiconductor layer 530, the height H of the semiconductor layer 530 is at least longer than the width L of the semiconductor layer 530. The height H of the semiconductor layer 530 is preferably greater than 1 time and less than 400 times the width L of the semiconductor layer 530, more preferably 2 times to 100 times, even more preferably 5 times to 40 times, and even more preferably 10 times to 20 times. Furthermore, for example, the height H is preferably 2 to 10 times the width L. Furthermore, for example, the width L is preferably 5 to 100 nm, more preferably 5 to 50 nm, and even more preferably 10 to 30 nm. Furthermore, for example, the height H is preferably 50 to 2000 nm, and more preferably 100 to 1000 nm. Furthermore, for example, the height H is preferably 50 to 100 nm.

[0335] 13B , in a cross-sectional view in the channel width direction, the angle θ between the side surface of the semiconductor layer 530 and the top surface of the insulating layer 522 is preferably perpendicular or approximately perpendicular. For example, the angle θ is preferably 80° to 100°, more preferably 85° to 95°.

[0336] An insulating layer 550, a conductive layer 560, and a conductive layer 542 are provided to cover the semiconductor layer 530 having such a high aspect ratio. In the transistor 500mf, as shown in FIG. 13B , a portion of the insulating layer 550 and a portion of the conductive layer 560 are provided so as to sandwich the semiconductor layer 530 in two. As a result, in a cross-sectional view in the channel width direction, the semiconductor layer 530 and the conductive layer 560 are provided facing each other with the insulating layer 550 sandwiched between the upper portion, the side surface on the A1 side, and the side surface on the A2 side of the semiconductor layer 530. In other words, the upper portion, the side surface on the A1 side, and the side surface on the A2 side of the semiconductor layer 530 each function as a channel formation region. Therefore, compared to when the semiconductor layer 530 is formed in a planar shape, the channel width of the transistor 500mf is larger by the amount of the side surface on the A1 side and the side surface on the A2 side of the semiconductor layer 530.

[0337] As described above, the increase in channel width allows the on-state current of the transistor 500mf to be increased. Furthermore, the mutual conductance of the transistor 500mf is improved. Furthermore, the frequency characteristics of the transistor 500mf are improved. By using the transistor 500mf in one or both of the pixel circuit and the driver circuit included in a display device, a display device with a high frame frequency can be provided. Furthermore, in the above structure, the provision of the semiconductor layer 530 allows the channel width to be increased without increasing the area occupied by the transistor 500mf. This allows for miniaturization or high integration of the pixel circuit and the driver circuit.

[0338] 13B , the upper portion of the semiconductor layer 530 may have a curved shape. Such a curved shape can prevent defects such as voids from forming in the insulating layer 550 and the conductive layer 542 near the upper portion of the semiconductor layer 530. While FIGS. 12B and 13C illustrate a symmetrical structure in which curved shapes are provided on both the A1 side (A3 side) and the A2 side (A4 side) of the upper portion of the semiconductor layer 530, the present invention is not limited to this. For example, an asymmetrical structure may also be obtained in which a curved shape is provided on either the A1 side (A3 side) or the A2 side (A4 side) of the upper portion of the semiconductor layer 530.

[0339] Because the semiconductor layer 530 has a shape with a high aspect ratio, it is preferable to form the semiconductor layer 530 by, for example, first forming a pillar and then forming the semiconductor layer 530 in a sidewall shape on the side surface of the pillar. Therefore, it is preferable to form the semiconductor layer 530 using the ALD method, which has good coverage. Furthermore, when the semiconductor layer 530 has a stacked structure, it is preferable to form at least one layer, preferably the layer in contact with the pillar, using the ALD method.

[0340] 12A, by forming the semiconductor layers 530 in a sidewall shape in contact with the side surfaces of the plurality of pillars, the plurality of semiconductor layers 530 can be formed simultaneously. By forming the plurality of semiconductor layers 530 in this manner, the distance between the semiconductor layers 530 can be set in accordance with the size and shape of the pillar. Therefore, the distance between the semiconductor layers 530 can be reduced, the area occupied by the transistors 500mf can be reduced, and a higher integration of the display device can be achieved.

[0341] Since the semiconductor layer 530 is formed in a sidewall shape in contact with the pillar, as shown in FIG. 12A , the top surface shape of the semiconductor layer 530 is a circumferential shape with both ends coinciding (which can also be called a frame shape, annular shape, doughnut shape, or closed curve shape). The semiconductor layer 530 can also be said to have a shape with an opening in the center. Note that in FIG. 12A , the top surface shape of the semiconductor layer 530 is line-symmetrical about the dashed dotted line A1-A2, but the present invention is not limited to this. For example, the top surface shape of the semiconductor layer 530 may be asymmetrical.

[0342] The structure shown in FIG. 12A includes two pillars arranged in the direction of the dashed-dotted line A1-A2, with a circumferential semiconductor layer 530 formed in contact with the side surface of each pillar. As shown in FIG. 12A , the semiconductor layer 530 preferably overlaps with the conductive layer 560 at two or more locations in a plan view. That is, the semiconductor layer 530 and the conductive layer 560 have two or more overlapping regions. This structure results in multiple fin-shaped semiconductor layers 530 being formed in a cross-sectional view in the channel width direction, as shown in FIG. 12B . Each of the multiple fin-shaped semiconductor layers 530 functions as a channel formation region. That is, the transistor 500mf functions as a multi-channel transistor. Therefore, the channel width of the transistor 500mf can be further increased. Because the transistor 500mf includes multiple fin-shaped semiconductor layers 530, it is sometimes referred to as a multi-fin structure transistor.

[0343] Although the above description has been given of a configuration in which two circumferential semiconductor layers 530 are provided, the present invention is not limited to this. For example, a configuration in which one or three or more circumferential semiconductor layers 530 are provided may also be used. Furthermore, the circumferential semiconductor layers 530 may be joined together to form a semiconductor layer 530 having a shape with a plurality of openings.

[0344] Although the above description has been given of the circumferential semiconductor layer 530, the present invention is not limited to this. For example, the semiconductor layer 530 may have a non-circumferential configuration. For example, in the transistor 500mf shown in FIGS. 12A to 12D , the conductive layer 540a, the insulating layer 550, the conductive layer 560, and the conductive layer 540b may intersect with the fin-shaped semiconductor layer 530 in one location. By reducing the number of locations in the fin-shaped semiconductor layer 530 where the conductive layer 540a, the insulating layer 550, the conductive layer 560, and the conductive layer 540b intersect, the area in which the transistor is formed can be reduced, and the area occupied by a circuit including the transistor can be reduced.

[0345] <Cross-Sectional Configuration Example 3 of Memory Device> FIG. 14 is a schematic cross-sectional view of an example of the memory device MDV shown in FIG. 7, which is different from those in FIGS. 9 and 11. In FIG.

[0346] The memory device MDV of FIG. 14 differs from the memory devices MDV of FIGS. 9 and 11 in that the transistors included in the layer SS2 are vertical channel transistors.

[0347] 14, the source electrode and the drain electrode are located at different heights, and the current flowing through the semiconductor layer flows in the height direction. That is, the channel length direction can be said to have a component in the height direction (vertical direction), and therefore, these transistors are called vertical channel transistors. Note that each of the transistors MO1 to MO4 can also be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, or the like, in addition to being called a vertical channel transistor.

[0348] Also, Fig. 15A shows a schematic plan view of an example of the memory device MDV, and Fig. 15B shows a schematic cross-sectional view of the memory device MDV. Note that Fig. 14 is a schematic cross-sectional view taken along dashed line A1-A2 in Fig. 15A, and Fig. 15B is a schematic cross-sectional view taken along dashed line A3-A4 in Fig. 15A. Note that Fig. 15B shows only transistors included in layer SS2.

[0349] The configurations of the vertical channel transistor and the capacitor included in the memory device MDV will be described with reference to FIG. 15B.

[0350] FIG. 15B shows a transistor MO4, which is a vertical channel transistor, and a capacitance element CD1 located below the transistor MO4.

[0351] As an example, the layer SS2 has a conductive layer ME1, an insulating layer IS1 that functions as an interlayer film, a conductive layer ME2, a conductive layer ME3, a conductive layer that functions as wiring WBL, a semiconductor layer SC1 that includes a channel formation region of the transistor MO4, an insulating layer GI that functions as a gate insulating film, an insulating layer IS2 that functions as an interlayer film, a conductive layer ME5, a conductive layer ME6, and an insulating layer DI that functions as a dielectric.

[0352] Above the conductive layer ME1, an insulating layer IS1, a conductive layer ME2, an insulating layer DI, and a conductive layer ME3 are stacked in this order. In particular, the conductive layers ME2 and ME3 each function as a pair of electrodes of the capacitance element CD1. In addition, an insulating layer DI, which functions as a dielectric, is formed between the conductive layers ME2 and ME3.

[0353] Although not shown in FIG. 15B, the insulating layer DI functions as a gate insulating film for each of the transistors MO2 and MO3.

[0354] Above the conductive layer ME3, a conductive layer functioning as the wiring WBL, an insulating layer IS2, and a conductive layer ME5 are formed in this order. A shared opening is formed among the conductive layer functioning as the wiring WBL, the insulating layer IS2, and the conductive layer ME5, and a semiconductor layer SC1 is formed on the side and bottom of the opening. The semiconductor layer SC1 is also formed on the upper surface of the conductive layer ME5. An insulating layer GI is formed on the upper surface of the semiconductor layer SC1, on the side of the conductive layer ME5, and above the insulating layer IS2. A conductive layer ME6 is formed on the upper surface of the insulating layer GI so as to fill the opening. A conductive layer that will become the wiring WWL is formed on the upper surface of the conductive layer ME6.

[0355] A part of the conductive layer that becomes the wiring WBL functions as one of the source and drain of the transistor MO4, a part of the conductive layer ME5 functions as the other of the source and drain of the transistor MO4, and a part of the conductive layer ME6 functions as the gate of the transistor MO4.

[0356] As described above, by forming the insulating layer, conductive layer, and semiconductor layer, a vertical channel transistor can be formed in which the channel length direction has a component in the height direction (vertical direction). Furthermore, the channel length of the vertical channel transistor depends on the film thickness of the insulating layer IS2. The thinner the insulating layer IS2, the shorter the channel length, which allows the on-current of the transistor MO4 to be increased. On the other hand, the thicker the insulating layer IS2, the longer the channel length, which allows the off-current of the transistor MO4 to be reduced. The same applies to the transistor MO1, which can be formed simultaneously with the transistor MO4.

[0357] 15B, the thinner the insulating layer IS2 is, the shorter the channel length of the vertical channel transistors MO2 and MO3 can be, and the larger the on-current of the transistors MO2 and MO3 can be. Also, the thicker the insulating layer IS2 is, the longer the channel length of the vertical channel transistors MO2 and MO3 can be, and the smaller the off-current of the transistors MO2 and MO3 can be.

[0358] Furthermore, the conductive layer that will become the wiring WBL, the conductive layer that will become the wiring RBL, and a portion of the conductive layer ME2 are each provided along the direction of the dotted line A3-A4, as shown in Figures 15A and 15B.

[0359] The wirings connecting the vertical channel transistors are not formed in the same process but in different processes. As a result, the wirings connecting the vertical channel transistors have overlapping regions in a plan view. In other words, the wirings connecting the vertical channel transistors are provided at different heights, which reduces the parasitic capacitance generated in each wiring. This increases the drive frequency of the transistors MO1 to MO4 and increases the drive speed of the memory device MDV.

[0360] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0361] Embodiment 3 In this embodiment, a transistor including an oxide semiconductor in a channel formation region (OS transistor) will be described. Note that the description of the OS transistor will be briefly compared with a Si transistor.

[0362] [OS Transistor] An OS transistor is preferably formed using an oxide semiconductor with a low carrier concentration. For example, the carrier concentration of a channel formation region of an oxide semiconductor is preferably 1×10 １８ cm −３ Below 1 × 10, preferably １７ cm −３ less than 1×10 １６ cm −３ less than 1×10 １３ cm −３ less than 1×10 １０ cm −３ is less than 1×10 −９ cm −３ That is all. Note that, when the carrier concentration of an oxide semiconductor film is reduced, it is preferable to reduce the impurity concentration in the oxide semiconductor film and reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0363] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor may have a low density of trap states due to a low density of defect states. Charges trapped in trap states of the oxide semiconductor take a long time to disappear and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0364] Therefore, reducing the impurity concentration in the oxide semiconductor is effective for stabilizing the electrical characteristics of a transistor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen and nitrogen. Note that the impurities in the oxide semiconductor refer to, for example, elements other than the main components constituting the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0365] Furthermore, when impurities and oxygen vacancies exist in a channel formation region of an oxide semiconductor, the electrical characteristics of an OS transistor are likely to fluctuate, and reliability may be reduced. Ｏ H) and generate electrons that become carriers. Ｏ When H is formed, the donor concentration in the channel formation region may increase. As the donor concentration in the channel formation region increases, the threshold voltage may vary. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor, the transistor is likely to be normally on (a state in which a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, in the channel formation region of the oxide semiconductor, impurities, oxygen vacancies, and V Ｏ It is preferable that H is reduced as much as possible.

[0366] The band gap of the oxide semiconductor is preferably larger than that of silicon (typically 1.1 eV), preferably 2 eV or more, more preferably 2.5 eV or more, and further preferably 3.0 eV or more. By using an oxide semiconductor having a band gap larger than that of silicon, the off-state current (also referred to as Ioff) of the transistor can be reduced.

[0367] Furthermore, as the size of Si transistors is reduced, a short channel effect (also referred to as SCE) occurs. This makes it difficult to reduce the size of Si transistors. One of the reasons for the short channel effect is the small band gap of silicon. On the other hand, an OS transistor uses an oxide semiconductor, which is a semiconductor material with a wide band gap, and therefore the short channel effect can be suppressed. In other words, an OS transistor is a transistor that does not have the short channel effect or has an extremely small short channel effect.

[0368] The short-channel effect is a degradation of electrical characteristics that becomes apparent as transistors are miniaturized (channel lengths are reduced). Specific examples of the short-channel effect include a decrease in threshold voltage, an increase in subthreshold swing (sometimes referred to as S value), and an increase in leakage current. Here, the S value refers to the amount of change in gate voltage in the subthreshold region that changes the drain current by one order of magnitude at a constant drain voltage.

[0369] Furthermore, the characteristic length is widely used as an index of resistance to the short channel effect. The characteristic length is an index of how easily the potential in the channel formation region bends. The smaller the characteristic length, the steeper the potential rises, and therefore the more resistant it is to the short channel effect.

[0370] An OS transistor is an accumulation-mode transistor, while a Si transistor is an inversion-mode transistor. Therefore, compared with a Si transistor, an OS transistor has a smaller characteristic length between a source region and a channel formation region and a smaller characteristic length between a drain region and a channel formation region. Therefore, an OS transistor is more resistant to the short-channel effect than a Si transistor. That is, when a transistor with a short channel length is to be manufactured, an OS transistor is more suitable than a Si transistor.

[0371] Even when the carrier concentration of the oxide semiconductor is reduced to the point where the channel formation region becomes i-type or substantially i-type, the conduction band minimum of the channel formation region in a short-channel transistor is lowered due to the conduction-band-lowering (CBL) effect, and therefore the energy difference between the conduction band minimums of the source or drain region and the channel formation region can be reduced to 0.1 eV or more and 0.2 eV or less. − The source and drain regions are n-type regions. ＋ The region of type n ＋ -n − -n ＋ accumulation type junction-less transistor structure or n ＋ -n − -n ＋ This can also be regarded as an accumulation type non-junction transistor structure.

[0372] By using an OS transistor with the above structure, good electrical characteristics can be obtained even when the semiconductor device is miniaturized or highly integrated. For example, good electrical characteristics can be obtained even when the gate length of the OS transistor is 20 nm or less, 15 nm or less, 10 nm or less, 7 nm or less, or 6 nm or less, or 1 nm or more, 3 nm or more, or 5 nm or more. On the other hand, a Si transistor may have difficulty in achieving a gate length of 20 nm or less or 15 nm or less due to the short-channel effect. Therefore, an OS transistor can be suitably used as a transistor having a shorter channel length than a Si transistor. Note that the gate length refers to the length of the gate electrode in the direction in which carriers move inside the channel formation region during transistor operation, and refers to the width of the bottom surface of the gate electrode in a plan view of the transistor.

[0373] Furthermore, miniaturization of an OS transistor can improve the high-frequency characteristics of the transistor. Specifically, the cutoff frequency of the transistor can be improved. When the gate length of an OS transistor is within the above range, the cutoff frequency of the transistor can be set to, for example, 50 GHz or higher, preferably 100 GHz or higher, and further preferably 150 GHz or higher at room temperature.

[0374] As described above, compared to Si transistors, OS transistors have excellent advantages such as a smaller off-state current and the ability to be manufactured as transistors with a short channel length.

[0375] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. For example, the configuration, structure, method, and the like described in this embodiment mode can be appropriately combined with the configuration, structure, method, and the like described in other embodiment modes.

[0376] Embodiment 4 In this embodiment, an application example of a memory circuit according to one embodiment of the present invention will be described.

[0377] Generally, various memory devices are used in semiconductor devices such as computers depending on the application. FIG. 16A shows various memory devices used in semiconductor devices by layer. The higher the layer, the faster the operating speed of the memory device is required, while the lower the layer, the larger the memory capacity and recording density are required. In FIG. 16A , from the top layer, there are memory integrated as a register in an arithmetic processing unit (sometimes referred to as a processing unit) such as a CPU, an L1 cache, an L2 cache, an L3 cache, a main memory, and storage. Note that while an example having up to an L3 cache is shown here, lower-level caches may also be included.

[0378] The memory embedded as a register in a processing unit such as a CPU is used for temporary storage of calculation results, and is therefore frequently accessed by the processing unit. Therefore, a higher operating speed is required than a larger memory capacity. Registers also have the function of storing setting information for the processing unit.

[0379] A cache has the function of duplicating and storing a portion of the data stored in main memory. By duplicating frequently used data and storing it in the cache, the access speed to the data can be increased. The storage capacity required for a cache is smaller than that of main memory, but it is required to operate at a faster speed than main memory. In addition, data rewritten in the cache is duplicated and supplied to the main memory.

[0380] The main memory has a function of holding programs, data, etc. read from storage.

[0381] Storage has the function of storing data that requires long-term storage, various programs used in computing devices (e.g., artificial neural network models), etc. Therefore, storage requires a large memory capacity and high recording density rather than an operating speed. For example, high-capacity, non-volatile storage devices such as 3D NAND can be used.

[0382] A memory circuit (OS memory) using an oxide semiconductor according to one embodiment of the present invention has high operating speed and can retain data for a long period of time. For example, the OS memory has the characteristics shown in Table 1.

[0383]

[0384] 16A, by utilizing the characteristics of the OS memory shown in Table 1, a memory circuit according to one embodiment of the present invention can be suitably used in both the hierarchy where the cache is located and the hierarchy where the main memory is located. In addition, the memory circuit according to one embodiment of the present invention can also be applied to the hierarchy where the storage is located.

[0385] FIG. 16B also shows an example in which a static random access memory (SRAM) is used as part of the cache and an OS memory of one embodiment of the present invention is used as the other part.

[0386] The lowest level cache can be called a last level cache (LLC). While an LLC does not require faster operating speed than higher level caches, it is desirable for the LLC to have a large storage capacity. The OS memory according to one embodiment of the present invention is suitable for use as an LLC because it operates quickly and can retain data for a long period of time. The OS memory according to one embodiment of the present invention can also be used as a final level cache (FLC).

[0387] For example, as shown in Fig. 16B, a configuration can be adopted in which SRAM is used for the higher-level caches (L1 cache, L2 cache, etc.) and the OS memory according to one aspect of the present invention is used for the LLC. Also, as shown in Fig. 16B, not only the OS memory but also DRAM can be applied to the main memory.

[0388] In supercomputers and servers using supercomputers, the power consumption of the L3 cache and the DRAM serving as the main memory is large, which is one of the causes of global warming. In FIG. 16A , OS memory is used for both the L3 cache and the main memory. In FIG. 16B , OS memory is used for the LLC. In this manner, by using an oxide semiconductor according to one embodiment of the present invention for a storage device, the power consumption of a supercomputer can be reduced, and the power consumption of a supercomputer can be reduced to the same level as that of a personal computer.

[0389] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0390] In this embodiment, an electronic component, an electronic device, a mainframe computer, a space equipment, and a data center (also referred to as a data center (DC)) that can include the memory circuit described in the above embodiment will be described. The electronic component, the electronic device, the mainframe computer, the space equipment, and the data center that include the memory circuit of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0391] [Electronic Component] Fig. 17A shows a perspective view of electronic component 700. Electronic component 700 shown in Fig. 17A has a substrate 701, a semiconductor device 710 on substrate 701, and a mold 711. In particular, semiconductor device 710 is sealed by mold 711. Note that Fig. 17A omits some parts in order to show the inside of electronic component 700.

[0392] The substrate 701 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate.

[0393] Electronic component 700 is provided with, for example, a lead frame 712. A portion of lead frame 712 located on substrate 701 is covered with mold 711, and another portion of lead frame 712 is exposed to the outside of mold 711. In particular, lead frame 712 exposed to the outside of mold 711 functions as, for example, a terminal for mounting electronic component 700 on a printed circuit board.

[0394] Within mold 711, electrode pads 713 are provided on lead frame 712, and electrode pads 713 are connected to semiconductor device 710 via wires 714. Electronic component 700 is mounted on a printed circuit board, for example, by contacting lead frame 712 with wiring on the printed circuit board. In this way, a mounted board is completed by combining multiple electronic components and connecting them on the printed circuit board.

[0395] Next, the semiconductor device 710 will be described. For example, as shown in FIG. 17B , the semiconductor device 710 includes a drive circuit layer 715 and a memory layer 716. The memory layer 716 can be configured with a plurality of stacked memory cell arrays. The stacked drive circuit layer 715 and memory layer 716 can be configured as a monolithic stack. In a monolithic stack configuration, the layers can be connected without using through-electrode technology (e.g., TSV (Through Silicon Via)) or bonding technology such as Cu-Cu (copper-copper) direct bonding. By configuring the drive circuit layer 715 and the memory layer 716 as a monolithic stack, for example, a so-called on-chip memory configuration can be achieved, in which the memory is formed directly on the processor. The on-chip memory configuration can speed up the operation of the interface between the processor and the memory. For example, by using the processor as a computing device, data transmission from the memory to the computing device can be accelerated.

[0396] Furthermore, by configuring an on-chip memory, it is possible to reduce the size of connection wiring, etc., compared to technologies that use through electrodes such as TSVs, and therefore it is possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0397] It is also preferable that the memory cell arrays included in the memory layer 716 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked structure, it is possible to improve either or both of the memory bandwidth and the memory access latency. Note that the bandwidth refers to the amount of data transferred per unit time, and the access latency refers to the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 716, it is more difficult to form a monolithic stacked structure than when OS transistors are used. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked structure.

[0398] The semiconductor device 710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes during the semiconductor chip manufacturing process. Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0399] Next, Fig. 17C shows a modified example of electronic component 700. Electronic component 700A shown in Fig. 17C differs from electronic component 700 in that it does not use lead frame 712, but has electrodes 733 provided on the bottom of substrate 701. Electrodes 733 function as connection terminals for mounting electronic component 700A on a printed circuit board.

[0400] 17C shows an example in which electrodes 733 are formed using solder balls. By providing solder balls in a matrix on the bottom of substrate 701, BGA (Ball Grid Array) mounting can be achieved. For this purpose, through-hole vias (penetrating vias) are provided in substrate 701, and conductive layers 732 that function as wiring are provided in these vias. Electrode pads 713 are provided above conductive layer 732 on substrate 701 so as to be in contact with them, and electrodes 733 are provided below conductive layer 732 below substrate 701 so as to be in contact with them.

[0401] Furthermore, the electrodes 733 may be formed of conductive pins instead of solder balls. By providing conductive pins in a matrix on the bottom of the substrate 701, PGA (Pin Grid Array) mounting can be achieved.

[0402] Furthermore, electronic component 700A can be mounted on other substrates using various mounting methods other than BGA and PGA, such as staggered pin grid array (SPGA), land grid array (LGA), quad flat package (QFP), quad flat J-leaded package (QFJ), and quad flat non-leaded package (QFN).

[0403] 17D , an electronic component 700C includes an interposer 731 provided on a package substrate 734 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 provided on the interposer 731.

[0404] 17D shows an example in which the semiconductor device 710 is used as a high bandwidth memory (HBM). For example, the semiconductor device 735 can be used as an arithmetic circuit in an integrated circuit such as a CPU, a GPU, or an FPGA (Field Programmable Gate Array).

[0405] The package substrate 734 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate, similar to the substrate 701. The interposer 731 may be, for example, a silicon interposer or a resin interposer.

[0406] The interposer 731 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 734. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 731, and the integrated circuits and the package substrate 734 are connected using the through electrodes. In addition, in a silicon interposer, TSVs can also be used as through electrodes.

[0407] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0408] Furthermore, in SiP and MCM using silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, since the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on the interposer.

[0409] On the other hand, when connecting multiple integrated circuits with different terminal pitches using a silicon interposer and TSVs, space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 700C, the width of the terminal pitch becomes an issue, and it may be difficult to provide the large number of wirings required to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked configuration using OS transistors is preferable. Also, for example, a memory cell array stacked using TSVs and a monolithically stacked memory cell array can be combined. A structure combining a memory cell array stacked using TSVs and a monolithically stacked memory cell array is sometimes called a hybrid structure.

[0410] Furthermore, if the temperature of the electronic component 700C increases due to heat generated by electric current or the like, the characteristics of the circuit elements (e.g., transistors) included in the electronic component 700C may be degraded. Therefore, it is preferable to provide a heat sink (heat sink) on the electronic component 700C so that the heat sink overlaps the electronic component 700C. When providing a heat sink, it is preferable to align the height of the integrated circuit provided on the interposer 731. For example, in the electronic component 700C shown in this embodiment, it is preferable to align the height of the semiconductor device 710 and the semiconductor device 735.

[0411] [Electronic Device] Next, a perspective view of an electronic device 6500 is shown in FIG. 18A . The electronic device 6500 shown in FIG. 18A is a portable information terminal that can be used as a smartphone. The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and a control device 6509. Note that the control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a memory circuit. In particular, the memory circuit of one embodiment of the present invention can be applied to the control device 6509, etc.

[0412] 18B is an information terminal that can be used as a laptop personal computer. The electronic device 6600 includes a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display unit 6615, and a control device 6616. Note that the control device 6616 includes, for example, one or more selected from a CPU, a GPU, and a memory circuit. The memory circuit of one embodiment of the present invention can be used as the control device 6616, etc.

[0413] The memory circuit of one embodiment of the present invention is preferably used for the control devices 6509 and 6616 because power consumption can be reduced. Furthermore, the speed of calculations by an artificial neural network can be increased.

[0414] [Mainframe] Next, Fig. 18C shows a perspective view of multiple mainframe computers 5600 installed in a server room or the like. The mainframe computer 5600 shown in Fig. 18C has multiple rack-mounted computers 5620 stored in a rack 5610. The mainframe computer 5600 is sometimes called a supercomputer.

[0415] The computer 5620 has a motherboard, which is provided with a plurality of slots, a plurality of connection terminals, etc. For example, one or a plurality of PC cards can be inserted into the slot.

[0416] The PC card is an example of a processing board equipped with a processing unit such as a CPU, a GPU, etc. For example, the electronic component 700 can be used as the processing unit.

[0417] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations necessary for learning and inference in artificial intelligence, for example.

[0418] [Space Equipment] The memory circuit of one embodiment of the present invention can be suitably used in space equipment (for example, equipment having a function of processing and storing information).

[0419] The memory circuit of one embodiment of the present invention can include an OS transistor. The OS transistor has small changes in electrical characteristics due to radiation exposure. That is, the OS transistor has high radiation resistance and can be preferably used in an environment where radiation may be incident. For example, the OS transistor can be preferably used in outer space.

[0420] Fig. 19 shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. In Fig. 19, a planet 6804 is shown in outer space. Note that outer space refers to an altitude of 100 km or higher, for example, but outer space described in this specification also includes the thermosphere, mesosphere, and stratosphere.

[0421] 19, a battery management system (also referred to as a BMS) or a battery control circuit may be provided for the secondary battery 6805. The use of an OS transistor in the battery management system or the battery control circuit is preferable because it consumes low power and has high reliability even in space.

[0422] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0423] When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is preferable to provide a secondary battery 6805 in the satellite 6800. Note that the solar panel may be called a solar cell module.

[0424] The satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received, for example, by a receiver on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be determined. As described above, the satellite 6800 can constitute a satellite positioning system.

[0425] The control device 6807 has a function of controlling the satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a memory circuit. Note that the memory circuit of one embodiment of the present invention is preferably used for the control device 6807. The change in electrical characteristics of an OS transistor due to radiation exposure is smaller than that of a Si transistor. That is, an OS transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.

[0426] The artificial satellite 6800 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Or, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an earth observation satellite.

[0427] Although an artificial satellite is used as an example of space equipment in this embodiment, the present invention is not limited thereto. For example, the memory circuit of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

[0428] As described above, OS transistors have excellent advantages over Si transistors, such as the ability to achieve a wide memory bandwidth and high radiation resistance.

[0429] [Data Center] The memory circuit of one embodiment of the present invention can be suitably used in a storage system applied to, for example, a data center. Data centers are required to perform long-term management of data, such as ensuring the immutability of data. Managing long-term data requires larger buildings, such as installing storage and servers for storing huge amounts of data, ensuring a stable power supply for maintaining the data, and ensuring cooling equipment required for maintaining the data.

[0430] By using a memory circuit according to one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required for calculation and the size of the calculation circuit. In particular, the latter can reduce the space required for the data center.

[0431] Furthermore, the memory circuit of one embodiment of the present invention consumes less power, and thus heat generation from the circuit can be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the memory circuit of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0432] Fig. 20 shows a storage system applicable to a data center. The storage system 7000 shown in Fig. 20 has a plurality of servers 7001sb as hosts 7001 (illustrated as Host Computers). It also has a plurality of storage devices 7003md as storage 7003 (illustrated as Storage). The host 7001 and storage 7003 are shown connected via a storage area network 7004 (illustrated as SAN: Storage Area Network) and a storage control circuit 7002 (illustrated as Storage Controller).

[0433] The host 7001 can be a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

[0434] Although the storage 7003 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, this time is significantly longer than the time required for DRAM (Dynamic Random Access Memory), which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 7003, a storage system typically provides cache memory within the storage to reduce the time required to store and output data.

[0435] The above-mentioned cache memory is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.

[0436] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refresh operations can be reduced, and power consumption can be reduced.

[0437] Note that the application of the memory circuit of one embodiment of the present invention to any one or more selected from electronic components, electronic devices, large-scale computers, space equipment, and data centers is expected to have an effect of reducing power consumption. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of memory circuits, the use of the memory circuit of one embodiment of the present invention can reduce carbon dioxide (CO ２ Furthermore, the memory circuit of one embodiment of the present invention is effective as a countermeasure against global warming because it consumes low power.

[0438] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0439] In this example, a simulation of a memory circuit of one embodiment of the present invention and the results thereof will be described.

[0440] Circuit configurations used in the simulations are shown in FIGS. 21A to 21C . The memory circuit MCS shown in FIG. 21A has a configuration similar to that of the memory circuit MC1 in FIG. 1 , which is one embodiment of the present invention and described in the above embodiment. Furthermore, as a comparison target for the memory circuit MC1, simulations were also performed on memory circuits MCSR1 shown in FIG. 21B and MCSR2 shown in FIG. 21C , which are conventional configuration examples. The memory circuit MCSR1 in FIG. 21B has a configuration similar to that of the memory circuit MCt1 in FIG. 2A , and the memory circuit MCSR2 in FIG. 21C has a configuration similar to that of the memory circuit MCt2 in FIG. 2B .

[0441] The transistors M1 to M3 and the capacitor C1 shown in Figures 21A to 21C correspond to the transistors MO1 to MO3 and the capacitor CD1 in Figures 1, 2A, and 2B, respectively. The transistor M4 and the capacitor C2 shown in Figures 21A and 21C correspond to the transistor MO4 and the capacitor CD2 in Figures 1 and 2B, respectively. The transistors M5 and M6 shown in Figure 21A correspond to the transistors MS1 and MS2 in Figure 1, respectively.

[0442] 21A to 21C correspond to the wirings RBL, WBL, and SL in FIGS. 1, 2A, and 2B. Also, the wirings VAR1 and VAR2 in FIGS. 21A to 21C correspond to the wirings WWL and RWL in FIGS. 1, 2A, and 2B. Also, the wiring CST4 in FIGS. 21A and 21C corresponds to the wiring VGE in FIGS. 1 and 2B. Also, the wirings CST5 to CST7 in FIG. 21A correspond to the wirings VDE, VSE, and VRE2 in FIG. 1.

[0443] 21A to 21C corresponds to the node N1 in Fig. 1, Fig. 2A, and Fig. 2B. Also, the node SN2 shown in Fig. 21A and Fig. 21C corresponds to the node N2 in Fig. 1 and Fig. 2B.

[0444] In the simulation described in this example, the retention characteristics of the potential at the node SN1 of each of the memory circuits MCS, MCSR1, and MCSR2 were calculated. Note that in this simulation, the leakage current between the gate and the source or drain of each of the transistors M1 to M6 and the leakage current of the capacitors C1 and C2 were not taken into consideration, and only the leakage current between the source and the drain of each of the transistors M1 to M6 when they are in an off state was taken into consideration.

[0445] As simulation conditions, the structures of the transistors M1 to M6 shown in Figures 21A to 21C were the same as those of the transistor MO having the GL structure shown in Figures 10A and 10B. The channel length and channel width of the transistors M1 to M6 were 200 nm and 60 nm, respectively. The capacitance elements C1 and C2 were parallel-plate capacitance elements, and each had a capacitance value of 4 fF.

[0446] The potentials applied to the wirings CST1 to CST7, wiring VAR1, and wiring VAR2 shown in FIGS. 21A to 21C are as shown in the table below.

[0447]

[0448] 21B, the potentials applied to the wirings in the above table are set so that a potential of 1.2 V can be maintained at the node SN1 for one hour in an environment of 85° C. Therefore, in the circuit configurations of the memory circuits MCS and MCSR2, the potentials applied to the wirings are based on the conditions of the memory circuit MCSR1.

[0449] Furthermore, the simulation was performed under three conditions of 0.1V, 0.6V, and 1.2V for the node SN1 of each of the memory circuits MCS, MCSR1, and MCSR2.

[0450] 22A to 22C show the results of a simulation in which the retention characteristics of the node SN1 of each of the memory circuits MCS, MCSR1, and MCSR2 were calculated. Note that the simulation was performed under an environment of 125° C.

[0451] 22A shows the retention characteristics of memory circuits MCS, MCSR1, and MCSR2 when 1.2 V is held at node SN1. Fig. 22B shows the retention characteristics of memory circuits MCS, MCSR1, and MCSR2 when 0.6 V is held at node SN1. Fig. 22C shows the retention characteristics of memory circuits MCS, MCSR1, and MCSR2 when 0.1 V is held at node SN1.

[0452] In this simulation, the time from the start of the simulation until the held potential of the node SN1 changes by ±10 mV is defined as the holding time.

[0453] 22A (the potential of node SN1 is 1.2 V), it was confirmed that memory circuit MCSR1 can hold the potential of node SN1 for 1.0 second, and memory circuit MCSR2 can hold the potential of node SN1 for 138.5 seconds. It was also confirmed that memory circuit MCS can hold the potential of node SN1 for 1000 seconds or more. Although not shown in FIG. 22A, it was confirmed that the potential of node SN1 did not fluctuate for 500 hours or more in memory circuit MCS.

[0454] From FIG. 22B (potential of node SN1 is 0.6 V), it was confirmed that the memory circuit MCSR1 can hold the potential of node SN1 for 1.4 seconds, and the memory circuit MCSR2 can hold the potential of node SN1 for 71.0 seconds. It was also confirmed that the memory circuit MCS can hold the potential of node SN1 for 1000 seconds or more. Although not shown in FIG. 22B, in the memory circuit MCS, the potential of node SN1 is 2.1×10 ６ It was confirmed that the temperature could be maintained for approximately 58 hours.

[0455] From Figure 22C (potential of node SN1 is 0.1 V), it was confirmed that memory circuit MCSR1 holds the potential of node SN1 for 1.8 seconds, memory circuit MCSR2 holds the potential of node SN1 for 11.5 seconds, memory circuit MCSR2 holds the potential of node SN1, and memory circuit MCSR can hold the potential of node SN1 for 20 seconds.

[0456] From the above simulation results, it can be expected that the memory circuit MCS of one embodiment of the present invention can hold a potential for a longer period of time than the conventional memory circuits MCSR1 and MCSR2.

[0457] ADDR: signal, BW: signal, CE: signal, CLK: signal, DI: insulating layer, GEM: conductive layer, GI: insulating layer, GW: signal, MCA: memory cell array, MCS: memory circuit, MDV: memory device, MEG: conductive layer, PLG: conductive layer, RBL[1]: wiring, RBL[j]: wiring, RBL[n]: wiring, RBL: wiring, RDA: signal, RWL[1]: wiring, RWL[i]: wiring, RWL[m]: wiring, RWL: wiring, SDM: conductive layer, SL: wiring, SMC: semiconductor layer, TrP: transistor, TrQ: transistor, MO: transistor, MO1: transistor ,MO2: transistor, MO3: transistor, MO4: transistor, VDE: wiring, VGE: wiring, VRE: wiring, VSE: wiring, WAKE: signal, WBL[1]: wiring, WBL[j]: wiring, WBL[n]: wiring, WBL: wiring, WDA: signal, WIR: conductive layer, WWL[1]: wiring, WWL[i]: wiring, WWL[m]: wiring, WWL: wiring, 10[1,1]: memory cell, 10[i,j]: memory cell, 10[m,n]: memory cell, 10: memory cell, 22: PSW, 23: PSW, 31: peripheral circuit, 32: control circuit, 33: voltage generation Circuit, 41: Peripheral circuit, 42: Row decoder, 43: Row driver, 44: Column decoder, 45: Column driver, 46: Sense amplifier, 47: Input circuit, 48: Output circuit, 50: Driver circuit region, 311: Substrate, 313: Semiconductor region, 314a: Low resistance region, 314b: Low resistance region, 315: Insulating layer, 316: Conductive layer, 317: Insulating layer, 320: Insulating layer, 324: Insulating layer, 326: Insulating layer, 328: Conductive layer, 330: Conductive layer, 350: Insulating layer, 352: Insulating layer, 354: Insulating layer, 356: Conductive layer, 357: Insulating layer, 400: Transistor, 500mf: Transistor , 505: conductive layer, 505a: conductive layer, 505b: conductive layer, 512: insulating layer, 514: insulating layer, 516: insulating layer, 520: insulating layer, 521: insulating layer, 522: insulating layer, 524: insulating layer, 530: semiconductor layer, 530a: semiconductor layer, 530b: semiconductor layer, 530c: semiconductor layer, 531: semiconductor layer, 531a: semiconductor layer, 531b: semiconductor layer, 540: conductive layer, 540a: conductive layer, 540b: conductive layer, 541a: insulating layer, 541b: insulating layer, 542a: conductive layer, 542b: conductive layer, 550: insulating layer, 550a: insulating layer, 550b: insulating layer, 550c: insulating layer,550d: insulating layer, 554: insulating layer, 560: conductive layer, 560a: conductive layer, 560b: conductive layer, 574: insulating layer, 575: insulating layer, 580: insulating layer, 581: insulating layer, 582: insulating layer, 583: insulating layer, 700: electronic component, 700A: electronic component, 700C: electronic component, 701: substrate, 710: semiconductor device, 711: mold, 712: lead frame, 713: electrode pad, 714: wire, 715: drive circuit layer, 716: memory layer, 731: interposer, 732: conductive layer, 733: electrode, 734: package substrate, 735: semiconductor device, 5600: mainframe computer, 5610: rack, 5620: computer, 6500: electronic device, 6501: housing, 65 02: display unit, 6503: power button, 6504: button, 6505: speaker, 6506: microphone, 6507: camera, 6508: light source, 6509: control device, 6600: electronic device, 6611: housing, 6612: keyboard, 6613: pointing device, 6614: external connection port, 6615: display unit, 6616: control device, 6800: artificial satellite, 6801: aircraft, 6802: solar panel, 6803: antenna, 6804: planet, 6805: secondary battery, 6807: control device, 7000: storage system, 7001: host, 7001sb: server, 7002: storage control circuit, 7003: storage, 7003md: storage device,

Claims

A first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first capacitive element, and a second capacitive element, One of the source or drain of the first transistor is electrically connected to the gate of the second transistor, the gate of the fifth transistor, and the first terminal of the first capacitive element, The other of the source or drain of the first transistor is electrically connected to one of the source or drain of the fourth transistor, one of the source or drain of the fifth transistor, one of the source or drain of the sixth transistor, and the first terminal of the second capacitive element, One of the source or drain of the second transistor is electrically connected to one of the source or drain of the third transistor, The other of the source or drain of the second transistor is electrically connected to the second terminal of the first capacitive element, The gate of the first transistor is electrically connected to the gate of the fourth transistor, A memory circuit. 　 A first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first capacitive element, and a second capacitive element, One of the source or drain of the first transistor is electrically connected to the gate of the second transistor, the gate of the fifth transistor, and the first terminal of the first capacitive element, The other of the source or drain of the first transistor is electrically connected to one of the source or drain of the fourth transistor, one of the source or drain of the fifth transistor, one of the source or drain of the sixth transistor, and the first terminal of the second capacitive element, One of the source or drain of the second transistor is electrically connected to one of the source or drain of the third transistor, The other of the source or drain of the second transistor is electrically connected to the second terminal of the first capacitive element and the second terminal of the second capacitive element, The gate of the first transistor is electrically connected to the gate of the fourth transistor, A memory circuit. 　 A first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a first capacitive element, One of the source or drain of the first transistor is electrically connected to the gate of the second transistor, the gate of the fifth transistor, and the first terminal of the first capacitor element. The other of the source or drain of the first transistor is electrically connected to one of the source or drain of the fourth transistor, one of the source or drain of the fifth transistor, and one of the source or drain of the sixth transistor. One of the source or drain of the second transistor is electrically connected to one of the source or drain of the third transistor. The other of the source or drain of the second transistor is electrically connected to the second terminal of the first capacitor element. The gate of the first transistor is electrically connected to the gate of the fourth transistor. Memory circuit. 　 In any one of claims 1 to 3, Each of the first transistor to the sixth transistor has an oxide semiconductor in a channel formation region. The oxide semiconductor has one or more selected from indium, zinc, and element M. The element M is one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony. Memory circuit. 　 A memory circuit according to claim 4 and a drive circuit. The memory circuit is located above the drive circuit. The drive circuit has a transistor including silicon in a channel formation region. Memory device. 　 An electronic device having the memory device according to claim 5 and a housing.

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