Display substrate and display apparatus

Abstract

A display substrate and a display apparatus. The display substrate comprises a base and at least one pixel driving circuit located on one side of the base, wherein the at least one pixel driving circuit comprises at least one transistor, the at least one transistor comprises an active layer, and the active layer comprises a channel region, and a first region and a second region which are located on two opposite sides of the channel region; the first region has a first end and a second end which are arranged opposite each other, the first end of the first region is connected to the channel region, and the second end extends in a second direction; and the channel region has a first width in a first direction, and the first region has a second width in the first direction, the first width being greater than the second width. The display substrate further comprises a compensation line (38), wherein a first end of the compensation line (38) is connected to the channel region, and a second end of the compensation line (38) is connected to the second end of the first region, the first direction intersecting with the second direction.

Description

Display substrate and display device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on January 23, 2024, with application number 202410096342.1 and invention name “A display substrate and display device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] This article relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a display device. Background Art

[0003] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field. Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] Embodiments of the present disclosure provide a display substrate and a display device.

[0006] In one aspect, an embodiment of the present disclosure provides a display substrate, comprising a substrate and at least one pixel driving circuit located on one side of the substrate, the at least one pixel driving circuit comprising at least one transistor, the at least one transistor comprising an active layer, the active layer comprising a channel region and a first region and a second region located on opposite sides of the channel region; the first region having a first end and a second end oppositely disposed, the first end of the first region being connected to the channel region, and the second end extending along a second direction;

[0007] The channel region has a first width along a first direction, the first region has a second width along the first direction, the first width is greater than the second width, and the display substrate further includes a compensation line, a first end of the compensation line is connected to the channel region, and a second end of the compensation line is connected to the second end of the first region; wherein the first direction intersects the second direction.

[0008] In some exemplary embodiments, an absolute value of a difference between the first width and the second width is greater than 10% of the first width.

[0009] In some exemplary embodiments, the display substrate further includes at least one capacitor, and the at least one capacitor is closer to the substrate than the compensation line, and the capacitor is located on one side of the extension direction of the compensation line. The capacitor includes two electrodes arranged opposite to each other, and the orthographic projection of the compensation line on the substrate and the orthographic projection of the two electrodes on the substrate do not overlap.

[0010] In some exemplary embodiments, the compensation line is disposed in the same layer as the active layer.

[0011] In some exemplary embodiments, the display substrate further includes a first connection bridge having a first end and a second end oppositely arranged along the first direction, the first end of the first connection bridge being connected to the second end of the compensation line, and the second end of the first connection bridge being connected to the second end of the first region of the active layer.

[0012] In some exemplary embodiments, the display substrate further includes at least one second connection bridge, wherein the at least one second connection bridge is located between the first connection bridge and the channel region, and the at least one second connection bridge is located between the first region and the compensation line; the second connection bridge extends along the first direction and includes a first end and a second end oppositely arranged; the first end of the second connection bridge is connected to the compensation line, and the second end of the second connection bridge is connected to the first region.

[0013] In some exemplary embodiments, the first connecting bridge, the at least one second connecting bridge, and the compensation line are an integrated structure connected to each other.

[0014] In some exemplary embodiments, the compensation line is located on a side of the active layer away from the substrate.

[0015] In some exemplary embodiments, in a plane perpendicular to the display substrate, the display substrate further includes a semiconductor layer, a first source-drain metal layer, and a second source-drain metal layer sequentially located on one side of the base;

[0016] The active layer is located in the semiconductor layer, and the compensation line is located in the first source-drain metal layer or the second source-drain metal layer.

[0017] In some exemplary embodiments, the display substrate further includes a first bridging electrode and a second bridging electrode; an orthographic projection of the first bridging electrode on the substrate at least partially overlaps with an orthographic projection of the first end of the first region on the substrate, and an orthographic projection of the second bridging electrode on the substrate at least partially overlaps with an orthographic projection of the second end of the first region on the substrate; and an orthographic projection of the compensation line on the substrate partially overlaps with both the orthographic projections of the first bridging electrode and the second bridging electrode on the substrate.

[0018] The compensation line is connected to the first end of the first region via the first bridging electrode, and the compensation line is connected to the second end of the first region via the second bridging electrode.

[0019] In some exemplary embodiments, the first bridging electrode and the second bridging electrode are both located in the first source-drain metal layer, and the compensation line is located in the second source-drain metal layer.

[0020] In some exemplary embodiments, an orthographic projection of the compensation line on the substrate at least partially overlaps with an orthographic projection of the first region on the substrate.

[0021] In some exemplary embodiments, an orthographic projection of the compensation line on the substrate is located within an orthographic projection of the first region on the substrate.

[0022] In some exemplary embodiments, the at least one transistor is a driving transistor; and the at least one pixel driving circuit further includes a light emission control transistor connected to the second end of the first region.

[0023] On the other hand, an embodiment of the present disclosure provides a display device, comprising the display substrate described in any of the aforementioned embodiments.

[0024] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0025] Summary of the Figures

[0026] The accompanying drawings are intended to facilitate understanding of the technical solutions of the present disclosure and constitute part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of one or more components in the accompanying drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0027] FIG1 is a schematic structural diagram of a display device;

[0028] FIG2 is a schematic diagram of a planar structure of a display substrate;

[0029] FIG3 is a schematic diagram of a cross-sectional structure of a display substrate;

[0030] FIG4 is an equivalent circuit diagram of a pixel driving circuit of a display substrate according to an embodiment of the present disclosure;

[0031] FIG4A is an equivalent circuit diagram of a pixel driving circuit of a display substrate according to another embodiment of the present disclosure;

[0032] FIG4B is an equivalent circuit diagram of a pixel driving circuit of a display substrate according to yet another embodiment of the present disclosure;

[0033] FIG5 is a schematic diagram of a partial planar structure of a display substrate according to an embodiment of the present disclosure;

[0034] FIG6 is a schematic diagram of a display substrate after forming a first conductive layer pattern according to an embodiment of the present disclosure;

[0035] 7A and 7B are schematic diagrams of a display substrate after forming a second conductive layer pattern according to an embodiment of the present disclosure;

[0036] 8A and 8B are schematic diagrams of a display substrate after a semiconductor layer pattern is formed according to an embodiment of the present disclosure;

[0037] 9A and 9B are schematic diagrams of a display substrate after a third conductive layer pattern is formed according to an embodiment of the present disclosure;

[0038] FIG10 is a schematic diagram of a display substrate after a fourth insulating layer pattern is formed according to an embodiment of the present disclosure;

[0039] 11A and 11B are schematic diagrams of a display substrate after a fourth conductive layer pattern is formed according to an embodiment of the present disclosure;

[0040] FIG12 is a schematic diagram of a partial planar structure of a display substrate according to another embodiment of the present disclosure;

[0041] 13A and 13B are schematic diagrams showing a display substrate after a semiconductor layer pattern is formed according to another embodiment of the present disclosure;

[0042] FIG14 is a schematic diagram of a display substrate after a fourth insulating layer pattern is formed according to another embodiment of the present disclosure;

[0043] 15A and 15B are schematic diagrams of a display substrate after a fourth conductive layer pattern is formed according to another embodiment of the present disclosure;

[0044] FIG16 is a schematic diagram of a display substrate after a fifth insulating layer pattern is formed according to another embodiment of the present disclosure;

[0045] 17A and 17B are schematic diagrams of a display substrate after a fifth conductive layer pattern is formed according to another embodiment of the present disclosure.

[0046] Details

[0047] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the method and content can be transformed into one or more forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other in any way.

[0048] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of one or more components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0049] The ordinal numbers such as "first," "second," and "third" in this disclosure are provided to avoid confusion among constituent elements, and are not intended to limit the number. The "plurality" in this disclosure includes two or more.

[0050] In this disclosure, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it should not be understood as a limitation of this disclosure. The positional relationships of constituent elements are appropriately changed according to the direction in which the constituent elements are described. Therefore, the words and phrases are not limited to those described in the specification and can be appropriately replaced according to the circumstances.

[0051] In this disclosure, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this disclosure based on the specific circumstances.

[0052] In this disclosure, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having one or more functions.

[0053] In this disclosure, a transistor refers to a device comprising at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0054] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in the present disclosure, "source electrode" and "drain electrode" may be interchanged.

[0055] In this disclosure, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus includes a state where the angle is greater than 85° and less than 95°.

[0056] In this disclosure, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0057] In the present disclosure, “about” and “approximately” refer to values ​​that are not strictly defined but allow for process and measurement errors.

[0058] The triangles, rectangles, trapezoids, pentagons or hexagons in the present disclosure are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0059] An embodiment of the present disclosure provides a display substrate, comprising a substrate and at least one pixel driving circuit located on one side of the substrate, wherein the at least one pixel driving circuit comprises at least one transistor, wherein the at least one transistor comprises an active layer, wherein the active layer comprises a channel region and a first region and a second region located on opposite sides of the channel region; wherein the first region has a first end and a second end oppositely disposed, wherein the first end of the first region is connected to the channel region, and the second end extends along a second direction;

[0060] The channel region has a first width along a first direction, the first region has a second width along the first direction, the first width is greater than the second width, and the display substrate further includes a compensation line, a first end of the compensation line is connected to the channel region, and a second end of the compensation line is connected to the second end of the first region; wherein the first direction intersects the second direction.

[0061] The display substrate provided by the embodiment of the present disclosure can avoid the problem of threshold voltage divergence of the transistor and improve the performance of the transistor by limiting the relationship between the first width and the second width and providing a compensation line.

[0062] FIG1 is a schematic diagram of the structure of a display device. As shown in FIG1 , the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is respectively connected to the data driver, the scan driver, and the light-emitting driver. The data driver is respectively connected to a plurality of data signal lines (D1 to Dn). The scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm). The light-emitting driver is respectively connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is respectively connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. The light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, may provide clock signals, scan start signals, etc. suitable for the specifications of the scan driver to the scan driver, and may provide clock signals, emission stop signals, etc. suitable for the specifications of the light-emitting driver to the light-emitting driver. The data driver can generate data voltages to be supplied to data signal lines D1, D2, D3, ..., and Dn using grayscale values ​​and control signals received from a timing controller. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a per-pixel basis, where n can be a natural number. The scan driver can generate scan signals to be supplied to scan signal lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, and the like from the timing controller. For example, the scan driver can sequentially supply scan signals having on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can sequentially transmit scan start signals provided in the form of on-level pulses to the next-stage circuit under the control of a clock signal, where m can be a natural number. The light driver can generate emission signals to be supplied to light signal lines E1, E2, E3, ..., and Eo by receiving clock signals, emission stop signals, and the like from the timing controller. For example, the light emitting driver may sequentially provide emission signals having off-level pulses to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be configured as a shift register and may generate emission signals by sequentially transmitting emission stop signals provided in the form of off-level pulses to the next stage circuit under the control of a clock signal. o may be a natural number. In an exemplary embodiment, the pixel array may be provided on a display substrate.

[0063] Figure 2 is a schematic diagram of a planar structure of a display substrate. In an exemplary embodiment, the display substrate may include a display area and a frame area located around the display area. As shown in Figure 2, the display area of ​​the display substrate may include a plurality of pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1 that emits a first color light, a second sub-pixel P2 that emits a second color light, and a third sub-pixel P3 that emits a third color light. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting unit may include at least a light-emitting device. The light-emitting device is respectively connected to the pixel driving circuit of the sub-pixel in which it is located. The light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which it is located.

[0064] In some exemplary embodiments, the first subpixel P1 may be a red subpixel (R) that emits red light, the second subpixel P2 may be a blue subpixel (B) that emits blue light, and the third subpixel P3 may be a green subpixel (G) that emits green light. In one example, the subpixels may be rectangular, diamond, pentagonal, or hexagonal, and the three subpixels may be arranged horizontally, vertically, or in a triangular pattern, although this disclosure is not limited thereto.

[0065] In some exemplary embodiments, a pixel unit may include four sub-pixels, and the four sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a square arrangement, etc., which is not limited in the present disclosure.

[0066] Figure 3 is a schematic cross-sectional view of a display substrate, illustrating the structure of three sub-pixels within the display substrate. As shown in Figure 3, in a plane perpendicular to the display substrate, the display area of ​​the display substrate may include a drive circuit layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on the side of the drive circuit layer 102 facing away from the substrate 101, and an encapsulation structure layer 104 disposed on the side of the light-emitting structure layer 103 facing away from the substrate 101. In some possible implementations, the display substrate may also include other film layers, such as a touch-sensitive structure layer, which is not limited in this disclosure.

[0067] In some exemplary embodiments, the substrate 101 may be a flexible substrate or a rigid substrate. The rigid substrate may be, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.

[0068] In some exemplary embodiments, the substrate 101 may be a flexible substrate or a rigid substrate. The flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The first flexible material layer and the second flexible material layer may be made of polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The first inorganic material layer and the second inorganic material layer may be made of silicon nitride (SiNx) or silicon oxide (SiOx) to improve the substrate's resistance to water and oxygen. The semiconductor layer may be made of amorphous silicon (a-Si).

[0069] In some exemplary embodiments, the driving circuit layer 102 may include multiple circuit units, each of which may include at least a pixel driving circuit, which may include multiple transistors and capacitors. The light-emitting structure layer 103 may include multiple light-emitting units, each of which may include at least a light-emitting device, which may include an anode, an organic light-emitting layer, and a cathode. The anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of a corresponding color when driven by the anode and cathode.

[0070] In some exemplary embodiments, the encapsulation structure layer 104 may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0071] In some exemplary embodiments, the organic light-emitting layer may include an emission layer (EML) and any one or more of the following layers: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0072] Figure 4 is an equivalent circuit diagram of a pixel driving circuit of a display substrate according to an embodiment of the present disclosure. In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, 8T1C, or 9T2C structure. As shown in Figure 4, the pixel driving circuit of the exemplary embodiment of the present disclosure adopts a 7T2C structure. The pixel driving circuit may include 7 transistors (a first transistor T1 to a seventh transistor T7) and 2 capacitors C. The pixel driving circuit is respectively connected to 9 signal lines (a first scan signal line S1, a second scan signal line S2, a third scan signal line S3, a fourth scan signal line S4, an luminous signal line EM, a reference signal line REF, an initial signal line INIT, a data signal line DATA, and a first power line VDD).

[0073] In some exemplary embodiments, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the second electrode of the first transistor T1, the first electrode of the sixth transistor T6, and the gate electrode of the third transistor T3, respectively; the second node N2 is connected to the second electrode of the fourth transistor T4, the second electrode of the sixth transistor T6, and the second end of the second capacitor C2, respectively; the third node N3 is connected to the second electrode of the third transistor T3, the second electrode of the seventh transistor T7, and the second end of the first capacitor C1, respectively; and the fourth node N4 is connected to the second electrode of the second transistor T2, the first end of the first capacitor C1, and the first end of the second capacitor C2, respectively.

[0074] In some exemplary embodiments, the first transistor T1 may be referred to as a first reset transistor, a gate electrode of the first transistor T1 is connected to the first scan signal line S1, a first electrode of the first transistor T1 is connected to the reference signal line REF, and a second electrode of the first transistor T1 is connected to the first node N1.

[0075] In some exemplary embodiments, the second transistor T2 may be referred to as a second reset transistor, a gate electrode of the second transistor T2 is connected to the first scan signal line S1, a first electrode of the second transistor T2 is connected to the reference signal line REF, and a second electrode of the second transistor T2 is connected to the fourth node N4.

[0076] In some exemplary embodiments, the third transistor T3 may be referred to as a driving transistor, a gate electrode of the third transistor T3 is connected to the first node N1, a first electrode of the third transistor T3 is connected to the second electrode of the fifth transistor T5, and a second electrode of the third transistor T3 is connected to the third node N3.

[0077] In some exemplary embodiments, the fourth transistor T4 may be referred to as a data writing transistor, a gate electrode of the fourth transistor T4 is connected to the third scan signal line S3, a first electrode of the fourth transistor T4 is connected to the data signal line DATA, and a second electrode of the fourth transistor T4 is connected to the second node N2.

[0078] In some exemplary embodiments, the fifth transistor T5 can be called a light emitting control transistor, the gate electrode of the fifth transistor T5 is connected to the light emitting signal line EM, the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the first electrode of the third transistor T3.

[0079] In some exemplary embodiments, the sixth transistor T6 may be referred to as a data control transistor, a gate electrode of the sixth transistor T6 is connected to the fourth scan signal line S4 , a first electrode of the sixth transistor T6 is connected to the first node N1 , and a second electrode of the sixth transistor T6 is connected to the second node N2 .

[0080] In some exemplary embodiments, the seventh transistor T7 may be referred to as a third reset transistor, a gate electrode of the seventh transistor T7 is connected to the second scan signal line S2, a first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and a second electrode of the seventh transistor T7 is connected to the third node N3.

[0081] In some exemplary embodiments, a first electrode of the light-emitting device EL is connected to the third node N3, and a second electrode of the light-emitting device EL is connected to the second power supply line VSS. The light-emitting device EL may be an OLED, including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or may be a QLED, including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode).

[0082] In some exemplary embodiments, the seven transistors of the pixel driving circuit may be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the difficulty of manufacturing the display substrate, and improve the product yield.

[0083] In some exemplary embodiments, the six transistors of the pixel driver circuit may be oxide transistors. The active layers of the oxide transistors may be made of oxide semiconductors. Oxide transistors have advantages such as high electron mobility, low operating voltage, and low leakage. Using a display substrate equipped with oxide transistors can achieve low-frequency driving, reduce power consumption, and improve display quality.

[0084] In some exemplary embodiments, the first power line VDD may be configured to provide a constant first voltage signal to the pixel driving circuit, and the second power line VSS may be configured to provide a constant second voltage signal to the light-emitting device, where the first voltage signal is greater than the second voltage signal. The reference signal and the initial signal may be constant voltage signals, which are not limited in this disclosure.

[0085] Figure 4A is an equivalent circuit diagram of a pixel driving circuit for a display substrate according to another embodiment of the present disclosure. As shown in Figure 4A, the pixel driving circuit of the exemplary embodiment of the present disclosure adopts a 7T2C structure. The pixel driving circuit may include seven transistors (first transistor T1 to seventh transistor T7) and two capacitors C. The pixel driving circuit is connected to 10 signal lines (first scan signal line S1, second scan signal line S2, third scan signal line S3, fourth scan signal line S4, first light emitting signal line EM1, second light emitting signal line EM2, reference signal line REF, initial signal line INIT, data signal line DATA, and first power line VDD).

[0086] In some exemplary embodiments, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the second electrode of the first transistor T1 and the gate electrode of the third transistor T3, respectively; the second node N2 is connected to the second electrode of the fourth transistor T4 and the second end of the second capacitor C2, respectively; the third node N3 is connected to the second electrode of the third transistor T3, the second electrode of the seventh transistor T7, the second electrode of the sixth transistor T6, and the second end of the first capacitor C1, respectively; and the fourth node N4 is connected to the second electrode of the second transistor T2, the first end of the first capacitor C1, and the first end of the second capacitor C2, respectively.

[0087] In some exemplary embodiments, the first transistor T1 may be referred to as a first reset transistor, a gate electrode of the first transistor T1 is connected to the first scan signal line S1, a first electrode of the first transistor T1 is connected to the reference signal line REF, and a second electrode of the first transistor T1 is connected to the first node N1.

[0088] In some exemplary embodiments, the second transistor T2 may be referred to as a second reset transistor, a gate electrode of the second transistor T2 is connected to the second scan signal line S2, a first electrode of the second transistor T2 is connected to the reference signal line REF, and a second electrode of the second transistor T2 is connected to the fourth node N4.

[0089] In some exemplary embodiments, the third transistor T3 may be referred to as a driving transistor, a gate electrode of the third transistor T3 is connected to the first node N1, a first electrode of the third transistor T3 is connected to the second electrode of the fifth transistor T5, and a second electrode of the third transistor T3 is connected to the third node N3.

[0090] In some exemplary embodiments, the fourth transistor T4 may be referred to as a data writing transistor, a gate electrode of the fourth transistor T4 is connected to the fourth scan signal line S4, a first electrode of the fourth transistor T4 is connected to the data signal line DATA, and a second electrode of the fourth transistor T4 is connected to the second node N2.

[0091] In some exemplary embodiments, the fifth transistor T5 can be referred to as a first light emitting control transistor, a gate electrode of the fifth transistor T5 is connected to the first light emitting signal line EM1, a first electrode of the fifth transistor T5 is connected to the first power line VDD, and a second electrode of the fifth transistor T5 is connected to the first electrode of the third transistor T3.

[0092] In some exemplary embodiments, the sixth transistor T6 may be referred to as a second light emitting control transistor, a gate electrode of the sixth transistor T6 is connected to the second light emitting signal line EM2, a second electrode of the sixth transistor T6 is connected to the third node N3, and a first electrode of the sixth transistor T6 is connected to the light emitting device EL.

[0093] In some exemplary embodiments, the seventh transistor T7 may be referred to as a third reset transistor, a gate electrode of the seventh transistor T7 is connected to the third scan signal line S3, a first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and a second electrode of the seventh transistor T7 is connected to the third node N3.

[0094] In some exemplary embodiments, a first electrode of the light-emitting device EL is connected to the first electrode of the sixth transistor T6, and a second electrode of the light-emitting device EL is connected to the second power supply line VSS. The light-emitting device EL may be an OLED, including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or may be a QLED, including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode).

[0095] Figure 4B is an equivalent circuit diagram of a pixel driving circuit for a display substrate according to yet another embodiment of the present disclosure. As shown in Figure 4B , the pixel driving circuit of the exemplary embodiment of the present disclosure adopts a 5T1C structure. The pixel driving circuit may include five transistors (first transistor T1 to fifth transistor T5) and one capacitor C. The pixel driving circuit is connected to eight signal lines (a first scanning signal line S1, a second scanning signal line S2, a third scanning signal line S3, an emission signal line EM, a reference signal line REF, an initial signal line INIT, a data signal line DATA, and a first power line VDD).

[0096] In some exemplary embodiments, the pixel driving circuit may include a first node N1 and a second node N2. The first node N1 is respectively connected to the second electrode of the first transistor T1, the second electrode of the second transistor T2, the gate electrode of the fifth transistor T5, and the first end of the first capacitor C1, and the second node N2 is respectively connected to the second end of the first capacitor C1, the second electrode of the fifth transistor T5, the second electrode of the third transistor T3, and the first end of the light emitting device EL.

[0097] In some exemplary embodiments, the first transistor T1 may be referred to as a data writing transistor, a gate electrode of the first transistor T1 is connected to the first scan signal line S1, a first electrode of the first transistor T1 is connected to the data signal line DATA, and a second electrode of the first transistor T1 is connected to the first node N1.

[0098] In some exemplary embodiments, the second transistor T2 may be referred to as a first reset transistor, a gate electrode of the second transistor T2 is connected to the second scan signal line S2, a first electrode of the second transistor T2 is connected to the reference signal line REF, and a second electrode of the second transistor T2 is connected to the first node N1.

[0099] In some exemplary embodiments, the third transistor T3 may be referred to as a second reset transistor, a gate electrode of the third transistor T3 is connected to the third scan signal line S3, a second electrode of the third transistor T3 is connected to the second node N2, and a first electrode of the third transistor T3 is connected to the initial signal line INIT.

[0100] In some exemplary embodiments, the fourth transistor T4 can be called a light emitting control transistor, the gate electrode of the fourth transistor T4 is connected to the light emitting signal line EM, the first electrode of the fourth transistor T4 is connected to the first power line VDD, and the second electrode of the fourth transistor T4 is connected to the first electrode of the fifth transistor T5.

[0101] In some exemplary embodiments, the fifth transistor T5 may be referred to as a driving transistor, a gate electrode of the fifth transistor T5 is connected to the first node N1, a first electrode of the fifth transistor T5 is connected to the second electrode of the fourth transistor T4, and a second electrode of the fifth transistor T5 is connected to the second node N2.

[0102] In some exemplary embodiments, a first electrode of the light-emitting device EL is connected to the second node N2, and a second electrode of the light-emitting device EL is connected to the second power supply line VSS. The light-emitting device EL may be an OLED, including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or may be a QLED, including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode).

[0103] Figure 5 is a schematic diagram of a partial planar structure of a display substrate according to an embodiment of the present disclosure. The display substrate may include a driving circuit layer arranged on a substrate and a light-emitting structure layer arranged on a side of the driving circuit layer away from the substrate. The driving circuit layer may include at least a plurality of circuit units, the light-emitting structure layer may include at least a plurality of light-emitting units, at least one circuit unit may include a pixel driving circuit, at least one light-emitting unit may include a light-emitting device, the light-emitting device may include at least an anode, an organic light-emitting layer and a cathode, and the anode in the light-emitting unit is connected to the pixel driving circuit in the corresponding circuit unit. The position of the positive projection of the light-emitting unit on the substrate may correspond to the position of the positive projection of the circuit unit on the substrate, or the position of the positive projection of the light-emitting unit on the substrate may not correspond to the position of the positive projection of the circuit unit on the substrate.

[0104] In a plane perpendicular to the display substrate, the display substrate may include a base and a first conductive layer, a second conductive layer, a semiconductor layer, a third conductive layer, and a fourth conductive layer, sequentially located on one side of the base. The display substrate may include a compensation line 38, which may be located in the semiconductor layer. The compensation line 38 may be in the form of a straight line extending along the second direction Y. The first end of the compensation line 38 may be connected to the channel region 33-3 of the third active layer 33, and the second end of the compensation line 38 may extend along the second direction Y, and the second end of the compensation line 38 may be connected to the second end of the first region 33-1 of the third active layer. The compensation line 38 and the first region 33-1 of the third active layer may form a parallel path, which can reduce the on-resistance of the third transistor and improve the threshold voltage divergence problem of the third transistor. In the embodiment of the present disclosure, the first direction X intersects the second direction Y.

[0105] The following is an illustrative explanation of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating, and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating, or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0106] The preparation process of the display substrate may include the following steps:

[0107] (11) Forming a first conductive layer pattern. Forming the first conductive layer pattern may include: depositing a first conductive film on a substrate, and patterning the first conductive film through a patterning process to form a first conductive layer pattern on the substrate, as shown in FIG6 . In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer. The first conductive layer pattern may include at least a first plate 11 of a first capacitor, a second plate 12 of a second capacitor, and a plate connecting block 15.

[0108] In some exemplary embodiments, the first electrode plate 11 of the first capacitor may be rectangular, and the corners of the rectangle may be chamfered or grooved. The first electrode plate 11 may serve as the lower electrode plate of the first capacitor.

[0109] In some exemplary embodiments, the second plate 12 of the second capacitor can be arranged on one side of the first plate 11 in the second direction Y. The second plate 12 can be shaped like a T, and the corners of the T can be chamfered or grooved. The second plate 12 can serve as the lower plate of the second capacitor. The second plate 12 can include a first sub-plate 12-1 and a second sub-plate 12-2 connected to each other. The first sub-plate 12-1 can be shaped like a rectangle extending along the first direction X, and the second sub-plate 12-2 can be shaped like a rectangle extending along the second direction Y. The first end of the first sub-plate 12-1 can be connected to the middle of the second sub-plate 12-2. For example, the middle can be the midpoint of the second sub-plate 12-2 along the second direction Y, and the second end of the first sub-plate 12-1 extends in the opposite direction of the first direction X. The first end of the second sub-plate 12-2 can be connected to the plate connecting block 15, and the second end of the second sub-plate 12-2 extends along the second direction Y. The plate connecting block 15 can be shaped like a rectangle extending along the second direction Y.

[0110] In some exemplary embodiments, the first electrode plate 11 and the second electrode plate 12 may be an integrated structure connected to each other, that is, the lower electrode plate of the first capacitor and the lower electrode plate of the second capacitor are an integrated structure connected to each other.

[0111] In some exemplary embodiments, the first electrode plate 11 , the second electrode plate 12 , and the electrode plate connecting block 15 may be an integrated structure connected to each other, and the electrode plate connecting block 15 may be located between the first electrode plate 11 and the second electrode plate 12 .

[0112] (12) Forming a second conductive layer pattern. Forming the second conductive layer pattern may include: sequentially depositing a first insulating film and a second conductive film on the substrate having the aforementioned pattern, and patterning the second conductive film through a patterning process to form a first insulating layer covering the first conductive layer pattern and a second conductive layer pattern disposed on the first insulating layer, as shown in FIG7A and FIG7B , where FIG7B is a plan view schematic diagram of the second conductive layer in FIG7A . In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0113] In some exemplary embodiments, the second conductive layer pattern in the display substrate may include at least: a third plate 13 of the first capacitor, a fourth plate 14 of the second capacitor, a fourth bottom gate electrode 24 , a sixth bottom gate electrode 26 and a shielding line 27 .

[0114] In some exemplary embodiments, the shape of the third plate 13 of the first capacitor may be rectangular, and the corners of the rectangle may be chamfered or grooved. The orthographic projection of the third plate 13 of the first capacitor on the substrate may at least partially overlap with the orthographic projection of the first plate 11 of the first capacitor on the substrate. For example, the orthographic projection of the third plate 13 on the substrate may be located within the orthographic projection of the first plate 11 on the substrate. The third plate 13 may serve as the upper plate of the first capacitor, and the first plate 11 and the third plate 13 may together constitute the first capacitor. In some exemplary embodiments, the fourth plate 14 of the second capacitor may be arranged on one side of the second direction Y of the third plate 13. The orthographic projection of the fourth plate 14 on the substrate may at least partially overlap with the orthographic projection of the second plate 12 on the substrate. For example, the orthographic projection of the fourth plate 14 on the substrate may be located within the orthographic projection of the second plate 12 on the substrate. In an exemplary embodiment, the second plate 12 and the fourth plate 14 may together constitute the second capacitor.

[0115] In some exemplary embodiments, the fourth plate 14 may include a first sub-block 14-1, a second sub-block 14-2, and a third sub-block 14-3. The first sub-block 14-1 may be rectangular and extend along the first direction X, the second sub-block 14-2 may be rectangular and extend along the second direction Y, and the third sub-block 14-3 may be rectangular and extend along the second direction Y. The first end of the first sub-block 14-1 may be connected to the middle of the second sub-block 14-2 (for example, the middle may be the center of the second sub-block 14-2 along the second direction Y), and the second end of the first sub-block 14-1 may extend in the opposite direction of the first direction X. The first end of the third sub-block 14-3 may be connected to the first end of the second sub-block 14-2, and the second end of the third sub-block 14-3 may extend in the opposite direction of the second direction Y. The second end of the second sub-block 14-2 may extend in the second direction Y.

[0116] In some exemplary embodiments, the fourth bottom-gate electrode 24 may be rectangular in shape. The fourth bottom-gate electrode 24 may be disposed on a side of the second sub-block 14-2 opposite to the first direction X. The fourth bottom-gate electrode 24 may serve as the bottom gate electrode of the fourth transistor T4 and as a shielding layer for the fourth transistor T4, shielding the channel region of the fourth transistor T4 and ensuring the electrical performance of the fourth transistor T4.

[0117] In some exemplary embodiments, a fourth bottom gate connection block 24-1 may be provided on the fourth bottom gate electrode 24. The fourth bottom gate connection block 24-1 may be block-shaped (e.g., rectangular) and may be provided on a side of the fourth bottom gate electrode 24 close to the sixth bottom gate electrode 26 and connected to the fourth bottom gate electrode 24. The fourth bottom gate connection block 24-1 may be configured to be connected to a third scan signal line formed subsequently.

[0118] In some exemplary embodiments, the sixth bottom-gate electrode 26 may be rectangular in shape and may be disposed on a side of the first sub-block 14-1 opposite to the second direction Y, and on a side of the fourth bottom-gate electrode 24 opposite to the second direction Y. The sixth bottom-gate electrode 26 may serve as the bottom gate electrode of the sixth transistor T6 and may also serve as a shielding layer for the sixth transistor T6, thereby shielding the channel region of the sixth transistor T6 and ensuring the electrical performance of the sixth transistor T6.

[0119] In some exemplary embodiments, the shielding line 27 may be in the shape of a straight line or a broken line extending along the first direction X, and may be disposed on the side of the fourth electrode plate 14 away from the third electrode plate 13. In some exemplary embodiments, the shielding line 27 may be a straight line of unequal width, and the width of the shielding line 27 at the location where it overlaps with the subsequently formed fifth active layer may be greater than the width at other locations. The shielding line 27 at the wider location may serve as a shielding layer for the fifth transistor T5, and may be used to shield the channel region of the fifth transistor T5, thereby ensuring the electrical performance of the fifth transistor T5. In some possible exemplary embodiments, the shielding line 27 may serve as the bottom gate electrode of the fifth transistor T5.

[0120] (13) Forming a semiconductor layer pattern. Forming the semiconductor layer pattern may include: depositing a second insulating film and a semiconductor film in sequence on the substrate on which the aforementioned pattern is formed, patterning the semiconductor film through a patterning process to form a second insulating layer covering the second conductive layer, and a semiconductor layer pattern disposed on the second insulating layer, as shown in FIG8A and FIG8B , where FIG8B is a plan view schematic diagram of the semiconductor layer in FIG8A .

[0121] In some exemplary embodiments, the semiconductor layer pattern in the display substrate may include at least the third active layer 33 of the third transistor T3 to the sixth active layer 36 of the sixth transistor T6. The third active layer 33 and the fifth active layer 35 may be interconnected as a single unitary structure, and the fourth active layer 34 and the sixth active layer 36 may be interconnected as a single unitary structure. In the first direction X, the fourth active layer 34 and the sixth active layer 36 may be located on one side of the third active layer 33 and the fifth active layer 35 opposite to the first direction X. The fourth active layer 34 may be located on one side of the sixth active layer 36 in the second direction Y, and the fifth active layer 35 may be located on one side of the third active layer 33 in the second direction Y. In some exemplary embodiments, the active layer of each transistor may include a first region, a second region, and a channel region located between the first and second regions. The orthographic projection of the third active layer 33 on the substrate may at least partially overlap with the orthographic projection of the third electrode plate 13 on the substrate, and the overlapping region may serve as the channel region of the third transistor T3. The orthographic projection of the fourth active layer 34 on the substrate may at least partially overlap with the orthographic projection of the fourth bottom-gate electrode 24 on the substrate, with the overlapping region serving as the channel region of the fourth transistor T4. The orthographic projection of the fifth active layer 35 on the substrate may at least partially overlap with the orthographic projection of the shielding line 27 on the substrate, with the overlapping region serving as the channel region of the fifth transistor T5. In some exemplary embodiments, the orthographic projection of the sixth active layer 36 on the substrate may at least partially overlap with the orthographic projection of the sixth bottom-gate electrode 26 on the substrate, with the overlapping region serving as the channel region of the sixth transistor T6.

[0122] In some exemplary embodiments, the first region 33-1 of the third active layer and the second region 35-2 of the fifth active layer may be interconnected, and the first region 33-1 of the third active layer may serve as the second region 35-2 of the fifth active layer. The second region 34-2 of the fourth active layer and the second region 36-2 of the sixth active layer may be interconnected, and the second region 34-2 of the fourth active layer may serve as the second region 36-2 of the sixth active layer. The first region 34-1 of the fourth active layer 34 and the first region 35-1 of the fifth active layer 35 may be provided separately. The first region 36-1 and the second region 36-2 of the sixth active layer are located on either side of the channel region of the sixth active layer along the second direction Y.

[0123] In some exemplary embodiments, the channel region 33-3 of the third active layer may be rectangular, and the corners of the rectangle may be chamfered or grooved. The channel region 33-3 of the third active layer has a first width W1 along the first direction X. In the disclosed embodiment, the first width W1 is the average width of the channel region 33-3 of the third active layer along the first direction X. The first region 33-1 of the third active layer is located on one side of the channel region 33-3 of the third active layer in the second direction Y. The first end of the first region 33-1 of the third active layer is connected to the channel region 33-3 of the third active layer, and the second end of the first region 33-1 of the third active layer extends along the second direction Y. The first region 33-1 of the third active layer has a second width W2 along the first direction X. In the disclosed embodiment, the second width W2 is the average width of the first region 33-1 of the third active layer along the first direction X. The absolute value of the difference between the first width W1 and the second width W2 is less than or equal to 10% of the first width W1. By limiting the difference between the first width W1 and the second width W2, the problem of threshold voltage divergence of the third transistor can be avoided, thereby improving the performance of the third transistor. In some examples, the first region of the third active layer and the second region of the third active layer can be interchangeable.

[0124] Table 1 below compares multiple performance parameters of two pixel driving circuits. In the embodiment of the present disclosure, "W1 equals W2" means that the first width W1 of the pixel driving circuit is equal to the second width W2, or the absolute value of the difference between the first width W1 and the second width W2 is greater than zero and less than or equal to 10% of the first width W1. In other words, in Table 1, "W1 equals W2" means that they are approximately equal. In the embodiment of the present disclosure, "W1 not equals W2" means that the absolute value of the difference between the first width W1 and the second width W2 of the pixel driving circuit is greater than 10% of the first width W1.

[0125] Table 1

[0126] As shown in Table 1 above, the pixel driver circuit with W1 equal to W2 performs better than the pixel driver circuit with W1 not equal to W2. The second width W2 is relatively small, resulting in a correspondingly large line resistance. When the third transistor is turned on, the current must pass through a channel with a relatively large line resistance. Due to the blocking effect of the channel, the number of carriers is reduced, resulting in poor conduction between the first and second regions of the third transistor. This shifts the threshold voltage positively, and the electron mobility (Mob) and on-state current (Ion) decrease. The second width W2 is relatively large, resulting in a correspondingly small line resistance. When the third transistor is turned on, the current must pass through a channel with a relatively small line resistance. Due to the relatively reduced blocking effect of the channel, the number of carriers is less affected, making conduction between the first and second regions of the third transistor easier. This shifts the threshold voltage slightly negatively, and improves the electron mobility (Mob) and on-state current (Ion). As shown in Table 1, the electron mobility (Mob) increases from 0.11 to 4.31, and the average on-state current (Ion) increases by two orders of magnitude.

[0127] In some exemplary embodiments, the first region 33 - 1 of the third active layer and the second region of the third active layer may be symmetrical with respect to the channel region 33 - 3 of the third active layer.

[0128] In some exemplary embodiments, the semiconductor layer pattern in the display substrate may include a compensation line 38, which may be a straight line extending along the second direction Y. The compensation line 38 is located on one side of the channel region 33-3 of the third active layer 33 in the second direction Y. A first end of the compensation line 38 may be connected to the channel region 33-3 of the third active layer 33, and a second end of the compensation line 38 extends along the second direction Y and is connected to the second end of the first region 33-1 of the third active layer. The compensation line 38 and the first region 33-1 of the third active layer may form a parallel path, which can reduce the on-resistance of the third transistor and improve the threshold voltage divergence of the third transistor.

[0129] In some exemplary embodiments, the orthographic projection of the compensation line 38 on the substrate does not overlap with the orthographic projection of the fourth electrode plate 14 on the substrate, and the orthographic projection of the compensation line 38 on the substrate does not overlap with the orthographic projection of the second electrode plate 12 on the substrate. This can avoid the adverse effect of the step difference formed at the edge of the fourth electrode plate and the second electrode plate on the compensation line, avoid the compensation line from breaking at the step formed at the edge of the fourth electrode plate and the second electrode plate, and improve the stability of the pixel driving circuit performance.

[0130] In some exemplary embodiments, the semiconductor layer pattern in the display substrate may further include a first connection bridge 38-1. The first connection bridge 38-1 may be rectangular and extend along the first direction X. A first end of the first connection bridge 38-1 may be connected to the second end of the compensation line 38, and a second end of the first connection bridge 38-1 may extend in a direction opposite to the first direction X. The second end of the first connection bridge 38-1 may be connected to the second end of the first region 33-1 of the third active layer.

[0131] In some exemplary embodiments, the semiconductor layer pattern in the display substrate may further include a second connecting bridge 38-2. The second connecting bridge 38-2 may be located between the first connecting bridge 38-1 and the channel region 33-3 of the third active layer 33, and may also be located between the first region 33-1 of the third active layer and the compensation line 38. The second connecting bridge 38-2 may be rectangular in shape, with a first end connected to the compensation line 38, and a second end extending in a direction opposite to the first direction X, and may be connected to the first region 33-1 of the third active layer.

[0132] In some possible exemplary embodiments, the semiconductor layer pattern in the display substrate may further include a plurality of second connection bridges 38-2. The plurality of second connection bridges 38-2 may be spaced apart along the second direction Y. For example, the plurality of second connection bridges 38-2 may be spaced evenly apart along the second direction Y. In the disclosed embodiment, the provision of the plurality of second connection bridges improves the reliability of the connection between the compensation line and the first region of the third active layer.

[0133] In some possible exemplary embodiments, the semiconductor layer pattern in the display substrate may include at least a third active layer 33 of the third transistor T3, a fourth active layer 34 of the fourth transistor T4, and a fifth active layer 35 of the fifth transistor T5. The third active layer 33 and the fifth active layer 35 may be an interconnected, integral structure. In the first direction X, the fourth active layer 34 may be located on a side of the third active layer 33 and the fifth active layer 35 opposite to the first direction X. The fifth active layer 35 may be located on a side of the third active layer 33 in the second direction Y.

[0134] In some exemplary embodiments, the semiconductor layer may be made of oxide, i.e., the third transistor T3 to the sixth transistor T6 are oxide transistors. Oxide transistors have advantages such as high electron mobility, low operating voltage, and low leakage. The oxide may be any one or more of the following: indium gallium zinc oxide (InGaZnO), indium gallium zinc oxynitride (InGaZnON), zinc oxide (ZnO), zinc oxynitride (ZnON), zinc tin oxide (ZnSnO), cadmium tin oxide (CdSnO), gallium tin oxide (GaSnO), titanium tin oxide (TiSnO), copper aluminum oxide (CuAlO), strontium copper oxide (SrCuO), lanthanum copper oxysulfide (LaCuOS), gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), indium gallium zinc oxide (IGZO), and indium gallium aluminum nitride (InGaAlN).

[0135] (14) Forming a third conductive layer pattern. Forming the third conductive layer pattern may include: sequentially depositing a third insulating film and a third conductive film on the substrate having the aforementioned pattern formed thereon, patterning the third conductive film through a patterning process to form a third insulating layer covering the semiconductor layer pattern, and a third conductive layer pattern disposed on the third insulating layer, as shown in FIG9A and FIG9B , where FIG9B is a schematic diagram of the third conductive layer in FIG9A . In an exemplary embodiment, the third conductive layer may be referred to as a third gate metal (GATE3) layer.

[0136] In some exemplary embodiments, the third conductive layer pattern in the display substrate may include at least a third top gate electrode 43 , a fourth top gate electrode 44 , a sixth top gate electrode 46 and a light emitting signal line 48 .

[0137] In some exemplary embodiments, the shape of the third top gate electrode 43 can be a rectangle extending along the first direction X, the orthographic projection of the third top gate electrode 43 on the substrate can at least partially overlap with the orthographic projection of the third active layer 33 on the substrate, and the third top gate electrode 43 can serve as the top gate electrode of the third transistor T3.

[0138] In some exemplary embodiments, the fourth top-gate electrode 44 may be rectangular in shape, and the orthographic projection of the fourth top-gate electrode 44 on the substrate at least partially overlaps with the orthographic projection of the fourth active layer 34 on the substrate. The fourth top-gate electrode 44 may serve as the top-gate electrode of the fourth transistor T4. The orthographic projection of the fourth top-gate electrode 44 on the substrate at least partially overlaps with the orthographic projection of the fourth bottom-gate electrode 24 on the substrate. The fourth top-gate electrode 44 and the fourth bottom-gate electrode 24 form the fourth transistor T4 with a top-gate and bottom-gate structure.

[0139] In some exemplary embodiments, a fourth top gate connection block 44-1 may be provided on the fourth top gate electrode 44. The fourth top gate connection block 44-1 may be in a block shape, such as a rectangular block or a hexagonal block. The fourth top gate connection block 44-1 may be provided on a side of the fourth top gate electrode 44 away from the fifth transistor T5, and the fourth top gate connection block 44-1 is connected to the fourth top gate electrode 44. The fourth top gate connection block 44-1 is configured to be connected to a third scan signal line formed subsequently.

[0140] In some exemplary embodiments, the sixth top-gate electrode 46 may be rectangular in shape. The orthographic projection of the sixth top-gate electrode 46 on the substrate at least partially overlaps with the orthographic projection of the sixth active layer 36 on the substrate. The sixth top-gate electrode 46 may serve as the top-gate electrode of the sixth transistor T6. The orthographic projection of the sixth top-gate electrode 46 on the substrate at least partially overlaps with the orthographic projection of the sixth bottom-gate electrode 26 on the substrate. The sixth top-gate electrode 46 and the sixth bottom-gate electrode 26 form a sixth transistor T6 with a top-gate and bottom-gate structure.

[0141] In some exemplary embodiments, a sixth top gate connection block 46-1 may be provided on the sixth top gate electrode 46. The sixth top gate connection block 46-1 may be in a block shape, such as a rectangular block or a hexagonal block. The sixth top gate connection block 46-1 may be provided on a side of the sixth top gate electrode 46 close to the third transistor T3, and the sixth top gate connection block 46-1 is connected to the sixth top gate electrode 46. The sixth top gate connection block 46-1 is configured to be connected to a fourth scan signal line formed subsequently.

[0142] In some exemplary embodiments, the shape of the light-emitting signal line 48 can be a straight line or a broken line extending along the first direction X, and can be arranged on one side of the fourth electrode 14 in the second direction Y. The light-emitting signal line 48 can at least partially overlap with the fifth active layer 35, and the overlapping area can serve as the top gate electrode of the fifth transistor T5.

[0143] In some exemplary embodiments, the light-emitting signal line 48 may be a straight line of unequal width, and the width of the light-emitting signal line 48 at the location where it overlaps with the fifth active layer 35 may be greater than the width at other locations. The orthographic projection of the light-emitting signal line 48 on the substrate may at least partially overlap with the orthographic projection of the shielding line 27 on the substrate. The light-emitting signal line 48 and the shielding line 27 may be connected to the same signal source, so that the shielding line 27 can serve as the bottom gate electrode of the fifth transistor T5, and the light-emitting signal line 48 can serve as the top gate electrode of the fifth transistor T5, forming a top-gate and bottom-gate structure of the fifth transistor T5.

[0144] In some exemplary embodiments, after forming the third conductive layer pattern, the third conductive layer can be used as a shield to perform conductorization on the semiconductor layer. The semiconductor layer in the area shielded by the third conductive layer forms the channel region of the third transistor T3 to the sixth transistor T6, and the semiconductor layer in the area not shielded by the third conductive layer is conductorized.

[0145] (15) Forming a fourth insulating layer pattern. Forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the third conductive layer, wherein a plurality of vias are provided on the fourth insulating layer, as shown in FIG. 10 .

[0146] In some exemplary embodiments, the plurality of via holes in the display substrate may include at least a first via hole V1, a second via hole V2, a third via hole V3, a fourth via hole V4, a fifth via hole V5, a sixth via hole V6, a seventh via hole V7, an eighth via hole V8, a ninth via hole V9 and a tenth via hole V10.

[0147] In some exemplary embodiments, the orthographic projection of the first via hole V1 on the substrate may be located within the orthographic projection of the first region 35-1 of the fifth active layer on the substrate. The third insulating layer and the fourth insulating layer within the first via hole V1 are both etched away, exposing the surface of the first region 35-1 of the fifth active layer. The first via hole V1 is configured so that a subsequently formed power connection line can be connected to the first region 35-1 of the fifth active layer through the via hole.

[0148] In some exemplary embodiments, the orthographic projection of the second via hole V2 on the substrate may be located within the orthographic projection of the first region 34-1 of the fourth active layer on the substrate. The third and fourth insulating layers within the second via hole V2 are both etched away, exposing the surface of the first region 34-1 of the fourth active layer. The second via hole V2 is configured such that a subsequently formed first connection electrode can be connected to the first region 34-1 of the fourth active layer through the via hole.

[0149] In some exemplary embodiments, the orthographic projection of the third via hole V3 on the substrate may be within the range of the orthographic projection of the fourth top gate connection block 44-1 on the substrate, and the fourth insulating layer within the third via hole V3 is etched away, exposing the surface of the fourth top gate connection block 44-1. The third via hole V3 is configured so that a subsequently formed third scan signal line can be connected to the fourth top gate connection block 44-1 through the via hole.

[0150] In some exemplary embodiments, the orthographic projection of the fourth via hole V4 on the substrate may be within the range of the orthographic projection of the fourth bottom gate connection block 24-1 on the substrate. The second insulating layer, the third insulating layer, and the fourth insulating layer within the fourth via hole V4 are all etched away, exposing the surface of the fourth bottom gate connection block 24-1. The fourth via hole V4 is configured so that a subsequently formed third scan signal line can be connected to the fourth bottom gate connection block 24-1 through the via hole.

[0151] In some exemplary embodiments, the orthographic projection of the fifth via hole V5 on the substrate may be located within the orthographic projection of the second region 36-2 of the sixth active layer (also the second region 34-2 of the fourth active layer) on the substrate. The third insulating layer and the fourth insulating layer within the fifth via hole V5 are both etched away, exposing the surface of the second region 36-2 of the sixth active layer (also the second region 34-2 of the fourth active layer). The fifth via hole V5 is configured so that a subsequently formed second connection electrode can be connected to the second region 36-2 of the sixth active layer (also the second region 34-2 of the fourth active layer) through the via hole.

[0152] In some exemplary embodiments, the orthographic projection of the sixth via hole V6 on the substrate may be within the range of the orthographic projection of the fourth electrode plate 14 on the substrate, and the second insulating layer, the third insulating layer, and the fourth insulating layer within the sixth via hole V6 are all etched away, exposing the surface of the fourth electrode plate 14. The sixth via hole V6 is configured such that a subsequently formed second connection electrode can be connected to the fourth electrode plate 14 through the via hole.

[0153] In some exemplary embodiments, the orthographic projection of the seventh via hole V7 on the substrate may be located within the range of the orthographic projection of the sixth bottom-gate electrode 26 on the substrate. The second insulating layer, the third insulating layer, and the fourth insulating layer within the seventh via hole V7 are all etched away, exposing the surface of the sixth bottom-gate electrode 26. The seventh via hole V7 is configured such that a subsequently formed fourth scan signal line can be connected to the sixth bottom-gate electrode 26 through the via hole.

[0154] In some exemplary embodiments, the orthographic projection of the eighth via hole V8 on the substrate may be within the range of the orthographic projection of the sixth top gate connection block 46-1 on the substrate. The fourth insulating layer within the eighth via hole V8 is etched away, exposing the surface of the sixth top gate connection block 46-1. The eighth via hole V8 is configured so that a subsequently formed fourth scan signal line can be connected to the sixth top gate connection block 46-1 through the via hole.

[0155] In some exemplary embodiments, the orthographic projection of the ninth via hole V9 on the substrate may be located within the orthographic projection of the first region 36-1 of the sixth active layer on the substrate. The third insulating layer and the fourth insulating layer within the ninth via hole V9 are both etched away, exposing the surface of the first region 36-1 of the sixth active layer. The ninth via hole V9 is configured such that a subsequently formed third connection electrode can be connected to the first region 36-1 of the sixth active layer through the ninth via hole.

[0156] In some exemplary embodiments, the orthographic projection of the tenth via hole V10 on the substrate may be located within the range of the orthographic projection of the third top gate electrode 43 on the substrate, and the fourth insulating layer within the tenth via hole V10 is etched away, exposing the surface of the third top gate electrode 43. The tenth via hole V10 is configured such that a subsequently formed third connection electrode can be connected to the third top gate electrode 43 through the via hole.

[0157] (16) Forming a fourth conductive layer pattern. Forming the fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on the fourth insulating layer, as shown in FIG. 11A and FIG. 11B , where FIG. 11B is a plan view schematic diagram of the fourth conductive layer in FIG. 11A . In an exemplary embodiment, the fourth conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0158] In some exemplary embodiments, the fourth conductive layer may include at least a power connection line 50 , a first connection electrode 51 , a second connection electrode 52 , a third connection electrode 53 , a third scan signal line 54 , and a fourth scan signal line 55 .

[0159] In some exemplary embodiments, the power connection line 50 may be located on one side of the light-emitting signal line 48 in the second direction Y. The power connection line 50 may be in the shape of a straight line or a broken line extending along the first direction X. The orthographic projection of the power connection line 50 on the substrate may at least partially overlap with the orthographic projection of the first region of the fifth active layer on the substrate. The orthographic projection of the power connection line 50 on the substrate may include the orthographic projection of the first via V1 on the substrate. The power connection line 50 may be connected to the first region of the fifth active layer through the first via V1.

[0160] In some exemplary embodiments, the first connection electrode 51 may be located between the power connection line 50 and the fourth top gate connection block 44-1. The first connection electrode 51 may be rectangular in shape. The orthographic projection of the first connection electrode 51 on the substrate may partially overlap with the orthographic projection of the light-emitting signal line 48 on the substrate. The orthographic projection of the first connection electrode 51 on the substrate may partially overlap with the orthographic projection of the first region of the fourth active layer on the substrate. The orthographic projection of the first connection electrode 51 on the substrate may include the orthographic projection of the second via V2 on the substrate. The first connection electrode 51 may be connected to the first region of the fourth active layer through the second via V2.

[0161] In some exemplary embodiments, the third scan signal line 54 may be located on a side of the first connection electrode 51 opposite to the second direction Y. The orthographic projection of the third scan signal line 54 on the substrate at least partially overlaps with the orthographic projections of the fourth top gate connection block 44-1 and the fourth bottom gate connection block 24-1 on the substrate. The third scan signal line 54 is connected to the fourth top gate connection block 44-1 via a third via V3 and to the fourth bottom gate connection block 24-1 via a fourth via V4. Because the fourth top gate connection block 44-1 is connected to the fourth top gate electrode 44 and the fourth bottom gate connection block 24-1 is connected to the fourth bottom gate electrode 24, the third scan signal line 54 is simultaneously connected to the bottom gate electrode and the top gate electrode of the fourth transistor T4. The third scan signal line 54 can control the conduction or disconnection of the fourth transistor T4.

[0162] In some exemplary embodiments, the third scan signal line 54 may include a first connecting block 54-1, a second connecting block 54-2, and a main body 54-3. The main body 54-3 may be linear and extend along a first direction X. A first end of the first connecting block 54-1 may be connected to the main body 54-3, and a second end of the first connecting block 54-1 may extend along a second direction Y. The orthographic projection of the first connecting block 54-1 on the substrate may include the orthographic projection of a third via V3 on the substrate. The first connecting block 54-1 may be connected to the fourth top gate connecting block 44-1 via the third via V3. A first end of the second connecting block 54-2 may be connected to the main body 54-3, and a second end of the second connecting block 54-2 may extend in a direction opposite to the second direction Y. The orthographic projection of the second connecting block 54-2 on the substrate may include the orthographic projection of a fourth via V4 on the substrate. The second connecting block 54-2 may be connected to the fourth bottom gate connecting block 24-1 via the fourth via V4.

[0163] In some exemplary embodiments, the second connection electrode 52 may be rectangular in shape and may be located on a side of the third scan signal line 54 opposite to the second direction Y. The orthographic projection of the second connection electrode 52 on the substrate may include the orthographic projection of the fifth via hole V5 on the substrate, and the orthographic projection of the second connection electrode 52 on the substrate may include the orthographic projection of the sixth via hole V6 on the substrate. The second connection electrode 52 may be connected to the second region of the sixth active layer through the fifth via hole V5, and the second connection electrode 52 may be connected to the fourth electrode plate through the sixth via hole V6.

[0164] In some exemplary embodiments, the fourth scan signal line 55 may be in the shape of a straight line or a zigzag line extending along the first direction X. The fourth scan signal line 55 may be located on the side of the second connection electrode 52 opposite to the second direction Y. The orthographic projection of the fourth scan signal line 55 on the substrate at least partially overlaps with the orthographic projections of the sixth top gate connection block 46-1 and the sixth bottom gate electrode 26 on the substrate. The fourth scan signal line 55 is connected to the sixth bottom gate electrode 26 via the seventh via V7 and to the sixth top gate connection block 46-1 via the eighth via V8. Since the sixth top gate connection block 46-1 is connected to the sixth top gate electrode 46, the fourth scan signal line 55 is simultaneously connected to the bottom gate electrode and the top gate electrode of the sixth transistor T6. The fourth scan signal line 55 can control the conduction or disconnection of the sixth transistor T6.

[0165] In some exemplary embodiments, the third connection electrode 53 may be rectangular in shape and may be located on a side of the fourth scan signal line 55 opposite to the second direction Y. The orthographic projection of the third connection electrode 53 on the substrate may include the orthographic projection of the ninth via hole V9 on the substrate, and the orthographic projection of the third connection electrode 53 on the substrate may include the orthographic projection of the tenth via hole V10 on the substrate. The third connection electrode 53 may be connected to the first region of the sixth active layer through the ninth via hole V9, and the third connection electrode 53 may be connected to the third top gate electrode through the tenth via hole V10.

[0166] Figure 12 is a schematic diagram of a partial planar structure of a display substrate according to another embodiment of the present disclosure. In a plane perpendicular to the display substrate, the display substrate may include a substrate and a first conductive layer, a second conductive layer, a semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer, sequentially located on one side of the substrate. A compensation line 38 may be located in the fifth conductive layer, and the orthographic projection of the compensation line 38 on the substrate may include the orthographic projection of the first region 33-1 of the third active layer on the substrate. The compensation line 38 and the first region 33-1 of the third active layer may form a parallel path, which may reduce the on-resistance of the third transistor and improve the threshold voltage divergence problem of the third transistor.

[0167] The preparation process of the display substrate may include the following steps:

[0168] (21) A first conductive layer pattern and a second conductive layer pattern are sequentially formed on the substrate. For reference, the aforementioned embodiment may be referred to and will not be described in detail here.

[0169] (22) Forming a semiconductor layer pattern. Forming the semiconductor layer pattern may include: depositing a second insulating film and a semiconductor film in sequence on the substrate on which the aforementioned pattern is formed, patterning the semiconductor film through a patterning process to form a second insulating layer covering the second conductive layer, and a semiconductor layer pattern disposed on the second insulating layer, as shown in FIG13A and FIG13B , where FIG13B is a plan view schematic diagram of the semiconductor layer in FIG13A .

[0170] In some exemplary embodiments, the semiconductor layer pattern in the display substrate may include at least the third active layer 33 of the third transistor T3 to the sixth active layer 36 of the sixth transistor T6. The third active layer 33 and the fifth active layer 35 may be interconnected as a single unitary structure, and the fourth active layer 34 and the sixth active layer 36 may be interconnected as a single unitary structure. In the first direction X, the fourth active layer 34 and the sixth active layer 36 may be located on a side of the third active layer 33 and the fifth active layer 35 opposite to the first direction X. The fourth active layer 34 may be located on a side of the sixth active layer 36 in the second direction Y, and the fifth active layer 35 may be located on a side of the third active layer 33 in the second direction Y.

[0171] In some exemplary embodiments, the active layer of each transistor may include a first region, a second region, and a channel region located between the first region and the second region. The orthographic projection of the third active layer 33 on the substrate may at least partially overlap with the orthographic projection of the third electrode 13 on the substrate, and the overlapping region may serve as the channel region of the third transistor T3. The orthographic projection of the fourth active layer 34 on the substrate may at least partially overlap with the orthographic projection of the fourth bottom gate electrode 24 on the substrate, and the overlapping region may serve as the channel region of the fourth transistor T4. The orthographic projection of the fifth active layer 35 on the substrate may at least partially overlap with the orthographic projection of the shielding line 27 on the substrate, and the overlapping region may serve as the channel region of the fifth transistor T5. The orthographic projection of the sixth active layer 36 on the substrate may at least partially overlap with the orthographic projection of the sixth bottom gate electrode 26 on the substrate, and the overlapping region may serve as the channel region of the sixth transistor T6.

[0172] In some exemplary embodiments, the first region 33-1 of the third active layer and the second region 35-2 of the fifth active layer may be interconnected, and the first region 33-1 of the third active layer may serve as the second region 35-2 of the fifth active layer. The second region 34-2 of the fourth active layer and the second region 36-2 of the sixth active layer may be interconnected, and the second region 34-2 of the fourth active layer may serve as the second region 36-2 of the sixth active layer. The first region 34-1 of the fourth active layer 34 and the first region 35-1 of the fifth active layer 35 may be provided separately. The first region 36-1 and the second region 36-2 of the sixth active layer are located on either side of the channel region of the sixth active layer along the second direction Y.

[0173] In some exemplary embodiments, the channel region 33-3 of the third active layer may be rectangular, and the corners of the rectangle may be chamfered or grooved. The channel region 33-3 of the third active layer has a first width W1 along the first direction X. The first region 33-1 of the third active layer is located on one side of the channel region 33-3 of the third active layer in the second direction Y. The first end of the first region 33-1 of the third active layer is connected to the channel region 33-3 of the third active layer, and the second end of the first region 33-1 of the third active layer extends along the second direction Y. The first region 33-1 of the third active layer has a second width W2 along the first direction X. The second width W2 is less than the first width W1.

[0174] In some possible exemplary embodiments, the semiconductor layer pattern in the display substrate may include at least a third active layer 33 of the third transistor T3, a fourth active layer 34 of the fourth transistor T4, and a fifth active layer 35 of the fifth transistor T5. The third active layer 33 and the fifth active layer 35 may be an interconnected, integral structure. In the first direction X, the fourth active layer 34 may be located on a side of the third active layer 33 and the fifth active layer 35 opposite to the first direction X. The fifth active layer 35 may be located on a side of the third active layer 33 in the second direction Y.

[0175] (23) The third conductive layer pattern is formed. Please refer to the above embodiment and will not be elaborated here.

[0176] (24) Forming a fourth insulating layer pattern. Forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the third conductive layer, wherein the fourth insulating layer is provided with a plurality of vias, as shown in FIG. 14 .

[0177] In some exemplary embodiments, the plurality of via holes in the display substrate may include at least a first via hole V1, a second via hole V2, a third via hole V3, a fourth via hole V4, a fifth via hole V5, a sixth via hole V6, a seventh via hole V7, an eighth via hole V8, a ninth via hole V9, a tenth via hole V10, an eleventh via hole V11, and a twelfth via hole V12. The first through tenth via holes V1 to V10 may refer to the aforementioned embodiments and are not further described here.

[0178] In some exemplary embodiments, the orthographic projection of the eleventh via hole V11 on the substrate may be located within the orthographic projection of the first region 33-1 of the third active layer on the substrate. The third insulating layer and the fourth insulating layer within the eleventh via hole V11 are both etched away, exposing the surface of the first region 33-1 of the third active layer. The eleventh via hole V11 is configured such that a subsequently formed first bridging electrode can be connected to the first end of the first region 33-1 of the third active layer through the via hole.

[0179] In some exemplary embodiments, the orthographic projection of the twelfth via hole V12 on the substrate may be located within the orthographic projection of the first region 33-1 of the third active layer on the substrate. The third insulating layer and the fourth insulating layer within the twelfth via hole V12 are both etched away, exposing the surface of the first region 33-1 of the third active layer. The twelfth via hole V12 is configured such that a subsequently formed second bridging electrode can be connected to the second end of the first region 33-1 of the third active layer through the via hole.

[0180] (25) Forming a fourth conductive layer pattern. Forming the fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on the fourth insulating layer, as shown in FIG15A and FIG15B , where FIG15B is a plan view schematic diagram of the fourth conductive layer in FIG15A . In an exemplary embodiment, the fourth conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0181] In some exemplary embodiments, the fourth conductive layer may include at least a power connection line 50, a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a third scan signal line 54, a fourth scan signal line 55, a first bridge electrode 56, and a second bridge electrode 57. The power connection line 50, the first connection electrode 51, the second connection electrode 52, the third connection electrode 53, the third scan signal line 54, and the fourth scan signal line 55 can be described with reference to the previous embodiment and will not be further described here.

[0182] In some exemplary embodiments, the first bridging electrode 56 may be rectangular in shape and may be located between the third connection electrode 53 and the fourth scan signal line 55. An orthographic projection of the first bridging electrode 56 on the substrate may include an orthographic projection of an eleventh via hole V11 on the substrate, and the first bridging electrode 56 may be connected to the first end of the first region of the third active layer through the eleventh via hole V11.

[0183] In some exemplary embodiments, the second bridging electrode 57 may be rectangular in shape and may be located between the power connection line 50 and the third scan signal line 54. An orthographic projection of the second bridging electrode 57 on the substrate may include an orthographic projection of a twelfth via hole V12 on the substrate, and the second bridging electrode 57 may be connected to the second end of the first region of the third active layer through the twelfth via hole V12.

[0184] (26) Forming a fifth insulating layer pattern. Forming the fifth insulating layer pattern may include: depositing a fifth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fifth insulating film using a patterning process to form a fifth insulating layer covering the fourth conductive layer, wherein the fifth insulating layer is provided with a plurality of vias, as shown in FIG16 .

[0185] In some exemplary embodiments, the plurality of via holes in the display substrate may include at least a twenty-first via hole V21 , a twenty-second via hole V22 , a twenty-third via hole V23 , and a twenty-fourth via hole V24 .

[0186] In some exemplary embodiments, the orthographic projection of the twenty-first via hole V21 on the substrate may be within the range of the orthographic projection of the first bridging electrode 56 on the substrate, and the fifth insulating layer within the twenty-first via hole V21 is etched away, exposing the surface of the first bridging electrode 56. The twenty-first via hole V21 is configured such that a subsequently formed compensation line can be connected to the first bridging electrode 56 through the via hole.

[0187] In some exemplary embodiments, the orthographic projection of the twenty-second via hole V22 on the substrate may be within the range of the orthographic projection of the second bridging electrode 57 on the substrate, and the fifth insulating layer within the twenty-second via hole V22 is etched away, exposing the surface of the second bridging electrode 57. The twenty-second via hole V22 is configured such that a subsequently formed compensation line can be connected to the second bridging electrode 57 through the via hole.

[0188] In some exemplary embodiments, the orthographic projection of the twenty-third via hole V23 on the substrate may be located within the range of the orthographic projection of the power connection line 50 on the substrate, and the fifth insulating layer within the twenty-third via hole V23 is etched away, exposing the surface of the power connection line 50. The twenty-third via hole V23 is configured such that a subsequently formed first power line can be connected to the power connection line 50 through the via hole.

[0189] In some exemplary embodiments, the orthographic projection of the twenty-fourth via hole V24 on the substrate may be located within the range of the orthographic projection of the first connection electrode 51 on the substrate, and the fifth insulating layer within the twenty-fourth via hole V24 is etched away, exposing the surface of the first connection electrode 51. The twenty-fourth via hole V24 is configured such that a subsequently formed data signal line can be connected to the first connection electrode 51 through the via hole.

[0190] (27) Forming a fifth conductive layer pattern. Forming the fifth conductive layer pattern may include: depositing a fifth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fifth conductive film using a patterning process to form a fifth conductive layer disposed on the fifth insulating layer, as shown in FIG17A and FIG17B , where FIG17B is a plan view schematic diagram of the fifth conductive layer in FIG17A . In an exemplary embodiment, the fifth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0191] In some exemplary embodiments, the fourth conductive layer may include at least a data signal line 61, a first power line 62, and a compensation line 38. The first power line 62 may be located between the data signal line 61 and the compensation line 38. The data signal line 61, the first power line 62, and the compensation line 38 may be straight lines extending along the second direction Y.

[0192] In some exemplary embodiments, the orthographic projection of the data signal line 61 on the substrate partially overlaps with the orthographic projection of the first connection electrode 51 on the substrate, and the orthographic projection of the data signal line 61 on the substrate may include the orthographic projection of the twenty-fourth via hole V24 on the substrate. The data signal line 61 can be connected to the first connection electrode 51 through the twenty-fourth via hole V24, and the first connection electrode 51 is connected to the first area of ​​the fourth active layer, thereby realizing the connection between the data signal line 61 and the first area of ​​the fourth active layer.

[0193] In some exemplary embodiments, the orthographic projection of the first power line 62 on the substrate partially overlaps with the orthographic projection of the power connection line 50 on the substrate. The orthographic projection of the first power line 62 on the substrate may include the orthographic projection of the twenty-third via V23 on the substrate. The first power line 62 can be connected to the power connection line 50 through the twenty-third via V23 to form a mesh structure for transmitting the first power signal, which can not only effectively reduce the resistance of the first power line and reduce the voltage drop of the first power signal, but also effectively improve the uniformity of the first power signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.

[0194] In some exemplary embodiments, the orthographic projection of the compensation line 38 on the substrate may include the orthographic projections of the twenty-first via hole V21 and the twenty-second via hole V22 on the substrate. The compensation line 38 may be connected to the first bridging electrode 56 through the twenty-first via hole V21, and the compensation line 38 may be connected to the second bridging electrode 57 through the twenty-second via hole V22. The orthographic projection of the compensation line 38 on the substrate partially overlaps with the orthographic projection of the first region 33-1 of the third active layer on the substrate. For example, the orthographic projection of the compensation line 38 on the substrate includes the orthographic projection of the first region 33-1 of the third active layer on the substrate. The compensation line 38 and the first region 33-1 of the third active layer may form a parallel path, which may reduce the on-resistance of the third transistor and improve the threshold voltage divergence problem of the third transistor.

[0195] The preparation process of the embodiment of the present disclosure is well compatible with the existing preparation process, and the process is simple to implement, easy to implement, high in production efficiency, low in production cost, and high in yield rate.

[0196] In some exemplary embodiments, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer may be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo. The first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be single-layer, multi-layer, or composite layers. The material of the fifth insulating layer may be one or more of epoxy resin, phenolic resin, urea-formaldehyde resin, melamine-formaldehyde resin, furan resin, silicone resin, polyester resin, polyamide resin, acrylic resin, polyurethane, vinyl resin, hydrocarbon resin, or polyether resin. The active layer can be made of materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, or polythiophene. This means that the present disclosure is applicable to transistors manufactured using oxide, silicon, or organic technologies. The structures and fabrication processes shown in the embodiments of the present disclosure are merely exemplary. In the exemplary embodiments, the corresponding structures can be modified and patterning processes can be added or removed as needed, and this disclosure does not limit these.

[0197] The present disclosure also provides a display device comprising the display substrate described in any of the aforementioned embodiments. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system, but the present disclosure is not limited thereto.

[0198] Although the embodiments disclosed herein are as described above, the contents described are merely embodiments for facilitating understanding of the present invention and are not intended to limit the present invention. It should be noted that the above embodiments or implementations are merely illustrative and not restrictive. Therefore, the present disclosure is not limited to the contents specifically shown and described herein. Various modifications, substitutions, or omissions may be made to the forms and details of the implementations without departing from the scope of the present disclosure.

Claims

1. A display substrate includes a substrate and at least one pixel driving circuit located on one side of the substrate. The at least one pixel driving circuit includes at least one transistor. The at least one transistor includes an active layer. The active layer includes a channel region and a first region and a second region located on opposite sides of the channel region. The first region has a first end and a second end disposed opposite to each other. The first end of the first region is connected to the channel region, and the second end extends along a second direction. The channel region has a first width in a first direction, the first region has a second width in the first direction, the first width is greater than the second width, and the display substrate further includes a compensation line, a first end of the compensation line is connected to the channel region, and a second end of the compensation line is connected to a second end of the first region; wherein, The first direction intersects the second direction.

2. The display substrate according to claim 1, wherein, The absolute value of the difference between the first width and the second width is greater than 10% of the first width.

3. The display substrate according to claim 1, further including at least one capacitor. The at least one capacitor is closer to the substrate than the compensation line, and the capacitor is located on one side of the extension direction of the compensation line. The capacitor includes two opposite plates, and the orthographic projection of the compensation line on the substrate does not overlap with the orthographic projections of the two plates on the substrate.

4. The display substrate according to claim 3, wherein, The compensation line is disposed on the same layer as the active layer.

5. The display substrate according to claim 4, further including a first connection bridge. The first connection bridge has a first end and a second end disposed opposite to each other along the first direction. The first end of the first connection bridge is connected to the second end of the compensation line, and the second end of the first connection bridge is connected to the second end of the first region of the active layer.

6. The display substrate according to claim 5, further including at least one second connection bridge. The at least one second connection bridge is located between the first connection bridge and the channel region, and the at least one second connection bridge is located between the first region and the compensation line. The second connection bridge extends along the first direction and includes a first end and a second end disposed opposite to each other. The first end of the second connection bridge is connected to the compensation line, and the second end of the second connection bridge is connected to the first region.

7. The display substrate according to claim 6, wherein, The first connection bridge, the at least one second connection bridge and the compensation line are an integrally connected structure.

8. The display substrate according to claim 1, wherein, The compensation line is located on the side of the active layer away from the substrate.

9. The display substrate according to claim 8, wherein, In a plane perpendicular to the display substrate, the display substrate further includes a semiconductor layer, a first source-drain metal layer and a second source-drain metal layer sequentially located on one side of the substrate. The active layer is located in the semiconductor layer, and the compensation line is located in the first source-drain metal layer or the second source-drain metal layer.

10. The display substrate according to claim 9, further including a first bridging electrode and a second bridging electrode. At least a part of the orthographic projection of the first bridging electrode on the substrate overlaps with at least a part of the orthographic projection of the first end of the first region on the substrate. At least a part of the orthographic projection of the second bridging electrode on the substrate overlaps with at least a part of the orthographic projection of the second end of the first region on the substrate. The orthographic projection of the compensation line on the substrate partially overlaps with the orthographic projections of the first bridging electrode and the second bridging electrode on the substrate. Among them, The compensation line is connected to the first end of the first region via the first bridging electrode, and the compensation line is connected to the second end of the first region via the second bridging electrode.

11. The display substrate according to claim 10, wherein, Both the first bridging electrode and the second bridging electrode are located in the first source-drain metal layer, and the compensation line is located in the second source-drain metal layer.

12. The display substrate according to claim 9, wherein, At least a part of the orthographic projection of the compensation line on the substrate overlaps with the orthographic projection of the first region on the substrate.

13. The display substrate according to claim 10, wherein, The orthographic projection of the compensation line on the substrate is located within the orthographic projection of the first region on the substrate.

14. The display substrate according to any one of claims 1 to 13, wherein The at least one transistor is a driving transistor; the at least one pixel driving circuit further includes a light-emitting control transistor, and the light-emitting control transistor is connected to the second end of the first region.

15. A display device, comprising the display substrate according to any one of claims 1 to 14.

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