Processor platform, circuit board, and server

Abstract

The present application relates to the technical field of computers. Disclosed are a processor platform, a circuit board, and a server. The processor platform comprises at least one processor, wherein any of the at least one processor has at least one hyperpath interconnect port; the hyperpath interconnect ports between the at least one processor correspond to each other on a one-to-one basis; the hyperpath interconnect ports between the at least one processor are correspondingly connected; and the at least one processor comprises at least one port extension processor, and each port extension processor has an extensible data port. By means of implementing the processor platform, the circuit board and the server as provided in the embodiments of the present application, a USB data transmission function can be realized when there is no south bridge module; since no south bridge module is needed, the cost of the whole machine is reduced; and the flexible configuration of a PCIe port is realized, and a high-performance Multi-Host PCIe x16 port is realized.

Description

Processor platform, circuit board and server

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on January 23, 2024, with application number 202410092910.0 and application name “A Processor Platform, Circuit Board and Server”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present application relates to the field of computer technology, and in particular to a processor platform, a circuit board, and a server. Background Art

[0004] In today's internet age, servers are the cornerstone of information transmission and drive the continuous development of infrastructure. The CPU (Central Processing Unit) is the computing hub of the server, responsible for handling various complex calculations and control instructions.

[0005] To improve server performance, more than one CPU is often used to enhance computing power and the ability to handle multiple concurrent tasks. Furthermore, the performance of individual CPUs is constantly evolving. Consequently, CPUs without a southbridge architecture have been introduced to the market, enhancing the CPU's hardware I / O capabilities and adding additional PCIe lanes.

[0006] Compared to the fixed PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) port assignments found in previous CPU products, PCIe port configurations offer greater flexibility. However, due to the lack of a southbridge architecture, CPUs cannot support USB (Universal Serial Bus) signal transmission. Furthermore, southbridge modules are expensive. Adding a southbridge module to a CPU without a southbridge will undoubtedly increase the overall cost of the server, weakening the product's competitiveness. Summary of the Invention

[0007] In order to solve the contradiction between the cost of the south bridge module and the USB transmission function after adopting a south bridge-less processor in the related art, as well as the problem of high-performance PCIe port configuration, this application provides the following technical solutions:

[0008] In one aspect, a processor platform is provided, comprising at least one processor;

[0009] Any processor of the at least one processor has at least one hyperpath interconnect port;

[0010] At least one inter-processor hyperpath interconnection port has a one-to-one correspondence;

[0011] At least one inter-processor hyperpath interconnect port is correspondingly connected; and

[0012] The at least one processor includes at least one port expansion processor, and the port expansion processor has an expandable data port.

[0013] Furthermore, in the case where the processor platform includes at least two processors, the processor platform further includes at least one scalable Open Computer Project (OCP) link.

[0014] Further, each scalable OCP link of the at least one scalable OCP link includes: a first processor, a first connector, and a second connector;

[0015] The first connector has a first connector first port set and a first connector second port set, and the second connector has a second connector port set;

[0016] The first processor has a first processor first port set, wherein the first processor first port set corresponds to the first connector first port set;

[0017] Each port in the first port set of the first processor is connected to each port in the first port set of the first connector; and

[0018] Each port in the second port set of the first connector is correspondingly connected to each port in the port set of the second connector.

[0019] Further, the processor platform further includes a third connector having a third connector port set;

[0020] The first processor also has a first processor second port set;

[0021] The third connector port set corresponds to the second connector port set, and the second port set of the first processor corresponds to the third connector port set;

[0022] Each port in the second connector port set is connected to each port in the third connector port set; and

[0023] Each port in the third connector port set is correspondingly connected to each port in the second port set of the first processor.

[0024] Furthermore, the processor platform further includes a second processor and a fourth connector;

[0025] The second processor has a second processor second port set;

[0026] The fourth connector has a fourth connector port set;

[0027] The fourth connector port set corresponds to the second connector port set, and the second processor second port set corresponds to the fourth connector port set;

[0028] Each port in the second set of connector ports is connected to each port in the fourth set of connector ports, replacing the corresponding connection of each port in the second set of connector ports with each port in the third set of connector ports; and

[0029] Each port in the fourth connector port set is correspondingly connected to each port in the second port set of the second processor.

[0030] Furthermore, the processor platform also includes complex programmable logic devices;

[0031] The complex programmable logic device has a complex programmable logic device first port and a complex programmable logic device second port;

[0032] The second connector also has a second connector first port and a second connector second port;

[0033] The first port of the second connector is connected to the first port of the complex programmable logic device, and is used to indicate whether the second connector is connected to the third connector or the fourth connector; and

[0034] The second port of the second connector is connected to the second port of the complex programmable logic device, and is used to indicate that the third connector is connected to the second connector, or that the fourth connector is connected to the second connector.

[0035] Further, the expandable data port has a plurality of PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) channel pairs, wherein a first number of PCIe channel pairs are connected to corresponding ports of the baseboard management controller;

[0036] The second number of PCIe channel pairs are connected to a USB (Universal Serial Bus) interface;

[0037] The third number of PCIe channel pairs are connected to a SATA (Serial ATA) interface.

[0038] Further, the link connecting the second number of PCIe lane pairs to the USB interface includes a USB controller;

[0039] The second number of PCIe lane pairs are connected to the USB interface via the USB controller.

[0040] Furthermore, the USB interface includes at least one of an SCM USB interface and an MB USB interface.

[0041] Furthermore, the USB interface is a USB 2.0 interface and / or a USB 3.0 interface.

[0042] Further, the link connecting the third number of PCIe channel pairs to the SATA interface includes a SATA converter;

[0043] The third number of PCIe channel pairs are connected to the SATA interface through a SATA converter.

[0044] Furthermore, the port expansion processor further includes a plurality of first transmission ports;

[0045] The first transmission port includes four pairs of PCIe lanes.

[0046] Furthermore, the port extension processor further includes at least one second transmission port;

[0047] The second transmission port includes 8 pairs of PCIe lanes.

[0048] Furthermore, the first port of the second connector is used to transmit a presence signal;

[0049] The second port of the second connector is used for transmitting a type signal;

[0050] The first port of the complex programmable logic device is used to receive a presence signal; and

[0051] The second port of the complex programmable logic device is used to receive a type signal.

[0052] Further, when the second connector is connected to the third connector or the fourth connector, the presence signal is at a low level; and when the third connector is connected to the second connector, the type signal is at a high level.

[0053] Furthermore, the port expansion processor is a processor without an integrated south bridge module.

[0054] Furthermore, the hyperpath interconnect port is used to transmit communication data between processors.

[0055] Furthermore, the scalable OCP link has a single-port Single-Host x8 interface.

[0056] On the other hand, a circuit board is provided, comprising the processor platform described in the first aspect.

[0057] On the other hand, a server is provided, comprising the circuit board according to the second aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0059] FIG1 is a schematic diagram of the structure of a processor platform provided in an embodiment of the present application;

[0060] FIG2 is a schematic diagram of a structure of a scalable OCP link formed by two processors according to an embodiment of the present application;

[0061] FIG3 is a schematic diagram of an scalable OCP link connection path provided in an embodiment of the present application;

[0062] FIG4 is a schematic diagram of the structure of a port expansion processor provided in an embodiment of the present application.

[0063] FIG5 is a schematic diagram of the structure of the circuit board provided in an embodiment of the present application.

[0064] FIG6 is a schematic diagram of the structure of the server provided in an embodiment of the present application. DETAILED DESCRIPTION

[0065] To make the purpose, technical solutions, and advantages of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0066] Unless otherwise defined, technical or scientific terms used in this disclosure should have the ordinary meaning understood by a person of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and similar expressions used in this disclosure do not indicate any order, quantity, or importance, but are simply used to distinguish different components. Similarly, terms such as "a," "an," or "the" do not indicate a quantitative limitation, but rather indicate the presence of at least one. The numbers in the drawings in this specification merely distinguish between various functional components or modules and do not indicate a logical relationship between the components or modules. Terms such as "include" or "comprising" mean that the element or object preceding the term includes the elements or objects listed after the term, and their equivalents, without excluding other elements or objects. Terms such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0067] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Note that, in the accompanying drawings, the same reference numerals are given to components having substantially the same or similar structures and functions, and repeated descriptions thereof will be omitted.

[0068] In response to the conflict between the cost of the south bridge module and the USB transmission function after adopting a south bridge-less processor in the related art, as well as the problem of high-performance PCIe port configuration, the present application provides the following embodiments.

[0069] In some embodiments, as shown in FIG1 , a processor platform includes at least one processor. Each of the at least one processor has at least one hyperpath interconnect port. The hyperpath interconnect ports between the at least one processors correspond one-to-one. The hyperpath interconnect ports between the at least one processors are correspondingly connected. The at least one processor includes at least one port expansion processor, which has an expandable data port.

[0070] In one or more embodiments, when the processor platform includes at least two processors, the processor platform further includes at least one scalable OCP link.

[0071] In one or more embodiments, each of the at least one scalable OCP link includes: a first processor, a first connector, and a second connector. The first connector has a first connector first port set and a first connector second port set, and the second connector has a second connector port set. The first processor has a first processor first port set, wherein the first processor first port set corresponds to the first connector first port set. Each port in the first processor first port set is connected to each port in the first connector first port set. Each port in the second connector port set corresponds to the first connector second port set. Each port in the first connector second port set is connected to each port in the second connector port set.

[0072] In one or more embodiments, the processor platform further includes a third connector having a third connector port set. The first processor further includes a first processor second port set. The third connector port set corresponds to the second connector port set, and the first processor second port set corresponds to the third connector port set. Each port in the second connector port set is connected to each port in the third connector port set. Each port in the third connector port set is connected to each port in the second port set of the first processor.

[0073] In one or more embodiments, the processor platform further includes a second processor and a fourth connector. The second processor has a second processor second port set. The fourth connector has a fourth connector port set. The fourth connector port set corresponds to the second connector port set, and the second processor second port set corresponds to the fourth connector port set. Each port in the second connector port set is connected to each port in the fourth connector port set, replacing the corresponding connection between each port in the second connector port set and each port in the third connector port set. Each port in the fourth connector port set is connected to each port in the second processor second port set.

[0074] In one or more embodiments, the processor platform further includes a complex programmable logic device (CPLD). The CPLD includes a first CPLD port and a second CPLD port. The second connector further includes a first second connector port and a second second connector port. The first second connector port is connected to the first CPLD port to indicate whether the second connector is connected to the third connector or the fourth connector. The second second connector port is connected to the second CPLD port to indicate whether the second connector is connected to the third connector or the fourth connector.

[0075] Ultra-Path Interconnect (UPI) ports are used to transmit communication data between processors. As shown in Figure 1, a processor platform consisting of two processors is used as an example. One processor includes Ultra-Path Interconnect ports: UPI0, UPI1, UPI2, and UPI3. The other processor also includes Ultra-Path Interconnect ports: UPI0, UPI1, UPI2, and UPI3. The Ultra-Path Interconnect ports corresponding to the two processors are connected to each other, enabling data transmission between the two processors in the processor platform.

[0076] The processor platform shown in FIG2 includes a scalable OCP link. Each scalable OCP link includes: a first processor, a first connector, and a second connector. The first connector has a first connector first port set and a first connector second port set, and the second connector has a second connector port set.

[0077] The first connector first port set includes channels numbered 0, 1, ... 7. The first connector second port set includes channels numbered 8, 9, ... 15. The first processor has a first processor first port set, including channels numbered 0, 1 ... 7, corresponding to the channels numbered 0, 1, ... 7 in the first connector first port set. Accordingly, the ports numbered 0, 1 ... 7 in the first processor first port set are connected to the ports numbered 0, 1, ... 7 in the first connector first port set. Each port in the second connector port set corresponds to the first connector second port set, including channels numbered 8, 9, ... 15. Accordingly, the ports numbered 8, 9, ... 15 in the second connector port set are connected to the ports numbered 8, 9, ... 15 in the first connector second port set.

[0078] The scalable OCP link obtained by adopting the above connection mode has a Single-Host x8 interface. A processor processes data transmitted by the first port set of the first connector.

[0079] In one or more embodiments, the processor platform further includes a third connector having a third connector port set, the third connector port set including channels numbered 8, 9, ..., 15. The first processor further includes a first processor second port set, including channels 8, 9, ..., 15. The third connector port set corresponds to the second connector port set, and the first processor second port set corresponds to the third connector port set. The ports numbered 8, 9, ..., 15 in the second connector port set are connected to the ports numbered 8, 9, ..., 15 in the third connector port set, as shown in connection path A in FIG3 .

[0080] When the scalable OCP link is connected using the connection path A shown in FIG3 , it has a Single-Host x16 interface. The interface has a processor that processes data transmitted between the first port set of the first connector and the second port set of the first connector.

[0081] In one or more embodiments, the processor platform further includes a second processor and a fourth connector. The second processor has a second processor second port set, including ports numbered 8, 9, ..., 15 channels. The fourth connector has a fourth connector port set, including ports numbered 8, 9, ..., 15 channels. The ports numbered 8, 9, ..., 15 channels in the fourth connector port set correspond to the ports numbered 8, 9, ..., 15 channels in the second connector port set, and the ports numbered 8, 9, ..., 15 channels in the second processor port set correspond to the ports numbered 8, 9, ..., 15 channels in the fourth connector port set. The ports numbered 8, 9, ..., 15 channels in the second connector port set are connected to the ports numbered 8, 9, ..., 15 channels in the fourth connector port set, replacing the corresponding connections between the ports numbered 8, 9, ..., 15 channels in the second connector port set and the ports numbered 8, 9, ..., 15 channels in the third connector port set. This is shown as connection path B in FIG. 3 .

[0082] When connected using connection path B as shown in Figure 3, the resulting scalable OCP link features a Multi-Host x16 interface. Two processors, one each processing data transmitted by the first port set of the first connector and the other by the second port set of the first connector, improve data processing efficiency.

[0083] The ports numbered 8, 9, ..., 15 in the fourth connector port set are correspondingly connected to the ports numbered 8, 9, ..., 15 in the second processor second port set.

[0084] In one or more embodiments, the processor platform further includes a complex programmable logic device (CPLD), as shown in FIG3 .

[0085] The complex programmable logic device has a first complex programmable logic device port for receiving a presence signal. The second complex programmable logic device port for receiving a type signal. The second connector further has a second connector first port for transmitting a presence signal. The second connector second port for transmitting a type signal. The second connector first port is connected to the first complex programmable logic device port for indicating whether the second connector is connected to the third connector or the fourth connector. The second connector second port is connected to the second complex programmable logic device port for indicating that the second connector is connected to the third connector or the fourth connector when the second connector is connected to the third connector or the fourth connector.

[0086] As an implementation, CABLE_PRSNT is a presence signal, and CPU_ADDR is a type signal. When the second connector is connected to the third or fourth connector, the CABLE_PRSNT signal is low (the CABLE_PRSNT signal defaults to high). When the third connector is connected to the second connector, the CPU_ADDR signal is high (the CPU_ADDR signal defaults to low). The level indications of the presence signal and the type signal can be used to determine the bandwidth allocation of the scalable OCP link.

[0087] In some other embodiments, the expandable data port has a plurality of PCIe channel pairs, wherein a first number of PCIe channel pairs are connected to corresponding ports of the baseboard management controller, a second number of PCIe channel pairs are connected to a USB interface, and a third number of PCIe channel pairs are connected to a SATA interface.

[0088] In one or more embodiments, the link connecting the second number of PCIe channel pairs and the USB interface includes a USB controller. The second number of PCIe channel pairs are connected to the USB interface via the USB controller.

[0089] In one or more embodiments, the USB interface includes at least one of an SCM USB interface and an MB USB interface.

[0090] In one or more embodiments, the USB interface is a USB 2.0 interface and / or a USB 3.0 interface.

[0091] In one or more embodiments, the link connecting the third number of PCIe channel pairs to the SATA interface includes a SATA converter. The third number of PCIe channel pairs are connected to the SATA interface via the SATA converter.

[0092] In one or more embodiments, the port expansion processor further includes a plurality of first transmission ports, wherein the first transmission ports include four pairs of PCIe lanes.

[0093] In one or more embodiments, the port expansion processor further includes at least one second transmission port, wherein the second transmission port includes eight pairs of PCIe lanes.

[0094] In the embodiments of this application, a port expansion processor refers to a processor that does not have an integrated southbridge module. Typically, a southbridge module has a SATA (Serial ATA) port for connecting to a disk or disk array. A southbridge module has a USB data transfer port for supporting data transmission via a USB 3.0 or USB 2.0 interface. The southbridge module has a direct connection port to the BMC (Baseboard Management Controller), interacting with the BMC and typically transmitting data corresponding to the content displayed by the BMC. Sacrificing the southbridge module in the processor means the processor's ability to interact with peripheral storage media is reduced, at the expense of improving the processor's hardware I / O performance. Furthermore, a set of PCIe ports is added for processor function expansion, which can improve the efficiency of data interaction between the processor and peripheral devices, thereby enhancing processor performance. A typical example of the processor described in this application is the processor used in the Birch Stream platform. In the latest generation of the Birch Stream platform, the southbridge module has been eliminated from the processor platform architecture. Accordingly, a hardware I / O module and a set of PCIe ports have been added to the processor for function expansion.

[0095] In the expandable data port of the port expansion processor, a new set of PCIe ports can be expanded to realize SATA hard disk interface, USB interface and data interaction with BMC.

[0096] Data transmission between the CPU and the BMC can be achieved by connecting the first number of PCIe channel pairs to corresponding PCIe ports in the BMC. One PCIe channel pair includes two PCIe channels. Typically, the first number is one. That is, one PCIe channel pair is connected to the corresponding PCIe port in the BMC.

[0097] Using the second number of PCIe channel pairs to connect to the USB interface via the USB controller can provide a data transmission interface for the USB device, enabling data transmission between the processor and the USB device. Typically, the second number is two. That is, two pairs of PCIe channel pairs are used to connect to the USB interface via the USB controller.

[0098] In one or more embodiments, the USB controller is a Renesas UPD720201.

[0099] In one or more embodiments, two pairs of PCIe channel pairs are connected to the USB interface through a Renesas UPD720201 module respectively. Each Renesas UPD720201 module can convert 4 groups of USB interfaces. Moreover, each USB interface supports USB2.0 or USB3.0 protocol. The USB interface converted by the Renesas UPD720201 module can be configured on the front window and / or rear window of the whole machine. The converted USB3.0 interface is usually used to connect external devices for data transfer. Furthermore, the TF card interface can be converted by connecting the Card Controller to transmit SDIO signals. The converted USB2.0 interface is usually connected to the BMC and used for KVM (Keyboard Video Mouse) information interaction.

[0100] By implementing the above-mentioned means, USB signal transmission is realized even when the Birch Stream platform does not have a south bridge module.

[0101] Using a third number of PCIe channel pairs to connect to a SATA interface via a SATA converter can provide a data transmission interface for a SATA hard drive, enabling data transmission between the processor and the SATA hard drive. Typically, the third number is 1. That is, one PCIe channel pair is used to connect to the SATA interface via a SATA converter.

[0102] In one or more embodiments, the SATA converter ASM1062R converts PCIe channels to SATA interfaces, supporting RAID 1 (Redundant Arrays of Independent Disks) disk arrays. This enables data transmission between SATA hard drives or RAID 1 disk arrays even when the Birch Stream platform lacks a southbridge module.

[0103] As one implementation, as shown in Figure 4, an additional set of PCIe ports is configured as a PE1 interface, including eight PCIe lanes PCIe<0:7>. Lane 0 and lane 1 form a PCIe lane pair, lane 2 and lane 3 form a PCIe lane pair, lane 4 and lane 5 form a PCIe lane pair, and lane 6 and lane 7 form a PCIe lane pair.

[0104] The PCIe channel pair consisting of channels 0 and 1 connects to the corresponding PCIe ports on the motherboard and BMC, enabling data exchange between the processor and BMC and transmitting data corresponding to BMC display content. The PCIe channel pair consisting of channels 2 and 3 connects to the USB interface (MB USB interface) through the Renesas UPD720201 module. The PCIe channel pair consisting of channels 4 and 5 connects to the USB interface (SCM USB interface) through the Renesas UPD720201 module. The PCIe channel pair consisting of channels 6 and 7 connects to the SATA interface through the ASM1062R module, used to connect SATA hard drives or RAID 1 disk arrays.

[0105] As shown in FIG4 , the port expansion processor further includes a plurality of first transmission ports. The first transmission ports are MCIOx8 ports. Each first transmission port includes four pairs of PCIe lanes.

[0106] As one implementation example, the first transmission port (MCIOx8 port) on the PE2 interface in Figure 4 includes channels 8, 9, ..., and 15. The first transmission port (MCIOx8 port) on the PE5 interface includes channels 0, 1, ..., and 7. This allows for flexible configuration of the MCIOx8 port. Similarly, other first transmission ports and the channel pairs they include are not listed here.

[0107] As shown in FIG4 , the port expansion processor further includes at least one second transmission port. The second transmission port is an MCIO x16 port. Each second transmission port includes eight PCIe lane pairs, enabling flexible configuration of high-performance MCIO x16 ports.

[0108] As one implementation manner, the second transmission port (MCIOx16 port) in the PE0 interface in FIG4 includes channel 0, channel 1, ..., channel 15.

[0109] In other embodiments, a circuit board is provided, comprising a processor platform, wherein the processor platform includes at least one processor. Each of the at least one processor has at least one hyperpath interconnect port. The hyperpath interconnect ports between the at least one processors correspond one-to-one. The hyperpath interconnect ports between the at least one processors are correspondingly connected. At least one processor includes at least one port expansion processor, and the port expansion processor has an expandable data port.

[0110] In one or more embodiments, when the processor platform includes at least two processors, the processor platform further includes at least one scalable OCP link.

[0111] In one or more embodiments, each of the at least one scalable OCP link includes: a first processor, a first connector, and a second connector. The first connector has a first connector first port set and a first connector second port set, and the second connector has a second connector port set. The first processor has a first processor first port set, wherein the first processor first port set corresponds to the first connector first port set. Each port in the first processor first port set is connected to each port in the first connector first port set. Each port in the second connector port set corresponds to the first connector second port set. Each port in the first connector second port set is connected to each port in the second connector port set.

[0112] In one or more embodiments, the processor platform further includes a third connector having a third connector port set. The first processor further includes a first processor second port set. The third connector port set corresponds to the second connector port set, and the first processor second port set corresponds to the third connector port set. Each port in the second connector port set is connected to each port in the third connector port set. Each port in the third connector port set is connected to each port in the second port set of the first processor.

[0113] In one or more embodiments, the processor platform further includes a second processor and a fourth connector. The second processor has a second processor second port set. The fourth connector has a fourth connector port set. The fourth connector port set corresponds to the second connector port set, and the second processor second port set corresponds to the fourth connector port set. Each port in the second connector port set is connected to each port in the fourth connector port set, replacing the corresponding connection between each port in the second connector port set and each port in the third connector port set. Each port in the fourth connector port set is connected to each port in the second processor second port set.

[0114] In one or more embodiments, the processor platform further includes a complex programmable logic device (CPLD). The CPLD includes a first CPLD port and a second CPLD port. The second connector further includes a first second connector port and a second second connector port. The first second connector port is connected to the first CPLD port to indicate whether the second connector is connected to the third connector or the fourth connector. The second second connector port is connected to the second CPLD port to indicate whether the second connector is connected to the third connector or the fourth connector.

[0115] The expandable data port has a plurality of PCIe channel pairs, wherein a first number of PCIe channel pairs are connected to corresponding ports of the baseboard management controller, a second number of PCIe channel pairs are connected to the USB interface, and a third number of PCIe channel pairs are connected to the SATA interface.

[0116] In one or more embodiments, the link connecting the second number of PCIe channel pairs and the USB interface includes a USB controller. The second number of PCIe channel pairs are connected to the USB interface via the USB controller.

[0117] In one or more embodiments, the USB interface includes at least one of an SCM USB interface and an MB USB interface.

[0118] In one or more embodiments, the USB interface is a USB 2.0 interface and / or a USB 3.0 interface.

[0119] In one or more embodiments, the link connecting the third number of PCIe lane pairs to the SATA interface includes a SATA converter.

[0120] The third number of PCIe channel pairs are connected to the SATA interface through a SATA converter.

[0121] In one or more embodiments, the port expansion processor further includes a plurality of first transmission ports, wherein the first transmission ports include four pairs of PCIe lanes.

[0122] In one or more embodiments, the port expansion processor further includes at least one second transmission port, wherein the second transmission port includes eight pairs of PCIe lanes.

[0123] In other embodiments, a computer is provided, comprising a circuit board, the circuit board comprising a processor platform, wherein the processor platform comprises at least one processor. Each of the at least one processor has at least one hyperpath interconnect port. The hyperpath interconnect ports between the at least one processors correspond one-to-one. The hyperpath interconnect ports between the at least one processors are correspondingly connected. At least one processor comprises at least one port expansion processor, the port expansion processor having an expandable data port.

[0124] In one or more embodiments, when the processor platform includes at least two processors, the processor platform further includes at least one scalable OCP link.

[0125] In one or more embodiments, each of the at least one scalable OCP link includes: a first processor, a first connector, and a second connector. The first connector has a first connector first port set and a first connector second port set, and the second connector has a second connector port set. The first processor has a first processor first port set, wherein the first processor first port set corresponds to the first connector first port set. Each port in the first processor first port set is connected to each port in the first connector first port set. Each port in the second connector port set corresponds to the first connector second port set. Each port in the first connector second port set is connected to each port in the second connector port set.

[0126] In one or more embodiments, the processor platform further includes a third connector having a third connector port set. The first processor further includes a first processor second port set. The third connector port set corresponds to the second connector port set, and the first processor second port set corresponds to the third connector port set. Each port in the second connector port set is connected to each port in the third connector port set. Each port in the third connector port set is connected to each port in the second port set of the first processor.

[0127] In one or more embodiments, the processor platform further includes a second processor and a fourth connector. The second processor has a second processor second port set. The fourth connector has a fourth connector port set. The fourth connector port set corresponds to the second connector port set, and the second processor second port set corresponds to the fourth connector port set. Each port in the second connector port set is connected to each port in the fourth connector port set, replacing the corresponding connection between each port in the second connector port set and each port in the third connector port set. Each port in the fourth connector port set is connected to each port in the second processor second port set.

[0128] In one or more embodiments, the processor platform further includes a complex programmable logic device (CPLD). The CPLD includes a first CPLD port and a second CPLD port. The second connector further includes a first second connector port and a second second connector port. The first second connector port is connected to the first CPLD port to indicate whether the second connector is connected to the third connector or the fourth connector. The second second connector port is connected to the second CPLD port to indicate whether the second connector is connected to the third connector or the fourth connector.

[0129] The expandable data port has a plurality of PCIe channel pairs, wherein a first number of PCIe channel pairs are connected to corresponding ports of the baseboard management controller, a second number of PCIe channel pairs are connected to the USB interface, and a third number of PCIe channel pairs are connected to the SATA interface.

[0130] In one or more embodiments, the link connecting the second number of PCIe channel pairs and the USB interface includes a USB controller. The second number of PCIe channel pairs are connected to the USB interface via the USB controller.

[0131] In one or more embodiments, the USB interface includes at least one of an SCM USB interface and an MB USB interface.

[0132] In one or more embodiments, the USB interface is a USB 2.0 interface and / or a USB 3.0 interface.

[0133] In one or more embodiments, the link connecting the third number of PCIe channel pairs to the SATA interface includes a SATA converter. The third number of PCIe channel pairs are connected to the SATA interface via the SATA converter.

[0134] In one or more embodiments, the port expansion processor further includes a plurality of first transmission ports, wherein the first transmission ports include four pairs of PCIe lanes.

[0135] In one or more embodiments, the port expansion processor further includes at least one second transmission port, wherein the second transmission port includes eight pairs of PCIe lanes.

[0136] By implementing the processor platform, circuit board, and server provided by the embodiments of the present application, as shown in Figures 1-5, USB data transmission can be achieved without a southbridge module. This eliminates the need for a southbridge module, reducing overall system costs. This also enables flexible configuration of PCIe ports, resulting in a high-performance multi-host PCIe x16 port.

[0137] All of the above technical solutions can be combined in any way to form embodiments of the present application, and will not be described in detail here.

[0138] A processor platform, as shown in FIG1 , includes at least one processor. Each of the at least one processor has at least one hyperpath interconnect port. The hyperpath interconnect ports between the at least one processors correspond one-to-one. The hyperpath interconnect ports between the at least one processors are correspondingly connected.

[0139] The at least one processor includes at least one port expansion processor, and the port expansion processor has an expandable data port.

[0140] In one or more embodiments, when the processor platform includes at least two processors, the processor platform further includes at least one scalable OCP link.

[0141] In one or more embodiments, each of the at least one scalable OCP link includes: a first processor, a first connector, and a second connector. The first connector has a first connector first port set and a first connector second port set, and the second connector has a second connector port set. The first processor has a first processor first port set, wherein the first processor first port set corresponds to the first connector first port set. Each port in the first processor first port set is connected to each port in the first connector first port set. Each port in the second connector port set corresponds to the first connector second port set. Each port in the first connector second port set is connected to each port in the second connector port set.

[0142] In one or more embodiments, the processor platform further includes a third connector having a third connector port set. The first processor further includes a first processor second port set. The third connector port set corresponds to the second connector port set, and the first processor second port set corresponds to the third connector port set. Each port in the second connector port set is connected to each port in the third connector port set. Each port in the third connector port set is connected to each port in the second port set of the first processor.

[0143] In one or more embodiments, the processor platform further includes a second processor and a fourth connector. The second processor has a second processor second port set. The fourth connector has a fourth connector port set. The fourth connector port set corresponds to the second connector port set, and the second processor second port set corresponds to the fourth connector port set. Each port in the second connector port set is connected to each port in the fourth connector port set, replacing the corresponding connection between each port in the second connector port set and each port in the third connector port set. Each port in the fourth connector port set is connected to each port in the second processor second port set.

[0144] In one or more embodiments, the processor platform further includes a complex programmable logic device (CPLD). The CPLD includes a first CPLD port and a second CPLD port. The second connector further includes a first second connector port and a second second connector port. The first second connector port is connected to the first CPLD port to indicate whether the second connector is connected to the third connector or the fourth connector. The second second connector port is connected to the second CPLD port to indicate whether the second connector is connected to the third connector or the fourth connector.

[0145] In one or more embodiments, the expandable data port has a plurality of PCIe channel pairs, wherein a first number of PCIe channel pairs are connected to corresponding ports of the baseboard management controller, a second number of PCIe channel pairs are connected to a USB interface, and a third number of PCIe channel pairs are connected to a SATA interface.

[0146] In one or more embodiments, the link connecting the second number of PCIe channel pairs and the USB interface includes a USB controller. The second number of PCIe channel pairs are connected to the USB interface via the USB controller.

[0147] In one or more embodiments, the USB interface includes at least one of an SCM USB interface and an MB USB interface.

[0148] In one or more embodiments, the USB interface is a USB 2.0 interface and / or a USB 3.0 interface.

[0149] In one or more embodiments, the link connecting the third number of PCIe channel pairs to the SATA interface includes a SATA converter. The third number of PCIe channel pairs are connected to the SATA interface via the SATA converter.

[0150] In one or more embodiments, the port expansion processor further includes a plurality of first transmission ports, wherein the first transmission ports include four pairs of PCIe lanes.

[0151] In one or more embodiments, the port expansion processor further includes at least one second transmission port, wherein the second transmission port includes eight pairs of PCIe lanes.

[0152] A circuit board includes the processor platform described above. The processor platform has been described in detail above and will not be repeated here.

[0153] A computer includes the circuit board described above. The circuit board has been described above and will not be described again here.

[0154] In particular, according to an embodiment of the present application, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present application includes a computer program product, which includes a computer program loaded on a computer-readable medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network via a communication device, or installed from a memory, or installed from a ROM. When the computer program is executed by an external processor, the above-mentioned functions defined in the method of the embodiment of the present application are executed.

[0155] It should be noted that the computer-readable medium of the embodiment of the present application can be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium can be a non-transitory computer-readable storage medium. The computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. The computer-readable storage medium can include, but is not limited to, an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (Erasable Programmable Read-Only Memory or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In an embodiment of the present application, a computer-readable storage medium can be any tangible medium containing or storing a program, which can be used by an instruction execution system, device or device or used in combination with it. In an embodiment of the present application, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, which carries a computer-readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium may be transmitted using any appropriate medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination of the above.

[0156] The computer-readable medium may be included in the server. Alternatively, it may exist independently and not be incorporated into the server. The computer-readable medium carries one or more programs. When executed by the server, the server: in response to detecting that the peripheral mode of the terminal is not activated, obtains the frame rate of the application on the terminal. In response to determining that the frame rate meets the screen-off condition, determines whether the user is accessing the terminal's screen information. In response to the determination that the user is not accessing the terminal's screen information, controls the screen to enter an immediate dimming mode.

[0157] Computer program code for performing the operations of embodiments of the present application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0158] Each embodiment in this specification is described in a progressive manner. The same or similar parts between the embodiments can be referred to each other. Each embodiment focuses on the differences from other embodiments. In particular, for system or system embodiments, since they are basically similar to method embodiments, the description is relatively simple. For relevant parts, refer to the partial description of the method embodiment. The system and system embodiments described above are merely schematic. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. A person of ordinary skill in the art can understand and implement it without making any creative efforts.

[0159] The technical solutions provided by this application are described in detail above. Specific examples are used herein to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only intended to help understand the methods and core concepts of this application. At the same time, those skilled in the art will appreciate that variations in the specific implementation methods and scope of application may occur based on the concepts of this application. In summary, the contents of this specification should not be construed as limiting this application.

[0160] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A processor platform, characterized in that, including multiple processors; each of the multiple processors has the same number of hyperpath interconnect ports, and the hyperpath interconnect ports among the multiple processors are set and connected in a one-to-one correspondence; and each of the multiple processors includes a port expansion processor, and the port expansion processor has expandable data ports.

2. The processor platform according to claim 1, wherein The processor platform further includes an expandable Open Compute Project (OCP) link.

3. The processor platform according to claim 2, wherein The expandable OCP link includes: a first processor, a first connector, and a second connector; the first connector has a first connector first port set and a first connector second port set, and the second connector has a second connector port set; the first processor has a first processor first port set, wherein the port numbers of the channels in the first processor first port set correspond to the port numbers of the channels in the first connector first port set; each port in the first processor first port set is connected to each port in the first connector first port set in a one-to-one correspondence according to the port numbers of the channels; and each port in the first connector second port set is connected to each port in the second connector port set in a one-to-one correspondence according to the port numbers of the channels.

4. The processor platform according to claim 3, wherein The processor platform further includes a third connector, and the third connector has a third connector port set; the first processor further has a first processor second port set; the port numbers of the channels in the third connector port set correspond to the port numbers of the channels in the second connector port set, and the port numbers of the channels in the first processor second port set correspond to the port numbers of the channels in the third connector port set; each port in the second connector port set is connected to each port in the third connector port set in a one-to-one correspondence according to the port numbers of the channels; and each port in the third connector port set is connected to each port in the first processor second port set in a one-to-one correspondence according to the port numbers of the channels.

5. The processor platform according to claim 4, wherein The processor platform further includes a second processor and a fourth connector; the second processor has a second processor second port set; the fourth connector has a fourth connector port set; the port numbers of the channels in the fourth connector port set correspond to the port numbers of the channels in the second connector port set, and the port numbers of the channels in the second processor second port set correspond to the port numbers of the channels in the fourth connector port set; each port in the second connector port set is connected to each port in the fourth connector port set in a one-to-one correspondence according to the port numbers of the channels, so as to replace the connection of each port in the second connector port set with each port in the third connector port set; and each port in the fourth connector port set is connected to each port in the second processor second port set in a one-to-one correspondence according to the port numbers of the channels.

6. The processor platform according to claim 5, characterized in that, The processor platform further includes a complex programmable logic device; the complex programmable logic device has a complex programmable logic device first port and a complex programmable logic device second port; the second connector further has a second connector first port and a second connector second port; The first port of the second connector is connected to the first port of the complex programmable logic device and is used to indicate whether the second connector is connected to the third connector or the fourth connector; as well as The second port of the second connector is connected to the second port of the complex programmable logic device, and is used to indicate that the third connector is connected to the second connector, or the fourth connector is connected to the second connector.

7. The processor platform according to claim 1, wherein The expandable data port has a plurality of PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) channel pairs, wherein a first number of PCIe channel pairs are connected to corresponding ports of the baseboard management controller; The second number of PCIe channel pairs are connected to a USB (Universal Serial Bus) interface; and The third number of PCIe channel pairs are connected to a SATA (Serial ATA) interface.

8. The processor platform according to claim 7, wherein The link connecting the second number of PCIe lane pairs to the USB interface includes a USB controller; The second number of PCIe channel pairs are connected to the USB interface through the USB controller.

9. The processor platform according to claim 8, wherein The USB interface includes at least one of an SCM USB (Universal Serial Bus) interface and an MB USB interface.

10. The processor platform according to claim 8, wherein The USB interface is a USB 2.0 interface and / or a USB 3.0 interface.

11. The processor platform according to claim 7, wherein The link connecting the third number of PCIe lane pairs to the SATA interface includes a SATA converter; The third number of PCIe channel pairs are connected to the SATA interface through the SATA converter.

12. The processor platform according to claim 7, wherein The port expansion processor further includes a plurality of first transmission ports; The first transmission port includes four pairs of PCIe channel pairs.

13. The processor platform according to claim 7, wherein The port expansion processor further includes a second transmission port; The second transmission port includes 8 pairs of PCIe channel pairs.

14. The processor platform according to claim 6, wherein: The first port of the second connector is used to transmit a presence signal; The second port of the second connector is used for transmitting type signals; The first port of the complex programmable logic device is used to receive the presence signal; as well as The second port of the complex programmable logic device is used to receive the type signal.

15. The processor platform according to claim 14, characterized in that When the second connector is connected to the third connector or the fourth connector, the presence signal is at a low level; and When the third connector is connected to the second connector, the type signal is at a high level.

16. The processor platform according to claim 1, wherein The port expansion processor is a processor without an integrated south bridge module.

17. The processor platform according to claim 1, characterized in that, The Hyper-Path Interconnect port is used to transmit communication data between processors.

18. The processor platform according to claim 2, wherein The scalable OCP link has a single-port Single-Host x8 interface.

19. A circuit board, characterized in that, The circuit board comprises the processor platform according to any one of claims 1-18.

20. A server, characterized in that, The server includes the circuit board of claim 19.

Images