Vertical nanostructure energy storage device with two-level substrate and manufacturing method

Abstract

An energy storage device (11) comprising: a substrate (27) having a first level (31), a second level (33) higher than the first level (31), and a surface (35) connecting the first level (31) and the second level (33); a plurality of nanostructures (37) vertically extending from the first level (31) of the substrate (27); a first electrode layer (39) covering each nanostructure in the plurality of nanostructures (37), the surface (35) connecting the first level (31) and the second level (33); a conduction controlling layer (41) conformally covering the first electrode layer (39); a second electrode layer (43) covering the conduction controlling layer (41); a first contact pad (21) conductively connected to the first electrode layer (39) on the second level (33) of the substrate (27); and a second contact pad (23) conductively connected to the second electrode layer (43).

Description

[0001] VERTICAL NANOSTRUCTURE ENERGY STORAGE DEVICE WITH TWO- LEVEL SUBSTRATE AND MANUFACTURING METHOD

[0002] Field of the Invention

[0003] The present invention relates to an energy storage device comprising a substrate and a plurality of nanostructures extending from the substrate, and to a method of manufacturing such an energy storage device.

[0004] Background of the Invention

[0005] To accommodate for increasing clock frequencies and decreased dimensions in electronic devices, there is a need for compact and high- capacity energy storage devices. Discrete MIM (metal-insulator-metal) capacitor components have been developed, that exhibit smaller size and higher capacitance.

[0006] US 2022 / 0013305 A1 discloses a discrete MIM energy storage component comprising a MIM-arrangement including first electrode layer; a plurality of conductive nanostructures grown from the first electrode layer; a conduction controlling material covering each nanostructure in the plurality of conductive nanostructures and the first electrode layer uncovered by the conductive nanostructures; and a second electrode layer covering the conduction controlling material; a first connecting structure for external electrical connection of the capacitor component; a second connecting structure for external electrical connection of the capacitor component; and an electrically insulating encapsulation material at least partly embedding the MIM-arrangement. The different configurations of the discrete MIM energy storage component in US 2022 / 0013305 A1 can be made very compact, and with a high energy storage capacity.

[0007] It would be desirable to provide an energy storage device having similar properties, enabling an advantageous electrical connection between the first electrode layer of the energy storage device and a first contact pad for external connection, and between the second electrode layer of the energy storage device and a second contact pad for external connection. Summary

[0008] According to a first aspect of the present invention, it is therefore provided an energy storage device comprising: a substrate having a first level, a second level higher than the first level, and a surface connecting the first level and the second level; a plurality of nanostructures vertically extending from the first level of the substrate; a first electrode layer covering each nanostructure in the plurality of nanostructures, the surface connecting the first level and the second level, and the second level of the substrate; a conduction controlling layer conformally covering the first electrode layer; a second electrode layer covering the conduction controlling layer; a first contact pad conductively connected to the first electrode layer on the second level of the substrate; and a second contact pad conductively connected to the second electrode layer.

[0009] It should be understood that the second level of the substrate is vertically higher than the first level of the substrate, when the substrate is macroscopically arranged in a horizontal plane. Analogously, that the nanostructures are “vertically extending” from the first level of the substrate should be understood to mean that the nanostructures extend substantially vertically, when the substrate is macroscopically arranged in a horizontal plane.

[0010] In the context of the present application, the term “conformally covering” should be understood to mean covering in such a way that a thickness of the conformally covering layer is substantially the same regardless of an orientation of a surface covered by the layer. Various deposition method for achieving conformal coverage are well-known to those skilled in the art. Notable examples of deposition methods that may be suitable are various vapor deposition methods, such as CVD, ALD, and PVD.

[0011] The present invention is based on the realization that it would be desirable to at least partly arrange the first electrode layer and the second electrode layer with a mutual vertical distance that is shorter than a maximum length of the nanostructures in the plurality of nanostructures. The present inventor has further realized that this can be achieved by providing a substrate with different vertical levels, provide the nanostructures vertically extending from a lower one of the different vertical levels, and deposit the first electrode layer to cover the nanostructures and a higher one of the different vertical levels. In this way, the first electrode layer can be brought closer to a vertical level of tips of the vertically extending nanostructures. This, in turn, facilitates conductive connection between the first electrode layer and the first contact pad.

[0012] This configuration of the energy storage device reduces the requirement for long connecting plugs. This, in turn, provides for facilitated manufacturing, and improved utilization of the substrate area. From this follows that energy storage devices can be manufactured with higher yield and / or higher energy storage capacity for a given energy storage device footprint. Additionally, the configuration according to aspects of the present disclosure allows for the use of longer vertically extending nanostructures, which may also contribute to higher energy storage capacity for a given energy storage device footprint.

[0013] In an example configuration, the second contact pad may advantageously be conductively connected to the second electrode layer directly above the plurality of conductive nanostructures. This example configuration may provide for an even distribution of first and second contact pads, and may further provide for a small difference in vertical position between the first electrode layer and the second electrode layer, between the positions where the first contact pad is conductively connected to the first electrode layer and the second contact pad is conductively connected to the second electrode layer.

[0014] Advantageously, the first contact pad and the second contact pad may be on substantially the same vertical level in relation to the second level of the substrate. This configuration may make it easier to mount the energy storage device, as a discrete component, on an integrated circuit or a PCB, etc.

[0015] In an example configuration of the energy storage device, a thickness of the first electrode layer on the surface connecting the first level and the second level may be greater than a thickness of the first electrode layer on the second level of the substrate. This configuration may provide for a reduced ESR (electrical serial resistance) and / or reduced ESL (electrical series inductance) of the energy storage device.

[0016] In an example configuration of the energy storage device, the conduction controlling layer may cover the first electrode layer on a portion of the second level of the substrate; and the second electrode layer may cover the conduction controlling layer on a portion of the second level of the substrate.

[0017] There may be an opening in the conduction controlling layer and second electrode layer on the second level of the substrate; and the energy storage device may further comprise a conductive structure that extends through the opening to conductively connect the first electrode layer on the second level of the substrate with the first contact pad.

[0018] In an example configuration of the energy storage device, the second electrode layer may comprise: a first sub-layer conformally covering the conduction controlling layer; and a second sub-layer covering the first sublayer in such a way that spaces between individual nanostructures in the plurality of conductive nanostructures are substantially completely filled by the second sub-layer, and spaces between the plurality of conductive nanostructures and the surface connecting the first level and the second level of the substrate are substantially completely filled by the second sub-layer. This example configuration may provide for improved structural strength and durability of the energy storage device and / or provide for a reduced ESR (electrical serial resistance) and / or reduced ESL (electrical series inductance) of the energy storage device.

[0019] In an example configuration of the energy storage device, the energy storage device may comprise an electrically insulating encapsulation material at least partly forming an outer boundary surface of the energy storage device; and each of the first contact pad and the second contact pad may at least partly form the outer boundary surface of the energy storage device. This configuration provides for a discrete energy storage device component that is robust and suitable for rational electronics production using massproduction equipment of the so-called “pick-and-place” type.

[0020] The energy storage device according to various example configurations of the present invention may advantageously be included in an electronic system, further comprising a substrate with a substrate conductor pattern, the substrate having substrate pads included in the substrate conductor pattern; a semiconductor component with active circuitry, and component pads coupled to the active circuitry of the semiconductor component, the component pads being connected to the substrate pads of the substrate; and a power source interface for receiving power from a power source, the power source interface being connected to the substrate conductor pattern. The energy storage device may be arranged between the substrate and the semiconductor component, the first contact pad of the energy storage device being conductively connected to a first component pad of the semiconductor component, and the second contact pad of the energy storage device being conductively connected to a second component pad of the semiconductor component.

[0021] The energy storage device according to various example configurations of the present invention may advantageously be included in an electronic system, further comprising a substrate with a substrate conductor pattern, the substrate having substrate pads included in the substrate conductor pattern; a semiconductor component with active circuitry, and component pads coupled to the active circuitry of the semiconductor component, the component pads being connected to the substrate pads of the substrate; and a power source interface for receiving power from a power source, the power source interface being connected to the substrate conductor pattern. The energy storage device may be embedded in the substrate, the first contact pad of the energy storage device being conductively connected to a first component pad of the semiconductor component via a first substrate pad of the substrate conductor pattern, and the second contact pad of the energy storage device being conductively connected to a second component pad of the semiconductor component via a second substrate pad of the substrate conductor pattern.

[0022] According to a second aspect of the present invention, there is provided a method of manufacturing an energy storage device, comprising: providing a substrate having a first level, a second level higher than the first level, and a surface connecting the first level and the second level; providing, on the first level of the substrate, a plurality of nanostructures in such a way that each nanostructure in the plurality of nanostructures extends substantially vertically from the first level of the substrate; providing a first electrode layer covering each nanostructure in the plurality of nanostructures, the surface connecting the first level and the second level, and the second level of the substrate; providing a conduction controlling layer conformally covering the first electrode layer; providing a second electrode layer covering the conduction controlling layer; removing at least a portion of the conduction controlling layer and the second electrode layer on the second level of the substrate, to thereby expose the first electrode layer on the second level of the substrate; forming a first contact pad conductively connected to the exposed first electrode layer on the second level of the substrate; and forming a second contact pad conductively connected to the second electrode layer.

[0023] According to an example, providing the substrate may comprise providing a single-level substrate that is exposed in a first portion of the single-level substrate and covered by a mask in a second portion of the single-level substrate; and subjecting the single-level substrate to a material removing technique resulting in removal of material from the single-level substrate in the first portion of the single-level substrate and under an edge portion of the mask, until the substrate is at the first level of the substrate where it is exposed and under the edge portion of the mask; providing the first electrode layer may comprise depositing, while the mask remains on the substrate, a first conductive layer using a first deposition technique resulting in formation of the first conductive layer on the first level of the substrate and on the surface connecting the first level and the second level; and providing the plurality of nanostructures may comprise: depositing, while the mask remains on the substrate, a catalyst layer using a second deposition technique resulting in formation of the catalyst layer on the first conductive layer on the first level of the substrate, as defined by a projection of the mask on the first level of the substrate; and growing nanostructures from the catalyst layer.

[0024] In this example embodiment of the method according to the present invention, a combination of an under-etch of the substrate and a suitable choice of different deposition techniques for deposition of a part of the first electrode layer and the catalyst layer provides several advantageous properties to the energy storage device. By depositing the first conductive layer using a first deposition technique resulting in formation of the first conductive layer not only on the first level of the substrate, but also on the surface connecting the first level and the second level contributes to reducing the ESR and / or ESL of the energy storage device. Through the under-etch and the choice of a second deposition technique for deposition of the catalyst layer, resulting in formation of the catalyst layer on the first conductive layer on the first level of the substrate as defined by a projection of the mask on the first level of the substrate, unwanted growth of nanostructures on the surface connecting the first level and the second level can be prevented, which is important for the performance and quality of the energy storage device. Through this example of the method according to the present invention, this can be achieved without the need for lithography on the first level of the substrate, which provides for a lower production cost and improved yield.

[0025] In an example of the method according to the present invention, the method may comprise removing the mask, together with the first conductive layer and the catalyst layer deposited on the mask; and providing the first electrode layer may comprise depositing a second conductive layer using a third deposition technique resulting in the second conductive layer conformally covering each nanostructure in the plurality of nanostructures, the first conductive layer on the surface connecting the first level and the second level of the substrate, and the second level of the substrate. Hereby, the first electrode layer delivers the dual functionality of high conductivity at the surface of each nanostructure (provided by the second conductive layer) and low series resistance (ESR) along the surface connecting the first level and the second level of the substrate. Both of these functionalities contribute to, for example, capacitor properties that are advantageous for decoupling capacitors in demanding applications.

[0026] According to an example, providing the second electrode layer may comprise: depositing a first sub-layer conformally covering the conduction controlling layer on each nanostructure in the plurality of nanostructures and on the surface connecting the first level and the second level of the substrate; and depositing a second sub-layer covering the first sub-layer in such a way that spaces between individual nanostructures in the plurality of nanostructures are substantially completely filled by the second sub-layer, and spaces between the plurality of nanostructures and the surface connecting the first level and the second level of the substrate are substantially completely filled by the second sub-layer.

[0027] According to an example the method may further comprise depositing an electrically insulating encapsulation material to at least partly form an outer boundary surface of the energy storage device; and forming the first contact pad may comprise: forming a hole in the electrically insulating encapsulation material over the second level of the substrate; filling the hole with conductive material making conductive contact with the first electrode layer; and forming the first contact pad on the conductive material; and forming the second contact pad may comprise: forming a hole in the electrically insulating encapsulation material over the plurality of nanostructures; filling the hole with conductive material making conductive contact with the second electrode layer; and forming the second contact pad on the conductive material.

[0028] Brief Description of the Drawings

[0029] These and other aspects of the present invention will now be described in more detail, with reference to the appended drawings, wherein: Fig 1 schematically illustrates an application for energy storage devices according to examples of the present invention, in the form of a schematic mobile phone;

[0030] Fig 2 schematically illustrates an example of a circuit board according to the prior art, which may represent a typical circuit board in a current electronic device;

[0031] Fig 3 schematically illustrates possible implications of replacing the conventional energy storage components on the circuit board in fig 2 with energy storage devices according to examples of the present invention;

[0032] Fig 4 is a schematic illustration of an energy storage device according to an example configuration;

[0033] Fig 5 is a schematic cross-section view of the energy storage device in fig 4;

[0034] Figs 6A-C are enlarged views of different parts the energy storage device in fig 5;

[0035] Fig 7 is a flow-chart illustrating an example method;

[0036] Fig 8 is a flow-chart illustrating an example method; and

[0037] Figs 9A-G schematically illustrate different steps of the method in fig 8.

[0038] Detailed Description of Examples

[0039] Fig 1 schematically illustrates an electronic device according to an embodiment of the present invention, here in the form of a mobile phone 1 . In the simplified and schematic illustration in fig 1 , it is indicated that the mobile phone, like most electronic devices, comprises an electronic system 3, including a circuit substrate, populated with semiconductor components 5, and passive components, including energy storage devices, here in the form of capacitors 7.

[0040] In fig 2, which is an exemplary illustration of an electronic system 3 using technology that is currently available for rational and cost-efficient mass-production, there is a large number of capacitors 7 mounted on the circuit substrate 9, which may be provided in the form of a printed circuit board (PCB). The capacitors 7 presently used are often so-called multilayer ceramic capacitors (MLCCs), with a minimum package height of about 0.4 mm.

[0041] To provide for even more compact electronic devices, with even higher processing speeds, it would be desirable to reduce the space occupied by the capacitors 7 needed for decoupling and temporary energy storage, and to reduce the distance between a semiconductor component 5 and the capacitors 7 serving that semiconductor component 5.

[0042] This can be achieved using energy storage devices according to examples of the present invention, such energy storage devices can be made with a considerably smaller package height than conventional MLCCs with similar capacitance and footprint.

[0043] Fig 3 is a schematic illustration of an electronic system 3 comprising a circuit substrate 9, a semiconductor component 5, a power source interface 15, and a plurality of energy storage devices according to examples of the present invention. In fig 3, only two energy storage devices 11 a-b are indicated by reference numerals to avoid cluttering the drawing. The circuit substrate 9 has a circuit substrate conductor pattern 17, and circuit substrate pads 19 included in the circuit substrate conductor pattern 17. The semiconductor component has active circuitry (not visible in fig 3) and component pads 13 coupled to the active circuitry. The component pads 13 are connected to the circuit substrate pads 19 of the circuit substrate 9. The power source interface 15 is configured to receive power from a power source, and is connected to the circuit substrate conductor pattern 17.

[0044] One of the indicated energy storage devices 11 a is arranged between the circuit substrate 9 and the semiconductor component 5. A first contact pad 21 of the energy storage device 11 a is conductively connected to a first component pad 13a of the semiconductor component 5, and a second contact pad 23 of the energy storage device 11 a is conductively connected to a second component pad 13b of the semiconductor component 5.

[0045] The other one of the indicated energy storage devices 11 b is embedded in the circuit substrate 9. A first contact pad 21 of the energy storage device 11 b is conductively connected to a first circuit substrate pad 19a of the circuit substrate conductor pattern 17, and a second contact pad 23 of the energy storage device 11 b is conductively connected to a second circuit substrate pad 19b of the circuit substrate conductor pattern 17.

[0046] As is evident from fig 3, the decreased package height of the energy storage devices 11 allows placement of the energy storage devices 11 under the semiconductor component 5, and / or embedded in the substrate 9. Obviously, this arrangement of the energy storage devices 11 allows for a smaller substrate 9, and thus for a more compact electronic system 3. Shorter distances between active circuitry in the semiconductor component 5 and the energy storage devices 11 are clearly also provided for, which reduces the ESL (electrical series inductance).

[0047] Fig 4 is a schematic illustration of an energy storage device 11 according to an example configuration. The exemplary energy storage device 11 in fig 4 has an outer boundary surface that is at least partly formed by an electrically insulating encapsulation material 25. In the example configuration of fig 4, a substrate 27 of the energy storage device 11 also partly forms the outer boundary surface of the energy storage device 11 .

[0048] The exemplary energy storage device 11 in fig 4 is a discrete capacitor component, that is connectable to, for example, a semiconductor component 5 or a substrate conductor pattern 17 by means of a plurality of first contact pads 21 and a plurality of second contact pads 23 substantially evenly distributed across a top surface of the energy storage device 11 . Only a few first contact pads 21 and second contact pads 23 are indicated with reference numerals in fig 4 to avoid cluttering the drawing. Through the provision of multiple first contact pads 21 , all being connected to the first electrode layer of the energy storage device 11 , and multiple second contact pads 23, all being connected to the second electrode layer of the energy storage device, the ESR and / or ESL of the energy storage device 11 can be reduced, providing for improved decoupling properties.

[0049] Fig 5 is a schematic cross-section view of the energy storage device 11 in fig 4, of a section taken along the line A-A’ in fig 4. Referring first to fig 5, the energy storage device 11 comprises the above-mentioned substrate 27, a nanostructure MIM (metal-insulator-metal) arrangement 29, the above-mentioned first contact pad(s) 21 , and the above-mentioned second contact pad(s) 23. The substrate 27, which may, for example, be made of doped or undoped silicon, has a first level 31 , a second level 33 vertically higher than the first level 31 , and a surface 35 connecting the first level 31 and the second level 33.

[0050] The nanostructure MIM arrangement 29 includes a plurality of nanostructures 37 extending substantially vertically from the first level 31 of the substrate 27. As is best seen in figs 6A-C, which are enlarged views of different parts the energy storage device in fig 5, the nanostructure MIM arrangement 29 further comprises a first electrode layer 39, a conduction controlling layer 41 , and a second electrode layer 43.

[0051] The nanostructures 37 may advantageously be grown nanostructures, and may be so-called carbon nanofibers (CNF). Other possibilities, however, exist, and may be advantageous depending on application.

[0052] The first electrode layer 39 covers each nanostructure 37, the surface 35 connecting the first level 31 and the second level 33 of the substrate 27, as well as the second level 33 of the substrate 27. The thickness of the first electrode layer 39 on the surface 35 connecting the first level 31 and the second level 33 of the substrate 27 may be greater than a thickness of the first electrode layer 39 on the second level 33, and greater than a thickness of the first electrode layer 39 on the nanostructures 37. At least on the surface 35 connecting the first level 31 and the second level 33, the first electrode layer 39 may comprise a first conductive layer 45 and a second conductive layer 47. As will be described in greater detail further below in connection with the flow-chart in fig 8, and the accompanying illustrations in figs 9A-G, the first conductive layer 45 may have been deposited before providing the nanostructures 37, while the second conductive layer 47 has been deposited after providing the nanostructures.

[0053] The conduction controlling layer 41 conformally covers the first electrode layer 39. The conduction controlling layer 41 may advantageously be made of a so-called high-k dielectric. The high k-dielectric materials may e.g. be HfOx, TiOx, TaOx or other well-known high k dielectrics. Alternatively, the conduction controlling layer 41 can be polymer based e.g. polypropylene, polystyrene, poly(p-xylylene), parylene etc.. Other well-known dielectric materials, such as SiOx or SiNx, etc may also be used for the conduction controlling layer 41 . The conduction controlling layer 41 may be a multi-layer structure, which may include sub-layers of different material compositions.

[0054] The second electrode layer 43 covers the conduction controlling layer 41 , and the first electrode layer 39, the conduction controlling layer 41 , and the second electrode layer 43 thus together form a large area MIM structure. Although not visible in fig 5 or figs 6A-C, the second electrode layer 43 may advantageously comprise a first sub-layer conformally covering the conduction controlling layer 41 ; and a second sub-layer covering the first sub-layer in such a way that spaces between individual nanostructures 37 in the plurality of conductive nanostructures are substantially completely filled by the second sub-layer, and spaces between the plurality of conductive nanostructures 37 and the surface 35 connecting the first level 31 and the second level 33 of the substrate 27 are substantially completely filled by the second sub-layer.

[0055] The first contact pads 21 are conductively connected to the first electrode layer 39 on the second level 33 of the substrate 27. In the example configuration shown in fig 5, the conductive connection between the first contact pads 21 and the first electrode layer 39 is achieved using first electrode plugs 48. The first contact pads 21 are conductively unconnected to the second electrode layer 43.

[0056] The conduction controlling layer 41 may cover the first electrode layer 39 on a portion of the second level 33 of the substrate 27, and the second electrode layer 43 may cover the conduction controlling layer 41 on a portion of the second level 33 of the substrate 27.

[0057] There may then be an opening in the conduction controlling layer 41 and the second electrode layer 43 on the second level 33 of the substrate 27, and the first electrode plugs 48 may extend through this opening to conductively connect the first electrode layer 39 on the second level 33 of the substrate 27 with the first contact pads 21.

[0058] The second contact pads 23 are conductively connected to the second electrode layer 43. As is shown in fig 5, the conductive connection between each second contact pad 23 and the second electrode layer 43 may be located directly above the plurality of nanostructures 37. In the example configuration shown in fig 5, the conductive connection between the second contact pads 23 and the second electrode layer 43 is achieved using second electrode plugs 49.

[0059] The first contact pads 21 and the second contact pads 23 may be on the same vertical level in relation to the second level 33 of the substrate 27. This may, for example, be achieved by adapting the vertical extensions of the first 48 and / or second 49 electrode plugs.

[0060] Fig 7 is a flow-chart illustrating an example method of manufacturing an energy storage device 11 . Further references are made to fig 5 and figs 6A-C as indicated.

[0061] In a first step 701 , a substrate 27 is provided, having a first level 31 , a second level 33 vertically higher than the first level 31 , and a surface 35 connecting the first level 31 and the second level 33.

[0062] Subsequently, a plurality of nanostructures 37 are provided 702 on the first level 31 of the substrate 27 in such a way that each nanostructure 37 in the plurality of nanostructures extends substantially vertically from the first level 31 of the substrate 27.

[0063] A first electrode layer 39 is provided 703 in such a way that the first electrode layer 39 covers each nanostructure 37 in the plurality of nanostructures, the surface 35 connecting the first level 31 and the second level 33, and the second level 33 of the substrate 27.

[0064] A conduction controlling layer 41 is provided 704 in such a way that the conduction controlling layer 41 conformally covers the first electrode layer 39.

[0065] A second electrode layer 43 is provided 705 in such a way that the second electrode layer 43 covers the conduction controlling layer 41. The first electrode layer 39 is exposed 706 on the second level 33 of the substrate 27 by removing at least a portion of the conduction controlling layer 41 and the second electrode layer 43 on the second level 33 of the substrate 27.

[0066] At least a first 21 and a second 23 contact pad are formed 707 in such a way that the first contact pad(s) is / are conductively connected to the exposed first electrode layer 39 on the second level 33 of the substrate 27, and the second contact pad(s) is / are conductively connected to the second electrode layer 43.

[0067] Fig 8 is a flow-chart illustrating an example method of manufacturing an energy storage device 11 , and figs 9A-G schematically illustrate different steps of the method in fig 8. Further references are made to fig 5, figs 6A-C as indicated.

[0068] In a first step 801 , a single-level substrate 27 is provided. The substrate 27 is covered by a patterned mask 51 , that is patterned to leave a first portion 53 of the substrate 27 uncovered by the mask 51 (exposed), and a second portion 55 of the substrate 27 covered by the mask 51 . The mask 51 may, for example, be provided as a thin oxide layer that is first deposited and then patterned using, perse, well-known lithography techniques. A part of the masked single-level substrate 27 is schematically shown in fig 9A.

[0069] Subsequently, the single-level substrate 27 is subjected 802 to a material removing technique resulting in removal of material from the single- level substrate 27 in the first portion 53 of the single-level substrate 27 and under an edge portion of the mask 51 , until the substrate 27 is at the first level 31 of the substrate 27 where it is exposed (not covered by the mask 51 ) and under the edge portion of the mask 51 . The desired under-etch can be done, for example, in a dry etch step through adjusting plasma conditions such as the substrate voltage bias, gas chemistry, and chamber pressure. By such adjustments one can tune the etch rate for the sidewall and for the bottom surface to obtain a specific etch ratio between the two. In doing so, a controlled under-etch under the mask 51 can be achieved as shown in fig 9B. Various processes resulting in under-etch are commonly used in the semiconductor industry. The single-level substrate 27 may advantageously be a silicon substrate, which may be doped or undoped. Other substrate materials are also possible, as long as they can be etched to achieve the desired under-etch.

[0070] While the mask 51 remains on the substrate 27, a first conductive layer 45 using a first deposition technique resulting in formation of the first conductive layer 45 on the first level 31 of the substrate 27 and on the surface 35 connecting the first level 31 and the second level 33, and on the mask 51 . As was described above with reference to fig 5 and figs 6A-C, the first conductive layer 45 will, when the manufacturing process has been completed, be included in the first electrode layer 39 of the finished energy storage device 11 . A suitable choice for the first deposition technique may be sputtering. The first conductive layer could be made of any of a number of metals, such as W, Ti, Al, Si, Ni, Pt, or Cr, or combinations thereof. Sputtering results in the desired side-wall (surface 35) coverage which eventually contributes to a desired low ESR.

[0071] In the next step 804, a catalyst layer 57 is deposited, while the mask 51 remains on the substrate 27. The catalyst layer 57 is deposited using a second deposition technique resulting in formation of the catalyst layer 57 on the first conductive layer 45 on the first level 31 of the substrate 31 , as defined by a projection of the mask 51 on the first level 31 of the substrate 27. An advantageous example of the second deposition technique may be evaporation, since evaporation does not result in side wall coverage, so that the catalyst layer 57 is substantially limited to the area on the first level 31 of the substrate 27 defined by the projection of the mask 51. The catalyst layer 57 can, for example, be made of nickel, iron, platinum, palladium, nickel-silicide, cobalt, molybdenum, Au or alloys thereof, or can be combined with other materials (e.g., silicon). Fig 9C schematically shows the substrate 27 with the first conductive layer 45 and the catalyst layer formed thereon, with the mask 51 remaining and covered by the first conductive layer 45 and the catalyst layer 57. After deposition of the catalyst layer 57, the mask 51 is removed 805, for example using a sacrificial etch of the mask 51 (being an oxide layer). For instance, a Buffered HF solution can be used to remove the oxide with minimal impact on other layers. The resulting coated substrate 27 is shown in fig 9D.

[0072] Nanostructures 37 are grown 806 on the catalyst layer 57. Since the catalyst layer 57 is not on the surface 35 connecting the first level 31 and the second level 33 of the substrate 27, parasitic growth of nanostructures on the walls can be avoided, and nanostructure-free regions can be created close to the side walls (the surface 35 connecting the first level 31 and the second level 33).

[0073] Vertically grown carbon nanofibers (CNF) may be particularly suitable for energy storage devices 11 . The use of vertically grown nanostructures 37 allows extensive tailoring of the properties of the nanostructures 37. For instance, the growth conditions may be selected to achieve a morphology giving a large surface area of each nanostructure 37, which may in turn increase the charge storing capacitance or capacitance per 2D footprint. As an alternative to CNF, the nanostructures may be metallic carbon nanotubes or carbide-derived carbon nanostructures, nanowires such as copper, aluminum, silver, silicide or other types of nanowires. Advantageously, the catalyst material, and growth gases etc. may be selected in, perse, known ways to achieve so-called tip growth of the nanostructures 37, which may result in catalyst layer material at tips of the nanostructures 37.

[0074] Subsequently, a second conductive layer 47 is deposited 807 using a third deposition technique resulting in the second conductive layer 47 conformally covering each nanostructure 37 in the plurality of nanostructures, the first conductive layer 45 on the surface 35 connecting the first level 31 and the second level 33 of the substrate 27, and the second level 33 of the substrate 27. The third deposition technique may advantageously be ALD (atomic layer deposition). For example, a thin layer of TiN (or similar) may be deposited. The second conductive layer 47 and the first conductive layer deposited in step 803 together form the first electrode layer 39 that extends from the nanostructures 37 to the second level 33 of the substrate 27. A conduction controlling layer 41 is then provided 808 using a deposition technique resulting in conformal covering of the first electrode layer 39. For instance, ALD deposition may be used to form the conduction controlling layer 41 as an oxide stack. The conduction controlling layer 41 may, for example, be made of a so-called high-k dielectric. The high k- dielectric materials may e.g. be HfOx, TiOx, TaOx or other well-known high k dielectrics. Alternatively, the conduction controlling layer 41 can be polymer based e.g. polypropylene, polystyrene, poly(p-xylylene), parylene etc.. Other well-known dielectric materials, such as SiOx or SiNx, etc may also be used as the conduction controlling layer 41 .

[0075] After formation of the conduction controlling layer 41 , a first sublayer 59 may be deposited 809 to conformally cover the conduction controlling layer 41 on each nanostructure 37 in the plurality of nanostructures and on the surface 35 connecting the first level 31 and the second level 33 of the substrate 27, and on the second level 33. The first sub-layer 59, of the second electrode layer 43 may, for example, be deposited using ALD (atomic layer deposition). For example, a thin layer of TiN (or similar) may be deposited. The resulting structure is schematically shown in fig 9E.

[0076] Optionally, in the subsequent step 810, a second sub-layer 61 may be deposited covering the first sub-layer 59 in such a way that spaces between individual nanostructures 37 in the plurality of nanostructures are substantially completely filled by the second sub-layer 61 , and spaces between the plurality of nanostructures 37 and the surface 35 connecting the first level 31 and the second level 33 of the substrate 27 are substantially completely filled by the second sub-layer 61 . Using, for example, a CVD process for depositing the second sub-layer 61 (could be tungsten, TiN, or similar) will fill up all the voids with an over-fill. The resulting structure is schematically shown in fig 9F. The over-fill may then be polished away with a CMP process creating a flush top surface.

[0077] Finally, in step 811 , encapsulation material 25 is deposited and first 21 and second 23 contact pads are formed. The contact pads may be formed using, perse, well known BEOL processes. A typical example using 2-metal- layer BEOL process is shown in fig 9G.

[0078] The person skilled in the art realizes that the present invention by no means is limited to the preferred embodiments described above. On the contrary, many modifications and variations are possible within the scope of the appended claims.

[0079] In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. Any reference signs in the claims should not be construed as limiting the scope.

Claims

CLAIMS1 . An energy storage device comprising: a substrate having a first level, a second level higher than the first level, and a surface connecting the first level and the second level; a plurality of nanostructures vertically extending from the first level of the substrate; a first electrode layer covering each nanostructure in the plurality of nanostructures, the surface connecting the first level and the second level, and the second level of the substrate; a conduction controlling layer conformally covering the first electrode layer; a second electrode layer covering the conduction controlling layer; a first contact pad conductively connected to the first electrode layer on the second level of the substrate; and a second contact pad conductively connected to the second electrode layer.

2. The energy storage device according to claim 1 , wherein the second contact pad is conductively connected to the second electrode layer directly above the plurality of nanostructures.

3. The energy storage device according to claim 1 or 2, wherein the first contact pad and the second contact pad are on the same vertical level in relation to the second level of the substrate.

4. The energy storage device according to any one of the preceding claims, wherein a thickness of the first electrode layer on the surface connecting the first level and the second level is greater than a thickness of the first electrode layer on the second level of the substrate.

5. The energy storage device according to any one of the preceding claims, wherein: the conduction controlling layer covers the first electrode layer on a portion of the second level of the substrate; and the second electrode layer covers the conduction controlling layer on a portion of the second level of the substrate.

6. The energy storage device according to claim 5, wherein: there is an opening in the conduction controlling layer and second electrode layer on the second level of the substrate; and the energy storage device further comprises a conductive structure that extends through the opening to conductively connect the first electrode layer on the second level of the substrate with the first contact pad.

7. The energy storage device according to any one of the preceding claims, wherein the second electrode layer comprises: a first sub-layer conformally covering the conduction controlling layer; and a second sub-layer covering the first sub-layer in such a way that spaces between individual nanostructures in the plurality of conductive nanostructures are substantially completely filled by the second sub-layer, and spaces between the plurality of conductive nanostructures and the surface connecting the first level and the second level of the substrate are substantially completely filled by the second sub-layer.

8. The energy storage device according to any one of the preceding claims, wherein: the energy storage device comprises an electrically insulating encapsulation material at least partly forming an outer boundary surface of the energy storage device; and each of the first contact pad and the second contact pad at least partly forms the outer boundary surface of the energy storage device.

9. An electronic system comprising: a circuit substrate with a circuit substrate conductor pattern, the circuit substrate having circuit substrate pads included in the circuit substrate conductor pattern; a semiconductor component with active circuitry, and component pads coupled to the active circuitry of the semiconductor component, the component pads being connected to the circuit substrate pads of the circuit substrate; a power source interface for receiving power from a power source, the power source interface being connected to the circuit substrate conductor pattern; and an energy storage device according to any one of the preceding claims arranged between the circuit substrate and the semiconductor component, the first contact pad of the energy storage device being conductively connected to a first component pad of the semiconductor component, and the second contact pad of the energy storage device being conductively connected to a second component pad of the semiconductor component.

10. An electronic system comprising: a circuit substrate with a circuit substrate conductor pattern, the circuit substrate having circuit substrate pads included in the circuit substrate conductor pattern; a semiconductor component with active circuitry, and component pads coupled to the active circuitry of the semiconductor component, the component pads being connected to the circuit substrate pads of the circuit substrate; a power source interface for receiving power from a power source, the power source interface being connected to the circuit substrate conductor pattern; and an energy storage device according to any one of the preceding claims embedded in the circuit substrate, the first contact pad of the energy storagedevice being conductively connected to a first component pad of the semiconductor component via a first circuit substrate pad of the circuit substrate conductor pattern, and the second contact pad of the energy storage device being conductively connected to a second component pad of the semiconductor component via a second circuit substrate pad of the circuit substrate conductor pattern.11 . A method of manufacturing an energy storage device, comprising: providing a substrate having a first level, a second level higher than the first level, and a surface connecting the first level and the second level; providing, on the first level of the substrate, a plurality of nanostructures in such a way that each nanostructure in the plurality of nanostructures extends substantially vertically from the first level of the substrate; providing a first electrode layer covering each nanostructure in the plurality of nanostructures, the surface connecting the first level and the second level, and the second level of the substrate; providing a conduction controlling layer conformally covering the first electrode layer; providing a second electrode layer covering the conduction controlling layer; removing at least a portion of the conduction controlling layer and the second electrode layer on the second level of the substrate, to thereby expose the first electrode layer on the second level of the substrate; forming a first contact pad conductively connected to the exposed first electrode layer on the second level of the substrate; and forming a second contact pad conductively connected to the second electrode layer.

12. The method according to claim 11 , wherein: the providing the substrate comprises:providing a single-level substrate that is exposed in a first portion of the single-level substrate and covered by a mask in a second portion of the single-level substrate; and subjecting the single-level substrate to a material removing technique resulting in removal of material from the single-level substrate in the first portion of the single-level substrate and under an edge portion of the mask, until the substrate is at the first level of the substrate where it is exposed and under the edge portion of the mask; providing the first electrode layer comprises depositing, while the mask remains on the substrate, a first conductive layer using a first deposition technique resulting in formation of the first conductive layer on the first level of the substrate and on the surface connecting the first level and the second level; and providing the plurality of nanostructures comprises: depositing, while the mask remains on the substrate, a catalyst layer using a second deposition technique resulting in formation of the catalyst layer on the first conductive layer on the first level of the substrate, as defined by a projection of the mask on the first level of the substrate; and growing nanostructures from the catalyst layer.

13. The method according to claim 12, wherein: the method comprises removing the mask, together with the first conductive layer and the catalyst layer deposited on the mask; and providing the first electrode layer comprises depositing a second conductive layer using a third deposition technique resulting in the second conductive layer conformally covering each nanostructure in the plurality of nanostructures, the first conductive layer on the surface connecting the first level and the second level of the substrate, and the second level of the substrate.

14. The method according to any one of claims 11 to 13, wherein providing the second electrode layer comprises:depositing a first sub-layer conformally covering the conduction controlling layer on each nanostructure in the plurality of nanostructures and on the surface connecting the first level and the second level of the substrate; and depositing a second sub-layer covering the first sub-layer in such a way that spaces between individual nanostructures in the plurality of nanostructures are substantially completely filled by the second sub-layer, and spaces between the plurality of nanostructures and the surface connecting the first level and the second level of the substrate are substantially completely filled by the second sub-layer.

15. The method according to any one of claims 11 to 14, wherein: the method further comprises depositing an electrically insulating encapsulation material to at least partly form an outer boundary surface of the energy storage device; and forming the first contact pad comprises: forming a hole in the electrically insulating encapsulation material over the second level of the substrate; filling the hole with conductive material making conductive contact with the first electrode layer; and forming the first contact pad on the conductive material; and forming the second contact pad comprises: forming a hole in the electrically insulating encapsulation material over the plurality of nanostructures; filling the hole with conductive material making conductive contact with the second electrode layer; and forming the second contact pad on the conductive material.

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