Semiconductor device

Abstract

This semiconductor device has a layered memory including: a plurality of memory circuits which are layered and which each include a plurality of memory cells; and a plurality of first data lines which are formed so as to pass through the plurality of memory circuits. The semiconductor device has an interface circuit that is formed on the layered memory, and that includes a data terminal and a second data line commonly connected to the plurality of first data lines via a plurality of switch circuits. The semiconductor device has a logic circuit that is disposed on the interface circuit, that is connected to the data terminal via a through-via, and that includes a control circuit for controlling operations of the plurality of memory circuits. As a result of this configuration, in the case where a memory having a layered structure and a peripheral circuit are layered, an increase in the bit line capacitance can be suppressed and the read margin can be improved.

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] A known method for manufacturing a semiconductor wafer including multiple semiconductor devices is to form a wafer including a three-dimensional memory by stacking multiple dynamic random access memories (DRAMs) on a substrate, and then bond the wafer to a wafer on which peripheral circuits are formed.The multiple semiconductor devices included in the semiconductor wafer are then singulated to form, for example, high bandwidth memories (HBMs).

[0003] In conventional DRAMs, capacitors are formed to extend perpendicular to the wafer surface. Hereinafter, DRAMs that extend perpendicular to the wafer surface will be referred to as 2D-DRAMs. On the other hand, in a 3D-DRAM, where DRAMs are stacked, for example, the capacitors in memory cells that store data are formed to extend horizontally along the wafer surface and connected to horizontally extending bit lines via transfer transistors. The word lines connected to the gates of the transfer transistors are formed to extend vertically, which is the stacking direction of the DRAM, in order to reduce the RC delay of the word line signal.

[0004] U.S. Patent No. 9,230,609 U.S. Patent No. 10,586,584

[0005] JW Han et al., “Ongoing Evolution of DRAM Scaling via Third Dimension - Vertically Stacked DRAM -”, 2023 Symposium on VLSI Technology and Circuits Digest of Technical Papers, TFS1-12018 IEDM Short CourseMeng Huang, et al., “A 3D Stackable 1T1C DRAM: Architecture, Process Integration and Circuit Simulation”, 15th International Memory Workshop, pp. 29-32, (2023).Applied Materials Memory Master Class, May 5, 2021.Qijun Li, et al., “BEOL-Compatible High-Performance a-IGZO Transistors with Record high Ids,max = 1207 μA / μm and on-off ratio exceeding 1011 at Vds = 1V”, IEDM digest of technical papers, pp. 43-45, (2022).EV Group, NanoCleaveTM - IR Laser Cleave Technology [online], [Retrieved December 28, 2023], Internet <URL: https: / / www.evgroup.com / ja / technologies / nanocleavetm-ir-laser-cleave-technology>

[0006] However, in a 3D-DRAM, when bit lines are extended horizontally, the larger the memory array, the longer the wiring length of the bit lines, and the larger the bit line capacitance becomes. When the bit line capacitance increases, the amount of signal appearing on the bit line when reading data from a memory cell decreases, which may reduce the read margin.

[0007] Furthermore, when a peripheral circuit is formed as a separate layer on a 3D-DRAM, the sense amplifiers formed in the peripheral circuit are connected to the bit lines of the stacked DRAMs. As a result, the total capacitance of the bit lines connected to the sense amplifiers becomes larger than the total capacitance of the bit lines connected to the sense amplifiers of a conventional 2D-DRAM, which may result in a reduced read margin.

[0008] Although extending the bit lines vertically reduces the bit line capacitance compared to extending the bit lines horizontally, the bit line capacitance increases as the number of stacked layers in a 3D-DRAM increases. However, no method has been proposed to suppress the increase in bit line capacitance when extending the bit lines vertically in a 3D-DRAM.

[0009] Therefore, an object of the present invention is to improve the read margin by suppressing an increase in bit line capacitance when stacking a memory and a peripheral circuit with a stacked structure.

[0010] A semiconductor device according to one aspect of the present invention comprises: a stacked memory including a plurality of stacked memory circuits, each including a plurality of memory cells, and a plurality of first data lines formed through the plurality of memory circuits; an interface circuit formed on the stacked memory and including a second data line common to the plurality of first data lines, a plurality of switch circuits connecting the plurality of first data lines to the second data lines, respectively, and a data terminal connected to the second data line; and a logic circuit disposed on the interface circuit and including a via connected to the data terminal, and a control circuit connected to the via, for controlling operation of the plurality of memory circuits.

[0011] According to the present invention, when a memory and a peripheral circuit having a stacked structure are stacked, an increase in bit line capacitance is suppressed, thereby improving the read margin.

[0012] 1. FIG. 1 is a partial cross-sectional view showing an example of a semiconductor device according to a first embodiment of the present invention. 2. FIG. 3 is a partial perspective view showing an overview of a memory section of the semiconductor device of FIG. 1. 3. FIG. 4 is a partial perspective view showing an example of a select transistor of FIG. 2. 4. FIG. 5 is a top view showing an example of an arrangement of bit line contacts connecting global bit lines to a logic section in the semiconductor device of FIG. 2. 5. FIG. 6 is a cross-sectional view showing an example of connecting a TSV formed in the logic section of FIG. 1 to the bit line contact of FIG. 4. 6. FIG. 7 is a circuit diagram showing an example of a connection between a cell capacitor and a global bit line of FIG. 2. 7. FIG. 8 is a block diagram showing an example of a circuit mounted on the semiconductor device of FIG. 1. 8. FIG. 9 is a flow chart showing an example of a method for manufacturing the semiconductor device of FIG. 1. 9. FIG. 10 is a flow chart showing a continuation of FIG. 10. 11 is a flow chart showing an example of a method for manufacturing a semiconductor device having the same circuit configuration as the semiconductor device of FIG. 1. 12 is a flow chart showing a continuation of FIG. 11. 13 is a flow chart showing a continuation of FIG. 14. 14 is an explanatory diagram showing an example of calculating the contact pitch, which is the layout pitch of vias connected to the pads shown in FIG. 5, for each number of stacked memory layers. 15 is a plan view showing an example of an arrangement of bit line contacts when the memory section in FIG. 16 has 128 memory layers. 21 is an explanatory diagram showing an example of calculating the length of a global bit line and the length of a local bit line for each number of stacked memory layers. FIG. 22 is a diagram showing the ratio of bit line capacitance for each number of stacked memory layers of a 3D-DRAM to a 2D-DRAM. FIG. 23 is a diagram showing an equation used to calculate the bit line capacitance characteristics of FIG. 19. FIG. 24 is a circuit diagram showing an example of a main part of a semiconductor device according to a second embodiment of the present invention. FIG. 25 is a timing chart showing an example of the operation of the semiconductor device 100C shown in FIG.

[0013] Hereinafter, embodiments will be described with reference to the drawings. In each drawing, the same components are designated by the same reference numerals, and duplicate explanations may be omitted. Reference numerals indicating signal names are also used to indicate signal line names or terminal names. A single signal line may be composed of multiple lines.

[0014] 1 is a partial cross-sectional view showing an example of a semiconductor device according to a first embodiment of the present invention. The semiconductor device 100 shown in Fig. 1 has a memory section 120 having a 3D-DRAM and a transistor switch section TR-SW, and a logic section 110 that controls the access operation of the memory section 120. The memory section 120 and the logic section 110 are bonded to each other via an adhesive layer ADHL.

[0015] 1, elements formed in semiconductor device 100 are shown enlarged for ease of understanding, but in reality, the elements shown in Fig. 1 are repeatedly arranged in the X and Y directions of Fig. 1. Semiconductor device 100 is formed by connecting a logic wafer having a plurality of logic units 110 and a memory wafer having a plurality of memory units 120 by WOW (Wafer-on-Wafer) technology, and then separating them into individual pieces by dicing.

[0016] The 3D-DRAM has multiple memory layers ML stacked on a semiconductor substrate SUB1. The 3D-DRAM is an example of a stacked memory. In FIG. 1, the 3D-DRAM has four memory layers ML, but the number of memory layers ML is not limited to four as long as it is two or more. Each memory layer ML has multiple memory cells MC, each including a cell capacitor CCAP and a transfer transistor TRT. The gate of the transfer transistor TRT is connected to a word line WL. The circuit formed in the memory layer ML is an example of a memory circuit. For example, the memory cells MC are dynamic memory cells that require periodic refreshing. The cell capacitor CCAP is an example of a storage node. The transfer transistor TRT is an example of a first transistor.

[0017] The cell capacitor CCAP of each memory layer ML is connected to a local bit line LBL common to the plurality of memory layers ML via a transfer transistor TRT. The local bit line LBL extends in the Z direction, which is the stacking direction of the memory layers ML. The end of the local bit line LBL in the Z direction is connected to the transistor switch unit TR-SW via a via VIA and a wiring. The local bit line LBL is an example of a first data line formed to penetrate the plurality of memory layers ML.

[0018] The transistor switch unit TR-SW has a pair of select transistors SELT corresponding to each local bit line LBL. The transistor switch unit TR-SW is an example of an interface circuit. The select transistor SELT is an example of a switch circuit. One of the source and drain of the select transistor SELT is connected to the local bit line LBL via a via and a wiring. The other of the source and drain of the select transistor SELT is connected to the global bit line GBL via a via. For example, the global bit line GBL is provided corresponding to a data input / output terminal (not shown). The global bit line GBL is an example of a second data line provided in common to multiple local bit lines LBL. The global bit line GBL is connected to a pad PAD1 formed on the surface of the memory unit 120 in a region different from the cross section shown in FIG. 1.

[0019] The logic unit 110 includes a control circuit CNTL such as a sense amplifier S / A and a data input / output circuit I / O, and a through silicon via (TSV) that penetrates to a pad PAD1 of the memory unit 120. The TSV is an example of a via. The pad PAD1, which is connected to a global bit line GBL, is connected to the sense amplifier S / A via a TSV formed in the logic unit 110. The control circuit CNTL includes a command decoder, an address decoder, a word line driver circuit, and the like. The word line driver circuit of the logic unit 110 drives each word line WL of the memory unit 120 via the TSV and the pad PAD1 of the memory unit 120.

[0020] FIG. 2 is a partial perspective view showing an overview of the memory unit 120 of the semiconductor device 100 of FIG. 1. In each memory layer ML, word lines WL (WL0-WL3) are formed extending in the Y direction at intervals in the X direction. The cell capacitor CCAP of the memory cell MC is connected to the local bit line LBL via a transfer transistor TRT whose gate is connected to the word line WL. Although not particularly limited, the word lines WL have a double-gate structure, and each memory cell MC has a pair of transfer transistors TRT corresponding to the double gate. For example, word lines WL that overlap in a plan view seen from the Z direction can be connected to the logic unit 110 by forming a staircase structure at their ends in the extension direction.

[0021] In FIG. 2, the local bit line LBL (LBL0-LBL3) located in the center is connected to a pair of memory cells MC adjacent to each other on both sides in the X direction in a plan view, but in reality, all of the local bit lines LBL except for the local bit lines LBL at both ends in the X direction are connected to a pair of memory cells MC.

[0022] During a read access of the memory unit 120, one of a pair of word lines WL adjacent to a local bit line LBL is driven to a high level in one of the multiple memory layers ML. Then, charge is read from the cell capacitor CCAP of the memory cell MC connected to the driven word line WL to the local bit line LBL. By sharing the local bit line LBL between a pair of memory cells MC in each memory layer ML, the number of local bit lines LBL can be reduced, and an increase in the layout size of the memory unit 120 can be suppressed.

[0023] The transistor switch unit TR-SW has select transistors SELT0-SELT3 that connect the local bit lines LBL0-LBL3 to the global bit lines GBL0-GBL3, respectively. The gates of the select transistors SELT (SELT0-SELT3) are connected to a bit line select signal line BLSEL. The bit line select signal line BLSEL is wired for each group of local bit lines LBL0-LBL3 aligned in the Y direction. The global bit lines GBL0-GBL3 are connected to sense amplifiers S / A0-S / A3, not shown, respectively.

[0024] During a read access to the memory unit 120, one of the multiple groups of local bit lines LBL0-LBL3 is connected to the global bit lines GBL0-GBL3. The other groups of local bit lines LBL0-LBL3 are not connected to the global bit lines GBL0-GBL3. Therefore, during a read access to the memory unit 120, any memory cell MC in the memory layer ML selected by the word line WL can be selectively connected to the global bit lines GBL0-GBL3 via one group of local bit lines LBL0-LBL3.

[0025] This allows the capacitance of the bit lines (GBL+LBL) connected to the sense amplifier S / A during read access to be reduced compared to when the global bit line GBL is also connected to a local bit line LBL that is not used for reading data. As a result, the amount of signal read from the memory cell MC to the global bit line GBL can be relatively increased, improving the data read margin by the sense amplifier S / A. Furthermore, since the data amplification speed by the sense amplifier S / A is increased, the read access time can be shortened. Furthermore, since the bit line capacitance can be reduced, the power consumption for refresh can be reduced.

[0026] 2 is actually arranged repeatedly in the Y direction, with, for example, 128 global bit lines GBL arranged and connected to 128 sense amplifiers S / A, respectively. During a read access to the memory unit 120, data read from the 128 memory cells onto the 128 global bit lines GBL via the local bit lines LBL is amplified by the 128 sense amplifiers S / A controlled by the logic unit 110. Of the 128 pieces of data amplified by the sense amplifiers S / A, for example, 64 pieces of data selected by column selection switches are output from 64 data input / output terminals. Furthermore, the 128 pieces of data amplified by the sense amplifiers S / A are written back to the memory cells MC.

[0027] Alternatively, the data amplified by the 128 sense amplifiers S / As may be output from the 128 data input / output terminals without providing column selection switches. The number of global bit lines GBL and the number of sense amplifiers S / As may be, for example, 1024, 2048, or 4096.

[0028] On the other hand, in a write operation of the memory unit 120, first, data is read from 128 memory cells MC to 128 global bit lines GBL and amplified by 128 sense amplifiers S / A. After this, 64 of the 128 data amplified by the sense amplifiers S / A are rewritten with data received at the data input / output terminals, and the 128 data including the rewritten data are written back to the memory cells MC.

[0029] 3 is a partial perspective view showing an example of the select transistor SELT in FIG. 2. For example, each of the select transistors SELT0-SELT3 is formed by a pair of TFTs (Thin Film Transistors) arranged on both sides of the local bit line LBL in the X direction in a plan view. The pair of TFTs is an example of a second transistor. The source / drain of each TFT is formed spaced apart in the X direction, and the channel CH of each TFT is formed on the 3D-DRAM side of the source / drain. A select gate SELGT extending in the Y direction is formed on the 3D-DRAM side of the channel CH of the TFTs aligned in the Y direction.

[0030] One of the source / drain of each of the pair of TFTs is connected to the Z-direction end of the local bit line LBL. The other of the source / drain of each of the pair of TFTs is connected to a global bit line GBL (one of GBL0-GBL3). Activation of the selection gate SELGT electrically connects the source / drain of each of the TFTs aligned in the Y direction via the channel CH, thereby electrically connecting each local bit line LBL to the global bit line GBL.

[0031] It is known that thin-film transistors such as TFTs are prone to asymmetry due to alignment during the manufacturing process. As shown in Figure 3, by forming the select transistor SELT using TFTs arranged on both sides of the local bit line LBL, it is possible to average out variations in electrical characteristics due to alignment asymmetry. As a result, it is possible to reduce variations in the on-resistance of the select transistor SELT.

[0032] 4 is a top view showing an example of the arrangement of bit line contacts BLCNT that connect the global bit lines GBL to the logic unit 110 in the memory unit 120 of FIG. 2. For example, the bit line contacts BLCNT may be formed by vias. As shown in FIG. 2, the global bit line GBL is provided in common to a plurality of local bit lines LBL.

[0033] The bit line contacts BLCNT are connected to each global bit line GBL, and the layout pitch of the bit line contacts BLCNT is larger than the layout pitch of the local bit lines LBL. Therefore, compared to the case where the local bit lines LBL are directly connected to the logic unit 110 via the bit line contacts BLCNT, the number of bit line contacts BLCNT can be reduced and the layout pitch of the bit line contacts BLCNT can be increased.

[0034] 4, the bit line contact BLCNT is depicted as being larger than the width of the global bit line GBL, but in reality, the diameter of the bit line contact BLCNT is equal to or smaller than the width of the global bit line GBL. Therefore, there is no need to worry about the EPE (Edge Placement Error) margin for the bit line contact BLCNT and the global bit line GBL adjacent to the global bit line GBL to which the bit line contact BLCNT is connected.

[0035] 5 is a cross-sectional view showing an example in which a TSV formed in the logic section 110 of FIG. 1 is connected to a bit line contact BLCNT of FIG. 4. A pad PAD1 formed on the surface of the memory section 120 is connected to the bit line contact BLCNT connected to the global bit line GBL. The pad PAD1 is formed at a position corresponding to the TSV in the logic section 110, in accordance with the cross-sectional shape of the lower end of the TSV. For example, the diameter of the TSV is about several μm. The bit line contact BLCNT and the pad PAD1 are examples of data terminals.

[0036] The TSV and the pad PAD1 are connected bumplessly. This allows the layout pitch of the pad PAD1 and the layout pitch of the TSV to be smaller than when the pad PAD1 and the TSV are connected via bumps, and makes it possible to suppress an increase in load capacitance.

[0037] 4, the layout pitch of the bit line contacts BLCNT can be made larger than the layout pitch of the local bit lines LBL, so that the pads PAD1 connected to the TSVs in the logic area 110 can be arranged without interfering with the adjacent pads PAD1.

[0038] Fig. 6 is a circuit diagram showing an example of the connection between the cell capacitor CCAP and the global bit line GBL in Fig. 2. Fig. 6 shows the area corresponding to the global bit lines GBL2-GBL3 out of the areas shown in Fig. 2.

[0039] 6, memory cells MC connected to each local bit line LBL are formed in different memory layers ML (not shown), and word lines WL0-WL3 are formed in different memory layers ML. The bit line selection signal line BLSEL, selection transistor SELT, global bit line GBL, bit line contact BLCNT, and pad PAD1 are formed in a transistor switch unit TR-SW (not shown). The TSVs and sense amplifiers S / A2 and S / A3 are formed in a logic unit 110.

[0040] 7 is a block diagram showing an example of a circuit mounted on the semiconductor device 100 of FIG. 1. Each memory unit 120 has a memory core 121 including n+1 banks BK0-BKn (n is an integer equal to or greater than 1). In the memory unit 120 facing the logic unit 110, the transistor switch unit TR-SW is formed on the 3D-DRAM as a monolithic integrated circuit. Therefore, compared to when a separate integrated circuit having the transistor switch unit TR-SW is placed on the 3D-DRAM, the thickness of the transistor switch unit TR-SW can be made thinner, and the alignment accuracy with the logic wafer LGCW can be improved.

[0041] The logic unit 110 has a configuration register 111, an operation control circuit 112, a command decoder 113, an address decoder 114, and a data input / output circuit 115. The data input / output circuit 115 includes a sense amplifier S / A. The logic unit 110 is an example of a logic circuit, and the operation control circuit 112, the command decoder 113, the address decoder 114, and the data input / output circuit 115 are an example of a control circuit that controls the operation of the memory unit 120. The logic unit 110 is connected to external terminals, namely a clock terminal CK, a command terminal CMD, an address terminal AD, a data strobe terminal DQS, and a data terminal DQ.

[0042] The configuration register 111 is configured with operational specifications for the memory unit 120, such as CAS latency and burst length. The operation control circuit 112 receives a clock signal CK, a command signal CMD, an address signal AD, and a data strobe signal. The operation control circuit 112 also receives a data signal DQ during write access to the memory unit 120 and outputs the data signal DQ during read access to the memory unit 120. For example, the command signal CMD may include a chip select terminal, a row address strobe signal, a column address strobe signal, and a write enable signal.

[0043] The command decoder 113 decodes the command signal CMD and outputs a control signal corresponding to the decoded command to the memory unit 120. The address decoder 114 decodes the address signal AD and drives the word lines WL via a word driver (not shown) and controls the operation of a column selection switch (not shown). The data input / output circuit 115 outputs write data received at a data terminal DQ to the memory unit 120 and outputs read data received from the memory unit 120 to the data terminal DQ.

[0044] The memory unit 120 may be formed on a memory wafer MEMW, and the logic unit 110 may be formed on a logic wafer LGCW. Then, the memory wafer MEMW on which the transistor switch unit TR-SW is formed and the logic wafer LGCW may be bonded together and then diced to cut out individual semiconductor devices 100. The memory wafer MEMW is an example of a first wafer, and the logic wafer LGCW is an example of a second wafer.

[0045] The memory wafer MEMW may be manufactured by sequentially bonding wafers formed for each memory layer ML and then forming the transistor switch unit TR-SW as a monolithic integrated circuit. Alternatively, the memory wafer MEMW may be manufactured by integrally forming the transistor switch unit TR-SW and a plurality of memory layers ML.

[0046] 8 to 10 are flow diagrams showing an example of a method for manufacturing the semiconductor device of FIG. 1. First, in FIG. 8A, a cell array of a 3D-DRAM is formed on a substrate SUB1 made of, for example, Si, using a known manufacturing method. Next, in FIG. 8B, an interlayer insulating film is formed on the 3D-DRAM, and then the surface of the interlayer insulating film is planarized.

[0047] 8(C), an opening is formed in a lithography process that penetrates to the local bit line LBL of the 3D-DRAM, and a via is formed by filling the opening with a metal material. Next, in FIG. 8(D), an IGZO film is deposited, and then a TFT using the IGZO film as a channel is formed in a lithography process.

[0048] Next, in FIG. 8E, the local bit line LBL and the TFTs located on both sides of the local bit line LBL in a plan view are connected by wiring MTL1 made of copper or the like and vias VIA. Next, in FIG. 8F, an interlayer insulating film is formed covering the wiring MTL1, and openings are formed that penetrate to the TFTs. The openings are filled with a metal material such as copper, and the TFTs are then interconnected with wiring made of copper or the like to form global bit lines GBL. After this, an interlayer insulating film is formed on the global bit lines GBL, and pads PAD1 connected to the global bit lines GBL are formed on the interlayer insulating film using copper or the like, thereby completing the memory wafer MEMW including the memory unit 120 shown in FIG. 1. Note that an insulating protective film may be formed on the surface of the memory unit 120 in areas other than the pads PAD1.

[0049] 9A, a logic wafer LGCW is prepared in which peripheral circuits, power supply pads, input / output pads, etc. of a 3D-DRAM are formed on a substrate SUB2 made of Si or the like. Next, in FIG. 9B, a support wafer is temporarily bonded to the front surface of the logic wafer LGCW. Next, in FIG. 9C, the substrate SUB2 located on the back surface of the logic wafer LGCW is polished to a thickness of, for example, about 5 μm, completing the logic wafer LGCW to be attached to the memory unit 120.

[0050] In FIG. 10A, the back surface of the logic wafer LGCW is bonded to the front surface of the memory wafer MEMW. After this, the support wafer is removed from the front surface of the logic wafer LGCW. Next, in FIG. 10B, openings are formed that penetrate from the front surface of the logic wafer LGCW to the pads PAD1 of the memory wafer MEMW, and copper is sputtered into the openings and the surface of the openings to form TSVs. For example, the pads PAD1 are used to connect global bit lines GBL or word lines WL. Next, in FIG. 10C, wiring MTL2 made of copper or the like that connects to the TSVs is formed, and a protective film is formed covering the front surface of the logic wafer LGCW. After this, a dicing process is performed to separate the semiconductor devices 100, and the semiconductor devices 100 are completed.

[0051] 11 and 12 are flow diagrams showing an example of a method for manufacturing a semiconductor device 100A having the same circuit configuration as the semiconductor device 100 of Fig. 1. The method for manufacturing the memory section 120 is the same as that of Fig. 8, and therefore description thereof will be omitted. The semiconductor device 100A is formed by placing a memory wafer MEMW and a logic wafer LGCW with their element regions facing each other (face-to-face type).

[0052] In Figure 11(A), the surface of a logic wafer LGCW, on which TSVs are formed partway through a substrate SUB2 made of Si or the like, is cleaned and activated. The TSVs are connected to pads PAD2 formed on the surface of the logic wafer LGCW through vias VIA and wiring W1. Next, in Figure 11(B), the pads PAD2 of the upside-down logic wafer LGCW are aligned with the pads PAD1 of the memory wafer MEMW, and the pads PAD1 and PAD2 are bonded by heat treatment (hybrid bonding). Next, in Figure 11(C), the substrate SUB2, which is the back surface of the logic wafer LGCW, is polished until the TSVs are exposed.

[0053] 12A, a redistribution layer RDL including vias and wiring made of copper or the like connected to the TSVs is formed on the substrate SUB2 of the logic wafer LGCW. Next, in FIG. 12B, a cover film CVR is formed on the redistribution layer RDL, and then bonding openings are formed, and stud bumps BMP are formed, thereby forming a semiconductor device 100A having a circuit configuration equivalent to that of the semiconductor device 100 shown in FIG. 1. After this, a dicing process is performed, and the semiconductor device 100A is divided into individual pieces, thereby completing the semiconductor device 100A.

[0054] 13 to 15 are flow charts showing an example of a method for manufacturing a semiconductor device 100B having the same circuit configuration as the semiconductor device 100 in Fig. 1. The method for manufacturing the logic section 110 is the same as that shown in Figs.

[0055] 13A, before forming the 3D-DRAM, a select transistor SELT is formed on a substrate SUB1 made of Si or the like instead of a TFT. In addition, taking into consideration the subsequent heat treatment, vias, wiring, etc. connected to the select transistor SELT are formed using a high-melting point metal such as W, Ru, or Mo.

[0056] The vias located between a pair of adjacent select transistors SELT and extending toward the substrate SUB1 will be connected to a global bit line GBL later, and the vias located on both sides of the pair of select transistors SELT and extending toward the opposite side of the substrate SUB1 will be connected to a local bit line LBL later.

[0057] Next, in Fig. 13(B), a wafer on which a Si / SiGe super lattice structure has been grown is bonded to the surface on which the select transistor SELT has been formed without alignment, and then, in Fig. 13(C), the Si layer on the surface of the bonded wafer with the super lattice structure is shaved until it becomes thin.

[0058] Next, in FIG. 13(D), the Si layer exposed on the surface is removed by deep RIE (Reactive Ion Etching). Next, in FIG. 13(E), the SiGe layer exposed on the surface is wet-etched. The etching is stopped at the Si surface. Next, in FIG. 13(F), patterning is performed by photolithography based on the pattern of the layer in which the select transistor SELT is formed, and the SiGe layer between the Si layers is removed by wet etching to form the structure of the cell capacitor CCAP of the 3D-DRAM.

[0059] Next, in Fig. 14A, transfer transistors TRT and local bit lines LBL are formed using a photolithography technique or the like, and a cell array structure of the 3D-DRAM is formed. Next, in Fig. 14B, an interlayer insulating film is formed on the 3D-DRAM, and then the surface of the interlayer insulating film is planarized.

[0060] Next, in FIG. 14(C), a support wafer is temporarily bonded to the surface of the interlayer insulating film. Next, in FIG. 14(D), the substrate SUB1 of the upside-down wafer is removed by polishing. The polishing is stopped when the STI (Shallow Trench Isolation) and the metal plug MPLG are exposed. Next, in FIG. 14(E), the metal plug MPLG is connected to wiring MTL3, such as copper, which is the global bit line GBL, through a via.

[0061] 15A, an interlayer insulating film is formed to cover the wiring MTL3 (GBL), and a pad PAD1 connected to the global bit line GBL is formed of copper on the interlayer insulating film, thereby completing a memory wafer MEMW including a memory section 120B similar to the memory section 120 shown in FIG.

[0062] 15(B), similarly to FIG. 10, a logic wafer LGCW is bonded onto the memory wafer MEMW, TSVs are formed to connect to the pads PAD1 of the memory wafer MEMW, and a semiconductor device 100B having a circuit configuration equivalent to that of the semiconductor device 100 shown in FIG. 1 is completed. After this, a protective film is formed covering the surface of the logic wafer LGCW, and a dicing process is performed to separate the semiconductor devices 100B. Note that the logic wafer LGCW may be bonded face-to-face to the memory wafer MEMW, as shown in FIG. 11.

[0063] 16 is an explanatory diagram showing an example of calculation of the contact pitch, which is the layout pitch of the via connected to the pad PAD1 (GBL) shown in Fig. 5, for each number of stacked memory layers ML. As prerequisites for the calculation, F (feature size), which is the minimum wiring width, is set to 35 nm, the size of two memory cells MC in the X direction is set to 45F, and the size of the memory cell MC in the Y direction is set to 2F.

[0064] The dimensions of each memory cell MC in the X direction are: cell capacitor CCAP = 15F, transfer transistor TRT = 6F, local bit line LBL = 1F, and the spacing between opposing cell capacitors CCAP in the X direction is 1F. The width of the local bit line LBL is 2F, but since it is shared by two memory cells MC, a local bit line LBL of 1F is allocated to each memory cell MC. Furthermore, 8,192 memory cells MC are connected to each global bit line GBL (i.e., each sense amplifier S / A), and 8,192 refresh operations are performed during the period (approximately 100 ms) in which each memory cell MC can retain data without loss (8k refresh).

[0065] 1, memory cells MC are connected to both sides of each local bit line LBL in the X direction. Therefore, the number of memory cells MC connected to each local bit line LBL is twice the number of stacked layers. The number of local bit lines LBL connected to each sense amplifier S / A is half the number of memory cells per memory layer ML (8,192 / number of stacked layers).

[0066] The contact pitch CPX of the bit line contacts BLCNT in the X direction and the contact pitch CPY of the bit line contacts BLCNT in the Y direction are expressed in terms of F number and actual layout pitch [μm] when the local bit lines LBL connected to each sense amplifier S / A are arranged two-dimensionally in the X and Y directions. The layout pitch expressed in μm shows an example where F=35 nm.

[0067] For example, when 128 memory layers ML are stacked, as shown in the shaded area, the number of memory cells MC connected to each local bit line LBL is 256, and the number of local bit lines LBL connected to each sense amplifier S / A is 32. In this case, the contact pitch CPX is set to 45F (1.575 μm), and the contact pitch CPY is set to 32F (1.12 μm).

[0068] Fig. 17 is a plan view showing an example of the arrangement of the bit line contacts BLCNT when the memory section 120 has 128 memory layers ML in Fig. 16. White circles indicate local bit lines LBL, and black circles indicate bit line contacts BLCNT.

[0069] When the memory unit 120 has 128 memory layers ML, for example, the contact pitch CX in the X direction is 45F and the contact pitch CPY in the Y direction is 32F. Thirty-two bit line contacts BLCNT are distributed and arranged in an area where 32 local bit lines LBL are arranged in the X direction and 32 local bit lines LBL in the Y direction. The distance between two adjacent bit line contacts BLCNT in the X direction is 90F (3.151 μm), and the distance between two adjacent bit line contacts BLCNT in the Y direction is 56F (1.974 μm). When the memory unit 120 has 512 memory layers ML, for example, the distance between two adjacent bit line contacts BLCNT in the X direction is 90F (3.151 μm), and the distance between two adjacent bit line contacts BLCNT in the Y direction is 46F (1.613 μm).

[0070] 5, the upper end of the bit line contact BLCNT is connected to a pad PAD1, and the pad PAD1 is connected to a TSV in the logic unit 110. In this embodiment, the layout pitch of the bit line contact BLCNT can be made larger than the layout pitch of the local bit line LBL, and therefore, as shown in FIG. 5, the pad PAD1 connected to the TSV in the logic unit 110 can be arranged without interfering with the adjacent pad PAD1.

[0071] 18 is an explanatory diagram showing an example in which the lengths of the global bit lines GBL and the local bit lines LBL are calculated for each number of stacked memory layers ML. As in FIG. 16, it is assumed that 8192 memory cells MC are connected to each global bit line GBL (i.e., each sense amplifier S / A).

[0072] As shown in the shaded area, for example, if the memory unit 120 has 128 memory layers ML, 32 local bit lines LBL are connected to each sense amplifier S / A. In this case, the length of the global bit line GBL corresponds to the width when the 32 local bit lines LBL are arranged in the X direction at a pitch of 45F, which is 1440F (32×45F), or 50.4 μm (1440F×35 nm).

[0073] Also, for example, assume that each memory layer ML is formed by stacking 3.5 layers of various wiring, elements, and other materials. If the memory unit 120 has 128 memory layers ML, the total number of materials for the 128 memory layers ML is 448 (3.5 × 128). For example, if the average thickness of each material is 20 nm, the length of the local bit line LBL extending in the Y direction is 8.96 μm (448 × 20 nm). Therefore, if the memory unit 120 has 128 memory layers ML, the length of the bit line (GBL + SBL) connected to the sense amplifier S / A when accessing the memory cell MC is 59.36 μm.

[0074] 19 is a diagram showing the ratio of bit line capacitance for each number of stacked memory layers ML of a 3D-DRAM to a 2D-DRAM. The 2D-DRAM has one memory layer ML. The bit line capacitance ratio shown in FIG. 19 was calculated assuming that the bit line pitch of the 2D-DRAM and the 3D-DRAM is the same (for example, 70 nm).

[0075] "Without select transistor SELT" indicates that all local bit lines LBL are connected to the global bit line GBL. "With select transistor SELT" indicates that only the local bit line LBL selected by the select transistor SELT is connected to the global bit line GBL.

[0076] In the case of "without select transistor SELT," the fewer the number of memory layers ML, the longer the global bit lines GBL. As a result, the capacitance overhead due to the global bit lines GBL increases, and the bit line capacitance ratio is always larger than that of 2D-DRAM. By increasing the number of memory layers ML, the bit line capacitance decreases, but because of the bit line capacitance of the local bit lines LBL, it does not become smaller than the bit line capacitance of 2D-DRAM.

[0077] In the case of "with select transistor SELT," the bit line capacitance ratio can always be made smaller than that of a 2D-DRAM, regardless of the number of memory layers ML. Because the effective bit line capacitance can be reduced when the sense amplifier S / A is operating, the amount of change in the bit line voltage due to data read from the memory cell MC can be made relatively large. As a result, the read margin for data from the memory cell MC can be improved, enabling stable operation of the 3D-DRAM. Furthermore, because the amount of change in the bit line voltage is relatively large, the sense amplifier S / A can be operated at high speed, thereby reducing the memory access time of the 3D-DRAM.

[0078] Equation (1) shows the data retention characteristics of a DRAM. From equation (1), it can be seen that the smaller the bit line capacitance CB is relative to the memory cell capacitance CS, the more the operating margin improves. Furthermore, the charge / discharge current due to the operation of the sense amplifier S / A is a major factor in increasing the power consumption during operation of the DRAM. Reducing the bit line capacitance CB and reducing the charge / discharge current of the sense amplifier S / A can also contribute to reducing the overall power consumption of the 3D-DRAM.

[0079] FIG. 20 is a diagram showing the equations used to calculate the bit line capacitance characteristics of FIG. 19. The effective bit line length L2DbitL in a 2D-DRAM is calculated using equation (2). RefreshCycle in equation (2) is set to 8192. cellPy in equation (2) indicates the pitch (F number) of the memory cells MC in the Y direction. F in equation (2) indicates the minimum wiring width (feature size). epsilon2D in equation (2) indicates the capacitance coefficient of the bit line in the 2D-DRAM, and is set according to the load connected to the bit line.

[0080] The effective bit line length L3DbitL with the select transistor SELT in the 3D-DRAM and the effective bit line length L3DbitL' without the select transistor SELT are calculated by equations (3) and (4), respectively. LglobalbitL in equations (3) and (4) indicates the effective length of the global bit line GBL and is calculated by equation (5). LverticalbitL in equations (3) and (4) indicates the effective length of the local bit line LBL and is calculated by equation (6). nVbitL in equation (4) indicates the total number of local bit lines LBL and is calculated by equation (7).

[0081] In equation (5), cellpx represents the pitch (F number) in the X direction of a pair of memory cells MC arranged on both sides of the local bit line LBL in the X direction in a plan view. In equation (6), matLperLcel0 represents the number of layers of material required for each memory layer ML (e.g., 3.5). In equation (6), matLthick represents the thickness of the material (e.g., 20 nm). In equation (6), nLayer represents the number of layers of the memory layer ML.

[0082] Then, by finding and plotting CapratiowithSELT in equation (8) for each number of stacked memory layers ML, a curve with the select transistor SELT in Fig. 19 can be obtained. By finding and plotting CapratiowithoutSELT in equation (9) for each number of stacked memory layers ML, a curve without the select transistor SELT in Fig. 19 can be obtained.

[0083] As described above, in the first embodiment, during read access to the memory unit 120 in which a plurality of memory layers ML are stacked, one of a plurality of local bit lines LBL formed to penetrate the memory layers ML is connected to the global bit line GBL.

[0084] This improves the data read margin by the sense amplifier S / A. That is, when stacking a stacked memory and a peripheral circuit, the read margin can be improved by suppressing an increase in bit line capacitance. Furthermore, the data amplification speed by the sense amplifier S / A is increased, thereby shortening the read access time.

[0085] By sharing the local bit line LBL between a pair of memory cells MC, the number of local bit lines LBL can be reduced, and an increase in the layout size of the memory unit 120 can be suppressed.

[0086] By forming the select transistor SELT using TFTs arranged on both sides of the local bit line LBL, it is possible to average out variations in electrical characteristics due to asymmetric alignment, thereby reducing variations in the on-resistance of the select transistor SELT.

[0087] The layout pitch of the bit line contacts BLCNT connected to the global bit line GBL is larger than the layout pitch of the local bit line LBL. Therefore, compared to when the local bit line LBL is directly connected to the bit line contacts BLCNT, the number of bit line contacts BLCNT can be reduced and the layout pitch of the bit line contacts BLCNT can be increased. This allows the pad PAD1 connected to the TSV of the logic unit 110 to be arranged without interfering with the adjacent pad PAD1.

[0088] Because the transistor switch unit TR-SW is formed as a monolithic integrated circuit, the thickness of the transistor switch unit TR-SW can be made thinner than when a separate integrated circuit having the transistor switch unit TR-SW is placed on the 3D-DRAM, which allows for higher accuracy in alignment with the logic wafer LGCW.

[0089] 21 is a circuit diagram showing an example of a main part of a semiconductor device according to a second embodiment of the present invention. Elements similar to those in FIG. 6 are given the same reference numerals, and detailed description thereof will be omitted. The semiconductor device 100C shown in FIG. 21 has a memory section 120 and a logic section 110, similar to FIG. 1. The structure of the memory section 120 is similar to the structure of the memory section 120 shown in FIGS. 2 to 4. The circuit configuration of the logic section 110 is similar to the circuit configuration of the logic section 110 shown in FIG. 7.

[0090] 21 , a pair of sense amplifiers S / A-A and S / A-B, each belonging to group A and group B, is provided for each global bit line GBL. Sense amplifier S / A-A is connected to global bit line GBL via switch SWA1 and to a reference bit line (not shown) via switch SWA2. Sense amplifier S / A-B is connected to global bit line GBL via switch SWB1 and to a reference bit line (not shown) via switch SWB2. Each of sense amplifiers S / A-A and S / A-B differentially amplifies the voltage read from memory cell MC onto global bit line GBL and the voltage on the reference bit line, thereby reading data stored in memory cell MC.

[0091] The switches SWA and SWB are turned on exclusively when the memory unit 120 is accessed and turned off when the memory unit 120 is not accessed, based on the control of the logic unit 110. In other words, the switch SWA is turned on when the sense amplifier S / A-A operates, and the switch SWB is turned on when the sense amplifier S / A-B operates.

[0092] The memory unit 120 has a memory array belonging to group A and a memory array belonging to group B. Data read from memory cells MC in group A is transmitted to the sense amplifiers S / A of group A via one local bit line LBL, select transistor SELT, global bit line GBL, and switch SWA, and amplified. Data read from memory cells MC in group B is transmitted to the sense amplifiers S / A of group B via one local bit line LBL, select transistor SELT, global bit line GBL, and switch SWB, and amplified.

[0093] 21, the select transistors connected only to the memory cells MC of group A are indicated by SELTA. The select transistors connected only to the memory cells MC of group B are indicated by SELTB. The select transistors connected in common to the memory cells MC of groups A and B are indicated by SELTA / B. The word lines of group A are indicated by the symbol WL-A, and the word lines of group B are indicated by the symbol WL-B.

[0094] The semiconductor device 100C can refresh the memory cells MC by sequentially operating the sense amplifiers S / A of groups A and B during one refresh cycle, amplifying data sequentially read from the memory cells MC of groups A and B, and writing the amplified data back to the memory cells MC from which it was read. Here, a refresh cycle refers to an operation cycle in which data is read from the memory cells MC, amplified by the sense amplifiers S / A, and written back to the memory cells MC. Although it generally refers to the read operation cycle in which data is read from the memory cells MC, it will be simply referred to as a refresh cycle to avoid confusion. For example, in FIG. 21 , 16 memory cells connected to global bit line GBL3 can be refreshed in eight refresh cycles.

[0095] The grouping of the memory unit 120 is not limited to the example shown in Figure 21. For example, groups A and B may be assigned to every four memory cells MC connected to a local bit line LBL. In this case, four memory cells arranged in the horizontal direction in Figure 21 and connected to a common local bit line LBL may be assigned alternately to groups A and B.

[0096] Alternatively, the memory unit 120 may be divided into four groups, and four sense amplifiers S / A corresponding to each of the four groups may be connected to each global bit line GBL and operated exclusively. In this case, the sense amplifiers S / A of the four groups may be operated in sequence during one refresh cycle, refreshing the memory cells MC of the four groups. For example, in the example shown in FIG. 21, 16 memory cells connected to the global bit line GBL3 may be refreshed in four refresh cycles.

[0097] Fig. 22 is a timing chart showing an example of the operation of the semiconductor device 100C shown in Fig. 21. In Fig. 22, waveforms showing the select transistors SELTA, SELTB and the switches SWA, SWB represent waveforms of switch control signals supplied to the select transistors SELTA, SELTB and the switches SWA, SWB, respectively. The select transistors SELTA, SELTB and the switches SWA, SWB are turned on when the corresponding switch control signals are at a high level, and are turned off when the corresponding switch control signals are at a low level.

[0098] During one refresh cycle, the semiconductor device 100C sequentially refreshes the memory cells MC of group A and the memory cells MC of group B. To this end, the logic unit 110 turns on the select transistor SELTA and the switch SWA in the first half of the refresh cycle (FIG. 22(a)), and turns on the select transistor SELTB and the switch SWB in the second half of the refresh cycle (FIG. 22(b)).

[0099] The logic unit 110 drives the word line WL-A in the first half of the refresh cycle to turn on the transfer transistor TRT (FIG. 22(c)), and drives the word line WL-B in the second half of the refresh cycle to turn on the transfer transistor TRT (FIG. 22(d)). The logic unit 110 also operates the sense amplifier S / A-A in the first half of the refresh cycle (FIG. 22(e)), and operates the sense amplifier S / A-B in the second half of the refresh cycle (FIG. 22(f)).

[0100] As a result, in the first half of the refresh cycle, data read from memory cells MC in group A to global bit lines GBL by driving word lines WL-A is amplified by the operation of sense amplifiers S / A-A and written back to memory cells MC (FIG. 22(g)). In the second half of the refresh cycle, data read from memory cells MC in group B to global bit lines GBL by driving word lines WL-B is amplified by the operation of sense amplifiers S / A-B and written back to memory cells MC (FIG. 22(h)).

[0101] In contrast, in a 2D-DRAM, the word line WL is driven once during one refresh cycle, and data read from the memory cell MC is amplified by the sense amplifier S / A and written back to the memory cell MC. For example, multiple memory cells MC connected to the sense amplifier S / A are connected to a common bit line. Therefore, in a 2D-DRAM, the load on the bit line connected to the sense amplifier S / A is greater than in the circuit configuration of FIG. 21, and the waveform of the bit line BL becomes slower.

[0102] In this embodiment, when a memory cell MC is accessed, only one local bit line LBL is connected to a global bit line GBL via a select transistor SELT, so that the load on the bit line from which data is read when the memory cell MC is accessed can be made smaller than that of a 2D-DRAM.

[0103] Therefore, data amplification by the sense amplifiers S / A can be performed at higher speeds than in 2D-DRAM, and two or more refresh operations can be included in each refresh cycle. For example, by connecting four sense amplifiers S / As to the global bit line GBL and operating them exclusively, four refresh operations can be included in each refresh cycle. Furthermore, since the capacitance of the bit lines (GBL+LBL) connected to the sense amplifiers S / A can be reduced, the power consumption for refreshing each memory cell MC can be reduced.

[0104] As described above, the second embodiment can also achieve the same effects as the first embodiment. Furthermore, in the second embodiment, by utilizing the small bit line capacitance connected to the sense amplifier S / A, it is possible to operate a plurality of sense amplifiers S / A during one refresh cycle to refresh a plurality of memory cells.

[0105] Although the present invention has been described above based on the embodiments, the present invention is not limited to the requirements shown in the above embodiments. These requirements can be changed without departing from the spirit of the present invention, and can be appropriately determined depending on the application form.

[0106] This application claims priority based on Japanese Patent Application No. 2024-009036 filed with the Japan Patent Office on January 24, 2024, and incorporates by reference all of the contents of said application.

[0107] 100 semiconductor device 110 logic section 111 configuration register 112 operation control circuit 113 command decoder 114 address decoder 115 data input / output circuit 120 memory section 121 memory core AD address terminal ADHL adhesive layer BK0-BKn bank BLCNT bit line contact BLSEL bit line selection signal line CCAP cell capacitor CH channel CK clock terminal CMD command terminal CNTL control circuit DQ data terminal DQS data strobe terminal GBL global bit line LBL local bit line LGCW logic wafer MC memory cell MEMW memory wafer ML memory layer MPLG metal plug MTL1, MTL2, MTL3 wiring PAD1, PAD2 pad S / A, S / A-A, S / A-B sense amplifier SELGT Select gate SELT, SELTA, SELTA / B, SELTB Select transistor SUB1, SUB2 Semiconductor substrate TR-SW Transistor switch section TRT Transfer transistor WL, WL-A, WL-B Word line VIA Via

Claims

1. A semiconductor device comprising: a stacked plurality of memory circuits each including a plurality of memory cells; a stacked memory including a plurality of first data lines formed through the plurality of memory circuits; an interface circuit formed on the stacked memory, including a second data line commonly provided to the plurality of first data lines, a plurality of switch circuits each connecting one of the plurality of first data lines to the second data line, and a data terminal connected to the second data line; and a logic circuit disposed on the interface circuit, including a via connected to the data terminal and a control circuit connected to the via and controlling operations of the plurality of memory circuits.

2. The semiconductor device according to claim 1, wherein the control circuit has a sense amplifier, turns on any one of the plurality of switch circuits when accessing the memory circuit, and amplifies data read from the memory cell to the second data line via the first data line connected to the turned-on switch circuit with the sense amplifier.

3. The semiconductor device according to claim 2, wherein the plurality of memory cells are dynamic memory cells that need to be refreshed periodically.

4. The semiconductor device according to claim 1, wherein the plurality of memory cells are dynamic memory cells that need to be refreshed periodically, the control circuit has a plurality of sense amplifiers connected to the second data line, and in each refresh cycle, sequentially reads data from the plurality of memory cells, amplifies the data with the plurality of sense amplifiers respectively, and writes the amplified data back to the memory cells from which the data was read.

5. The semiconductor device according to any one of claims 1 to 4, wherein the first data line is connected to a pair of the memory cells located on both sides of the first data line in a plan view in each of the plurality of memory circuits, and each of the plurality of memory cells has a data storage node and a first transistor selectively connecting the storage node to the first data line.

6. The semiconductor device according to any one of claims 1 to 4, wherein each of the plurality of switch circuits has a pair of second transistors disposed on both sides of the first data line in a plan view.

7. The semiconductor device according to claim 6, wherein the pair of second transistors are thin film transistors.

8. The semiconductor device according to any one of claims 1 to 4, wherein a layout pitch of each of the data terminal and the via is larger than a layout pitch of the first data line.

9. The semiconductor device according to any one of claims 1 to 4, wherein the interface circuit is formed as a monolithic integrated circuit on the stacked memory, and the logic circuit is disposed on the interface circuit.

10. A first wafer having a plurality of stacked memories arranged side by side in a plan view and a plurality of interface circuits respectively formed as monolithic integrated circuits on the plurality of stacked memories, and a second wafer disposed on the plurality of interface circuits, each of the plurality of stacked memories including a plurality of stacked memory circuits each including a plurality of memory cells and a plurality of first data lines formed through the plurality of memory circuits, each of the plurality of interface circuits including a second data line commonly provided to the plurality of first data lines of the opposing stacked memories, a plurality of switch circuits respectively connecting the plurality of first data lines and the second data line, and a data terminal connected to the second data line, the second wafer including a plurality of logic circuits including a via connected to the data terminal and a control circuit connected to the via and controlling operations of the plurality of memory circuits.

11. The semiconductor device according to claim 10, wherein the via of the second wafer is formed from a surface of the second wafer after the second wafer is disposed on the plurality of interface circuits and is connected to a wiring disposed on the via after formation of the via.

12. The semiconductor device according to claim 10, wherein the via is formed on a formation surface of a transistor included in the second wafer, and the second wafer is disposed on the plurality of interface circuits with the formation surface of the transistor facing the plurality of interface circuits.

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