Distributed voltage sampling for measurements

Abstract

Methods, systems, and apparatus, for measuring an electrical characteristic of a computer device die. In one aspect, the system and method include voltage probes at a variety of locations across a computer device die including on a power rail connected to a power supply for the computer device die. The system is calibrated during a calibration step that sets scaling factors to scale the measured voltages, referenced to the power rail voltage, to a current for that location. During operation, the system can monitor an electrical characteristic, e.g., power consumption, based on the voltages at the various locations on the computer device die.

Description

Distributed Voltage Sampling For MeasurementsBACKGROUND

[0001] To measure power consumed in a processing device, some systems utilize an explicit or dedicated sense resistor placed in series with the load (e.g., the processing device) to obtain an accurate estimate of the power consumption. Such resistors, however, are lossy, dissipate power, and generate heat, leading to a trade-off between large signal swing and power dissipation.

[0002] Additionally, traditional current sensing front-ends employ large anti-alias filters for band limiting and noise-conditioning. These filters require large area or power, or both, and are traditionally used in low-noise current sensing systems.SUMMARY

[0003] In general, one innovative aspect of the subject matter described in this specification can be embodied in an apparatus comprising: a package component, wherein the package component includes a power distribution network, the package component defines a first side to which a computing device die is mounted, wherein the computing device die is configured to receive power from the power distribution network; a package probe connected to the power distribution network; one or more die probes connected to the computing device die at a first set of locations; and a monitoring circuit configured to measure, for each of the one or more die probes, a difference between a voltage of the die probe and a voltage of the package probe and determines, based on the differences, an electrical characteristic of the computing device die. Other embodiments of this aspect include corresponding systems, methods and computer programs, configured to perform the actions of the methods, encoded on computer storage devices.

[0004] These and other embodiments can each optionally include one or more of the following features. In an aspect, the first set of locations comprises a plurality of locations.

[0005] In another aspect, a distribution of the first set of locations on the computing device die is based on an estimated distribution of powder consumption across the computing device die.

[0006] In another aspect, the monitoring circuit is further configured to convert each of the one or more voltage differences to one or more currents and estimates an overall die power consumption based on a total of the one or more currents. The monitoring circuit may be further configured to convert each of the one or more voltage differences to a respective one or more currents.

[0007] In another aspect, the monitoring circuit, when converting each of the one or more voltage differences to one or more currents, is configured to scale each voltage difference by one or more scaling factors.

[0008] In another aspect, the one or more scaling factors are determined in a calibration step.

[0009] In another aspect, the scaling factors are learned to generate currents that are used to estimate power consumption.

[0010] Another innovative aspect of the subject matter described in this specification can be embodied in methods that include the actions of: measuring, by a monitoring circuit, for each of one or more die probes at a first set of locations and a package probe, a difference between the voltage of the die probe and the voltage of a package probe, wherein the package probe is connected to a power distribution network within a package component, and each die probe is connected to a computing device die that is mounted to a first side of the package component and that receives power from the power distribution network; and detemiining, by the monitoring circuit, based on the one or more differences in voltage, an electrical characteristic of the computing device die.

[0011] In another aspect, the method further includes the actions of converting, by the monitoring circuit, each of the one or more voltage differences to one or more currents; and estimating, by the monitoring circuit, an overall die power consumption based on a total of the one or more currents.

[0012] In another aspect, converting further comprises scaling, by the monitoring circuit, each of the one or more voltage differences by one or more scaling factors.

[0013] In another aspect, the method detennines the one or more scaling factors by a calibration step.

[0014] In another aspect, the method further comprises learning the scaling factors to estimate the power consumption from the one or more currents.

[0015] Another innovative aspect of the subject matter described in this specification can be embodied in an apparatus, comprising: a plurality of converters, wherein eachconverter is configured to: receive a voltage from a package probe connected to a power distribution network in a package component, receive a voltage from a die probe of a computer die mounted to the package component, wherein the voltage from the die probe is unique to that converter, and generate, based on a difference between the voltage from the package probe and the voltage from the die probe, an output current; a first filtering stage that is configured to: receive an input current that is a sum of the plurality of output currents, and perform an anti-aliasing filtering operation on the input current to generate a first output signal; and an analog-to-digital converter (ADC) that is configured to sample the first output signal and convert the first output signal to a measurement signal. Other embodiments of this aspect include corresponding systems, methods and computer programs, configured to perform the actions of the methods, encoded on computer storage devices.

[0016] These and other embodiments can each optionally include one or more of the following features. In an aspect, each of the plurality of converters is configured to scale the difference between the voltage from the package probe and the voltage from the die probe by a scaling factor to generate the output current. A respective scaling factor may be provided for each of the plurality of converters.

[0017] In another aspect, the first filtering stage comprises: an integrator connected to the outputs of each of the plurality of converters and connected to the ADC; and a reset switch configured to reset the integrator when the reset switch is in a first state and to enable the integrator when the reset switch is in a second state.

[0018] In another aspect, the apparatus further comprises control circuitry configured to generate a sample signal and a reset signal, wherein: the reset signal has a first state that resets the integrator, and a second state that enables the integrator; the sample signal causes the ADC to sample the first output signal when the sample signal changes from a first state to a second state and when the reset signal is in the second state; and the reset signal and the sample signal are of respective periods and duty7cycles such that the sample signal changes from the first state to the second state when the reset signal is in the second state for each respective period.

[0019] In another aspect, the apparatus further comprises comprising a second filtering stage configured to: receive the input current that is the sum of the plurality of output currents; and perform an anti-aliasing filtering operation on the input current to generate a second output signal: wherein: the first filtering stage is configured to periodicallygenerate the first output signal during a first integration time; the second filtering stage is configured to periodically generate the second output signal during a second integration time that is different from first integration time; and the ADC is configured to sample the second output signal and convert the second output signal to a measurement signal. The ADC may be configured to sample the second output signal at a different time from the first output signal.

[0020] In another aspect, a power consumption for the computer device die is estimated from the measurement signal.

[0021] Another innovative aspect of the subject matter described in this specification can be embodied in methods that include the actions of receiving, at each of a plurality of converters: a voltage from a package probe connected to a power distribution network in a package component, a voltage from a die probe connected to a computer die that is connected to the package component, wherein the voltage from the die probe is unique to that converter; generating, by each of the plurality of converters, an output current, based on a difference between the package probe voltage and the die probe voltage; receiving, by a first filtering stage, an input current that is a sum of the plurality of output currents; performing, by the first filtering stage, an anti-aliasing filtering operation on the input current to generate an output signal; and converting, by an analog-to-digital converter (ADC), the output signal to a measurement signal. Other embodiments of this aspect include corresponding systems, apparatus, and computer programs, configured to perform the actions of the methods, encoded on computer storage devices.

[0022] These and other embodiments can each optionally include one or more of the following features. In an aspect, the method further comprises scaling, for each of the plurality of converters, the difference between the package probe voltage and the die probe voltage by a scaling factor to generate the output current.

[0023] In an aspect, the first filtering stage periodically samples the output signal after a first integration time and a second filtering stage periodically samples the output signal after a second integration time that is different from the first integration time.

[0024] In an aspect, the method includes a power consumption for the computer device die from the measurement signal.

[0025] Aspects described herein may be combined. For example, the apparatus (and associated method) comprising the plurality of converters described above, and optional features thereof, may be combined with the apparatus (and associated method)comprising the package component, the package probe, one or more die probes, and the monitoring circuit, and optional features thereof.

[0026] Particular embodiments of the subject matter described in this specification can be implemented so as to realize one or more of the following advantages. Applying the methods and apparatuses will enable systems-on-a-chip (SoCs) to operate efficiently without unwanted power loss and also to prevent damage or miscalculations due to locally overheating certain portions of the SoC. Conversion scaling values may be learned, which enables the systems and methods to utilize the same components for a variety of SoCs, thereby reducing the need for specially designed hardware for each particular SoC type. Overall silicon real estate is reduced by eliminating the need for a series resistor and / or a large anti-aliasing filter. Yet another advantage is that all of the signals of interest are available in the SoC, and thus the connections can be contained inside the SoC without requiring additional package pins that connect to elements on the printed circuit board; this is in contrast to a sensor that uses an impedance or device outside the package, for instance, for measuring the cunent. Additionally, the systems and methods described herein enable the ability to log and manipulate power across the SoC smartly and at a higher rate than would be available by sending signals off chip.

[0027] The details of one or more embodiments of the subject matter described in this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, the drawings, and the claims.BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figs. 1 A and IB are illustrations of a package with a distributed voltage sampling and measurement circuit for a computing device die powered by a power distribution network.

[0029] Fig. 2 is a flow7diagram of an example process for measuring the voltages and estimating an electrical characteristic based on the voltage measurements.

[0030] Fig. 3 is an illustration of a particular measuring circuit with an anti-aliasing filter used in combination with the distributed voltage sampling circuit.

[0031] Fig. 4 is a flow diagram of an example process for converting the voltages to an estimate of an electrical characteristic.

[0032] Fig. 5 is an illustration of another implementation that includes a multi-switch anti-aliasing filter.

[0033] Like reference numbers and designations in the various drawings indicate like elements.DETAILED DESCRIPTION

[0034] This disclosure describes measuring the voltage drop across the implicit or intrinsic shunt impedance that is created by a power-distribution network (PDN) supplying power to a processing device. This voltage drop is measured in a distributed fashion and used to estimate one or more electrical performance characteristics, e.g., power consumption, of the processing device.

[0035] By way of example, power consumption will be described as the measured electrical characteristic. However, other electrical characteristics, such as current, etc., can also be measured.

[0036] In an example implementation, the power consumption is measured for a computing device mounted in a package component. The package component includes a power distribution network, and has a first side to which a computing device die is mounted. The computing device die receives power from the power distribution network.

[0037] To measure the voltage drop in a distributed manner, a package probe is connected to the power distribution network. Additionally, one or more die probes are connected to the computing device die at a first set of locations. While one die probe could be used, typically multiple die probes are used, as will be explained in more detail below.

[0038] A monitoring circuit measures, for each of the one or more die probes, a difference between a voltage of the die probe and a voltage of the package probe. Based on these voltage differences, the monitoring circuit determines an overall power consumption of the computing device die.

[0039] To reduce error, multiple die probes are used. Additionally, the die probes are distributed at locations on the computing device die based on an estimated distribution of power consumption across the computing device die. For example, the die probes can be located near circuitry that performs the most processing-intense operations relative to other circuity on the die. Likewise, a consolidated heat map of the computing device die under various operations can be determined, and the die probes can be placed at thelocations of the power rail nearest the highest heat readings, or regions with large uncorrelated power consumption.

[0040] In some implementations, the monitoring circuit converts each of the one or more voltage differences to one or more currents and estimates an overall computing device die power consumption based on a total of the one or more currents. The voltage differences may be scaled by learned scaling components that are learned during a calibration process.

[0041] This disclosure also describes a design of a distributed integration-sampler based front-end. This front-end can be used with other systems, such as the system described above, to perform filtering, amplification and signal conditioning. The voltage drop is measured in a distributed fashion and is used to estimate the power consumption of the processing device.

[0042] The monitoring circuit is a front-end that includes a plurality of converters. Each converter receives a voltage from a package probe connected to a pow er distribution network in the package component, and receives a voltage from a die probe of a computer die mounted to the package component. The voltage from the die probe is unique to that converter, i.e., each converter receives a voltage from a different die probe. On the other hand, the voltage from the package probe connected to a power distribution network in the package component may be received by several, or even all, of the converters.

[0043] The monitoring circuit generates, based on a difference between the voltage from the package probe and the voltage from the die probe, an output current. The output current is provided to a filtering stage that receives an input current that is a sum of the plurality of output currents. The filtering stage performs an anti-aliasing filtering operation on the input current to generate an output signal. This output signal is provided to an analog-to-digital converter (ADC) that samples the output signal and converts the output signal to a measurement signal (e.g., a power consumption signal).

[0044] In some implementations, each of the plurality of converters scales the difference betw een the voltage from the package probe and the voltage from the die probe by a scaling factor to generate the output current. The scaling factor for each converter may be learned during a calibration process, and may be unique to that particular converter.

[0045] In some implementations, the filtering stage comprises an integrator. An example integrator may include a capacitor with a first node connected to the outputs ofeach of the plurality of converters and with a second node connected to ground. A reset switch isolates the first node of the capacitor connected an ADC input from ground when the reset switch is in an open state, and that connects the first node of the capacitor to ground when the reset switch is in a closed state. More complex integrators may also be used.

[0046] For sampling, control circuitry generates a sample signal and a reset signal.The reset signal has a first state that places the reset switch in the open state, and a second state that places the reset switch in the closed state. The sample signal causes the ADC to sample the first output signal when the sample signal changes from a first state to a second state. The reset signal and the sample signal are of respective periods and duty cycles such that the sample signal changes from the first state to the second state when the reset signal is in the first state for each respective period.

[0047] In some implementations, the system can include a second filtering stage identical to the filtering stage described above, and that samples and integrates at different times from the first filtering stage.

[0048] These features and additional features are described in more detail below.

[0049] Figs. 1A and IB are illustrations of a package 100 with a distributed voltage sampling and measurement circuit 200 for a computing device die powered by a power distribution network. In some implementations, the distributed voltage sampling and measurement circuit 200 is part of a larger monitoring circuit 150 that determines an electrical characteristic based on monitored voltages, as will be described in more detail below.

[0050] The package 100 includes a package component 102, to which is mounted a computer device die 106. An example packing component may be an interposer. The computer device die 106 may be part of a system on system on a chip (SoC) and may have one or more compute cores 108.

[0051] The package 100 is pow ered by a power source 104. The pow er source 104 provides power to a power distribution network 110, e.g., a pow er rail with multiple connection points, which, in turn, distribute power to the various components of the package 100. In the example shown in Fig. 1, N compute cores (108-1, 108-2, ... 108-N) are depicted, but the computing device die 106 may include only one core 108.

[0052] As shown in Fig. IB, the package component 102 defines a first side 104 to which the computing device die 106 is mounted, and the computing device die 106 isconnected to the power distribution netw ork 110. The computing device die 106 includes a die power grid 112 for distribution of power within the computer device die 106.

[0053] A package probe 120-0 is connected to the power distribution network, and one or more die probes 120-1 . .. 120-N are connected to the computing device die at a first set of locations, e.g., at locations on in the die power grid 112. The locations may be spaced evenly across the grid 112. or, alternatively, may be spaced such that they are located in areas where the power consumption is the highest, e g., dispersed directly below the cores 108, for example. In yet another implementation, the locations may be dispersed according to a die 106 heat map, where the probes are at locations where the highest temperatures occur. Other locations may be selected as appropriate. More generally, the distribution of the first set of locations on the computing device die may be based on an estimated distribution of power consumption across the computing device die.

[0054] As will be explained in more detail below, by measuring the voltages at these probes, the distributed voltage sampling and measurement circuit 200 can measure the voltage drop across the PDN 1 10. These measurements can be used to generate an input to the measuring circuit 400 to determine an electrical characteristic, e.g., power consumption, of the SoC without requiring extra sense resistors, thus saving power and form-factor.

[0055] To determine an electrical characteristic of the SOC, e.g., an estimation of power consumption of the computer device die 106, the distributed voltage sampling and measurement circuit 200 measures a voltage Vo at a package probe 120-0 in the power distribution network 110. Additionally, the circuit 200 measures one or more additional voltages Vi, V2, ... VN, which correspond to the voltages at die probes 120-1, 120-2, ... 120-N at the probe locations on the computer device die 106.

[0056] These measured voltages are provided to a set converters 202-1 .. . 202 -N, which convert each of the measured voltage differences (Vi - Vo, V2 - Vo, ... VN - Vo) into a current. The conversion for each particular converter 202 may be based on a scaling component G of the converter. The determination of each scaling component for each converter is done during a calibration process, described in more detail below;

[0057] The currents output by each converter 202 are then summed by a summer 204 to produce a sum of the output currents, IE. The current IE is then provided to a measuring circuit 400 to generate the estimated electrical characteristic.

[0058] During a calibration process, the current drawn (Ii, I2, ... IN) for each of the probed locations on the computer device die 106 is measured and compared with the measured voltage at that location. The cores 108 of the computer device die 106 may be operated at various loads to measure the voltages and currents under various loads, e.g., when all cores 1 8 are fully utilized, and when some cares are only partially utilized or idle, etc. The actual electrical characteristic to be monitored (e.g., consumed power) may also be recorded for each load condition. Based on these measurements, the calibration process determines appropriate scaling factors G1 . . . GN. In an example, a lookup table may be created for determining a current associated w ith a measured voltage for each location of a probe on the computer device die. In another example, a machine learning model for the currents may be created and trained based on the currents and voltages measured during the calibration process. Other appropriate methods for learning or determining the scaling factors can also be used.

[0059] The scaling factors G1 .. . GN may be static, meaning each converter 202 has a value G that does not change over a voltage difference range. In another implementation, the scaling factors G1 . . . GN may be dynamic, meaning, the scaling factor G for a particular converter may adjust depending on the voltage difference, and. in some implementations, on the voltage differences observed at other converters 202.

[0060] Fig. 2 is a flow diagram of an example process 300 for measuring the voltages and estimating an electrical characteristic based on the voltage measurements. The process 300 may be implemented in the monitoring circuit 150 shown in Figs. 1A and IB.

[0061] The process 300 obtains a package probe voltage (302). For example, the voltage Vo of Fig. 1A may be determined from the package probe 120-0.

[0062] The process 300 obtains die probe voltages (304). For example, the voltages Vi- VN may be obtained from the die probes 120-1... 120-N.

[0063] The process 300 measures the voltage differences between the die probe and the package probes (306). For example, the voltages Vo -VN are provided to the converters 200 as show n in Fig. 1A, each of which determines a difference between the voltage from the package probe and the voltage from a respective die probe, e.g., Vi - Vo, V2 - V0, ... VN - VO.

[0064] The process 300 determines an electrical characteristic based on the voltage differences (308). For example, each of the converters 200 determines and estimated current component based on the voltage difference and the scaling factor G. The estimated currents are then summed and provided to the measuring circuit 400 as input. An electrical characteristic is then determined, based on the particular measuring circuit 400 used.

[0065] Fig. 3 is an illustration of a particular measuring circuit 400 with an antialiasing fdter 402 used in combination with the distributed voltage sampling circuit 200. Together these circuits realize an example monitoring circuit 150.

[0066] As shown in Fig. 3, the converters 202 each receive the voltage Vo at a package probe 120-0 in the power distribution network 110. Additionally, each converter 202 -X receives a respective voltage Vx from a respective die probe 202-X, resulting in respective voltage difference betw een the voltages of the die probes and a voltage of the package probe, denoted as Ai, A2, ... AN. Each converter then generates, based on a difference between the voltage from the package probe and the voltage from the die probe, an output current. The output current of each converter 202 may be based on the adjustable scaling value G determined during the calibration process. In some implementations, the scaling factor G of each converter 202 may not be a scalar value, but may instead adjust based on the voltage difference measured at the input of the converter 202.

[0067] An anti-aliasing filtering stage 402 receives an input current that is a sum of the plurality of output currents, i.e., the input current is represented by the sum S{ Ai}*Gi, and performs an anti-aliasing filtering operation on the input current to generate a first output signal. As shown in Fig. 4, the filter 402 is an integrator with a capacitor CINT and a switch driven by an RST signal input. Other anti-aliasing filter circuits can also be used. Other such examples include operational transconductance amplifying circuits or an operational amplifier w ith a capacitor in feedback.

[0068] The anti-aliasing filtering stage 402 generates an output signal, e.g., VINT = (2{Ai}*Gi) / CiNi * TINT, where TINT is an integration time period for the integrator of Fig. 3. This signal is provided to an analog to digital converter (ADC) 404 as input, which at an appropriate sample time (as indicated by the Sample input signal to the ADC 404) generates a digital measurement value of the electrical characteristic. For example, if the measured electrical characteristic is power, the output of the ADC 404 is a digitalrepresentation of a power consumption value in Watts. It will be appreciated that some further scaling may be required to convert the output of the ADC 404 to a value in Watts. It will also be appreciated that it is not necessary for such scaling to be performed, and that the output value being indicative of the power consumption in Watts may be useful.

[0069] The reset switch signal RST and the sample signal Sample are periodic, but may have a phase delay between the two signals, and / or may have a different duty cycle, as shown in timing diagram 420. For example, the sample signal Sample may be offset by half a period from the reset signal RST, or may be only offset by 10% of a period, etc. The ADC 402 generates the output signal on the rising edge of the sample signal Sample. Each of the sample signal Sample and the reset signal RST may have a first state (e.g. logic low or logic high) and a second state (e.g. logic low or logic high). When the reset switch is in the first state, the capacitor CINT may be connected to ground. When the reset switch is in the second state, the capacitor CINT may be configured to integrate the input current. In the example shown, the reset signal RST may be active high, such that a logic high value corresponds to a reset event. The sample signal Sample may also be active high, such that a transition to the high value causes the ADC to sample the output signal.

[0070] Fig. 4 is a flow diagram of an example process 500 for converting the voltages to an estimate of an electrical characteristic. The process can be used in the monitoring circuit 150 of Fig. 4.

[0071] The process 500, for each converter of a plurality of converters, receives a package probe voltage (502). For example, each converter 202 receives the die probe voltage Vo.

[0072] The process 500, for each converter of the plurality of converters, receives a die probe voltage (504). For example, each converter 202 -X receives a respective voltage Vx from a respective die probe 202 -X.

[0073] The process 500 generates, based on a difference between the package probe voltage and the die probe voltages, an input current to the measuring circuit (506). For example, each converter generates an estimated current based on the voltage difference of the scaling value G, and the currents are summed to generate the input current.

[0074] The process 500 filters the input current to generate an output signal (508). For example, the anti-aliasing filter is used to filter the input current to generate the voltage VINT.

[0075] The process 500 converts, by an ADC, the filtered input current to generate a signal indicative of an electrical characteristic ( 10). For example, the ADC 404 receives the samples the output signal VINT according to the Sample signal and generates the signal indicative of an electrical characteristic.

[0076] Fig. 5 is an illustration of another implementation that includes a multi-switch anti-aliasing filter. In this implementation, the voltage-to-current converter 200 outputs an overall current for the computer device die as described above. A multi-switch antialiasing filter includes a first filter 402-A and a second filter 402-B. The anti-aliasing filters 402-A and 402-B sample over first and second separate, non-overlapping time periods. The first and second filtering stages may be identical to one another, but operated such that the second filtering stage samples and integrates at different times from the first filtering stage. The end of the integration time for one of the filtering stages may correspond to the start of the integration time for the other filtering stage, and vice versa.

[0077] In the previous example, there is a time period when the reset switch is resetting the integrator (e.g., draining the charge on the capacitor to zero). During this resetting, current is still flowing as the output current from the voltage-to-current converter. This information is lost if there is a single reset switch. By adding a second set of accumulators (or integrators) and reset switches, the time period when the first example’s reset switch is used can be used to accumulate charge to a second capacitor. Switches SAI and SA2 are operatively associated so that when switch SAI is in the closed position, then switch SA2 is in the open position. Likewise, switches SB1 and SB2 are also operatively associated (with each other, and with switches SAI, and SA2) so that when switch SAI is closed, then switches SB1 and SA2 are open and SB2 is closed. The two reset switches SI and S2 are also closed at different times. This enables sampling of the first output signal at a faster rate and with less loss of information than in the implementation of Fig. 3.

[0078] The calibration step performed prior to normal operation of the SoC may involve the step of operating individual sections of the computer device die at different power consumption levels while measuring both the current and the voltage drop across each individual probe. By measuring current consumption under a variety’ of conditions, the measured voltage drop for each probe can be correlated with a particular current. Thus, by knowing the voltage and other aspects of the state of the SoC, it will be possibleto predict the power being consumed and the current flowing through each portion of the SoC.

[0079] The calibration may also take into account the heating at each location as measured by an infra-red (“thermal”) camera. While the thermal camera gives an accurate reading of the temperature across the chip, it does not react quickly enough to stop local heating since the response time is several milliseconds. By using the method and system of this disclosure, response times on the order of a few microseconds are achievable. If, for instance, the computer device is in danger of overheating locally, based on the measured voltages and the estimated local power consumption, an instruction could be sent back to the central processor to reduce current to that location or to reduce the clock frequency or take some other action (e.g., re-allocate some calculations to another core or to multiple other cores, in the event that a parallelizable process is ongoing and overheating one core).

[0080] Embodiments of the subject matter and the operations described in this specification can be implemented in digital electronic circuitry, or in computer software, firmware, or hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. Embodiments of the subject matter described in this specification can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions, encoded on computer storage medium for execution by, or to control the operation of, data processing apparatus.

[0081] A computer storage medium can be, or be included in, a computer-readable storage device, a computer-readable storage substrate, a random or serial access memory array or device, or a combination of one or more of them. Moreover, while a computer storage medium is not a propagated signal, a computer storage medium can be a source or destination of computer program instructions encoded in an artificially -generated propagated signal. The computer storage medium can also be, or be included in, one or more separate physical components or media (e.g., multiple CDs, disks, or other storage devices).

[0082] The operations described in this specification can be implemented as operations performed by a data processing apparatus on data stored on one or more computer-readable storage devices or received from other sources.

[0083] The term “data processing apparatus'’ encompasses all kinds of apparatus, devices, and machines for processing data, including by way of example a programmable processor, a computer, a system on a chip, or multiple ones, or combinations, of the foregoing. The apparatus can include special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit). The apparatus can also include, in addition to hardware, code that creates an execution environment for the computer program in question, e.g.. code that constitutes processor firmware, a protocol stack, a database management system, an operating system, a crossplatform runtime environment, a virtual machine, or a combination of one or more of them. The apparatus and execution environment can realize various different computing model infrastructures, such as web services, distributed computing and grid computing infrastructures.

[0084] A computer program (also know n as a program, softw are, software application, script, or code) can be w ritten in any form of programming language, including compiled or interpreted languages, declarative or procedural languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, object, or other unit suitable for use in a computing environment. A computer program may, but need not, correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store one or more modules, sub-programs, or portions of code). A computer program can be deployed to be executed on one computer or on multiple computers that are located at one site or distributed across multiple sites and interconnected by a communication network.

[0085] The processes and logic flows described in this specification can be performed by one or more programmable processors executing one or more computer programs to perform actions by operating on input data and generating output. The processes and logic flows can also be performed by, and apparatus can also be implemented as, special purpose logic circuitry, e.g., a FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit).

[0086] While this specification contains many specific implementation details, these should not be construed as limitations on the scope of any features or of what may be claimed, but rather as descriptions of features specific to particular embodiments. Certainfeatures that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

[0087] Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0088] Thus, particular embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In certain implementations, multitasking and parallel processing may be advantageous.

Claims

CLAIMSWhat is claimed is:

1. An apparatus, comprising: a package component, wherein: the package component includes a power distribution network; and the package component defines a first side to which a computing device die is mounted, wherein the computing device die is configured to receive power from the power distribution network; a package probe connected to the power distribution network; one or more die probes connected to the computing device die at a first set of locations; and a monitoring circuit configured to measure, for each of the one or more die probes, a difference between a voltage of the die probe and a voltage of the package probe and determines, based on the differences, an electrical characteristic of the computing device die.

2. The apparatus of claim 1, wherein the first set of locations comprises a plurality of locations.

3. The apparatus of claim 2, wherein a distribution of the first set of locations on the computing device die is based on an estimated distribution of power consumption across the computing device die.

4. The apparatus of any preceding claim, wherein the monitoring circuit is further configured to convert each of the one or more voltage differences to one or more currents, and to estimate an overall die power consumption based on a total of the one or more currents.

5. The apparatus of claim 4, wherein the monitoring circuit, when converting each of the one or more voltage differences to one or more currents, is configured to scale each voltage difference by one or more scaling factors.

6. The apparatus of claim 5, wherein the one or more scaling factors are determined in a calibration step.

7. The apparatus of claim 5 or 6, wherein the scaling factors are learned to generate currents that are used to estimate power consumption.

8. A computer-implemented method comprising: measuring, by a monitoring circuit, for each of one or more die probes at a first set of locations, a difference between a voltage of the die probe and a voltage of a package probe, wherein the package probe is connected to a power distribution network within a package component, and each die probe is connected to a computing device die that is mounted to a first side of the package component and that receives power from the power distribution network; and determining, by the monitoring circuit, based on the one or more differences in voltage, an electrical characteristic of the computing device die.

9. The method of claim 8, wherein the first set of locations comprises a plurality of locations.

10. The method of claim 9. wherein a distribution of the first set of locations on the computing device die is based on an estimated distribution of power consumption across the computing device die.

11. The method of any one of claims 8 to 10, further comprising: converting, by the monitoring circuit, each of the one or more voltage differences to one or more currents; and estimating, by the monitoring circuit, an overall die power consumption based on a total of the one or more currents.

12. The method of claim 11, wherein the converting step further comprises scaling, by the monitoring circuit, each of the one or more voltage differences by one or more scaling factors.

13. The method of claim 12, further comprising determining the one or more scaling factors by a calibration step.

14. The method of claim 12 or 13, further comprising learning the scaling factors to estimate the power consumption from the one or more currents.

Images