Stack-based memory renaming avoiding register multi-sharing

Abstract

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for performing a stack-based memory renaming process. In one aspect, a processor is configured to perform operations including receiving a stack-based store instruction specifying a logical register name and an address, performing a stack-based memory renaming process that maps a stack register pointer to a temporary physical register and moves data from a source physical register indicated by the logical register name to the temporary physical register, receiving a stack-based load instruction, identifying the temporary physical register based on the stack register pointer, retrieving data for the load instruction from the temporary physical register indicated by the stack register pointer, and storing the data for the load instruction in a destination physical register.

Description

[0001] STACK-BASED MEMORY RENAMING AVOIDING REGISTER MULTI-SHARING

[0002] BACKGROUND

[0003] This specification relates to processor design and memory renaming.

[0004] Loading from memory7and storing to memory are performance critical memory operations for processors when running a program.

[0005] Memory renaming is a micro-architectural technique for a processor that predicts address dependencies between store instructions and load instructions to avoid the latency of accessing the memory7. In particular, memory7renaming involves predicting a mapping of logical registers (e.g., architectural registers used by the processor during run-time) to physical registers (e.g., micro-architectural registers ) based on identifying one or more dependencies between the logical registers and the physical registers used by store instructions and the load instructions. For example, memory renaming involves mapping an architectural destination logical register of a load instruction to a source phy sical register of a store instruction, where the load instruction loads a value from the same address as the address that the store instruction stored a value.

[0006] Consider the following example assembly code shown in Table 1 having multiple instructions, including an addition instruction and a store instruction followed by a load instruction and a subtraction instruction.

[0007] TAB E 1

[0008] The addition instruction on line 1 adds a numeric value of 16 to the value stored in register XI and places the result of the addition in a logical register XL The store instruction on line 2 stores the value in register XI to an address stored by logical register X8 plus an offset of 8. Several lines later, the load instruction on line 10 loads into logical register X2 a value at an address in logical register X2 plus an offset of 8. The subtraction instruction on line 11 subtracts a numeric value of 16 from the value stored in logical register X2 and places the result of the subtraction in logical register X3.

[0009] In this case, a processor can perform memory renaming by leveraging shared dependencies between load and store instructions. For example, the processor can identify that the address accessed by the store instruction in line 2 (e.g., X8 + 8) is the same as the address accessed by the load instruction in line 10. Thus, the processor identifies that the data stored in the logical register XI by the store instruction is the same data that is loaded in logical register X2 by the load instruction. Accordingly, the subtraction instruction is dependent on logical register XI, as the data of X2 minus 16 is being stored in logical register X3. As such, the processor can cause the subtraction instruction to directly consume (e.g., access) the result of the addition instruction by making the subtraction instruction dependent on the addition instruction, rather than having to perform the store and the load, bypassing the memory operations completely.

[0010] In some cases, the processor can perform memory renaming by assigning a respective physical register to each logical register (e.g., physical register Pl to logical register XI and physical register P2 to logical register X2).

[0011] However, doing so can create some unwanted complexity. For example, the processor might end up assigning the same physical register to multiple logical registers to leverage the shared dependency between the load and store instructions. This phenomenon is known as physical register multi-sharing, which greatly complicates the logic for physical register reclaiming. This in turn requires more silicon area and increases the latency of these processes. In the example above, in order to make the subtraction instruction dependent on the addition instruction, the processor can assign a same physical register (e.g., Pl) to both the logical register XI and the logical register X2. since logical register XI and logical register X2 have the same data.

[0012] Another problem with predictive memory renaming is that there is a high cost associated with a misprediction. For example, in some cases, the processor may incorrectly identify a dependency, which can result in false dependencies between instructions and increased latency and overhead in the processor. When this happens, the processor must perform a flush operation and re-initiate execution, which can significantly impact performance. SUMMARY

[0013] The systems and techniques described in this specification allow a processor to reduce physical register multi-sharing and to increase the accuracy of memory renaming predictions by performing a stack-based memory renaming process for particular sets of instructions. The processor can perform the stack-based memory renaming process by leveraging dependencies between stack-based load instructions and store instructions. Stack-based instructions are instructions that indicate addresses of data in reference to a base logical register in a stack of the main memory. The base logical register can be referred to as a stack register pointer. In general, for a stack, a store instruction is referred to as a “push” and a load instruction is referred to as a “pop.”

[0014] During decoding, the processor can determine whether an instruction is a stack-based instruction, and accordingly, the processor can determine whether the instruction is a stack push, a stack pop, or an adjustment to the stack register pointer. Stack-based instructions are generally used in a system when the system identifies that the number of instructions to be executed is greater than the number of reserved registers.

[0015] In the case of receiving a stack-based store instruction with a logical register name and an address, the processor can perform the stack -based memory renaming process by mapping a stack register pointer to a temporary physical register and moving data from a source physical register indicated by the logical register name to the temporary physical register.

[0016] In the case that the processor then receives a stack-based load instruction, the processor can identify the temporary physical register based on the stack register pointer, retrieve data for the load instruction from the temporary' physical register indicated by the stack register pointer, and store the data for the load instruction in a destination phy sical register.

[0017] Particular embodiments of the subject matter described in this specification can be implemented so as to realize one or more of the following advantages. The systems and techniques described in this specification solve multiple problems with inclusive caches.

[0018] In conventional systems, a processor can perform stack-based memory renaming by predicting load and store instruction dependencies. However, identifying dependency predictions for every load instruction and every store instruction can result in increased overhead in the system because the processor requires extensive training to predict the dependencies with high accuracy. In the case that the processor mistakenly identifies load and store dependencies, the system must reset (e g., flush) the assigned logical registers to physical registers because a load instruction can access the wrong data as a result of the mistake. If the prediction accuracy does not satisfy a threshold, the system must also reset the register assignments, which can result in increased latency in the system, reducing the performance gain from memory renaming.

[0019] Additionally, conventional memory renaming techniques can result in increased overhead in the system because the processor must monitor the sharing of the physical registers during run-time. In particular, the processor must track the mapping of the physical registers to logical registers and determine when to release physical registers by re-assigning the mapping, which result in challenges with timing when running a program, memory availability, and power consumption.

[0020] In contrast, the systems described in this specification implement efficient stack-based memory renaming techniques. In particular, the processor of the system can replicate the stack in the main memory by using a register mapping table to extend the logical registers by a certain number and mapping the logical registers to the same data as the stack using stack-based registers (e.g., stack registers). Additionally, the system uses the register mapping table to track the stack registers. By using the register mapping table to replicate the stack, the processor can issue a new physical register for a stack-based instruction without mapping the physical register to multiple logical registers. In particular, the system tracks store instructions and load instructions in pairs, and the system allows only one load instruction coupled to a store instruction to map the logical register to the physical register, which eliminates the latency and increased overhead of physical register multi-sharing while maintaining the benefits of mapping the logical registers to physical registers to leverage dependencies between load instructions and store instructions, such as increasing memory availability and decreasing latency in the system.

[0021] Additionally, unlike typical store instructions which do not include a destination physical register, the system described in this specification allocates a temporary physical register for stack-based store instructions. The processor can populate the temporary physical register with the data from a source physical register indicated by the logical register name of the store instructions using the register mapping table. For a subsequent load instruction, the processor can identify the temporary physical register using the register mapping table, and the processor can retrieve the data for the load instruction from the temporary physical register and store the data in a destination physical register. By assigning the temporary physical register to the stack-based store instruction, the system can leverage the temporary' physical register for a load instruction in order to prevent the latency of having to access the memory and prevent the increased overhead associated with multi-sharing. In particular, the system can implement the described stack-based memory renaming techniques to greatly reduce multi-sharing and the complexity associated with multi-sharing and to increase memory renaming prediction accuracy due to tightly coupling the stack-based instructions.

[0022] The details of one or more embodiments of the subject matter of this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, the drawings, and the claims.

[0023] BRIEF DESCRIPTION OF THE DRAWINGS

[0024] FIG. 1 is a block diagram of an example system.

[0025] FIG. 2 is a block diagram of an example memory renaming unit.

[0026] FIG. 3 is a flow diagram of an example process for performing a stack-based memory renaming process.

[0027] Like reference numbers and designations in the various drawings indicate like elements.

[0028] DETAILED DESCRIPTION

[0029] FIG. 1 illustrates an example system 100. The system 100 is an example of a system in which the systems, components, and techniques described in this specification can be implemented. The system 100 includes a processor 102 coupled to a memory' 110. The processor 102 is an example of a device that can be installed on or integrated into any appropriate computing device.

[0030] The processor 102 includes main execution logic 104, a memory renaming unit 106, and a register mapping table 108.

[0031] The main execution logic 104 executes instructions. In particular, the processor 102 can be configured to perform Out of Order (OOO) execution of the instructions. The processor 102 can process the instructions by fetching the instructions from the main execution log 104, decoding the instructions, executing the instructions, and committing the instructions to the memory7110. The processor 102 performs memory renaming techniques during the decoding stage of processing the instructions.

[0032] In some cases, the instructions are stack-based instructions, and the stack-based instructions can be store instructions 112, load instructions 114, addition instructions, or subtraction instructions included in a stack. The processor 102 can determine that the instructions are stack-based instructions based on the address being a stack address of the stack.

[0033] The memory renaming unit 106 is configured to perform a general predictive memory renaming process for fetched instructions. In some cases, such as for stack-based instructions, the memory' renaming unit 102 can perform a stack-based memory renaming process using the register mapping table 108. The register mapping table 108 includes a mapping of logical registers to physical registers.

[0034] In particular, the processor 102 can fetch the stack-based store instruction 112 from the main execution logic 104. The store instruction 112 includes a logical register name corresponding to a logical register associated with an Instruction Set Architecture (ISA) to store the data and an address of the data. In particular, the ISA is a model of the behavior of a particular family of processors that does not depend on a specific hardware implementation or microarchitectural details of any of the processors in the family. ISAs commonly define the types of instructions that can be executed and provide an abstraction that allows processors having different physical characteristics and capabilities to execute the same software. In this case, the processor 102 can decode the stack-based instruction 112 to determine whether to perform predictive memory renaming (e.g., regular predictive memory renaming), or to perform the particular stack-based memory renaming process based on whether the instructions are stack-based.

[0035] If the processor 102 determines the instruction 112 is stack based and determines to perform the stack-based memory renaming process, the processor 102 uses the memory renaming unit 106 to perform the stack-based memory' renaming process by mapping the stack register pointer 116 to a temporary physical register using the register mapping table 108 to obtain a source physical register name 118. The processor 102 then moves data from a source physical register indicated by the logical register name of the store instruction 1 12 to the temporary' physical register indicated by the register mapping table 108, as described below with reference to FIG. 2.

[0036] The processor 102 then receives a stack-based load instruction 114, and the processor 102 can identity the temporary' physical register based on the stack register pointer 116.

[0037] The processor 102 can then retrieve the data for the load instruction from the temporary physical register, and the processor 102 can store the data for the load instruction 114 in a destination physical register, as described beloyv with reference to FIGs. 2 and 3.

[0038] Thus, performing the stack-based memory renaming process prevents multi-sharing of physical register names for stack-based memory' instructions by ensuring that physical register names are assigned to only one logical register in order to replicate the stack in the main memory, which decreases the latency associated with multi-sharing while maintaining the benefits of mapping the logical registers to physical registers to leverage dependencies between pairs of load instructions and store instructions. FIG. 2 illustrates an example memory renaming unit. For example, a processor, e.g., the processor 102 of FIG. 1 can use the memory renaming unit, e.g., the memory renaming unit 106 of FIG. 1, appropriately configured in accordance with this specification, to perform stackbased memory renaming.

[0039] The processor can use the memory renaming unit 106 to perform the stack-based memory renaming process.

[0040] The memory renaming unit 106 includes a source physical register 202. a temporary physical register 204, and a destination physical register 206.

[0041] The processor 102 receives the stack-based store instruction with the logical register name and address. In some cases, the processor receives a stack-based store instruction 112. The stack-based store instruction can be an STR instruction that instructs the processor to store data in a particular register by reading the data at an address of instructions usingthe registers.

[0042] The processor 102 can assume that the store instructions 112 and the load instructions 114 are happening in pairs (e.g., each store instruction 112 corresponds to a load instruction 114).

[0043] In this case, the processor 102 uses the memory renaming unit 106 to map the stack register pointer 116 to a temporary physical register 204 using the register mapping table 108 to obtain the source physical register name 118.

[0044] The register mapping table 108 includes multiple entries for logical register names and one or more entries for stack register pointers (e.g., SR0 and SRI). Unlike the logical registers, physical registers are not conventionally assigned to the stack register pointers. However, this implementation assigns a physical register (e.g., a temporary7physical register) to each of the stack register pointers for stack-based store instructions in order to replicate the stack.

[0045] In particular, the processor 102 increments a register stack counter that counts how many more store instructions have been received than load instructions to track the assignments of stack registers pointers to temporary physical registers. In this case, the processor 102 performs the stack-based memory renaming process only when the register stack counter is nonzero. The processor 102 can increment the register stack counter when accessing the register mapping table 108 for the stack-based renaming process in the case of future references to the stack register pointers for a subsequent load instruction.

[0046] Additionally, the register mapping table includes an attribute representing whether or not each stack register pointer is valid, and the processor can modify an entry in the register mapping table corresponding to the stack register pointer to indicate that the stack register pointer is valid. The processor 102 then moves data 208 from the source physical register 202 indicated by the logical register name of the store instruction 112 to the temporary physical register 204 indicated by the register mapping table 108.

[0047] Consider the following examples of assembly code shown in the tables below having multiple instructions. In these examples, the assembly code uses four logical registers (X0, XI, X2, and X3) and two stack register pointers (SR0 and SRI). In some other examples, the assembly code can use any number of stack register pointers.

[0048] For example, the processor 102 can receive two store instructions as shown in Table 2 below. The store instruction on line 1 stores the data in the logical register X0 to the address of the stack register pointer 116. The store instruction on line 2 stores the data present in the logical register XI to a memory location whose address is stack register pointer 116 plus an offset of 8.

[0049] The processor 102 can identify that the two store instructions are stack-based store instructions because each of the store instructions references the stack pointer (sp) for accessing the data.

[0050] The processor 102 can use the register mapping table of Table 3 to obtain the source physical register name 118 of each of the logical registers. For example, logical register X0 maps to source physical register p 10 and logical register XI maps to source physical register p20.

[0051] In this example, the processor modifies the corresponding entry of the valid bit column (e.g., the second column of Table 3) from 0 to 1 to validate each respective stack register pointer. In this case, the processor 102 modifies the valid bit corresponding to stack register pointer SR0 from 0 to 1 and modifies the valid bit corresponding to stack register pointer SRI from 0 to 1 to validate the stack register pointers.

[0052] The processor then increments the stack register counter by two to represent the two store instructions mapped to the stack register pointers SR0 and SRI. Since there are no load instructions, there are two more store instructions than load instructions. In particular, the processor increments the stack register counter from 0x0 to 0x1 to represent the first available stack register pointer SR0 for the first store instruction, and the processor then increments the stack register pointer from 0x1 to 0x0 representing the second stack register pointer SRI for the second store instruction is the last available stack register pointer.

[0053] TABLE 3

[0054] The processor performs the stack-based memory renaming process based on the stack register counter being non-zero. In particular, the processor obtains each of the source physical register names 118 from the register mapping table 103 (e.g., Table 3). The processor 102 can then map each of the stack register pointers to a temporary physical register.

[0055] For example, the processor 102 can map the stack register pointer SR0 from null (e.g., no temporary physical register) to temporary' physical register pO and stack register SRI from null to temporary physical register pl. Based on the obtained source physical register names 118, the processor can move the data from each of the source physical registers 202 to the corresponding temporary' physical register 204 according to the store instructions. For example, for the first store instruction, the processor can move the data of source physical register plO that is mapped to logical register X0 to temporary physical register pO. For the second store instruction, the processor can move the data of source physical register p20 that is mapped to logical register XI to temporary physical register pl for the second store instruction, such that there are no duplicate copies of the temporary' physical registers in order to prevent multi-sharing.

[0056] In another example, the processor 102 may then receive two load instructions 114 after the two store instructions 1 12 of Table 2, as shown in Table 4 below. As discussed, the store instruction on line 1 writesthe content (e.g., the value) of the logical register X0 in the main memory' at the address of the content of the stack register pointer 116. The store instruction on line 2 stores the data present at the logical register XI to a memory’ location whose address is stack register pointer 116 plus an offset of 8. Thus, the store instruction on line 2 is at the top of the stack because it is the most recent store instruction. Several lines later, the load instruction on line 10 loads into logical register X2 the data at an address of the stack register pointer 116 plus an offset of 8. which is the same data stored by store instruction of line 2 in logical register XI. The load instruction on line 11 loads into logical register X3 the data at the address of the stack register pointer 116, which is the same data stored by the store instruction of line 1 in logical register X0.

[0057] The processor 102 can identify that the two load instructions are stack-based store instructions because each of the instructions references the stack pointer (sp) for accessing the data.

[0058] The processor 102 can use the register mapping table of Table 5 to obtain the source physical register name 118 of each of the logical registers. For example, logical register X2 maps to source physical register p30 and logical register X3 maps to source physical register p40.

[0059] In this example, the processor modifies the corresponding entry of the valid bit column (e.g., the second column of Table 3) from 0 to 1 to validate each respective stack register pointer. In this case, the processor 102 modifies the valid bit corresponding to stack register pointer SRI from 1 to 0 first since SRI is at the top of the stack, and the processor modifies the valid bit corresponding to stack register pointer SRO from 1 to 0 to invalidate the stack register pointers. By invalidating the stack register pointers, the processor maps the source physical registers of the load instructions to the temporary physical registers previously mapped to the stack register pointers. For example, the processor maps the source physical register p30 corresponding to logical register X2 to temporary physical register pl, and the processor maps the source physical register p40 corresponding to logical register X3 to temporary7physical register pO.

[0060] The processor then decrements the stack register counter by two to represent the two load instructions. In particular, the processor decrements the stack register counter from 0x0 to 0x1 to represent the first available stack register pointer SRI for the first load instruction, and the processor then decrements the stack register pointer from 0x1 to 0x0 representing the second stack register pointer SRO for the second load instruction.

[0061] Register Mapping T able ;

[0062] Vai PhyDest i

[0063] TABLE 5

[0064] During run-time, the processor identifies the temporary physical registers based on the stack register pointer using the register mapping table. For example, for the first load instruction, the processor can access the data from temporary physical register pl based on moving data from p20 corresponding to XI to pl during the earlier store instruction. For the second load instruction, the processor can access the data from temporary physical register pO based on moving data from plO corresponding to X0 to pO during the earlier store instruction. For each load instruction, the processor can store the data for the load instruction in a destination physical register 206.

[0065] Thus, if the processor receives a subtraction instruction prior to the store instructions and an addition instruction subsequent to the load instructions, the processor can perform the memory7renaming process in order to make the subtraction instruction directly dependent on the addition instruction without having to access the main memory and without having duplicate physical registers assigned to logical registers.

[0066] For example, as shown below in Table 6, the subtraction instruction on line 1 subtracts 1 from the data in logical register X32 and stores the result in the logical register XI. Several lines later, after the two store instruction and the two load instructions, the addition instruction on line 12 adds 1 to the data in logical register X2 and stores the result in logical register XI 0.

[0067] TAB E 6

[0068] As described with reference to Tables 2 through 5 above, the processor performed the memory renaming process by moving the data of logical register XI to stack register pointer SRI and mapping the logical register X2 to the temporary physical register pl. In particular, the logical register X2 is now mapped to temporary physical register pl because the processor identified the dependency between the store and load instruction pair (e g., the store instruction of line 3 and the load instruction of line 10).

[0069] During run-time, the logical register XI is mapped to p20, and the processor can execute the subtraction instruction by copying the data of source physical register p20 to temporary physical register pl based on the memory-renaming process, which is a relatively fast operation that is much faster than executing a store operation. As such, since the logical register X2 is now mapped to temporary physical register pl, the processor can execute the addition instruction on line 12 can read the data directly from the physical register pl to perform the addition operation. Thus, the processor can bypass executing the store instructions and the load instructions by performing the memory renaming process because the subtraction instruction and the addition instruction are no longer dependent on the store instructions and the load instructions. In particular, the store instruction and the load instruction can miss into the cache, and the execution of the addition instruction is not dependent on the load instructions or the store instructions, which decreases latency in the system and prevents multi-sharing between logical registers and physical registers.

[0070] In another example, the processor 102 can receive four store instructions 112 as shown in Table 7 below. The store instruction on line 1 stores the data at the address of the stack register pointer 1 16 in the logical register X0. The store instruction on line 2 stores the data at the address of the stack register pointer 116 plus an offset of 8 into logical register XI . The store instruction on line 3 stores the data at the address of the stack register pointer 11 plus an offset of 16 into logical register X2. The store instruction on line 4 stores the data at the address of the stack register pointer 116 plus an offset of 24 into logical register X3.

[0071] TAB E 7

[0072] The processor 102 can identify that the store instructions are stack-based store instructions because each of the instructions references the stack pointer (sp) for accessing the data. The processor 102 can also identify that there are four consecutive store instructions without any load instructions and there are two available stack register pointers.

[0073] The processor 102 can use the register mapping table of Table 8 to obtain the source physical register name 118 of each of the logical registers. For example, logical register X0 maps to source physical register plO, logical register XI maps to source physical register p20, logical register X2 maps to source physical register p30, and logical register X3 maps to source physical register p40.

[0074] In this example, the processor modifies the corresponding entry' of the valid bit column (e.g., the second column of Table 3) from 0 to 1 to validate each respective stack register pointer. In this case, the processor 102 modifies the valid bit corresponding to stack register pointer SRO from 0 to 1 and modifies the valid bit corresponding to stack register pointer SRI from 0 to 1 to validate the stack register pointers.

[0075] The processor then increments the stack register counter by four to represent the four store instructions mapped to the stack register pointers SRO and SRI. Since there are no load instructions, there are four more store instructions than load instructions. In particular, the processor increments the stack register counter from 0x0 to 0x1 to represent the first available stack register pointer SRO for the first store instruction, and the processor then increments the stack register pointer from 0x1 to 0x0 representing the second stack register pointer SRI for the second store instruction. The processor then increments the stack register counter from 0x0 to 0x1 to represent the first available stack register pointer SRO for the third store instruction, and the processor then increments the stack register pointer from 0x1 to 0x0 representing the second stack register pointer SRI for the fourth store instruction. Register Mapping Table

[0076] TAB E 8

[0077] The processor performs the stack-based memory’ renaming process based on the stack register counter being non-zero. In particular, the processor obtains each of the source physical register names 118 from the register mapping table (e.g., Table 8). The processor 102 can then map each of the stack register pointers to a temporary physical register.

[0078] For example, for the first store instruction, the processor 102 can map the stack register pointer SRO from null (e.g., no temporary physical register) to temporary physical register pO and, for the second store instruction, the processor can map stack register SRI from null to temporary physical register pl. In this case, the third store instruction and the fourth store instruction overwrite the mapping because they are the store instructions at the top of the stack. In particular, for the third store instruction, the processor maps the stack register pointer SRO from temporary physical register pO to temporary physical register p2, and for the fourth store instruction, the processor maps the stack register pointer SRI from temporary’ physical register pl to temporary phy sical register p3.

[0079] Based on the obtained source physical register names 118, the processor can move the data from each of the source physical registers 202 to the corresponding temporary physical register 204 according to the store instructions. For example, for the third store instruction, the processor can move the data of source physical register p30 that is mapped to logical register X2 to temporary physical register p2. For the fourth store instruction, the processor can move the data of source physical register p40 that is mapped to logical register X3 to temporary physical register p3, such that there are no duplicate copies of the temporary' physical registers in order to prevent multi-sharing.

[0080] The processor can assign the temporary’ physical registers pO and pl to the first two stack-based store instructions. In this case, when there are two younger stack-based store instructions in the program order, as shown in Table 7, the processor can rename the mapping of the stack registers SRO and SRI to temporary’ physical registers p2 and p3. Thus, the processor can perform the memory -renaming process by identifying and leveraging dependencies between subsequent younger stack-based load instructions that map to the logical registers of the third store instruction and the fourth store instruction (e.g., the last pair of store instructions). In particular, younger stack-based load instructions renamed (e.g., for which the processor performs the memory-renaming process) after the third store instruction and fourth store instruction will benefit from the last two store instructions through the memory-renaming process based on the processor mapping their respective destination logical registers to temporary physical registers p2 and p3. In this case, during execution, the first store instruction and the second store instruction will move the data from source physical register plO to temporary physical register pO and the data from source physical register p20 to temporary physical register pl. After execution, the processor can reclaim temporary' physical registers pO and pl based on the processor retiring the third store instruction and the fourth store instruction, respectively. Additionally, the processor can reclaim temporary physical registers p2 and p3 based on the processor retiring subsequent store instructions mapped to stack registers SRO and SRI.

[0081] In another example, the processor may receive store instructions that do not access data from the stack pointer address without an offset. In this case, the processor can track the offset with respect to the stack pointer using the register mapping table. In particular, if the processor receives two store instructions to the stack that do not start at offset 0, the processor can still rename each respective store instruction to stack register pointer SRO and stack register pointer SRI, and the processor can store them in the respective temporary physical registers with the respective offsets.

[0082] For example, the processor can receive two store instructions as shown in Table 9 below. The store instruction on line 1 stores the data in the address of the stack register pointer 116 plus an offset of 16 to the logical register XI . The store instruction on line 2 stores the data at the address of the stack register pointer 116 plus an offset of 24 into logical register X2.

[0083] TABLE 9

[0084] In this case, the processor maps each stack register pointer to a temporary physical register and moves the data from the source physical registers corresponding to logical registers XI and X2 along with the offsets (16 and 24). For subsequent load instructions, the processor can access the register mapping table to identify the temporary physical register to retrieve the data for the load instruction based on the offsets. Additionally, the processor can track an adjustment to the address of the stack pointer by adjusting the offset values by the same amount, thus, the processor maintains a reference address of the stack pointer.

[0085] FIG. 3 is a flow diagram of an example process for performing a stack-based memory renaming process. For convenience, the process 300 will be described as being performed by a processor. For example, a processor, e.g., the processor 102 of FIG. 1, appropriately configured in accordance with this specification, can perform the process 300.

[0086] The processor can receive a stack-based store instruction specifying a logical register name and an address (302). The processor can determine that the store instruction is a stackbased store instruction based on the address being a stack address corresponding to a stack. For example, with reference to Table 10, the store instruction of line 1 is stack-based because the instruction references the stack pointer (sp). The store instruction stores the data in the address of the stack pointer in logical register X0.

[0087] TABLE 10

[0088] Based on the processor determining that the instruction is a stack-based instruction, the processor can perform a stack-based memory7renaming process that is different than a normal memory renaming process.

[0089] The processor can perform the stack-based memory renaming process by mapping a stack register pointer to a temporary^ physical register and moving data from a source physical register indicated by the logical register name to the temporary physical register (304). The stack-based memory renaming process prevents multi-sharing of logical register names for stack-based memory instructions

[0090] In particular, the processor can obtain a source physical register name from a register mapping table based on the logical register name, where the register mapping table maintains a mapping of logical registers to physical registers. The register mapping table can include multiple entries for logical register names and one or more entries for stack register pointers.

[0091] For example, the processor can access the register mapping table of Table 11 and obtain the source physical register name for the store instruction of line 1. In particular, the processor obtains the source physical register name plO that maps to the logical register X0 of the store instruction. The processor then maps the stack register pointer SRO to a temporary physical register pO and moves data from a source physical register plO indicated by the logical register name to the temporary physical register pO.

[0092] TABLE 11

[0093] Additionally, the register mapping table can include an attribute representing whether or not each stack register pointer is valid, and the processor can modify an entry’ in the register mapping table corresponding to the stack register pointer to indicate that the stack register pointer is valid. For example, the processor can modify the entry of stack register pointer SRO from 0 to 1 to indicate that the stack register pointer SRO is valid.

[0094] In some cases, the processor can increment a register stack counter that represents how many more stack-based store instructions have been received than stack-based load instructions, and the processor can perform the stack-based memory renaming process only when the register stack counter is nonzero. For example, after receiving the store instruction of line 1, the processor can increment the counter from 0x0 to 0x1, and the processor can perform the memory renaming process based on the counter being nonzero.

[0095] The processor can then receive a stack-based load instruction (306). For example, the processor can receive the load instruction of line 10 in Table 10. The load instruction loads the data from the address of the stack pointer in logical register X3.

[0096] The processor can identify the temporary physical register based on the stack register pointer (308). For example, the processor identifies that the stack register pointer SRO is mapped to the temporary physical register pO based on the register mapping table.

[0097] The processor can retrieve data for the load instruction from the temporary physical register indicated by the stack pointer (310). For example, the processor can access the data for the load instruction by retrieving the data from the temporary physical register pO.

[0098] The processor can store the data for the load instruction in a destination physical register (312). For example, the processor can store the data for the load instruction in a destination phy sical register p20 that maps to the logical register X3. This specification uses the term “configured'’ in connection with systems and computer program components. For a system of one or more computers to be configured to perform particular operations or actions means that the system has installed on it software, firmware, hardware, or a combination of them that in operation cause the system to perform the operations or actions. For one or more computer programs to be configured to perform particular operations or actions means that the one or more programs include instructions that, when executed by data processing apparatus, cause the apparatus to perform the operations or actions.

[0099] Embodiments of the subject matter and the functional operations described in this specification can be implemented in digital electronic circuitry, in tangibly-embodied computer software or firmware, in computer hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. Embodiments of the subject matter described in this specification can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a tangible non-transitory storage medium for execution by, or to control the operation of. data processing apparatus. The computer storage medium can be a machine- readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more of them. Alternatively or in addition, the program instructions can be encoded on an artificially-generated propagated signal, e.g., a machine-generated electrical, optical, or electromagnetic signal, that is generated to encode information for transmission to suitable receiver apparatus for execution by a data processing apparatus.

[0100] The term “data processing apparatus” refers to data processing hardware and encompasses all kinds of apparatus, devices, and machines for processing data, including by way of example a programmable processor, a computer, or multiple processors or computers. The apparatus can also be, or further include, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit). The apparatus can optionally include, in addition to hardware, code that creates an execution environment for computer programs, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.

[0101] A computer program, which may also be referred to or described as a program, software, a software application, an app, a module, a softw are module, a script, or code, can be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages; and it can be deployed in any form, including as a stand- alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A program may, but need not, correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data, e.g., one or more scripts stored in a markup language document, in a single file dedicated to the program in question, or in multiple coordinated files, e.g., files that store one or more modules, subprograms, or portions of code. A computer program can be deployed to be executed on one computer or on multiple computers that are located at one site or distributed across multiple sites and interconnected by a data communication network.

[0102] In this specification the term “engine” is used broadly to refer to a software-based system, subsystem, or process that is programmed to perform one or more specific functions. Generally, an engine will be implemented as one or more software modules or components, installed on one or more computers in one or more locations. In some cases, one or more computers will be dedicated to a particular engine; in other cases, multiple engines can be installed and running on the same computer or computers.

[0103] The processes and logic flows described in this specification can be performed by one or more programmable computers executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows can also be performed by special purpose logic circuitry, e.g., an FPGA or an ASIC, or by a combination of special purpose logic circuitry and one or more programmed computers.

[0104] Computers suitable for the execution of a computer program can be based on general or special purpose microprocessors or both, or any other kind of central processing unit. Generally, a central processing unit will receive instructions and data from a read-only memory or a random access memory' or both. The essential elements of a computer are a central processing unit for performing or executing instructions and one or more memory devices for storing instructions and data. The central processing unit and the memory can be supplemented by, or incorporated in, special purpose logic circuitry. Generally, a computer will also include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto-optical disks, or optical disks. However, a computer need not have such devices. Moreover, a computer can be embedded in another device, e.g., a mobile telephone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a Global Positioning System (GPS) receiver, or a portable storage device, e g., a universal serial bus (USB) flash drive, to name just a few.

[0105] Computer-readable media suitable for storing computer program instructions and data include all forms of non-volatile memory7, media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices; magnetic disks, e.g.. internal hard disks or removable disks; magneto-optical disks; and CD- ROM and DVD-ROM disks.

[0106] To provide for interaction with a user, embodiments of the subject matter described in this specification can be implemented on a computer having a display device, e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor, for displaying information to the user and a keyboard and a pointing device, e.g.. a mouse or a trackball, by which the user can provide input to the computer. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback, e.g., visual feedback, auditory feedback, or tactile feedback; and input from the user can be received in any form, including acoustic, speech, or tactile input. In addition, a computer can interact with a user by sending documents to and receiving documents from a device that is used by the user; for example, by sending web pages to a web browser on a user’s device in response to requests received from the web browser. Also, a computer can interact with a user by sending text messages or other forms of message to a personal device, e.g., a smartphone that is running a messaging application, and receiving responsive messages from the user in return.

[0107] Data processing apparatus for implementing machine learning models can also include, for example, special-purpose hardware accelerator units for processing common and computeintensive parts of machine learning training or production, i.e., inference, workloads.

[0108] Machine learning models can be implemented and deployed using a machine learning framework, e.g., a TensorFlow framework.

[0109] Embodiments of the subject matter described in this specification can be implemented in a computing system that includes a back-end component, e.g., as a data server, or that includes a middleware component, e.g., an application server, or that includes a front-end component, e.g., a client computer having a graphical user interface, a web browser, or an app through which a user can interact with an implementation of the subject matter described in this specification, or any combination of one or more such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication, e.g., a communication network. Examples of communication networks include a local area network (LAN) and a wide area network (WAN), e.g., the Internet.

[0110] The computing system can include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. In some embodiments, a server transmits data, e.g., an HTML page, to a user device, e.g., for purposes of displaying data to and receiving user input from a user interacting with the device, which acts as a client. Data generated at the user device, e.g., a result of the user interaction, can be received at the server from the device.

[0111] In addition to the embodiments described above, the following embodiments are also innovative:

[0112] Embodiment 1 is a processor configured to perform operations comprising: receiving a stack-based store instruction specifying a logical register name and an address; performing a stack-based memory renaming process that maps a stack register pointer to a temporary physical register and moves data from a source physical register indicated by the logical register name to the temporary physical register; receiving a stack-based load instruction; identifying the temporary physical register based on the stack register pointer; retrieving data for the load instruction from the temporary physical register indicated by the stack register pointer; and storing the data for the load instruction in a destination physical register.

[0113] Embodiment 2 is the processor of embodiment 1, wherein the operations further comprise: obtaining, based on the logical register name, a source physical register name from a register mapping table that is configured to maintain a mapping of logical registers to physical registers.

[0114] Embodiment 3 is the processor of embodiment 1-2, wherein the register mapping table includes an attribute representing whether or not each stack register pointer is valid, and wherein operations further comprise modifying an entry7in the register mapping table corresponding to the stack register pointer to indicate that the stack register pointer is valid.

[0115] Embodiment 4 is the processor of embodiment 2. wherein the register mapping table comprises a plurality of entries for logical register names and one or more entries for stack register pointers. Embodiment 5 is the processor of any one of embodiments 1-4, wherein the operations further comprise determining that the store instruction is a stack-based store instruction based on the address being a stack address.

[0116] Embodiment 6 is the processor of any one of embodiments 1-5, wherein the operations further comprise incrementing a register stack counter that represents how many more stackbased store instructions have been received than stack-based load instructions.

[0117] Embodiment 7 is the processor of embodiment 6, further comprising performing the stack-based memory renaming process only when the register stack counter is nonzero.

[0118] Embodiment 8 is the processor of any one of embodiments 1-7, wherein the stack-based memory renaming process prevents multi-sharing of logical register names for stack-based memory instructions.

[0119] Embodiment 9 is the processor of any one of embodiments 1-8, wherein receiving the stack-based store instruction further comprises: determining that the instruction is a stack-based instruction; and in response, performing a stack-based memory’ renaming process that is different than a normal memory renaming process.

[0120] Embodiment 10 is a method comprising: receiving a stack-based store instruction specifying a logical register name and an address; performing a stack-based memory renaming process that maps a stack register pointer to a temporary physical register and moves data from a source physical register indicated by the logical register name to the temporary' physical register; receiving a stack-based load instruction; identifying the temporary physical register based on the stack register pointer; retrieving data for the load instruction from the temporary physical register indicated by the stack register pointer; and storing the data for the load instruction in a destination physical register. Embodiment 11 is the method of embodiment 10, further comprising: obtaining, based on the logical register name, a source physical register name from a register mapping table that is configured to maintain a mapping of logical registers to physical registers.

[0121] Embodiment 12 is the method of any’ one of embodiments 10-11, wherein the register mapping table includes an attribute representing whether or not each stack register pointer is valid, and wherein operations further comprise modifying an entry in the register mapping table corresponding to the stack register pointer to indicate that the stack register pointer is valid.

[0122] Embodiment 13 is the method of embodiment 11, wherein the register mapping table comprises a plurality of entries for logical register names and one or more entries for stack register pointers.

[0123] Embodiment 14 is the method of any one of embodiments 10-13. further comprising: determining that the store instruction is a stack-based store instruction based on the address being a stack address.

[0124] Embodiment 15 is the method of any one of embodiments 10-14, further comprising: incrementing a register stack counter that represents how many more stack-based store instructions have been received than stack-based load instructions.

[0125] Embodiment 16 is a system comprising: a memory that is configured to store data; and one or more processors configured to repeatedly perform operations comprising: receiving a stack-based store instruction specifying a logical register name and an address; performing a stack-based memory renaming process that maps a stack register pointer to a temporary physical register and moves data from a source physical register indicated by the logical register name to the temporary physical register; receiving a stack-based load instruction; identify ing the temporary’ physical register based on the stack register pointer; retrieving data for the load instruction from the temporary physical register indicated by the stack register pointer; and storing the data for a load instruction in a destination physical register.

[0126] Embodiment 17 is the system of embodiment 16, wherein the operations further comprise: obtaining, based on the logical register name, a source physical register name from a register mapping table that is configured to maintain a mapping of logical registers to physical registers.

[0127] Embodiment 18 is the system of any one of the embodiments 16-17, wherein the register mapping table includes an attribute representing whether or not each stack register pointer is valid, and wherein operations further comprise modifying an entry in the register mapping table corresponding to the stack register pointer to indicate that the stack register pointer is valid.

[0128] Embodiment 19 is the system of embodiment 17, wherein the register mapping table comprises a plurality of entries for logical register names and one or more entries for stack register pointers.

[0129] Embodiment 20 is the system of any one of the embodiments 16-19, wherein the operations further comprise determining that the store instruction is a stack-based store instruction based on the address being a stack address.

[0130] While this specification contains many specific implementation details, these should not be construed as limitations on the scope of any invention or on the scope of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments of particular inventions. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially be claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

[0131] Similarly, while operations are depicted in the drawings and recited in the claims in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system modules and components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0132] Particular embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. For example, the actions recited in the claims can be performed in a different order and still achieve desirable results. As one example, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some cases, multitasking and parallel processing may be advantageous.

Claims

CLAIMS1. A processor configured to perform operations comprising: receiving a stack-based store instruction specifying a logical register name and an address; performing a stack-based memory renaming process that maps a stack register pointer to a temporary physical register and moves data from a source physical register indicated by the logical register name to the temporary physical register; receiving a stack-based load instruction; identifying the temporary physical register based on the stack register pointer; retrieving data for the load instruction from the temporary physical register indicated by the stack register pointer; and storing the data for the load instruction in a destination physical register.

2. The processor of claim 1, wherein the operations further comprise: obtaining, based on the logical register name, a source physical register name from a register mapping table that is configured to maintain a mapping of logical registers to physical registers.

3. The processor of any one of claims 1-2, wherein the register mapping table includes an attribute representing whether or not each stack register pointer is valid, and wherein operations further comprise modifying an entry in the register mapping table corresponding to the stack register pointer to indicate that the stack register pointer is valid.

4. The processor of claim 2, wherein the register mapping table comprises a plurality of entries for logical register names and one or more entries for stack register pointers.

5. The processor of any one of claims 1-4, wherein the operations further comprise determining that the store instruction is a stack-based store instruction based on the address being a stack address.

6. The processor of any one of claims 1-5, wherein the operations further comprise incrementing a register stack counter that represents how many more stack-based store instructions have been received than stack-based load instructions.

7. The processor of claim 6, further comprising performing the stack-based memoryrenaming process only when the register stack counter is nonzero.

8. The processor of any one of claims 1-7, wherein the stack-based memory renaming process prevents multi-sharing of logical register names for stack-based memory instructions.

9. The processor of any one of claims 1-8, wherein receiving the stack-based store instruction further comprises: determining that the instruction is a stack-based instruction; and in response, performing a stack-based memory- renaming process that is different than a normal memory renaming process.

10. A method comprising: receiving a stack-based store instruction specifying a logical register name and an address; performing a stack -based memory renaming process that maps a stack register pointer to a temporary- physical register and moves data from a source physical register indicated by the logical register name to the temporary physical register; receiving a stack-based load instruction; identifying the temporary' physical register based on the stack register pointer; retrieving data for the load instruction from the temporary- physical register indicated by the stack register pointer; and storing the data for the load instruction in a destination physical register.

11. The method of claim 10, further comprising: obtaining, based on the logical register name, a source physical register name from a register mapping table that is configured to maintain a mapping of logical registers to physical registers.

12. The method of any- one of claims 10-11, w-herein the register mapping table includes an attribute representing whether or not each stack register pointer is valid, and wherein operations further comprise modifying an entry in the register mapping table corresponding to the stack register pointer to indicate that the stack register pointer is valid.

13. The method of claim 11, wherein the register mapping table comprises a plurality of entries for logical register names and one or more entries for stack register pointers.

14. The method of any one of claims 10-13, further comprising: determining that the store instruction is a stack-based store instruction based on the address being a stack address.

15. The method of any one of claims 10-14, further comprising: incrementing a register stack counter that represents how many more stack-based store instructions have been received than stack-based load instructions.

16. A sy stem compri sing : a memory that is configured to store data; and one or more processors configured to repeatedly perform operations comprising: receiving a stack-based store instruction specifying a logical register name and an address; performing a stack-based memory renaming process that maps a stack register pointer to a temporary physical register and moves data from a source physical register indicated by the logical register name to the temporary physical register; receiving a stack-based load instruction; identify ing the temporary’ physical register based on the stack register pointer; retrieving data for the load instruction from the temporary physical register indicated by the stack register pointer; and storing the data for a load instruction in a destination physical register.

17. The system of claim 1, wherein the operations further comprise: obtaining, based on the logical register name, a source physical register name from a register mapping table that is configured to maintain a mapping of logical registers to physical registers.

18. The system of any one of claims 16-17, wherein the register mapping table includes an attribute representing whether or not each stack register pointer is valid, and whereinoperations further comprise modifying an entry in the register mapping table corresponding to the stack register pointer to indicate that the stack register pointer is valid.

19. The system of claim 17, wherein the register mapping table comprises a plurality of entries for logical register names and one or more entries for stack register pointers.

20. The system of any one of claims 16-19, wherein the operations further comprise determining that the store instruction is a stack-based store instruction based on the address being a stack address.

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