L3 cache extension apparatus, access method, access apparatus, device, and medium

Abstract

The present application relates to the technical field of storage, and provides an L3 cache extension apparatus, an access method, an access apparatus, a device, and a medium. The L3 cache extension apparatus comprises a processor, an SRAM, and a CXL interface; the SRAM serves as a memory for an extended L3 cache; the processor is connected to the SRAM, and the CXL interface is built in the processor; and firmware of the processor is configured to: receive, by means of the CXL interface, a CXL.CACHE access command sent by a CPU, and access the extended L3 cache in response to the CXL.CACHE access command.

Description

L3 cache expansion device, access method, access device, equipment and medium

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on January 31, 2024, with application number 202410130869.1, and application name “L3 cache extension device, access method, access device, equipment and medium”, all contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to an L3 cache expansion device, access method, access device, equipment and medium. Background Art

[0004] Currently, computer system memory uses a multi-level pyramid-like structure. From the top to the bottom, the pyramid consists of registers, L1 cache, L2 cache, L3 cache, main memory, and local disk. Each CPU core has its own L1 cache and L2 cache, while all CPU cores share the L3 cache.

[0005] The inventors realized that due to limitations of CPU size, power consumption and other factors, the L3 cache cannot be increased; at the same time, because current PCIe devices cannot achieve cache consistency between the L3 cache and main memory, the L3 cache cannot be expanded.

[0006] Summary of the Invention

[0007] According to an embodiment of the present application, in a first aspect, an L3 cache expansion device is provided, comprising: a processor, a static random access memory (SRAM), and a CXL interface, wherein the SRAM serves as a memory for the L3 extended cache; wherein the processor is connected to the SRAM, and the processor has a built-in CXL interface; and

[0008] The firmware of the processor is configured to receive a CXL.CACHE access command sent by the CPU through the CXL interface, respond to the CXL.CACHE access command, and access the L3 extended cache.

[0009] According to an embodiment of the present application, in a second aspect, a method for accessing an L3 extended cache is provided, which is applied to the firmware of a processor. The method includes:

[0010] receiving CXL.CACHE access commands sent by the CPU via a CXL interface built into the processor; and

[0011] In response to the CXL.CACHE access command, the L3 extended cache is accessed; the SRAM serves as the memory of the L3 extended cache, and the processor is connected to the SRAM.

[0012] According to an embodiment of the present application, in a third aspect, a method for accessing an L3 extended cache is provided, which is applied to a CPU. The method includes:

[0013] In response to an L3 cache access operation, determining that the L3 cache to be accessed is an L3 extended cache based on a flag bit carried in the L3 cache access operation; an SRAM is used as a memory of the L3 extended cache, and the processor is connected to the SRAM; and

[0014] Send a CXL.CACHE access command to the CXL interface, which is built into the processor, to access the L3 extended cache.

[0015] According to a fourth aspect of an embodiment of the present application, there is further provided an L3 level extended cache access device, applied to a CPU, the device comprising:

[0016] a determination module, configured to respond to an L3 cache access operation and determine, based on a flag bit carried in the L3 cache access operation, that the L3 cache to be accessed is an L3 extended cache; an SRAM serving as a memory of the L3 extended cache, the processor being connected to the SRAM; and

[0017] The sending module is used to send a CXL.CACHE access command to the CXL interface, where the CXL.CACHE access command is used to access the L3 extended cache. The CXL interface is built into the processor.

[0018] According to an embodiment of the present application, in a fifth aspect, a CPU is also provided, comprising a memory, a processor, and computer-readable instructions stored in the memory and executable on the processor, wherein when the processor executes the program, the steps of the L3 extended cache access method as described in any one of the third aspects are implemented.

[0019] According to an embodiment of the present application, in a sixth aspect, a server is further provided, comprising: a CPU as in the fifth aspect and an L3 cache expansion device as in any one of the first aspect.

[0020] According to an embodiment of the present application, in the seventh aspect, a non-volatile computer-readable storage medium is also provided, on which computer-readable instructions are stored. When the computer-readable instructions are executed by a processor, the steps of the L3 level extended cache access method as described in any one of the second aspect or the third aspect are implemented.

[0021] According to an embodiment of the present application, in an eighth aspect, a computer-readable instruction product is also provided, comprising computer-readable instructions / instructions, which, when executed by a processor, implement the steps of the L3 level extended cache access method of any one of the second aspect or the third aspect described above.

[0022] The details of one or more embodiments of the present application are set forth in the accompanying drawings and the description below. Other features and advantages of the present application will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0024] FIG1 is a schematic diagram of the hierarchical structure of the L1-L3 cache within a CPU provided by the related art;

[0025] FIG2 is a schematic diagram of a structure of an L3 cache expansion device according to an embodiment of the present application;

[0026] FIG3 is a schematic diagram showing a comparison before and after the L3 cache expansion according to an embodiment of the present application;

[0027] FIG4 is a second structural diagram of the L3 cache expansion device provided in an embodiment of the present application;

[0028] FIG5 is a schematic diagram of a module composition of the FPGA firmware provided in an embodiment of the present application;

[0029] FIG6 is a second schematic diagram of the module composition of the FPGA firmware provided in an embodiment of the present application;

[0030] FIG7 is a flow chart of a method for accessing an L3 extended cache according to an embodiment of the present application;

[0031] FIG8 is a second flow chart of the L3 extended cache access method provided in an embodiment of the present application;

[0032] FIG9 is a schematic structural diagram of an L3 level extended cache access device provided in an embodiment of the present application;

[0033] FIG10 is a schematic diagram of the structure of a CPU provided in an embodiment of the present application;

[0034] FIG11 is a schematic diagram of the structure of a server according to an embodiment of the present application;

[0035] FIG12 is a second structural diagram of a server provided in an embodiment of the present application;

[0036] FIG13 is a schematic diagram of a non-volatile computer-readable storage medium provided in an embodiment of the present application. DETAILED DESCRIPTION

[0037] To make the objectives, technical solutions, and advantages of this application more clear, the technical solutions of this application will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0038] The terms "first," "second," and the like in the specification of this application are used to distinguish similar objects, and are not used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of this application can be implemented in an order other than that illustrated or described herein, and that the objects distinguished by "first," "second," and the like are generally of the same type, and do not limit the number of objects; for example, the first object can be one or more. Furthermore, the term "and / or" in this specification indicates at least one of the connected objects, and the character " / " generally indicates that the objects connected are in an "or" relationship.

[0039] Currently, computer system memory utilizes a multi-layered pyramid-like structure. From top to bottom, the pyramid consists of registers, L1 cache, L2 cache, L3 cache, main memory, and local disks. Each layer of storage serves as a cache for the next lower layer. In this hierarchy, memory units closer to the CPU core operate faster but have smaller capacity and higher costs. In theory, the larger the capacity of the memory units at the top of the pyramid, the higher the system performance.

[0040] Please refer to Figure 1, which is a schematic diagram of the hierarchical structure of the L1-L3 cache within a CPU provided by the related art. As shown in Figure 1, registers and L1, L2, and L3 caches are located within the CPU. Each CPU core independently occupies L1 and L2 caches, with a storage capacity of the KB (Kilobyte) level. All CPU cores share the L3 cache, with a storage capacity of the MB (Megabyte) level. Moreover, within a CPU, the L3 cache accounts for more than 60% of the total number of CPU transistors. The larger the storage capacity of the storage medium below the pyramid, the slower the speed, which seriously affects the CPU's operating efficiency.

[0041] Due to limitations of CPU size, power consumption, and other factors, the L3 cache cannot be increased. Also, because current PCIe devices cannot achieve cache consistency between the L3 cache and main memory, the L3 cache cannot be expanded.

[0042] Based on this, the embodiments of the present application provide an L3 cache expansion device, access method, access device, equipment and medium, which are described in detail below.

[0043] The L3 cache expansion device provided in the embodiment of the present application is described in detail below with reference to Figures 2-6 through specific embodiments and their application scenarios.

[0044] Please refer to Figure 2, which is one of the structural diagrams of the L3 cache expansion device provided in an embodiment of the present application. As shown in Figure 2, the L3 cache expansion device may include: a processor, which may be a field programmable gate array (FPGA) 21, a static random access memory (SRAM) 22, a CXL (Compute Express Link) interface 23, a power supply 24, a complex programmable logic device (CPLD) 25 and a FLASH 26. Exemplarily, the processor may be an FPGA, or other hardware board or other processor that can implement the above functions.

[0045] FPGA 21 is connected to SRAM 22, which serves as a memory for L3 extended cache. That is, L3 extended cache is extended outside the CPU and is not limited by factors such as CPU size and power consumption.

[0046] FPGA 21 has a built-in CXL interface 23. The firmware of FPGA 21 is configured to receive CXL.CACHE access commands from the CPU through CXL interface 23, respond to CXL.CACHE access commands, and access the L3 extended cache. CXL interface 23 supports the CXL.CACHE protocol, ensuring data consistency between the L3 extended cache and main memory.

[0047] The power supply 24 is used to supply power to the FPGA 21 , the CPLD 25 is used to control the power-on timing of the FPGA 21 , and the FLASH 26 stores the firmware of the FPGA 21 , which is a software program.

[0048] As shown in Figure 3, before the L3 cache is expanded using the L3 cache expansion device provided by this embodiment, the L3 cache only includes the CPU's local L3 cache. After the L3 cache is expanded using the L3 cache expansion device provided by this embodiment, the L3 cache includes the CPU's local L3 cache and an L3 expansion cache outside the CPU. It can be seen that the L3 cache expansion device provided by this embodiment can expand the L3 cache outside the CPU.

[0049] The L3 cache expansion device provided in the embodiment of the present application includes an FPGA, SRAM, and a CXL interface. The FPGA is connected to the SRAM, and the SRAM serves as the memory of the L3 extended cache. That is, the L3 extended cache is expanded outside the CPU and is not limited by factors such as CPU size and power consumption. The FPGA has a built-in CXL interface, and the FPGA firmware is configured to receive CXL.CACHE access commands sent by the CPU through the CXL interface, respond to CXL.CACHE access commands, and access the L3 extended cache. The CXL interface supports the CXL.CACHE protocol, which can ensure data consistency between the L3 extended cache and main memory. Because the L3 extended cache is expanded outside the CPU, it is not limited by factors such as CPU size and power consumption; and it can ensure data consistency between the L3 extended cache and main memory. Therefore, the embodiment of the present application can achieve L3 cache expansion outside the CPU, thereby significantly improving the overall performance of the CPU system.

[0050] In some embodiments, as shown in Figure 4, the L3 cache expansion device further includes a peripheral interface 41. The CXL interface 23 is connected to the peripheral interface 41, and the peripheral interface 41 is a PCIe gold finger or a PCIe connector.

[0051] Exemplarily, the peripheral interface 41 is a PCIe gold finger, and the L3 cache expansion device can be directly inserted into the PCIe slot of the host through the PCIe gold finger, so that the CXL interface 23 can communicate with the CPU in the host.

[0052] The peripheral interface 41 is a PCIe connector, and the host can be connected to the PCIe connector of the L3 cache expansion device via a cable, so that the CXL interface 23 can communicate with the CPU in the host.

[0053] In this embodiment, the CXL interface is connected to the peripheral interface, which is a PCIe gold finger or a PCIe connector. The peripheral interface can realize communication between the CXL interface and the CPU in the host, and can increase the L3 cache capacity, thereby improving the CPU system performance.

[0054] In some embodiments, as shown in FIG5 , the firmware of FPGA 21 includes: a CXL parsing module 51 , an SRAM control module 52 , and a CXL protocol module 53 .

[0055] The CXL parsing module 51 is configured to parse the CXL.CACHE read command to obtain a first start address and a first data length when the CXL.CACHE access command is a CXL.CACHE read command.

[0056] Specifically, the CXL.CACHE access command sent by the CPU is received through the CXL interface 23 . When the CXL.CACHE access command is a CXL.CACHE read command, the CXL.CACHE read command is parsed through the CXL.IO protocol to obtain the first start address and the first data length.

[0057] The SRAM control module 52 is configured to read first data of a first data length starting from a first starting address of the L3 extended cache.

[0058] Specifically, the starting position of the data is searched in the L3 extended cache using the first starting address, and the first data of the first data length is read starting from the starting position of the data.

[0059] The CXL protocol module 53 is configured to encapsulate the first data into a CXL packet and send the CXL packet to the CPU, thereby enabling the CPU to read the first data.

[0060] The CXL parsing module 51 is further configured to: when the CXL.CACHE access command is a CXL.CACHE write command, parse the CXL.CACHE write command to obtain a second start address, a second data length, and second data.

[0061] Specifically, the CXL.CACHE access command sent by the CPU is received through the CXL interface 23. When the CXL.CACHE access command is a CXL.CACHE write command, the CXL.CACHE write command is parsed through the CXL.IO protocol to obtain the second start address, the second data length, and the second data.

[0062] The SRAM control module 52 is further configured to write second data of a second data length starting from a second starting address of the L3 extended cache.

[0063] Specifically, the starting position of the data is searched in the L3 extended cache based on the second starting address, and the second data of the second data length is written starting from the starting position of the data, thereby completing the CPU's write access to the second data.

[0064] In this embodiment, the FPGA firmware includes a CXL parsing module, an SRAM control module, and a CXL protocol module. Since the CXL protocol module encapsulates the first data read by the SRAM control module based on the first starting address and first data length parsed by the CXL parsing module into a CXL packet, and sends the CXL packet to the CPU, the CPU can complete read access to the first data. The SRAM control module writes the second data into the L3 level extended cache based on the second starting address, second data length, and second data parsed by the CXL parsing module, and the CPU can complete write access to the second data. Thus, the CPU can realize read and write access to the L3 level extended cache.

[0065] In some embodiments, as shown in FIG6 , the firmware of FPGA 21 further includes: a replacement algorithm module 61 for selecting a corresponding replacement algorithm based on actual application requirements; the replacement algorithm is used to replace data of one thread with data of another thread.

[0066] For example, assuming that the actual application requirements are: part of the data of the first thread enters the L3 extended cache first, and part of the data of the second thread enters the L3 extended cache later. At this time, the third thread needs the L3 extended cache, and the selected replacement algorithm is the first-in-first-out algorithm, that is, the part of the data of the first thread that enters the L3 extended cache first is replaced with the data of the third thread.

[0067] Assume that the actual application requirements are: the data of the first thread and the second thread are in the L3 extended cache, and the data of the first thread is used less time. At this time, the third thread needs the L3 extended cache, and the selected replacement algorithm is the least-used replacement algorithm, that is, the data of the first thread that takes the least time is replaced with the data of the third thread.

[0068] In this embodiment, the replacement algorithm module can select a corresponding replacement algorithm based on actual application requirements, and can fully utilize temporal locality and spatial locality to improve the CPU program running speed.

[0069] In some embodiments, the bit width of the L3 extended cache is the size of a cache line.

[0070] The bit width of the L3 extended cache can be expanded as needed. In this embodiment, the bit width of the L3 extended cache can be configured to 512 bits, or 64 bytes. 512 bits is exactly the size of a cache line, ensuring that a single read or write cycle accesses a cache line's data, significantly reducing latency. Furthermore, SRAM does not require refresh operations or row and column selection, further ensuring low latency.

[0071] Next, the L3 extended cache access method provided in the embodiment of the present application is described in detail below with reference to specific embodiments and their application scenarios with reference to Figures 7-8.

[0072] Please refer to Figure 7, which is a flow chart of a method for accessing an L3 extended cache provided by an embodiment of the present application. The method is applied to the firmware of the FPGA, as shown in Figure 7, and may include the following steps:

[0073] Step 701: Receive a CXL.CACHE access command sent by the CPU via the CXL interface; the CXL interface is built into the FPGA;

[0074] Step 702: respond to the CXL.CACHE access command to access the L3 extended cache; the SRAM serves as the memory of the L3 extended cache, and the FPGA is connected to the SRAM.

[0075] Specifically, the FPGA is connected to the SRAM, which serves as the memory for the L3 extended cache. In other words, the L3 extended cache is extended outside the CPU and is not limited by factors such as CPU size and power consumption.

[0076] The FPGA has a built-in CXL interface, which receives CXL.CACHE access commands from the CPU and responds to them to access the L3 extended cache. The CXL interface supports the CXL.CACHE protocol, ensuring data consistency between the L3 extended cache and main memory.

[0077] The L3 extended cache access method provided in an embodiment of the present application first receives a CXL.CACHE access command sent by a CPU through a CXL interface; the CXL interface is built into an FPGA; then, in response to the CXL.CACHE access command, the L3 extended cache is accessed; since SRAM serves as the memory for the L3 extended cache, the FPGA is connected to the SRAM; the L3 extended cache is extended outside the CPU and is not limited by factors such as CPU size and power consumption; the CXL interface supports the CXL.CACHE protocol, which can ensure data consistency between the L3 extended cache and main memory; therefore, the embodiment of the present application can implement L3 cache extension outside the CPU, thereby significantly improving the overall performance of the CPU system.

[0078] In some embodiments, step 702 may include: when the CXL.CACHE access command is a CXL.CACHE read command, parsing the CXL.CACHE read command to obtain a first starting address and a first data length; reading first data of the first data length starting from the first starting address of the L3 extended cache; encapsulating the first data into a CXL packet, and sending the CXL packet to the CPU, thereby completing the CPU's read access to the first data.

[0079] In some embodiments, step 702 may include: when the CXL.CACHE access command is a CXL.CACHE write command, parsing the CXL.CACHE write command to obtain a second starting address, a second data length, and the second data; and writing the second data of the second data length starting from the second starting address of the L3 extended cache, thereby completing the CPU's write access to the second data.

[0080] Please refer to Figure 8, which is a second flow chart of the L3 level extended cache access method provided by an embodiment of the present application. The method is applied to the CPU, as shown in Figure 8, and the method may include the following steps:

[0081] Step 801: In response to an L3 cache access operation, determine that the L3 cache to be accessed is an L3 extended cache based on a flag bit carried in the L3 cache access operation; SRAM serves as a memory of the L3 extended cache, and the FPGA is connected to the SRAM;

[0082] Step 802: Send a CXL.CACHE access command to the CXL interface, where the CXL.CACHE access command is used to access the L3 extended cache; the CXL interface is built into the FPGA.

[0083] In step 801, in response to an L3 cache access operation, a flag bit carried in the L3 cache access operation is obtained. If the flag bit is 1, the L3 cache to be accessed is determined to be the L3 extended cache. SRAM serves as the memory for the L3 extended cache, and the FPGA is connected to the SRAM; that is, the L3 extended cache is extended outside the CPU and is not limited by factors such as CPU size and power consumption.

[0084] If the flag bit is 0, it is determined that the L3 cache to be accessed is the local L3 cache of the CPU, and read and write access is performed according to the original access mechanism of the CPU to the local L3 cache.

[0085] In step 802, the CXL interface built into the FPGA sends a CXL.CACHE access command to the CXL interface. The CXL.CACHE access command is used to access the L3 extended cache. The CXL interface supports the CXL.CACHE protocol, which can ensure data consistency between the L3 extended cache and the main memory.

[0086] The L3 extended cache access method provided in an embodiment of the present application first responds to an L3 cache access operation and determines that the L3 cache to be accessed is the L3 extended cache based on a flag bit carried in the L3 cache access operation; SRAM serves as the memory of the L3 extended cache, and the FPGA is connected to the SRAM; that is, the L3 extended cache is extended outside the CPU and is not limited by factors such as CPU size and power consumption; then, a CXL interface is built into the FPGA and sends a CXL.CACHE access command to the CXL interface, which is used to access the L3 extended cache; the CXL interface supports the CXL.CACHE protocol, which can ensure data consistency between the L3 extended cache and main memory; therefore, the embodiment of the present application can implement L3 cache extension outside the CPU, thereby significantly improving the overall performance of the CPU system.

[0087] In some embodiments, step 802 may include: determining whether the access operation of the L3 extended cache is a read or a write; if the access operation of the L3 extended cache is a read, determining that the CXL.CACHE access command is a CXL.CACHE read command, and sending the CXL.CACHE read command to the CXL interface; if the access operation of the L3 extended cache is a write, determining that the CXL.CACHE access command is a CXL.CACHE write command, and sending the CXL.CACHE write command to the CXL interface.

[0088] Specifically, if the L3 cache being accessed is the L3 extended cache, a read / write check is performed on the access operation to the L3 extended cache. If the access operation is a read, a CXL.CACHE read command is sent to the CXL interface to instruct the FPGA firmware to complete the CPU's read access to the first data. If the access operation is a write, a CXL.CACHE write command is sent to the CXL interface to instruct the FPGA firmware to complete the CPU's write access to the second data. This enables the CPU to read and write the L3 extended cache.

[0089] It should be noted that the L3 extended cache access method provided in the embodiments of the present application can be executed by an L3 extended cache access device, or a control module in the L3 extended cache access device for executing the L3 extended cache access method. In the embodiments of the present application, the L3 extended cache access device provided in the embodiments of the present application is described by taking the L3 extended cache access device executing the L3 extended cache access method as an example.

[0090] It should be noted that, in the embodiments of the present application, the L3 extended cache access method illustrated in any one or more of the method figures above is described for illustrative purposes in conjunction with the figures in the embodiments of the present application. In specific implementations, the L3 extended cache access method illustrated in any one or more of the method figures above may also be implemented in conjunction with any other combinable figures illustrated in the embodiments above, and no further details will be given here.

[0091] The L3 level extension cache access device provided by the present application is described below. The L3 level extension cache access method described below and the L3 level extension cache access method described above can be referenced to each other.

[0092] Please refer to Figure 9, which is a schematic diagram of the structure of the L3 level extended cache access device provided by an embodiment of the present application. The L3 level extended cache access device is applied to a CPU, as shown in Figure 9, and the device may include:

[0093] A determination module 901 is configured to respond to an L3 cache access operation and determine, based on a flag bit carried in the L3 cache access operation, that the L3 cache to be accessed is an L3 extended cache; an SRAM is used as a memory for the L3 extended cache, and an FPGA is connected to the SRAM;

[0094] The sending module 902 is configured to send a CXL.CACHE access command to the CXL interface, where the CXL.CACHE access command is used to access the L3 extended cache. The CXL interface is built into the FPGA.

[0095] In some embodiments, the sending module 902 is specifically configured to:

[0096] Determine whether the access operation of the L3 extended cache is read or write;

[0097] When the access operation of the L3 extended cache is a read operation, determining that the CXL.CACHE access command is a CXL.CACHE read command, and sending the CXL.CACHE read command to the CXL interface;

[0098] When the access operation of the L3 extended cache is a write operation, the CXL.CACHE access command is determined to be a CXL.CACHE write command, and the CXL.CACHE write command is sent to the CXL interface.

[0099] Please refer to Figure 10, which is a schematic diagram of the structure of the CPU provided in an embodiment of the present application. As shown in Figure 10, the CPU may include: a processor 1010, a communication interface 1020, a memory 1030 and a communication bus 1040, wherein the processor 1010, the communication interface 1020, and the memory 1030 communicate with each other through the communication bus 1040. The processor 1010 can call the logic instructions in the memory 1030 to execute the L3 level extension cache access method, which includes: responding to the L3 level cache access operation, determining that the L3 level cache to be accessed is the L3 level extension cache based on the flag bit carried in the L3 level cache access operation; SRAM is used as the memory of the L3 level extension cache, and the FPGA is connected to the SRAM; sending a CXL.CACHE access command to the CXL interface, and the CXL.CACHE access command is used to access the L3 level extension cache; the CXL interface is built into the FPGA.

[0100] In addition, the logic instructions in the above-mentioned memory 1030 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method of any one or more embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a disk or an optical disk, etc., which can store program code.

[0101] Please refer to Figure 11, which is one of the structural diagrams of a server provided in an embodiment of the present application. As shown in Figure 11, the server includes a CPU 1101 and an L3 cache expansion device 1102. CPU 1101 may be the CPU shown in Figure 10. L3 cache expansion device 1102 may be the L3 cache expansion device shown in Figure 2 or Figure 4.

[0102] In some embodiments, as shown in FIG12 , the server further includes: a CXL switch 1103 ; wherein, there are multiple CPUs 1101 , and the multiple CPUs 1101 are connected to the L3 cache extension device 1102 via the CXL switch 1103 , so that the multiple CPUs 1101 can share the L3 extended cache, so that the L3 extended cache can be used as a cache pool.

[0103] On the other hand, referring to FIG13 , the present application further provides a computer program product, the computer program product including computer-readable instructions stored on a non-volatile computer-readable storage medium, and the computer program including computer-readable instructions.

[0104] When the computer-readable instructions are executed by a computer, the computer can execute the L3 level extended cache access method for firmware applied to FPGA provided by the above method embodiment.

[0105] Alternatively, when the computer-readable instructions are executed by a computer, the computer can execute the L3 level extended cache access method applied to a CPU provided by any one or more of the above method embodiments.

[0106] On the other hand, referring to FIG13 , the present application further provides a non-volatile computer-readable storage medium having computer-readable instructions stored thereon.

[0107] When the computer-readable instructions are executed by a processor, the processor executes the L3 level extended cache access method for firmware applied to FPGA provided by any one or more of the above method embodiments.

[0108] Alternatively, when the computer-readable instructions are executed by a processor, the L3 level extended cache access method applied to the firmware of the CPU provided by any one or more of the above method embodiments is implemented.

[0109] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units. That is, they may be located in one place or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of the solutions of this embodiment. Persons of ordinary skill in the art will be able to understand and implement the present invention without inventive effort.

[0110] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, or of course, by hardware. Based on this understanding, the essence of the above technical solution or the part that contributes to the existing technology can be embodied in the form of a software product. The computer software product can be stored in a non-volatile computer-readable storage medium, such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the method described in any one or more embodiments or certain parts of the embodiments.

[0111] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in any one or more of the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application.

Claims

1. An L3 cache expansion device, characterized in that: include: A processor, a static random access memory (SRAM) and a CXL interface, wherein the SRAM serves as a memory for an L3 level extended cache; wherein the processor is connected to the SRAM, and the processor has the CXL interface built in; as well as The firmware of the processor is configured to: receive a CXL.CACHE access command sent by the CPU through the CXL interface, respond to the CXL.CACHE access command, and access the L3 extended cache.

2. The L3 cache expansion device according to claim 1, wherein: Also includes: Peripheral interface; wherein the CXL interface is connected to the peripheral interface, and the peripheral interface is a PCIe gold finger or a PCIe connector.

3. The L3 cache expansion device according to claim 1 or 2, characterized in that: The processor firmware includes: a CXL parsing module, an SRAM control module and a CXL protocol module; wherein: the CXL parsing module being configured to parse the CXL.CACHE read command to obtain a first start address and a first data length when the CXL.CACHE access command is a CXL.CACHE read command; The SRAM control module is configured to read first data of the first data length starting from the first starting address of the L3 extended cache; The CXL protocol module is configured to encapsulate the first data into a CXL packet and send the CXL packet to the CPU; The CXL parsing module is further configured to: when the CXL.CACHE access command is a CXL.CACHE write command, parse the CXL.CACHE write command to obtain a second start address, a second data length, and second data; and The SRAM control module is further configured to write the second data of the second data length starting from the second starting address of the L3 extended cache.

4. The L3 cache expansion device according to claim 3, wherein: The processor firmware also includes: The replacement algorithm module is used to select a corresponding replacement algorithm based on actual application requirements; the replacement algorithm is used to replace the data of one thread with the data of another thread.

5. The L3 cache expansion device according to claim 1 or 2, characterized in that: The bit width of the L3 extended cache is the size of a cache line.

6. The L3 cache expansion device according to claim 1, wherein: The device further comprises: A power supply is configured to supply power to the processor.

7. The L3 cache expansion device according to claim 1, wherein: The device further comprises: A complex programmable logic device (CPLD) is configured to control a power-on sequence of the processor.

8. The L3 cache expansion device according to claim 2, wherein: The peripheral interface is a PCIe connector, and the host is connected to the PCIe connector via a cable, so that the CXL interface communicates with the CPU in the host.

9. A method for accessing an L3 extended cache, characterized in that: The method is applied to the firmware of the processor, and includes: receiving a CXL.CACHE access command sent by the CPU via a CXL interface built into the processor; and In response to the CXL.CACHE access command, the L3 extended cache is accessed; SRAM serves as the memory of the L3 extended cache, and the processor is connected to the SRAM.

10. The L3 extended cache access method according to claim 9, wherein: The step of responding to the CXL.CACHE access command and accessing the L3 extended cache includes: When the CXL.CACHE access command is a CXL.CACHE read command, parsing the CXL.CACHE read command to obtain a first start address and a first data length; Reading first data of the first data length from the first starting address of the L3 extended cache; and The first data is encapsulated into a CXL packet, and the CXL packet is sent to the CPU.

11. The L3 extended cache access method according to claim 9, wherein: The step of responding to the CXL.CACHE access command and accessing the L3 extended cache includes: When the CXL.CACHE access command is a CXL.CACHE write command, parsing the CXL.CACHE write command to obtain a second start address, a second data length, and second data; and The second data of the second data length is written starting from the second starting address of the L3 extended cache.

12. The L3 extended cache access method according to claim 11, wherein: The method further includes: selecting a corresponding replacement algorithm based on actual application requirements; the replacement algorithm is used to replace data of one thread with data of another thread.

13. The L3 extended cache access method according to claim 12, wherein: The selection of a corresponding replacement algorithm based on actual application requirements includes: In response to the actual application requirement that part of the data of the first thread enters the L3 extended cache first and part of the data of the second thread enters the L3 extended cache later, a first-in-first-out algorithm is selected as the replacement algorithm.

14. A method for accessing an L3 extended cache, characterized in that: Applied to a CPU, the method includes: In response to an L3 cache access operation, determining that the L3 cache to be accessed is an L3 extended cache based on a flag bit carried in the L3 cache access operation; an SRAM is used as a memory of the L3 extended cache, and the processor is connected to the SRAM; and A CXL.CACHE access command is sent to a CXL interface, where the CXL.CACHE access command is used to access the L3 extended cache; the CXL interface is built into the processor.

15. The L3 extended cache access method according to claim 14, wherein: The sending of the CXL.CACHE access command to the CXL interface includes: Determining whether the access operation of the L3 extended cache is read or write; If the access operation to the L3 extended cache is a read operation, determining that the CXL.CACHE access command is a CXL.CACHE read command, and sending the CXL.CACHE read command to the CXL interface; and When the access operation of the L3 extended cache is a write operation, the CXL.CACHE access command is determined to be a CXL.CACHE write command, and the CXL.CACHE write command is sent to the CXL interface.

16. An L3 level extended cache access device, characterized in that: Applied to a CPU, the device comprises: a determination module, configured to respond to an L3 cache access operation and determine, based on a flag bit carried in the L3 cache access operation, that the L3 cache to be accessed is an L3 extended cache; an SRAM serving as a memory of the L3 extended cache, the processor being connected to the SRAM; and The sending module is configured to send a CXL.CACHE access command to a CXL interface, wherein the CXL.CACHE access command is used to access the L3 extended cache; the CXL interface is built into the processor.

17. A CPU, characterized in that: The method comprises a memory, a processor and computer-readable instructions stored in the memory and executable on the processor. When the processor executes the program, the steps of the L3 extended cache access method as claimed in claim 14 or 15 are implemented.

18. A server, characterized in that: include: The CPU according to claim 17 and the L3 cache expansion device according to any one of claims 1 to 7.

19. The server according to claim 18, wherein: Also includes: CXL switch; wherein, there are multiple CPUs, and the multiple CPUs are connected to the L3 cache expansion device through the CXL switch.

20. A non-volatile computer-readable storage medium, characterized in that Computer-readable instructions are stored thereon, and when the computer-readable instructions are executed by a processor, the steps of the L3 level extended cache access method as described in any one of claims 9 to 13 are implemented, or the steps of the L3 level extended cache access method as described in claim 14 or 15 are implemented.

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