Integrated circuit and manufacturing method therefor, power amplification circuit, and electronic device

Abstract

Embodiments of the present application relate to the technical field of semiconductors, and provide an integrated circuit and a manufacturing method therefor, a power amplification circuit, and an electronic device, for use in reducing parasitic capacitance and parasitic inductance and improving the performance of the integrated circuit. The integrated circuit comprises a substrate, an HEMT device, and a first matching circuit. The HEMT device comprises an epitaxial layer, a gate electrode, a first electrode, a second electrode, and a first bonding pad, wherein the gate electrode, the first electrode, the second electrode, and the first bonding pad are all located on the side of the epitaxial layer distant from the substrate, and the gate electrode is connected to the first bonding pad. The first matching circuit comprises a first capacitor, and the first capacitor is located on the side of the epitaxial layer distant from the substrate. The first capacitor comprises a first plate and a second plate which are oppositely arranged, the second plate is located on the side of the first plate distant from the substrate, the first plate of the first capacitor is grounded, and the second plate of the first capacitor is connected to the gate electrode. The integrated circuit is applied to the electronic device so as to improve the performance of the electronic device.

Description

Integrated circuit and manufacturing method thereof, power amplifier circuit and electronic equipment

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on January 31, 2024, with application number 202410142456.5 and application name “Integrated Circuit and Method for Making the Same, Power Amplifier Circuit and Electronic Device”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present application relates to the field of semiconductor technology, and in particular to an integrated circuit and a manufacturing method thereof, a power amplifier circuit and an electronic device. Background Art

[0003] Mobile communication technology, as a type of wireless communication technology, will be widely used in typical scenarios such as intelligent transportation, environmental monitoring, intelligent public facilities, remote medical diagnosis, intelligent manufacturing, smart homes, and smart living. With the development of communication technology, the requirements for electronic equipment parameters such as energy consumption, efficiency, power, and size are also increasing.

[0004] Gallium nitride (GaN) material has been widely used in communications technology due to its advantages, including wide bandwidth, high critical breakdown electric field, high electron saturation velocity, high thermal conductivity, and strong radiation resistance. When GaN devices are applied to RF applications, they are typically packaged with internal matching circuits to optimize the GaN device's input impedance and adjust the position of its second harmonic. However, the introduction of internal matching circuits increases parasitic capacitance and inductance, preventing integrated circuits (ICs) using these circuits from fully realizing their superior characteristics.

[0005] Summary of the Invention

[0006] The embodiments of the present application provide an integrated circuit and a method for manufacturing the same, a power amplifier circuit, and an electronic device for reducing parasitic capacitance and parasitic inductance and improving the performance of the integrated circuit.

[0007] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0008] In a first aspect, an integrated circuit is provided, comprising a substrate, a HEMT device, and a first matching circuit.

[0009] A HEMT device is located on the substrate. The HEMT device includes an epitaxial layer, a gate, a first electrode, a second electrode, and a first pad. The gate, the first electrode, the second electrode, and the first pad are all located on a side of the epitaxial layer away from the substrate. The gate is located between the first electrode and the second electrode and is connected to the first pad.

[0010] The first matching circuit includes a first capacitor. The first capacitor is located on a side of the epitaxial layer away from the substrate. The first capacitor includes a first plate and a second plate disposed opposite each other, the second plate being located on a side of the first plate away from the substrate. The first plate of the first capacitor is grounded, and the second plate of the first capacitor is connected to the gate.

[0011] In the integrated circuit provided in an embodiment of the present application, a HEMT device is connected to a first matching circuit. A first capacitor of the first matching circuit is disposed on the epitaxial layer of the HEMT device. The first capacitor includes a first plate and a second plate. The first plate is grounded, and the second plate is connected to the gate of the HEMT device. This eliminates the need for bonding wires between the first capacitor and the gate in the first matching circuit, minimizing parasitic inductance and capacitance between the first capacitor and the gate. This reduces parasitic capacitance and inductance within the integrated circuit, thereby improving the output power and efficiency of the integrated circuit and the consistency of its high- and low-frequency performance. Furthermore, the reduced parasitic inductance and capacitance between the first capacitor and the gate also speeds up signal transmission between the first capacitor and the gate, thereby reducing signal delay and increasing the signal transmission speed of the integrated circuit.

[0012] Furthermore, the absence of a bonding wire between the first capacitor and the gate can improve the connection stability between the first capacitor and the gate, thereby improving the operational stability of the integrated circuit. Furthermore, the absence of a bonding wire between the first capacitor and the gate can also reduce costs, shrink the integrated circuit packaging area, shorten the integrated circuit packaging cycle, and improve the integrated circuit packaging efficiency.

[0013] In some embodiments, the first pad serves as the second plate of the first capacitor. Thus, the second plate of the first capacitor is directly connected to the gate, eliminating the need for a connecting wire between the first capacitor and the gate, thereby further simplifying the structure of the integrated circuit and reducing the cost of the integrated circuit.

[0014] In some embodiments, the HEMT device further includes a second pad located on a side of the epitaxial layer away from the substrate, the gate being further connected to the second pad; and the first pad being located between the first electrode and the second pad. Thus, the first and second pads are connected in parallel, thereby reducing the total resistance across the first and second pads and improving the performance of the HEMT device. Furthermore, by providing a second pad connected to the gate, the second pad can be used to connect to other devices in the integrated circuit (e.g., other HEMT devices or components such as resistors, capacitors, and inductors). This prevents the first pad from being connected to other devices in the first matching circuit via bonding wires, which could result in etching and damage to the first plate beneath the first pad, thereby facilitating improved yield of the integrated circuit.

[0015] In some embodiments, the HEMT device further includes a third pad, the third pad being located on a side of the epitaxial layer away from the substrate and between the first electrode and the first pad; the third pad connecting the gate and the first pad.

[0016] The provision of a third pad in the HEMT device provided in the embodiments of the present application allows the first and third pads to be connected in parallel, thereby reducing the total resistance of the first and third pads and improving the performance of the HEMT device. Furthermore, the provision of a third pad connected to the gate allows the third pad to be used for connection to other devices in the integrated circuit, thereby preventing the first pad from being connected to other devices via bonding wires, which could cause etching and damage to the first plate beneath the first pad. This, in turn, helps ensure the yield of the integrated circuit.

[0017] In some embodiments, the HEMT device includes a plurality of first electrodes, the plurality of first electrodes are arranged along a first direction parallel to the substrate, and the first capacitor is located between two adjacent first electrodes.

[0018] In the embodiment of the present application, the first capacitor is disposed between two adjacent first electrodes of the HEMT device, so that the projection area of ​​the first capacitor and the HEMT device on the substrate can be small, thereby facilitating reduction in the package area of ​​the integrated circuit and facilitating miniaturization of a power amplifier using the integrated circuit.

[0019] In some embodiments, the integrated circuit includes a plurality of HEMT devices, the plurality of HEMT devices are arranged along a first direction parallel to the substrate, the first capacitor is located between two adjacent HEMT devices, and the second plate of the first capacitor is connected to the first pads of the two adjacent HEMT devices.

[0020] In the embodiment of the present application, a first capacitor is provided in a gap between two adjacent HEMT devices in a first direction, effectively utilizing the space between the two HEMT devices. Compared with a solution in which additional space is reserved for providing the first capacitor, this solution can improve the level of integration of the integrated circuit and also shorten the distance between the first capacitor and the HEMT device, thereby simplifying the connection structure between the HEMT device and the first capacitor and simplifying the structure of the integrated circuit.

[0021] In some embodiments, the first electrode serves as the first plate of the first capacitor. In this case, the projection area of ​​the first capacitor and the HEMT device on the substrate can be relatively small, thereby reducing the footprint of the integrated circuit and facilitating the miniaturization of a power amplifier using the integrated circuit provided by the embodiments of the present application.

[0022] In some embodiments, the first plate of the first capacitor is connected to the first electrode.

[0023] In some embodiments, the first plate of the first capacitor includes a main portion and an extension portion that are perpendicular to each other, wherein the extension portion connects the main portion and the first electrode. At least a portion of the projection of the main portion on the substrate overlaps with a projection of the second plate on the substrate. At least a portion of the projection of the extension portion on the substrate lies outside the projection of the second plate on the substrate.

[0024] In some embodiments, the integrated circuit further comprises a conductive layer located on a side of the substrate distal from the HEMT device. The conductive layer extends through the substrate and the epitaxial layer and is connected to the first plate of the first capacitor. In the integrated circuit provided in the embodiments of the present application, the first plate and the first electrode are interconnected by the conductive layer and are grounded through the conductive layer, thereby shortening the signal transmission path, increasing the signal transmission rate, and reducing impedance during signal transmission.

[0025] In some embodiments, the first electrode plate of the first capacitor includes a first sublayer and a second sublayer arranged in a stacked manner, the second sublayer is located on a side of the first sublayer away from the substrate, and the first sublayer is in direct contact with the second sublayer; the first sublayer is arranged in the same layer as the first electrode, and the material of the first sublayer is the same as the material of the first electrode.

[0026] In the integrated circuit provided in the embodiments of the present application, the first plate includes a first sublayer and a second sublayer stacked together, which can increase the total thickness of the first plate of the first capacitor, thereby increasing the cross-sectional area of ​​the first plate, thereby reducing the resistance of the first plate and improving the performance of the first capacitor. Furthermore, the greater thickness of the first plate of the first capacitor also helps to increase the process window, preventing the first plate from being damaged or punctured during the preparation of the second back via, thereby protecting the first plate and ensuring the yield of the integrated circuit.

[0027] At the same time, the first sublayer is arranged in the same layer as the first electrode, and the material of the first sublayer is the same as the material of the first electrode, so that during the preparation process of the integrated circuit, the first sublayer can be prepared synchronously with the first electrode, which is beneficial to reduce the preparation cost of the integrated circuit, simplify the preparation process of the integrated circuit, and improve the preparation efficiency of the integrated circuit.

[0028] In some embodiments, the HEMT device further includes a first inductor, the first inductor being located on a side of the epitaxial layer away from the substrate, and the first inductor connecting the gate and the first pad.

[0029] In some embodiments, the HEMT device includes multiple gates arranged along a first direction parallel to the substrate, and the first inductor is connected to the multiple gates. This can reduce the number of first inductors in the HEMT device, thereby simplifying the HEMT device structure and reducing the manufacturing cost of the HEMT device. Furthermore, the inductance of the first inductor can be increased.

[0030] In some embodiments, the first inductor includes a first routing segment and a second routing segment, the projection of the first routing segment on the substrate intersecting with the projection of the second routing segment on the substrate; the second routing segment includes a first sub-segment, a second sub-segment, and a third sub-segment connected in sequence, the first sub-segment and the second sub-segment both including a first conductive pattern and a second conductive pattern stacked together, the second conductive pattern being located on a side of the first conductive pattern away from the substrate and connected to the first conductive pattern; one of the first routing segment and the third sub-segment includes the first conductive pattern, and the other includes the second conductive pattern.

[0031] In an embodiment of the present application, the first inductor includes a multi-turn coil. By setting a first routing segment and a second routing segment, one end of the innermost coil in the multi-turn coil of the first inductor can be led out, so that one end of the innermost coil in the multi-turn coil can be connected to the gate or the first pad.

[0032] In some embodiments, the first conductive pattern is disposed on the same layer as the first plate of the first capacitor, and the second conductive pattern is disposed on the same layer as the first pad.

[0033] In this way, the first conductive pattern can be fabricated simultaneously with the first inductor, and the second conductive pattern can be fabricated simultaneously with the first pad, thereby reducing the cost of integrated circuit fabrication, simplifying the integrated circuit fabrication process, and improving integrated circuit fabrication efficiency. Furthermore, the second conductive pattern and the first pad are arranged on the same layer, which further simplifies the connection structure between the first inductor and the first pad, simplifies the structure of the HEMT device, further reducing the cost of integrated circuit fabrication and shrinking the integrated circuit's footprint.

[0034] In some embodiments, the first matching circuit further includes a second capacitor and a second inductor, the second capacitor and the second inductor are both located outside the substrate, and the second inductor connects the second capacitor and the first capacitor.

[0035] In some embodiments, the first matching circuit further includes a second capacitor and a second inductor, and the second capacitor and the second inductor are both located on the side of the epitaxial layer away from the substrate; the second capacitor includes a third plate and a fourth plate arranged opposite to each other, and the fourth plate is located on the side of the third plate away from the substrate; the third plate of the second capacitor is grounded, and the fourth plate of the second capacitor is connected to the second plate of the first capacitor through the second inductor.

[0036] In this way, the first capacitor, the second capacitor and the second inductor in the first matching circuit are all arranged on the epitaxial layer. Not only is there no need to set a bonding wire between the first capacitor and the gate, but there is also no need to set a bonding wire between the second capacitor and the first capacitor. This can make the parasitic inductance and parasitic capacitance between the first capacitor and the gate smaller, and the parasitic inductance and parasitic capacitance between the second capacitor and the first capacitor smaller. The parasitic capacitance and parasitic inductance in the integrated circuit are smaller, which can further improve the output power and efficiency of the integrated circuit and improve the consistency of the high and low frequency performance of the integrated circuit.

[0037] Moreover, the parasitic inductance and parasitic capacitance between the first capacitor and the gate are small, and the parasitic inductance and parasitic capacitance between the second capacitor and the first capacitor are also small, which can also make the signal transmission between the first capacitor and the gate and between the first capacitor and the second capacitor faster, thereby improving the signal delay and increasing the signal transmission speed of the integrated circuit.

[0038] At the same time, the first capacitor, the second capacitor and the second inductor in the first matching circuit are all arranged on the epitaxial layer, which can also improve the connection stability between the first capacitor and the gate, between the first capacitor and the second inductor, and between the second capacitor and the second inductor, thereby improving the use stability of the integrated circuit.

[0039] Of course, there is no need to set a bonding wire between the first capacitor and the gate, and there is no need to set a bonding wire between the second capacitor and the first capacitor. It can also reduce costs, reduce the packaging area of ​​the integrated circuit, shorten the packaging cycle of the integrated circuit, and improve the packaging efficiency of the integrated circuit.

[0040] In some embodiments, the third plate of the second capacitor is disposed on the same layer as the first plate of the first capacitor, and the fourth plate of the second capacitor is disposed on the same layer as the second plate of the first capacitor.

[0041] In this way, during the preparation process of the first matching circuit, the first plate of the first capacitor and the third plate of the second capacitor can be prepared simultaneously, and the second plate of the first capacitor and the fourth plate of the second capacitor can be prepared simultaneously, thereby simplifying the preparation process of the first matching circuit, improving the preparation efficiency of the first matching circuit, and reducing the preparation cost of the first matching circuit.

[0042] In some embodiments, the HEMT device further comprises a fourth pad, the fourth pad being located on a side of the epitaxial layer away from the substrate; the first electrode being located between the first pad and the fourth pad; and the fourth pad being connected to the second electrode. The integrated circuit further comprises a second matching circuit, the second matching circuit comprising a third capacitor; the third capacitor comprising a fifth plate and a sixth plate disposed opposite each other, the sixth plate being located on a side of the fifth plate away from the substrate; the fifth plate of the third capacitor being grounded, and the sixth plate of the third capacitor being connected to the second electrode.

[0043] In an embodiment of the present application, a HEMT device is connected to a second matching circuit. The third capacitor of the second matching circuit is disposed on the epitaxial layer of the HEMT device. The third capacitor includes a fifth plate and a sixth plate. The fifth plate is grounded, and the sixth plate is connected to the second electrode of the HEMT device. This eliminates the need for bonding wires between the third capacitor and the second electrode in the second matching circuit, minimizing parasitic inductance and capacitance between the third capacitor and the second electrode. This reduces parasitic capacitance and inductance within the integrated circuit, thereby improving the output power and efficiency of the integrated circuit and the consistency of its high- and low-frequency performance. Furthermore, the reduced parasitic inductance and capacitance between the third capacitor and the second electrode also speeds up signal transmission between the third capacitor and the second electrode, thereby reducing signal delay and increasing the signal transmission speed of the integrated circuit.

[0044] Furthermore, the absence of a bonding wire between the third capacitor and the second electrode improves the connection stability between the third capacitor and the second electrode, thereby improving the operational stability of the integrated circuit. Furthermore, the absence of a bonding wire between the third capacitor and the second electrode also reduces costs, reduces the integrated circuit packaging area, shortens the integrated circuit packaging cycle, and improves the integrated circuit packaging efficiency.

[0045] In a second aspect, a method for preparing an integrated circuit is provided, which comprises: forming an epitaxial layer on a substrate; forming a gate, a first electrode, a second electrode, a first pad and a first capacitor on a side of the epitaxial layer away from the substrate; the gate is located between the first electrode and the second electrode, and the gate is connected to the first pad; the first capacitor comprises a first plate and a second plate arranged opposite to each other, the second plate is located on a side of the first plate away from the substrate, the first plate of the first capacitor is grounded, and the second plate of the first capacitor is connected to the gate.

[0046] In a third aspect, a power amplifier circuit is provided. The power amplifier circuit includes a packaging structure and an integrated circuit as described in any of the above embodiments, wherein the integrated circuit is packaged inside the packaging structure.

[0047] In a fourth aspect, an electronic device is provided, comprising a power amplifier and an antenna, wherein the power amplifier is configured to amplify a radio frequency signal and output the amplified signal to the antenna for outward radiation, and the power amplifier comprises the power amplifier circuit described in the above embodiment.

[0048] Among them, the technical effects brought about by any design method in the second aspect and the fourth aspect can refer to the technical effects brought about by different design methods in the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] To more clearly illustrate the technical solutions of this application, the following briefly introduces the drawings required for use in some embodiments of this application. Obviously, the drawings described below are only drawings of some embodiments of this application, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of this application.

[0050] FIG1 is a schematic structural diagram of an electronic device provided in an embodiment of the present application;

[0051] FIG2 is a schematic structural diagram of another electronic device provided in an embodiment of the present application;

[0052] FIG3 is a schematic structural diagram of a power amplifier circuit provided in an embodiment of the present application;

[0053] FIG4 is a schematic top view of a power amplifier circuit provided in an embodiment of the present application;

[0054] FIG5 is a schematic top view of an integrated circuit provided in an embodiment of the present application;

[0055] FIG6 is a schematic cross-sectional view of the integrated circuit shown in FIG5 taken at AA′;

[0056] FIG7 is a schematic cross-sectional view of the integrated circuit shown in FIG5 taken at BB′;

[0057] FIG8 is a schematic cross-sectional view of the integrated circuit shown in FIG5 taken at CC';

[0058] FIG9 is a schematic top view of another integrated circuit provided in an embodiment of the present application;

[0059] FIG10 is a schematic top view of another integrated circuit provided in an embodiment of the present application;

[0060] FIG11 is a schematic top view of another integrated circuit provided in an embodiment of the present application;

[0061] FIG12 is a schematic cross-sectional view of the integrated circuit shown in FIG11 taken at DD′;

[0062] FIG13 is a schematic top view of another integrated circuit provided in an embodiment of the present application;

[0063] FIG14 is a schematic top view of another integrated circuit provided in an embodiment of the present application;

[0064] FIG15 is a schematic cross-sectional view of the integrated circuit shown in FIG14 taken along line EE′;

[0065] FIG16 is a schematic top view of another integrated circuit provided in an embodiment of the present application;

[0066] FIG17 is a schematic top view of another integrated circuit provided in an embodiment of the present application;

[0067] FIG18 is a schematic top view of another integrated circuit provided in an embodiment of the present application;

[0068] FIG19 is a schematic top view of another integrated circuit provided in an embodiment of the present application;

[0069] FIG20 is a schematic cross-sectional view of the integrated circuit shown in FIG19 taken along line H-H';

[0070] FIG21 is a schematic top view of another integrated circuit provided in an embodiment of the present application;

[0071] FIG22 is a schematic cross-sectional view of the integrated circuit shown in FIG21 taken along line II′;

[0072] FIG23 is a schematic top view of another integrated circuit provided in an embodiment of the present application;

[0073] FIG24 is a schematic top view of another integrated circuit provided in an embodiment of the present application;

[0074] FIG25 is a schematic top view of another integrated circuit provided in an embodiment of the present application;

[0075] FIG26 is a schematic top view of another integrated circuit provided in an embodiment of the present application;

[0076] FIG27 is a schematic top view of a first inductor or a second inductor provided in an embodiment of the present application;

[0077] FIG28 is a schematic cross-sectional view of the first inductor or the second inductor shown in FIG27 at line J-J';

[0078] FIG29 is a schematic cross-sectional view of the first inductor or the second inductor shown in FIG27 at line K-K';

[0079] FIG30 is a schematic top view of another integrated circuit provided in an embodiment of the present application;

[0080] FIG31 is a schematic top view of another integrated circuit provided in an embodiment of the present application;

[0081] FIG32 is a schematic cross-sectional view of the integrated circuit shown in FIG31 taken at position N-N';

[0082] FIG33 is a schematic top view of another integrated circuit provided in an embodiment of the present application;

[0083] FIG34 is a schematic cross-sectional view of the integrated circuit shown in FIG33 taken at FF′;

[0084] Figure 35 is a preparation flow chart of a method for preparing an integrated circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0085] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0086] In the following embodiments of the present application, the terms "first," "second," etc. are used for convenience of description only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0087] In the embodiments of the present application, “upper”, “lower”, “left” and “right” are not limited to being defined relative to the orientations of the components schematically placed in the drawings. It should be understood that these directional terms may be relative concepts. They are used for relative description and clarification, and may change accordingly according to changes in the orientations of the components in the drawings.

[0088] In the embodiments of the present application, unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0089] When describing some embodiments, the term "coupled" and its derivatives may be used. For example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents herein.

[0090] In the embodiments of the present application, exemplary embodiments are described with reference to cross-sectional views and / or plan views and / or equivalent circuit diagrams as idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0091] The present application provides an electronic device, which may be, for example, a lidar driver, a laser, a detector, a radar, or a 5G (fifth generation mobile network) communication device, and may also be a network device such as a base station. The electronic device may also be a device such as a power amplifier used in the above-mentioned electronic devices. The present application does not impose any particular restrictions on the specific form of the above-mentioned electronic device.

[0092] In some examples, the electronic device provided in the embodiments of the present application may be a mobile phone. Figure 1 shows a schematic structural diagram of a mobile phone 100. The mobile phone 100 may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, an earphone jack 170D, a sensor module 180, a camera 190, and a display screen 191.

[0093] It should be understood that the structures illustrated in the embodiments of the present application do not constitute a specific limitation on the mobile phone 100. In other embodiments of the present application, the mobile phone 100 may include more or fewer components than shown, or may combine or separate certain components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0094] The processor 110 may include one or more processing units. For example, the processor 110 may include an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU). The different processing units may be independent devices or integrated into one or more processors.

[0095] Processor 110 may also include a memory for storing instructions and data. In some embodiments, the memory in processor 110 is a cache memory. This memory can store instructions or data that have just been used or are being recycled by processor 110. If processor 110 needs to use the same instruction or data again, it can directly access the memory. This avoids duplicate accesses, reduces processor 110 latency, and thus improves system efficiency.

[0096] In some embodiments, the processor 110 may include one or more interfaces. The interfaces may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a universal serial bus (USB) interface.

[0097] The charging management module 140 is configured to receive charging input from a charger. The charger can be either a wireless charger or a wired charger. In some wired charging embodiments, the charging management module 140 can receive charging input from the wired charger via the USB interface 130. In some wireless charging embodiments, the charging management module 140 can receive wireless charging input via the wireless charging coil of the mobile phone 100. While the charging management module 140 is charging the battery 142, it can also provide power to the mobile phone through the power management module 141.

[0098] The power management module 141 is used to connect the battery 142, the charging management module 140, and the processor 110. The power management module 141 receives input from the battery 142 and / or the charging management module 140, and provides power to the processor 110, the internal memory 121, the display 191, the camera 190, and the wireless communication module 160. The power management module 141 can also be used to monitor parameters such as battery capacity, battery cycle count, and battery health status (leakage, impedance). In some other embodiments, the power management module 141 can also be set in the processor 110. In other embodiments, the power management module 141 and the charging management module 140 can also be set in the same device.

[0099] The wireless communication function of the mobile phone 100 can be implemented through the antenna 1, the antenna 2, the mobile communication module 150, the wireless communication module 160, the modem processor and the baseband processor.

[0100] Antenna 1 and Antenna 2 are used to transmit and receive electromagnetic wave signals. Each antenna in mobile phone 100 can be used to cover a single or multiple communication frequency bands. Different antennas can also be reused to improve antenna utilization. For example, antenna 1 can be reused as a diversity antenna for a wireless local area network. In other embodiments, the antennas can be used in conjunction with a tuning switch.

[0101] The mobile communication module 150 can provide solutions for wireless communications including 2G / 3G / 4G / 5G applied on the mobile phone 100. The mobile communication module 150 may include one or more filters, switches, power amplifiers, low noise amplifiers (LNA), etc. The mobile communication module 150 can receive electromagnetic waves from the antenna 1, and filter, amplify and process the received electromagnetic waves, and transmit them to the modulation and demodulation processor for demodulation. The mobile communication module 150 can also amplify the signal modulated by the modulation and demodulation processor, and convert it into electromagnetic waves for radiation through the antenna 1. In some embodiments, at least some of the functional modules of the mobile communication module 150 can be set in the processor 110. In some embodiments, at least some of the functional modules of the mobile communication module 150 can be set in the same device as at least some of the modules of the processor 110.

[0102] The modem processor may include a modulator and a demodulator. The modulator is used to modulate the low-frequency baseband signal to be transmitted into a medium-high frequency signal. The demodulator is used to demodulate the received electromagnetic wave signal into a low-frequency baseband signal. The demodulator then transmits the demodulated low-frequency baseband signal to the baseband processor for processing. After being processed by the baseband processor, the low-frequency baseband signal is passed to the application processor. The application processor outputs a sound signal through an audio device (not limited to the speaker 170A, the receiver 170B, etc.) or displays an image or video through the display screen 191. In some embodiments, the modem processor may be an independent device. In other embodiments, the modem processor may be independent of the processor 110 and be set in the same device as the mobile communication module 150 or other functional modules.

[0103] The wireless communication module 160 can provide wireless communication solutions including wireless local area networks (WLAN) (such as wireless fidelity (Wi-Fi) networks), Bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), infrared (IR), etc., which are applied to the mobile phone 100. The wireless communication module 160 can be one or more devices that integrate one or more communication processing modules. The wireless communication module 160 receives electromagnetic waves via the antenna 2, frequency modulates and filters the electromagnetic wave signals, and sends the processed signals to the processor 110. The wireless communication module 160 can also receive the signal to be sent from the processor 110, frequency modulate it, amplify it, and convert it into electromagnetic waves for radiation through the antenna 2.

[0104] In some embodiments, the antenna 1 of the mobile phone 100 is coupled to the mobile communication module 150, and the antenna 2 is coupled to the wireless communication module 160, so that the mobile phone 100 can communicate with the network and other devices through wireless communication technology. The wireless communication technology may include global system for mobile communications (GSM), general packet radio service (GPRS), code division multiple access (CDMA), wideband code division multiple access (WCDMA), time-division code division multiple access (TD-SCDMA), long term evolution (LTE), BT, GNSS, WLAN, NFC, FM, and / or IR technology. The GNSS may include a global positioning system (GPS), a global navigation satellite system (GLONASS), a Beidou navigation satellite system (BDS), a quasi-zenith satellite system (QZSS) and / or a satellite based augmentation system (SBAS).

[0105] Mobile phone 100 implements display functions through a GPU, display screen 191, and an application processor. The GPU is a microprocessor for image processing that connects display screen 191 and the application processor. The GPU is used to perform mathematical and geometric calculations for graphics rendering. Processor 110 may include one or more GPUs that execute program instructions to generate or modify display information.

[0106] The display screen 191 is used to display images, videos, etc. The display screen 191 includes a display panel. The display panel can be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode or an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), a Miniled, a MicroLed, a Micro-oLed, a quantum dot light-emitting diode (QLED), etc. In some embodiments, the mobile phone 100 may include one or N display screens 191, where N is a positive integer greater than 1. The mobile phone 100 can implement a shooting function through an ISP, a camera 190, a video codec, a GPU, a display screen 191, and an application processor.

[0107] The ISP processes data fed back by camera 190. For example, when taking a photo, the shutter is opened, and light is transmitted through the lens to the camera's photosensitive element. The light signal is converted into an electrical signal, which is then passed to the ISP for processing and transformed into a visible image. The ISP can also perform algorithmic optimization for image noise, brightness, and skin tone. It can also optimize parameters such as exposure and color temperature of the captured scene. In some embodiments, the ISP can be located within camera 190.

[0108] The camera 190 is used to capture still images or videos. The object generates an optical image through the lens and projects it onto the photosensitive element. The photosensitive element can be a charge coupled device (CCD) or a complementary metal-oxide-semiconductor (CMOS) phototransistor. The photosensitive element converts the light signal into an electrical signal, and then passes the electrical signal to the ISP to be converted into a digital image signal. The ISP outputs the digital image signal to the DSP for processing. The DSP converts the digital image signal into an image signal in a standard RGB, YUV or other format. In some embodiments, the mobile phone 100 may include 1 or N cameras 190, where N is a positive integer greater than 1.

[0109] The external memory interface 120 can be used to connect an external memory card, such as a Micro SD card, to expand the storage capacity of the mobile phone 100. The external memory card communicates with the processor 110 through the external memory interface 120 to implement data storage functions. For example, files such as music and videos can be stored on the external memory card.

[0110] The internal memory 121 can be used to store one or more computer programs, each of which includes instructions. The processor 110 can execute the instructions stored in the internal memory 121, thereby enabling the mobile phone 100 to perform various functional applications and data processing. The internal memory 121 may include a program storage area and a data storage area. The program storage area may store an operating system; the program storage area may also store one or more application programs (such as a gallery, contacts, etc.). The data storage area may store data created during the use of the mobile phone 100 (such as photos, contacts, etc.). In addition, the internal memory 121 may include high-speed random access memory and non-volatile memory, such as one or more disk storage devices, flash memory devices, universal flash storage (UFS), etc. In other embodiments, the processor 110 executes instructions stored in the internal memory 121 and / or instructions stored in a memory provided in the processor, thereby enabling the mobile phone 100 to perform various functional applications and data processing.

[0111] The mobile phone 100 can implement audio functions such as music playback and recording through the audio module 170, the speaker 170A, the receiver 170B, the microphone 170C, the headphone jack 170D, and the application processor.

[0112] The audio module 170 is used to convert digital audio information into analog audio signal output, and is also used to convert analog audio input into digital audio signals. The audio module 170 can also be used to encode and decode audio signals. In some embodiments, the audio module 170 can be provided in the processor 110, or some functional modules of the audio module 170 can be provided in the processor 110.

[0113] The speaker 170A, also called a "horn," is used to convert audio electrical signals into sound signals. The mobile phone 100 can listen to music or make hands-free calls through the speaker 170A.

[0114] The receiver 170B, also called the "earpiece", is used to convert audio electrical signals into sound signals. When the mobile phone 100 receives a call or a voice message, the voice can be heard by placing the receiver 170B close to the ear.

[0115] Microphone 170C, also known as "microphone" or "microphone", is used to convert sound signals into electrical signals. When making a call or sending a voice message, the user can speak by putting their mouth close to the microphone 170C to input the sound signal into the microphone 170C. The mobile phone 100 can be provided with one or more microphones 170C. In other embodiments, the mobile phone 100 can be provided with two microphones 170C, which can not only collect sound signals but also realize noise reduction function. In other embodiments, the mobile phone 100 can also be provided with three, four or more microphones 170C to realize sound signal collection, noise reduction, and identification of sound sources, and realize directional recording function, etc.

[0116] The headphone jack 170D is used to connect a wired headphone and can be the USB interface 130 or a 3.5mm open mobile terminal platform (OMTP) standard interface or a cellular telecommunications industry association of the USA (CTIA) standard interface.

[0117] The sensor module 180 may include a pressure sensor, a gyro sensor, an air pressure sensor, a magnetic sensor, an acceleration sensor, a distance sensor, a proximity light sensor, a fingerprint sensor, a temperature sensor, a touch sensor, an ambient light sensor, a bone conduction sensor, and the like.

[0118] In the embodiments of the present application, the touch sensor is also referred to as a "touch device". The touch sensor can be provided on the display screen 191, and the touch sensor and the display screen 191 form a touch screen, also referred to as a "touch screen". The touch sensor is used to detect touch operations acting on or near it. The touch sensor can transmit the detected touch operation to the application processor to determine the type of touch event. Visual output related to the touch operation can be provided through the display screen. In other embodiments, a touch panel having a touch sensor array formed by a plurality of touch sensors can be provided in an external form on the surface of the display panel. In other embodiments, the touch sensor can also be located at a different position from the display screen 191. In the embodiments of the present application, there is no limitation on the form of the touch sensor, for example, it can be a device such as a capacitor or a piezoresistor.

[0119] In addition, the mobile phone 100 may further include one or more components such as buttons, a motor, an indicator, and a subscriber identification module (SIM) card interface, and the embodiments of the present application do not impose any limitation on this.

[0120] In other embodiments, the electronic device provided in the embodiments of the present application may be a 5G base station. The 5G base station may be divided into different architectures, such as baseband unit (BBU)-active antenna unit (AAU), centralized unit-distributed unit (CU-DU)-AAU, BBU-remote radio unit (RRU)-antenna, CU-DU-RRU-Antenna, and integrated 5G node base station (gNB).

[0121] Figure 2 shows a base station 200 with a BBU-RRU architecture. The base station 200 may include a BBU 210, an RRU 220, and an antenna 230. The BBU 210 and the RRU 220 are connected via optical fiber, and the interface between the two is based on the open common public radio interface (CPRI) and the open base station architecture initiative (OBSAI). The BBU 210 processes the generated baseband signal through the RRU 220 and sends it to the antenna 230 for transmission. The RRU 220 includes a digital intermediate frequency module 221, a transceiver module 222, a power amplifier 223 (power amplifier, PA), and a filter 224. The digital intermediate frequency module 221 is used for modulation and demodulation, digital up and down conversion, digital to analog conversion (D / A), etc. of the baseband signal transmitted via optical fiber to form an intermediate frequency signal. The transceiver module 222 is used to complete the conversion of the intermediate frequency signal to the radio frequency signal. The power amplifier 223 is used to amplify the low-power radio frequency signal. The filter 224 is used to filter the radio frequency signal and then transmit the radio frequency signal through the antenna 230 .

[0122] The embodiments of the present application also provide a power amplifier circuit that can be applied to the power amplifier of the mobile communication module 150 or the wireless communication module 160 shown in Figure 1, or to the power amplifier of the RRU 220 in the base station 200 shown in Figure 2. Of course, the specific application scenarios are not limited to the mobile phone 100 shown in Figure 1 or the base station 200 shown in Figure 2. It is understood that any of the above-mentioned electronic devices that need to use the power amplifier circuit in the power amplifier to amplify the signal fall within the application scenarios of the embodiments of the present application.

[0123] As shown in FIG. 3 , the power amplifier circuit 300 may include an integrated circuit 310 and a packaging structure 320 , wherein the integrated circuit 310 is packaged inside the packaging structure 320 .

[0124] Continuing with FIG3 , package structure 320 may include a heat sink substrate 321. To improve the conductivity and heat dissipation of heat sink substrate 321, heat sink substrate 321 may be made of a composite material, such as a laminated structure of copper (Cu), molybdenum (Mo), and copper. Integrated circuit 310 is bonded to heat sink substrate 321 using sintered silver or directly soldered.

[0125] In addition, the package structure 320 may further include a package housing 322, which is bonded to the heat sink substrate 321 via an insulating adhesive. The integrated circuit 310 is disposed in the space enclosed by the package housing 322 and the heat sink substrate 321. The power amplifier circuit 300 also includes a pin 330, one end of which is exposed from the package structure 320 for connection to other circuits.

[0126] The integrated circuit 310 may include at least one transistor, and a portion of the transistor's electrodes (e.g., source S) are electrically connected to the heat dissipation substrate 321 to achieve grounding of the source S. A portion of the transistor's electrodes (e.g., drain D and gate G) are bonded to a pin 330 via a wire 340. The pin 330 is disposed on an insulating layer (e.g., insulating ceramic), which is bonded to the heat dissipation substrate 321 via an insulating adhesive.

[0127] A high electron mobility transistor (HEMT) is a semiconductor device that is widely used as a transistor in integrated circuit 310 due to its advantages such as high breakdown electric field, high channel electron concentration, high electron mobility, and high temperature stability. The following is a schematic illustration of an integrated circuit provided in an embodiment of the present application including a HEMT device.

[0128] As shown in Figure 4, to improve the output power and drain efficiency of the integrated circuit, as well as the consistency of its high- and low-frequency performance, the integrated circuit may further include an internal matching circuit connected to the HEMT device. The internal matching circuit may include components such as capacitors (e.g., capacitors C1 and C2) and inductors (e.g., inductors L1, L2, L3, and Ld).

[0129] On the one hand, installing an internal matching circuit can optimize input impedance, achieving better device performance. For example, when performing parameter testing on an integrated circuit without an internal matching circuit, its reflection coefficient (gamma value) is 0.9. However, when an internal matching circuit is installed, the gamma value is 0.56. A gamma value of 0.9 results in high losses and poor broadband characteristics. On the other hand, a gamma value of 0.56 results in low losses and better broadband characteristics. Furthermore, installing an internal matching circuit can adjust the position of the input second harmonic, optimizing device performance.

[0130] However, because the internal matching circuit and HEMT device are independently configured, bonding wires are required to connect the HEMT device to the internal matching circuit. This bonding wire increases parasitic inductance, and the longer the bond wire, the greater the parasitic inductance within the integrated circuit, which in turn affects the frequency characteristics of the integrated circuit. Furthermore, parasitic capacitance is easily generated where the bond wires overlap with other leads within the integrated circuit. The presence of parasitic inductance and capacitance severely impacts the performance of the integrated circuit.

[0131] Based on this, as shown in Figures 5 to 7, an embodiment of the present application provides an integrated circuit 310. Figure 5 shows a top view of an integrated circuit 310 provided in an embodiment of the present application. Figure 6 shows a schematic cross-sectional view of the integrated circuit 310 shown in Figure 5 taken at line AA'. Figure 7 shows a schematic cross-sectional view of the integrated circuit 310 shown in Figure 5 taken at line BB'.

[0132] Integrated circuit 310 includes a substrate 10, a HEMT device 20, and a first matching circuit 30. As shown in FIG6 , HEMT device 20 is located on substrate 10 and includes an epitaxial layer 21, a gate 22, a first electrode 23, a second electrode 24, and a first pad 25. Gate 22, first electrode 23, second electrode 24, and first pad 25 are all located on the side of epitaxial layer 21 away from substrate 10. Gate 22 is located between first electrode 23 and second electrode 24 and is connected to first pad 25.

[0133] As shown in Figures 5 and 6, the gate 22, the first electrode 23, and the second electrode 24 can be alternately arranged along a first direction X parallel to the substrate 10. The first pad 25 can extend along the first direction X. The first electrode 23, the second electrode 24, and the gate 22 can all extend along a second direction Y parallel to the substrate 10. The first direction X intersects the second direction Y. In the second direction Y, the first electrode 23 and the second electrode 24 are both located on one side of the first pad 25.

[0134] It is understood that the first direction X is not limited to a single plane parallel to the substrate 10, and the second direction Y is not limited to a single plane parallel to the substrate 10. The first direction X and the second direction Y can exist in any plane parallel to the substrate 10, and the first direction X and the second direction Y intersect. Figure 5 illustrates an example in which the first direction X and the second direction Y are perpendicular to each other.

[0135] For example, the material of the substrate 10 may include silicon carbide (SiC), silicon (Si), sapphire, diamond, etc.

[0136] In some examples, the epitaxial layer 21 may include a stacked channel layer and a barrier layer, with the barrier layer located on a side of the channel layer away from the substrate. The channel layer and the barrier layer may be made of different materials, thereby forming a heterojunction and generating a two-dimensional electron gas through polarization.

[0137] The material of the channel layer may include one or more of GaN, AlGaN, InAlN (indium aluminum nitride), AlN (aluminum nitride), and ScAlN (scandium aluminum nitride). The material of the barrier layer may include one or more of GaN, AlGaN, InAlN, AlN, and ScAlN.

[0138] In other examples, the epitaxial layer 21 may include a nucleation layer, a buffer layer, a channel layer, and a barrier layer, which are sequentially spaced away from the substrate 10. The provision of the nucleation layer facilitates the growth of the upper epitaxial material (e.g., the material of the buffer layer) and improves the quality of the epitaxial layer 21. The provision of the buffer layer can, on the one hand, alleviate stress in the epitaxial layer 21, ensuring the structural stability of the HEMT device, and, on the other hand, improve the breakdown resistance of the HEMT device, ensuring the performance of the HEMT device.

[0139] For example, the material of the nucleation layer may include one or more of GaN, AlGaN, and AlN. The material of the buffer layer may include AlGaN and / or AlN. For example, the buffer layer may include AlGaN, and the Al content in the AlGaN may decrease with increasing thickness. For another example, the buffer layer may include AlGaN and AlN, in which case the buffer layer may have a superlattice structure.

[0140] The gate 22, first electrode 23, and second electrode 24 are located on the epitaxial layer 21. The gate 22 forms a Schottky contact with the epitaxial layer 21, while the first electrode 23 and second electrode 24 each form an ohmic contact with the epitaxial layer 21. When the HEMT device 20 is in operation, the first electrode 23 and second electrode 24, under the influence of an electric field, enable the two-dimensional electron gas (2DEG) to flow within the channel layer between the first electrode 23 and second electrode 24. Conductivity between the first electrode 23 and second electrode 24 occurs at the 2DEG in the channel layer. Along a first direction X, the gate 22 is located between the first electrode 23 and second electrode 24, enabling or blocking the flow of the 2DEG, thereby controlling the conduction or cutoff of the HEMT device.

[0141] In some examples, the first electrode 23 can be a source electrode, and the second electrode 24 can be a drain electrode. In other examples, the first electrode 23 can be a drain electrode, and the second electrode 24 can be a source electrode. The following embodiments of this application are described using the example of the first electrode 23 being a source electrode and the second electrode 24 being a drain electrode.

[0142] In some examples, as shown in FIG5 , the HEMT device 20 may include a plurality of gates 22 , a plurality of first electrodes 23 , and a plurality of second electrodes 24 . The plurality of gates 22 , the plurality of first electrodes 23 , and the plurality of second electrodes 24 are all arranged along a first direction X. When the HEMT device 20 includes a plurality of gates 22 , the plurality of gates 22 are all connected to the first pad 25 .

[0143] 6 , the HMET device 20 may further include a field plate (FP) 26, which is located on a side of the gate 22 away from the substrate 10. In the first direction X, an edge of a projection of the field plate 26 on the substrate 10 is closer to the second electrode 24 than an edge of a projection of the gate 22 on the substrate 10.

[0144] The field plate 26 may be made of any conductive material, may be in a suspended state, and not loaded with any signal, and may be electrically connected to the gate 22.

[0145] When the HEMT device 20 is in operation, an electric field is generated between the gate 22 and the second electrode 24. The electric field is concentrated at the sharp corner of the gate 22 near the second electrode 24, which can easily cause material breakdown (irreversible physical damage) in the epitaxial layer 21, leading to HEMT device failure. By providing a field plate 26 on the side of the gate 22 away from the substrate 10, the field plate 26 effectively extends the gate 22 toward the second electrode 24, thereby changing the electric field distribution between the gate 22 and the second electrode 24. The electric field concentration is directed to the sharp corner of the field plate 26 near the second electrode 24, rather than at the sharp corner of the gate 22 near the second electrode 24. This effectively reduces the electric field strength on the side of the gate 22 near the second electrode 24.

[0146] Although the electric field is concentrated at one end of the field plate 26 close to the second pole 24, due to the spacing between the field plate 26 and the epitaxial layer 21 in the third direction Z perpendicular to the substrate 10, the material of the epitaxial layer 21 is not easily broken down at the position of the epitaxial layer 21 close to the second pole 24, thereby increasing the breakdown voltage of the HEMT device 20 and improving the reliability of the HEMT device 20.

[0147] In some examples, as shown in FIG6 , the HEMT device 20 may further include a first thickened electrode 231 and a second thickened electrode 241. The first thickened electrode 231 is located on a side of the first electrode 23 away from the substrate 10 and is in contact with the first electrode 23. The second thickened electrode 241 is located on a side of the second electrode 24 away from the substrate 10 and is in contact with the second electrode 24.

[0148] In the embodiment of the present application, there is no limitation on the material of the first thickened electrode 231 and the material of the second thickened electrode 241. For example, the material of the first thickened electrode 231 can be the same as the material of the first electrode 23, and the material of the second thickened electrode 241 can be the same as the material of the second electrode 24.

[0149] By providing the first thickened electrode 231 on the first electrode 23 and the second thickened electrode 241 on the second electrode 24, the thickness of the first electrode 23 and the second electrode 24 are increased, thereby facilitating a reduction in the resistance of the first electrode 23 and the second electrode 24 and improving the current conducting capability of the HEMT device 20.

[0150] In some examples, as shown in FIG6 , the integrated circuit 310 may further include a conductive layer 40, which is located on a side of the substrate 10 away from the epitaxial layer 21. The integrated circuit 310 also includes a first backside via 301, which is located below the first electrode 23 and extends through the substrate 10 and the epitaxial layer 21. The conductive layer 40 is connected to the first electrode 23 via the first backside via 301. The first electrode 23 can be connected to the conductive layer 40 for grounding. This reduces the overlap of the leads corresponding to the first electrode 23, the gate 22, and the second electrode 24, and the length of the grounding line, thereby reducing the parasitic capacitance and parasitic inductance of the HEMT device 20.

[0151] The conductive layer 40 may be made of, for example, gold, titanium, etc. The thickness of the conductive layer 40 may range from 500 nm to 30,000 nm. The conductive layer 40 may be prepared by, for example, electroplating, evaporation, or sputtering.

[0152] As shown in FIG7 , the first matching circuit 30 includes a first capacitor 31, which is located on the side of the epitaxial layer 21 away from the substrate 10. The first capacitor 31 includes a first plate 311 and a second plate 312 disposed opposite each other, with the second plate 312 located on the side of the first plate 311 away from the substrate 10. The first plate 311 of the first capacitor 31 is grounded, and the second plate 312 of the first capacitor 31 is connected to the gate 22. As shown in FIG7 , the first capacitor 31 may further include a first dielectric layer 313 located between the first plate 311 and the second plate 312.

[0153] In the embodiment of the present application, there is no limitation on the material, thickness and size of the first electrode plate 311 , the second electrode plate 312 and the first dielectric layer 313 , and they can be designed according to actual needs.

[0154] For example, referring to FIG5 , the projected area of ​​the first plate 311 of the first capacitor 31 on the substrate 10 may be smaller than the projected area of ​​the second plate 312 of the first capacitor 31 on the substrate 10. Alternatively, the projected area of ​​the first plate 311 of the first capacitor 31 on the substrate 10 may be larger than the projected area of ​​the second plate 312 on the substrate 10. Of course, the projected area of ​​the first plate 311 of the first capacitor 31 on the substrate 10 may also be equal to the projected area of ​​the second plate 312 of the first capacitor 31 on the substrate 10.

[0155] In the integrated circuit 310 provided in the embodiment of the present application, the HEMT device 20 is connected to a first matching circuit 30. The first capacitor 31 of the first matching circuit 30 is disposed on the epitaxial layer 21 of the HEMT device 20. The first capacitor 31 includes a first plate 311 and a second plate 312. The first plate 311 is grounded, and the second plate 312 is connected to the gate 22 of the HEMT device 20. This eliminates the need for bonding wires between the first capacitor 31 in the first matching circuit 30 and the gate 22. This reduces the parasitic inductance and capacitance between the first capacitor 31 and the gate 22, and reduces the parasitic capacitance and inductance in the integrated circuit 310. This improves the output power and efficiency of the integrated circuit 310 and the consistency of the high- and low-frequency performance of the integrated circuit 310. Furthermore, the reduced parasitic inductance and capacitance between the first capacitor 31 and the gate 22 speeds up signal transmission between the first capacitor 31 and the gate 22, thereby reducing signal delay and increasing the signal transmission speed of the integrated circuit 310.

[0156] Furthermore, the absence of bonding wires between the first capacitor 31 and the gate 22 can improve the connection stability between the first capacitor 31 and the gate 22, thereby improving the operational stability of the integrated circuit 310. Furthermore, the absence of bonding wires between the first capacitor 31 and the gate 22 can also reduce costs, shrink the packaging area of ​​the integrated circuit 310, shorten the packaging cycle of the integrated circuit 310, and improve the packaging efficiency of the integrated circuit 310.

[0157] 5 to 20 , several configuration positions of the first capacitor 31 in the embodiment of the present application are described below.

[0158] As shown in FIG. 5 and FIG. 6 , in some embodiments, the first pad 25 serves as the second plate 312 of the first capacitor 31 .

[0159] In this way, the first pad 25 serves as the second plate 312 of the first capacitor 31, and the second plate 312 of the first capacitor 31 is directly connected to the gate 22. There is no need to set a connecting line between the first capacitor 31 and the gate 22, which is conducive to further simplifying the structure of the integrated circuit 310 and reducing the cost of the integrated circuit 310.

[0160] In some examples, as shown in FIG8 , when the first pad 25 serves as the second electrode 312 of the first capacitor 31, the first electrode 311 of the first capacitor 31 can be provided on the same layer as the first electrode 23. In this way, the first electrode 311 can be manufactured simultaneously with the first electrode 23, thereby simplifying the manufacturing process of the integrated circuit 310 and improving manufacturing efficiency.

[0161] In other examples, when the first pad 25 serves as the second plate 312 of the first capacitor 31, the first plate 311 of the first capacitor 31 can also be provided on the same layer as the gate 22. In this way, the first plate 311 can be manufactured simultaneously with the gate 22, thereby simplifying the manufacturing process of the integrated circuit 310 and improving manufacturing efficiency.

[0162] Of course, when the first pad 25 serves as the second electrode 312 of the first capacitor 31, the first electrode 311 of the first capacitor 31 may not be provided on the same layer as the gate 22 and the first electrode 23. In this case, the first electrode 311 of the first capacitor 31 may be prepared separately.

[0163] In the present embodiment, there are no restrictions on the shape of the projection of the first plate 311 of the first capacitor 31 on the substrate 10, and the shape of the projection of the second plate 312 of the first capacitor 31 on the substrate 10. These shapes can be designed based on actual conditions. FIG5 illustrates an example in which the projection of the second plate 312 of the first capacitor 31 on the substrate 10 is a rounded rectangle.

[0164] In some embodiments, as shown in FIG9 , when the first pad 25 serves as the second plate 312 of the first capacitor 31, the HEMT device 20 further includes a second pad 27. The second pad 27 is also located on a side of the epitaxial layer 21 away from the substrate 10, and the gate 22 is further connected to the second pad 27. In the second direction Y, the first pad 25 is located between the first electrode 23 and the second pad 27.

[0165] In this way, the first pad 25 and the second pad 27 are connected in parallel, thereby reducing the total resistance of the first pad 25 and the second pad 27 and improving the performance of the HEMT device 20. Furthermore, by providing the second pad 27 connected to the gate 22, the second pad 27 can be used to connect to other devices in the integrated circuit 310 (e.g., other HEMT devices or components such as resistors, capacitors, and inductors). This avoids the connection between the first pad 25 and other devices in the first matching circuit 30 via bonding wires, which could cause etching and damage to the first plate below the first pad. This helps ensure the yield of the integrated circuit 310.

[0166] The embodiment of the present application does not limit the shape, size, and material of the second pad 27. For example, as shown in FIG9 , the shape of the projection of the second pad 27 on the substrate 10 can be the same as the shape of the projection of the first pad 25 on the substrate 10. The size of the projection of the second pad 27 on the substrate 10 can also be the same as the size of the projection of the first pad 25 on the substrate 10. The material of the second pad 27 can also be the same as the material of the first pad 25.

[0167] In some examples, the second pad 27 can be provided on the same layer as the first pad 25. In this way, the second pad 27 can be fabricated simultaneously with the first pad 25, thereby simplifying the fabrication process of the HEMT device 20, improving the fabrication efficiency of the integrated circuit 310, and reducing costs.

[0168] In other embodiments, as shown in FIG10 , when the first pad 25 serves as the second plate 312 of the first capacitor 31, the HEMT device 20 may further include a third pad 28. The third pad 28 is also located on a side of the epitaxial layer 21 away from the substrate 10. In the second direction Y, the third pad 28 is located between the first pad 25 and the first electrode 23. The third pad 28 connects the gate 22 to the first pad 25.

[0169] The embodiment of the present application does not limit the shape, size, and material of the third pad 28. For example, as shown in FIG10 , the shape of the projection of the third pad 28 on the substrate 10 can be the same as the shape of the projection of the first pad 25 on the substrate 10. The size of the projection of the third pad 28 on the substrate 10 can also be the same as the size of the projection of the first pad 25 on the substrate 10. The material of the third pad 28 can also be the same as the material of the first pad 25.

[0170] The third pad 28 is provided in the HEMT device 20 provided in the embodiment of the present application. This allows the first pad 25 and the third pad 28 to be connected in parallel, thereby reducing the total resistance of the first and third pads 25, 28 and improving the performance of the HEMT device 20. Furthermore, the third pad 28 connected to the gate 22 can be used to connect to other devices in the integrated circuit 310. This prevents the first pad 25 from being connected to other devices via bonding wires, which could cause etching and damage to the first plate below the first pad 25. This helps ensure the yield of the integrated circuit 310.

[0171] In other embodiments, as shown in FIG. 11 , the HEMT device 20 includes a plurality of first electrodes 23 , which are arranged along a first direction X parallel to the substrate 10 , and the first capacitor 31 is located between two adjacent first electrodes 23 .

[0172] In the embodiments of the present application, the number of first electrodes 23 is not limited and can be designed according to actual needs. In some examples, the first matching circuit 30 may include one first capacitor 31. In other examples, as shown in FIG11 , the first matching circuit 30 may include multiple first capacitors 31. It will be understood that FIG11 illustrates an example of a first matching circuit 30 including two first capacitors 31, and does not limit the number of first capacitors 31 in the first matching circuit 30.

[0173] In the embodiment of the present application, the first capacitor 31 is disposed between two adjacent first electrodes 23 of the HEMT device 20 , so that the projection area of ​​the first capacitor 31 and the HEMT device 20 on the substrate 10 can be small, thereby facilitating reduction in the packaging area of ​​the integrated circuit 310 and facilitating miniaturization of a power amplifier using the integrated circuit 310 .

[0174] For example, as shown in FIG12 , the first plate 311 of the first capacitor 31 can be provided in the same layer as the gate 22. In this way, the first plate 311 can be fabricated simultaneously with the gate 22, thereby simplifying the fabrication process of the HEMT device 20, improving the fabrication efficiency of the integrated circuit 310, and reducing costs.

[0175] For example, as shown in FIG12 , the second plate 312 of the first capacitor 31 can be provided in the same layer as the field plate 26. In this way, the second plate 312 can be fabricated simultaneously with the field plate 26, thereby simplifying the fabrication process of the HEMT device 20, improving the fabrication efficiency of the integrated circuit 310, and reducing costs.

[0176] It is understandable that the arrangement positions of the first electrode plate 311 and the second electrode plate 312 of the first capacitor 31 in the embodiment of the present application are not limited thereto.

[0177] In yet other embodiments, as shown in FIG13 , an integrated circuit 310 includes a plurality of HEMT devices 20. The plurality of HEMT devices 20 may be arranged along a first direction X parallel to the substrate 10, and a first capacitor 31 is located between two adjacent HEMT devices 20. The second plate 312 of the first capacitor 31 is connected to the first pads 25 of the two adjacent HEMT devices 20.

[0178] In the embodiment of the present application, the first capacitor 31 is provided in the gap between two adjacent HEMT devices 20 in the first direction X, effectively utilizing the space between the two HEMT devices 20. Compared with a solution in which additional space is reserved for the first capacitor 31, this solution can improve the integration level of the integrated circuit 310 and shorten the distance between the first capacitor 31 and the HEMT device 20, thereby simplifying the connection structure between the HEMT device 20 and the first capacitor 31 and simplifying the structure of the integrated circuit 310.

[0179] In some examples, referring to FIG12 , the first plate 311 of the first capacitor 31 can be disposed on the same layer as the gate 22, and the second plate 312 of the first capacitor 31 can be disposed on the same layer as the field plate 26. It is understood that the locations of the first plate 311 and the second plate 312 of the first capacitor 31 in the embodiment of the present application are not limited thereto.

[0180] In some embodiments, the first electrode 23 can be grounded. To achieve grounding of the first electrode plate 311 of the first capacitor 31, in some examples, as shown in Figures 8, 10, 11, and 13, the first electrode 23 can be connected to the first electrode plate 311 of the first capacitor 31. Alternatively, in other examples, as shown in Figures 14 and 15, the first electrode 23 can directly serve as the first electrode plate 311 of the first capacitor 31.

[0181] When the first electrode 23 serves as the first plate 311 of the first capacitor 31, the projection area of ​​the first capacitor 31 and the HEMT device 20 on the substrate 10 can be small, thereby facilitating reduction in the occupied area of ​​the integrated circuit 310 and facilitating the miniaturization of a power amplifier using the integrated circuit 310 provided in the embodiment of the present application.

[0182] As shown in FIG. 15 , when the first electrode 23 serves as the first electrode plate 311 of the first capacitor 31 , the second electrode plate 312 of the first capacitor 31 may be short-circuited with the first pad 25 , thereby being connected to the gate 22 .

[0183] 14 and 15 , the second plate 312 can be located on a different layer than the first pad 25. In this case, the projection of the second plate 312 of the first capacitor 31 on the substrate 10 can partially overlap with the projection of the first pad 25 on the substrate 10. Alternatively, the second plate 312 and the first pad 25 can be integrally formed.

[0184] When the first electrode plate 311 of the first capacitor 31 is connected to the first electrode 23, as shown in Figures 10, 11, and 13, the first electrode plate 311 of the first capacitor 31 includes a main portion 311a and an extension portion 311b that are perpendicular to each other. The extension portion 311b is connected to the first electrode 23. At least a portion of the projection of the main portion 311a on the substrate 10 overlaps with the projection of the second electrode plate 312 of the first capacitor 31 on the substrate 10. At least a portion of the projection of the extension portion 311b on the substrate 10 is located outside the projection of the second electrode plate 312 of the first capacitor 31 on the substrate 10.

[0185] Among them, "at least part of the projection of the main body 311a on the substrate 10 overlaps with the projection of the second plate 312 of the first capacitor 31 on the substrate 10" can be as shown in Figures 11 and 13, that is, a part of the projection of the main body 311a on the substrate 10 overlaps with the projection of the second plate 312 of the first capacitor 31 on the substrate 10, and another part of the projection of the main body 311a on the substrate 10 is located outside the projection of the second plate 312 of the first capacitor 31 on the substrate 10.

[0186] Alternatively, "at least part of the projection of the main body 311a on the substrate 10 overlaps with the projection of the second plate 312 of the first capacitor 31 on the substrate 10", or as shown in Figure 10, the projection of the main body 311a on the substrate 10 is located inside the projection of the second plate 312 of the first capacitor 31 on the substrate 10.

[0187] The above-mentioned “at least part of the projection of the extension portion 311b on the substrate 10 is located outside the projection of the second plate 312 of the first capacitor 31 on the substrate 10” may mean, as shown in Figures 10, 11 and 13, that a part of the projection of the extension portion 311b on the substrate 10 is located outside the projection of the second plate 312 of the first capacitor 31 on the substrate 10, and another part of the projection of the extension portion 311b on the substrate 10 is located inside the projection of the second plate 312 of the first capacitor 31 on the substrate 10.

[0188] Of course, “at least part of the projection of the extension portion 311b on the substrate 10 is located outside the projection of the second plate 312 of the first capacitor 31 on the substrate 10” can also mean that the projection of the extension portion 311b on the substrate 10 is located outside the projection of the second plate 312 of the first capacitor 31 on the substrate 10.

[0189] In some examples, as shown in FIG16 , the projection of the main portion 311a on the substrate 10 can be rectangular. In other examples, as shown in FIG17 , the projection of the main portion 311a on the substrate 10 can be stepped. In still other examples, as shown in FIG18 , the projection of the main portion 311a on the substrate 10 can be triangular. Of course, the shapes of the projections of the main portion 311a on the substrate 10 provided in the embodiments of the present application are not limited to these. Referring to FIG16 , FIG17 , and FIG18 , the projection of the extension portion 311b on the substrate 10 can be rectangular.

[0190] As shown in FIG. 16 to FIG. 18 , the HEMT device 20 may include a plurality of first electrodes 23 , and the first electrode plate 311 may include a main portion 311 a and a plurality of extension portions 311 b , and one first electrode 23 may correspond to one extension portion 311 b .

[0191] In some embodiments, as shown in Figures 19 and 20, the integrated circuit 310 may further include a conductive layer 40. The conductive layer 40 is located on a side of the substrate 10 away from the HEMT device 20. The conductive layer 40 penetrates the substrate 10 and the epitaxial layer 21 and is connected to the first plate 311 of the first capacitor 31.

[0192] It can be seen from the above embodiments that the conductive layer 40 is also connected to the first electrode 23 . Therefore, when the conductive layer 40 is connected to the first electrode plate 311 , the first electrode plate 311 can be connected to the first electrode 23 .

[0193] In the integrated circuit 310 provided in the embodiment of the present application, the first electrode plate 311 and the first electrode 23 are interconnected through the conductive layer 40 and grounded through the conductive layer 40, which is beneficial to shorten the signal transmission path, increase the signal transmission rate, and reduce the impedance during the signal transmission process.

[0194] 19 and 20 , the integrated circuit 310 may further include a second back hole 302 , which is located below the first plate 311 of the first capacitor 31 and penetrates the substrate 10 and the epitaxial layer 21 . The conductive layer 40 is connected to the first plate 311 through the second back hole 302 .

[0195] The embodiment of the present application does not limit the number, size, and opening shape of the second back holes 302. FIG19 illustrates an example in which one first electrode plate 311 corresponds to two second back holes 302, and the opening shape of the second back holes 302 is a strip.

[0196] In some examples, as shown in Figures 21 and 22, the first electrode plate 311 of the first capacitor 31 includes a first sublayer 3111 and a second sublayer 3112 that are stacked. The second sublayer 3112 is located on a side of the first sublayer 3111 away from the substrate 10, and the first sublayer 3111 is in direct contact with the second sublayer 3112. The first sublayer 3111 is provided in the same layer as the first electrode 23, and the material of the first sublayer 3111 is the same as that of the first electrode 23.

[0197] The specific thicknesses of the first sublayer 3111 and the second sublayer 3112 are not limited in the present embodiment and can be designed according to actual needs. For example, the thickness of the first sublayer 3111 can be the same as the thickness of the second sublayer 3112. Alternatively, the thickness of the first sublayer 3111 can be greater than the thickness of the second sublayer 3112. Alternatively, the thickness of the first sublayer 3111 can be less than the thickness of the second sublayer 3112.

[0198] In the integrated circuit 310 provided in the embodiment of the present application, the first plate 311 includes a first sublayer 3111 and a second sublayer 3112 arranged in a stacked manner. This allows the first plate 311 of the first capacitor 31 to have a greater overall thickness, thereby increasing the cross-sectional area of ​​the first plate 311. This reduces the resistance of the first plate 311 and improves the performance of the first capacitor 31. Furthermore, the greater thickness of the first plate 311 of the first capacitor 31 also helps expand the process window, preventing the first plate 311 from being damaged or pierced during the preparation of the second back via 302, thereby protecting the first plate 311 and ensuring the yield of the integrated circuit 310.

[0199] At the same time, the first sublayer 3111 is arranged in the same layer as the first pole 23, and the material of the first sublayer 3111 is the same as the material of the first pole 23, so that during the preparation process of the integrated circuit 310, the first sublayer 3111 can be prepared synchronously with the first pole 23, which is beneficial to reduce the preparation cost of the integrated circuit 310, simplify the preparation process of the integrated circuit 310, and improve the preparation efficiency of the integrated circuit 310.

[0200] Figures 23 and 24 respectively illustrate top views of two integrated circuits 310 provided in embodiments of the present application. Compared to the structure of the integrated circuit 310 shown in Figure 21 , the HEMT device 20 shown in Figure 23 includes a third pad 28 . Compared to the structure of the integrated circuit 310 shown in Figure 19 , the HEMT device 20 in the integrated circuit 310 shown in Figure 24 includes multiple first electrodes 23 arranged along a first direction X, with a first capacitor 31 disposed between two adjacent first electrodes 23. Of course, when the first capacitor 31 is located between two adjacent HEMT devices 20, the first electrode 311 of the first capacitor 31 can also be grounded via the conductive layer 40 and the second back via 302 .

[0201] In some embodiments, as shown in FIG. 25 , the HEMT device 20 further includes a first inductor L1 . The first inductor L1 is located on a side of the epitaxial layer 21 away from the substrate 10 . The first inductor L1 connects the gate 22 and the first pad 25 .

[0202] In some examples, as shown in FIG26 , the HEMT device 20 includes multiple gates 22 arranged along a first direction X parallel to the substrate 10 , and the first inductor L1 is connected to the multiple gates 22 . In the embodiments of the present application, there is no limitation on the number of gates 22 to which the first inductor L1 is connected. For example, one first inductor L1 can be connected to two gates 22 , three gates 22 , four gates 22 , and so on. FIG26 illustrates an example in which one first inductor L1 is connected to two gates 22 .

[0203] In some examples, as shown in FIG26 , different first inductors L1 may be connected to the same number of gates 22. In other examples, different first inductors L1 may be connected to different numbers of gates 22. In still other examples, some of the plurality of first inductors L1 may be connected to the same number of gates 22, while another portion of the plurality of first inductors L1 may be connected to different numbers of gates 22.

[0204] In the embodiment of the present application, the first inductor L1 is connected to multiple gates 22. This can, on the one hand, reduce the number of first inductors L1 in the HEMT device 20, thereby simplifying the structure of the HEMT device 20 and reducing the manufacturing cost of the HEMT device 20. On the other hand, the inductance value of the first inductor L1 can be increased.

[0205] Figure 27 shows a top view of the first inductor L1 provided in an embodiment of the present application, Figure 28 shows a cross-sectional schematic diagram of the first inductor L1 provided in Figure 27 at J-J', and Figure 29 shows a cross-sectional schematic diagram of the first inductor L1 provided in Figure 27 at K-K'.

[0206] As shown in FIG28 , in some examples, the first inductor L1 includes a first routing segment M1 and a second routing segment M2. The projection of the first routing segment M1 on the substrate 10 intersects the projection of the second routing segment M2 on the substrate 10. The second routing segment M2 includes a first sub-segment M21, a second sub-segment M22, and a third sub-segment M23, which are sequentially connected. The first sub-segment M21 and the third sub-segment M23 each include a first conductive pattern N1 and a second conductive pattern N2, which are stacked. The second conductive pattern N2 is located on a side of the first conductive pattern N1 away from the substrate 10 and is connected to the first conductive pattern N1. One of the first routing segment M1 and the second sub-segment M22 includes the first conductive pattern N1, and the other includes the second conductive pattern N2. FIG28 illustrates an example in which the first routing segment M1 includes the first conductive pattern N1 and the second sub-segment M22 includes the second conductive pattern N2.

[0207] In some examples, a projection of the first routing segment M1 on the substrate 10 and a projection of the second routing segment M2 on the substrate 10 may be perpendicular to each other.

[0208] As shown in Figure 27, the first inductor L1 can include a multi-turn coil. By setting the first routing segment M1 and the second routing segment M2, one end of the innermost coil among the multi-turn coils of the first inductor L1 can be led out so that one end of the innermost coil among the multi-turn coils can be connected to the gate 22 or the first pad 25.

[0209] As shown in Figures 27 and 29, in the first inductor L1, except for the first and second routing segments M1 and M2, the remaining routing segments include a first conductive pattern N1 and a second conductive pattern N2 that are stacked and insulated from each other. The first inductor L1 may further include an insulating layer N3 located between the first and second conductive patterns N1 and N2.

[0210] In some examples, the first conductive pattern N1 may be disposed on the same layer as the first electrode 23 , and the second conductive pattern N2 may be disposed on the same layer as the first pad 25 .

[0211] In this way, the first conductive pattern N1 can be fabricated simultaneously with the first electrode 23, and the second conductive pattern N2 can be fabricated simultaneously with the first pad 25, thereby reducing the manufacturing cost of the integrated circuit 310, simplifying the manufacturing process of the integrated circuit 310, and improving the manufacturing efficiency of the integrated circuit 310. Furthermore, the second conductive pattern N2 and the first pad 25 are arranged on the same layer, which further simplifies the connection structure between the first inductor L1 and the first pad 25, simplifies the structure of the HEMT device, further reduces the manufacturing cost of the integrated circuit 310, and reduces the occupied area of ​​the integrated circuit 310.

[0212] In some embodiments, as shown in FIG30 , the first matching circuit 30 further includes a second capacitor 32 and a second inductor L2 . The second capacitor 32 and the second inductor L2 are both located outside the substrate 10 . The second inductor L2 connects the second capacitor 32 and the first capacitor 31 .

[0213] The second inductor 33 may be, for example, a bonding wire inductor.

[0214] In other embodiments, as shown in FIG31 , the first matching circuit 30 further includes a second capacitor 32 and a second inductor L2, both of which are located on the side of the epitaxial layer 21 away from the substrate 10. As shown in FIG32 , the second capacitor 32 includes a third plate 32 a and a fourth plate 32 b that are disposed opposite each other, with the fourth plate 32 b being located on the side of the third plate 32 a away from the substrate 10. The third plate 32 a of the second capacitor 32 is grounded, and the fourth plate 32 b of the second capacitor 32 is connected to the second plate 312 of the first capacitor 31 via the second inductor L2.

[0215] In the embodiment of the present application, there is no limit on the number of second capacitors 32 and second inductors L2 in the first matching circuit 30, and the number can be designed according to actual needs. FIG31 illustrates an example in which the first matching circuit 30 includes one second capacitor 32 and four second inductors L2.

[0216] In this way, the first capacitor 31, the second capacitor 32 and the second inductor L2 in the first matching circuit 30 are all arranged on the epitaxial layer 21. Not only is there no need to set a bonding wire between the first capacitor 31 and the gate 22, but there is also no need to set a bonding wire between the second capacitor 32 and the first capacitor 31. This can make the parasitic inductance and parasitic capacitance between the first capacitor 31 and the gate 22 smaller, and the parasitic inductance and parasitic capacitance between the second capacitor 32 and the first capacitor 31 smaller. The parasitic capacitance and parasitic inductance in the integrated circuit 310 are smaller, which can further improve the output power and efficiency of the integrated circuit 310 and improve the consistency of the high and low frequency performance of the integrated circuit 310.

[0217] Moreover, the parasitic inductance and parasitic capacitance between the first capacitor 31 and the gate 22 are small, and the parasitic inductance and parasitic capacitance between the second capacitor 32 and the first capacitor 31 are also small, which can also make the signal transmission between the first capacitor 31 and the gate 22 and between the first capacitor 31 and the second capacitor 32 faster, thereby improving the signal delay and increasing the signal transmission speed of the integrated circuit 310.

[0218] At the same time, the first capacitor 31, the second capacitor 32 and the second inductor L2 in the first matching circuit 30 are all arranged on the epitaxial layer 21, which can also improve the connection stability between the first capacitor 31 and the gate 22, between the first capacitor 31 and the second inductor L2, and between the second capacitor 32 and the second inductor L2, thereby improving the use stability of the integrated circuit 310.

[0219] Of course, there is no need to set bonding wires between the first capacitor 31 and the gate 22, and there is no need to set bonding wires between the second capacitor 32 and the first capacitor 31. This can also reduce costs, reduce the packaging area of ​​the integrated circuit 310, shorten the packaging cycle of the integrated circuit 310, and improve the packaging efficiency of the integrated circuit 310.

[0220] The structure of the second inductor L2 may be similar to that of the first inductor L1. For the structure of the second inductor L2, please refer to FIG. 27 , FIG. 28 and FIG. 29 , as well as the above description of the structure of the first inductor L1 , which will not be repeated here.

[0221] Unlike the first inductor L1, the first conductive pattern N1 in the second inductor L2 can be provided on the same layer as the first electrode plate 311 of the first capacitor 31, and the second conductive pattern N2 in the second inductor L2 can be provided on the same layer as the second electrode plate 312 of the first capacitor 31. This simplifies the manufacturing process of the first matching circuit 30 and improves the manufacturing efficiency of the first matching circuit 30. It also facilitates the connection of the second inductor L2 to the first capacitor 31 and simplifies the connection structure between the second inductor L2 and the first capacitor 32.

[0222] In some examples, as shown in FIG32 , the third plate 32 a of the second capacitor 32 is disposed on the same layer as the first plate 311 of the first capacitor 31 , and the fourth plate 32 b of the second capacitor 32 is disposed on the same layer as the second plate 312 of the first capacitor 31 .

[0223] In this way, during the preparation process of the first matching circuit 30, the first electrode plate 311 of the first capacitor 31 and the third electrode plate 32a of the second capacitor 32 can be prepared simultaneously, and the second electrode plate 312 of the first capacitor 31 can be prepared simultaneously with the fourth electrode plate 32b of the second capacitor 32, thereby simplifying the preparation process of the first matching circuit 30, improving the preparation efficiency of the first matching circuit 30, and reducing the preparation cost of the first matching circuit 30.

[0224] The embodiment of the present application does not restrict the shape of the projection of the third plate 32a of the second capacitor 32 on the substrate 10, nor does it restrict the shape of the projection of the fourth plate 32b of the second capacitor 32 on the substrate 10. These shapes can be designed based on actual needs. Similarly, the embodiment of the present application does not restrict the size of the projection area of ​​the third plate 32a and the fourth plate 32b of the second capacitor 32 on the substrate 10, nor does it restrict the overlapping area between the projection of the third plate 32a and the projection of the fourth plate 32b on the substrate 10.

[0225] In some embodiments, as shown in Figures 33 and 34 , the HEMT device 20 further includes a fourth pad 29, which is located on the side of the epitaxial layer 21 away from the substrate 10. The first electrode 23 is located between the first pad 25 and the fourth pad 29, and the fourth pad 29 is connected to the second electrode 24. The integrated circuit 310 further includes a second matching circuit 50, which includes a third capacitor 51, which is located on the side of the epitaxial layer 21 away from the substrate 10. The third capacitor 51 includes a fifth plate 511 and a sixth plate 512, which are arranged opposite each other. The sixth plate 512 is located on the side of the fifth plate 511 away from the substrate 10. The fifth plate 511 of the third capacitor 51 is grounded, and the sixth plate 512 of the third capacitor 51 is connected to the second electrode 24.

[0226] As shown in FIG. 34 , the third capacitor may further include a second dielectric layer 513 , and the second dielectric layer 513 is located between the fifth electrode plate 511 and the sixth electrode plate 512 .

[0227] In the embodiment of the present application, there is no limitation on the shape and size of the projection of the fourth pad 29 on the substrate 10. For example, the projection of the fourth pad 29 on the substrate 10 may be rectangular, and the fourth pad 29 may extend along the first direction X.

[0228] As shown in FIG. 33 , the HEMT device 20 may include a plurality of second electrodes 24 , and each of the plurality of second electrodes 24 may be connected to the fourth pad 29 .

[0229] It is understandable that, in addition to the third capacitor 51 , the second matching circuit 50 provided in the embodiment of the present application may further include other components.

[0230] In the embodiment of the present application, the HEMT device 20 is connected to the second matching circuit 50. The third capacitor 51 of the second matching circuit 50 is disposed on the epitaxial layer 21 of the HEMT device 20. The third capacitor 51 includes a fifth plate 511 and a sixth plate 512. The fifth plate 511 is grounded, and the sixth plate 512 is connected to the second electrode 24 of the HEMT device 20. This eliminates the need for bonding wires between the third capacitor 51 in the second matching circuit 50 and the second electrode 24. This reduces the parasitic inductance and capacitance between the third capacitor 51 and the second electrode 24, and also reduces the parasitic capacitance and inductance in the integrated circuit 310. This improves the output power and efficiency of the integrated circuit 310 and the consistency of the high- and low-frequency performance of the integrated circuit 310. Furthermore, the reduced parasitic inductance and capacitance between the third capacitor 51 and the second electrode 24 also speeds up signal transmission between the third capacitor 51 and the second electrode 24, thereby reducing signal delay and increasing the signal transmission speed of the integrated circuit 310.

[0231] Furthermore, the absence of bonding wires between the third capacitor 51 and the second electrode 24 can improve the connection stability between the third capacitor 51 and the second electrode 24, thereby improving the operational stability of the integrated circuit 310. Furthermore, the absence of bonding wires between the third capacitor 51 and the second electrode 24 can also reduce costs, reduce the packaging area of ​​the integrated circuit 310, shorten the packaging cycle of the integrated circuit 310, and improve the packaging efficiency of the integrated circuit 310.

[0232] In some embodiments, as shown in Figures 33 and 34, the fourth pad 29 can serve as the sixth plate 512 of the third capacitor 51. In this way, the sixth plate 512 of the third capacitor 51 is directly connected to the second electrode 24, and no connecting wires are required between the third capacitors 51, thereby further simplifying the structure of the integrated circuit 310 and reducing the cost of the integrated circuit 310.

[0233] When the fourth pad 29 serves as the sixth electrode plate 512 of the third capacitor 51, the fifth electrode plate 511 of the third capacitor 51 can be provided on the same layer as the first electrode 23, and the fifth electrode plate 511 of the third capacitor 51 can also be provided on the same layer as the gate 22. Of course, the first electrode plate 311 of the first capacitor 31 can also be provided on a different layer than the gate 22 and the first electrode 23. In this case, the fifth electrode plate 511 of the third capacitor 51 can be prepared separately.

[0234] It is understandable that, in the embodiment of the present application, the third capacitor 51 is not limited to this location.

[0235] An embodiment of the present application also provides a method for preparing an integrated circuit, as shown in FIG35 , the method includes step S100 and step S200.

[0236] S100 , as shown in FIG. 35 , an epitaxial layer 21 is formed on the substrate 10 .

[0237] For example, the material of the substrate 10 may include silicon carbide, silicon, sapphire, diamond, etc.

[0238] For example, the epitaxial layer 21 may include a stacked channel layer and a barrier layer, wherein the barrier layer is located on a side of the channel layer away from the substrate. The channel layer and the barrier layer are made of different materials, thereby forming a heterojunction and generating a two-dimensional electron gas through polarization.

[0239] The epitaxial layer 21 may be formed by, for example, a metal-organic chemical vapor deposition (MOCVD) growth method or a molecular beam epitaxy (MBE) growth method.

[0240] S200, referring to FIG5 and FIG35, a gate 22, a first electrode 23, a second electrode 24, a first pad 25, and a first capacitor 31 are formed on the side of the epitaxial layer 21 away from the substrate 10. The gate 22 is located between the first electrode 23 and the second electrode 24, and the gate 22 is connected to the first pad 25. The first capacitor 31 includes a first electrode plate 311 and a second electrode plate 312 arranged opposite to each other. The second electrode plate 312 is located on the side of the first electrode plate 311 away from the substrate 10. The first electrode plate 311 of the first capacitor 31 is grounded, and the second electrode plate 312 of the first capacitor 31 is connected to the gate 22.

[0241] It can be understood that the epitaxial layer 21 , the gate 22 , the first electrode 23 , the second electrode 24 and the first pad 25 all belong to the HEMT device 20 , and the first capacitor 31 belongs to the first matching circuit 30 .

[0242] For example, a metal deposition process, sputtering process, evaporation process, electroplating process, etching process or the like can be used to form a gate 22, a first electrode 23, a second electrode 24, a first pad 25 and a first capacitor 31 on the side of the epitaxial layer 21 away from the substrate 10.

[0243] In some examples, the first electrode 23 and the second electrode 24 may be formed first on the side of the epitaxial layer 21 away from the substrate 10 , and then the gate 22 may be formed, and finally the first pad 25 may be formed.

[0244] When the position of the first capacitor 31 is different, the formation process of the first capacitor 31 is also different. For example, in Figure 35, the first pad 25 serves as the second electrode 312 of the first capacitor 31. The first electrode 311 of the first capacitor 31 is arranged on the same layer as the first electrode 23 and is connected to each other. In this case, the first electrode 311 of the first capacitor 31 can be prepared simultaneously with the first electrode 23. When the first pad 25 is prepared, the second electrode 312 of the first capacitor 31 is also prepared.

[0245] The beneficial effects that can be achieved by the method for preparing the integrated circuit provided in the embodiment of the present application are the same as the beneficial effects that can be achieved by the integrated circuit provided in any of the above embodiments, and will not be repeated here.

[0246] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0247] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. An integrated circuit, characterized in that: include: substrate; A HEMT device is located on the substrate; the HEMT device includes an epitaxial layer, a gate, a first electrode, a second electrode, and a first pad, wherein the gate, the first electrode, the second electrode, and the first pad are all located on a side of the epitaxial layer away from the substrate, the gate is located between the first electrode and the second electrode, and the gate is connected to the first pad; The first matching circuit includes a first capacitor, which is located on a side of the epitaxial layer away from the substrate; the first capacitor includes a first plate and a second plate arranged opposite to each other, the second plate is located on a side of the first plate away from the substrate, the first plate of the first capacitor is grounded, and the second plate of the first capacitor is connected to the gate.

2. The integrated circuit according to claim 1, wherein: The first pad serves as a second plate of the first capacitor.

3. The integrated circuit according to claim 2, wherein: The HEMT device further includes a second pad, which is located on a side of the epitaxial layer away from the substrate, and the gate is also connected to the second pad; the first pad is located between the first electrode and the second pad.

4. The integrated circuit according to claim 2, wherein: The HEMT device further includes a third pad, which is located on a side of the epitaxial layer away from the substrate and between the first electrode and the first pad; the third pad connects the gate and the first pad.

5. The integrated circuit according to claim 1, wherein: The HEMT device includes a plurality of first electrodes, which are arranged along a first direction parallel to the substrate; and the first capacitor is located between two adjacent first electrodes.

6. The integrated circuit according to claim 1, wherein: The integrated circuit includes a plurality of HEMT devices arranged along a first direction parallel to the substrate. The first capacitor is located between two adjacent HEMT devices. The second plate of the first capacitor is connected to the first pads of the two adjacent HEMT devices.

7. The integrated circuit according to claim 1, wherein: The first electrode serves as a first plate of the first capacitor.

8. The integrated circuit according to any one of claims 1 to 6, characterized in that: The first plate of the first capacitor is connected to the first electrode.

9. The integrated circuit according to claim 8, wherein: The first electrode plate of the first capacitor includes a main portion and an extension portion perpendicular to each other, the extension portion connecting the main portion and the first electrode; at least a portion of the projection of the main portion on the substrate overlaps with the projection of the second electrode plate on the substrate; At least a portion of a projection of the extension portion on the substrate is located outside a projection of the second electrode plate on the substrate.

10. The integrated circuit according to any one of claims 1 to 9, characterized in that: Also includes: A conductive layer is located on a side of the substrate away from the HEMT device; the conductive layer penetrates the substrate and the epitaxial layer and is connected to the first plate of the first capacitor.

11. The integrated circuit according to claim 10, wherein: The first electrode plate of the first capacitor includes a first sublayer and a second sublayer that are stacked, the second sublayer is located on a side of the first sublayer away from the substrate, and the first sublayer is in direct contact with the second sublayer; The first sublayer and the first pole are provided in the same layer, and the material of the first sublayer is the same as that of the first pole.

12. The integrated circuit according to any one of claims 1 to 11, characterized in that: The HEMT device further includes: A first inductor is located on a side of the epitaxial layer away from the substrate, and the first inductor connects the gate and the first pad.

13. The integrated circuit according to claim 12, wherein: The HEMT device includes a plurality of gates arranged along a first direction parallel to the substrate, and the first inductor is connected to the plurality of gates.

14. The integrated circuit according to claim 12 or 13, characterized in that The first inductor includes a first routing segment and a second routing segment, wherein the projection of the first routing segment on the substrate intersects with the projection of the second routing segment on the substrate; the second routing segment includes a first sub-segment, a second sub-segment, and a third sub-segment connected in sequence; the first sub-segment and the third sub-segment each include a first conductive pattern and a second conductive pattern arranged in a stacked manner; the second conductive pattern is located on a side of the first conductive pattern away from the substrate and is connected to the first conductive pattern; one of the first routing segment and the second sub-segment includes the first conductive pattern, and the other includes the second conductive pattern.

15. The integrated circuit according to claim 14, wherein: The first conductive pattern is provided on the same layer as the first electrode, and the second conductive pattern is provided on the same layer as the first pad.

16. The integrated circuit according to any one of claims 1 to 15, characterized in that: The first matching circuit further includes a second capacitor and a second inductor. The second capacitor and the second inductor are both located outside the substrate. The second inductor connects the second capacitor and the first capacitor.

17. The integrated circuit according to any one of claims 1 to 15, characterized in that: The first matching circuit also includes a second capacitor and a second inductor, and the second capacitor and the second inductor are both located on the side of the epitaxial layer away from the substrate; the second capacitor includes a third plate and a fourth plate arranged opposite to each other, and the fourth plate is located on the side of the third plate away from the substrate; the third plate of the second capacitor is grounded, and the fourth plate of the second capacitor is connected to the second plate of the first capacitor through the second inductor.

18. The integrated circuit according to claim 17, wherein: The third electrode plate of the second capacitor is arranged in the same layer as the first electrode plate of the first capacitor, and the fourth electrode plate of the second capacitor is arranged in the same layer as the second electrode plate of the first capacitor.

19. The integrated circuit according to any one of claims 1 to 18, wherein: The HEMT device further includes a fourth pad, the fourth pad being located on a side of the epitaxial layer away from the substrate; the first electrode being located between the first pad and the fourth pad; and the fourth pad being connected to the second electrode; The integrated circuit also includes a second matching circuit, which includes a third capacitor, and the third capacitor is located on the side of the epitaxial layer away from the substrate; the third capacitor includes a fifth plate and a sixth plate arranged opposite to each other, and the sixth plate is located on the side of the fifth plate away from the substrate; the fifth plate of the third capacitor is grounded, and the sixth plate of the third capacitor is connected to the second plate.

20. A method for preparing an integrated circuit, characterized in that: include: forming an epitaxial layer on a substrate; forming a gate, a first electrode, a second electrode, a first pad and a first capacitor on a side of the epitaxial layer away from the substrate; The gate is located between the first electrode and the second electrode, and the gate is connected to the first pad; the first capacitor includes a first plate and a second plate arranged opposite to each other, the second plate is located on the side of the first plate away from the substrate, the first plate of the first capacitor is grounded, and the second plate of the first capacitor is connected to the gate.

21. A power amplifier circuit, characterized in that: include: Package structure, The integrated circuit according to any one of claims 1 to 19, wherein the integrated circuit is packaged inside the packaging structure.

22. An electronic device, characterized in that: It includes a power amplifier and an antenna, the power amplifier is used to amplify the radio frequency signal and output it to the antenna for outward radiation, and the power amplifier includes the power amplifier circuit as described in claim 21.

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