Semiconductor device and related circuit, chip, electronic device and manufacturing method

Abstract

A semiconductor device and a related circuit, chip, electronic device and manufacturing method. The semiconductor device comprises: a first semiconductor layer (310) and a second semiconductor layer (320), wherein the first semiconductor layer (310) comprises a plurality of pillars (313); the second semiconductor layer (320) is arranged above the first semiconductor layer (310); the semiconductor device is divided into an IGBT area, a diode area, and a MOSFET area in a first direction; the semiconductor device further comprises a third semiconductor layer (330) and a fourth semiconductor layer (340); the third semiconductor layer (330) is arranged below the first semiconductor layer (310) and located in the diode area and the MOSFET area; the fourth semiconductor layer (340) is arranged below the first semiconductor layer (310) and located in the IGBT area; and the semiconductor device further comprises: at least one first conductive material area (323), wherein the at least one first conductive material area (323) is located in the diode area. The semiconductor device has good synchronous rectification performance.

Description

Semiconductor devices and related circuits, chips, electronic devices, and preparation methods

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on February 1, 2024, with application number 202410145204.8, and priority to the Chinese patent application entitled “Semiconductor devices and related circuits, chips, electronic devices, and preparation methods,” all of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of semiconductor technology, and more specifically, to a semiconductor device and related circuits, chips, electronic equipment, and preparation methods. Background Art

[0003] Insulated-gate bipolar transistors (IGBTs) combine the advantages of metal-oxide semiconductor field-effect transistors (MOSFETs) and bipolar junction transistors (BJTs), and have been widely used in medium and high power electronic devices in new energy vehicles, smart grids, rail transportation, industrial control, communication power supplies, consumer electronics and other fields.

[0004] To increase the power density of IGBTs, an effective solution is to integrate the IGBT and diode into a single chip, forming a reverse conduction IGBT (RC-IGBT). The RC-IGBT chip integrates the functions of the IGBT and diode into a single chip, thus turning the two chips into one. This integrated design reduces the required chip area and enables devices with the same package size to provide higher power density. In addition, during the operation of the RC-IGBT, the IGBT area and the diode area can assist each other in dissipating heat. Through this mutually supportive design, heat can be conducted and dispersed more efficiently, thereby reducing the overall thermal resistance and improving the thermal performance of the system. Summary of the Invention

[0005] The present application provides a semiconductor device and related circuits, chips, electronic devices, and manufacturing methods. The present application provides a semiconductor device with better synchronous rectification performance.

[0006] In a first aspect, an embodiment of the present application provides a semiconductor device, comprising: a first semiconductor layer and a second semiconductor layer, wherein the conductivity type of the first semiconductor layer is a first conductivity type, the first semiconductor layer comprises a plurality of pillars, the plurality of pillars are arranged along a first direction, the first direction is perpendicular to the thickness direction of the semiconductor device, and the conductivity type of the pillars is a second conductivity type; the second semiconductor layer is arranged above the first semiconductor layer, and the conductivity type of the second semiconductor layer is the second conductivity type; the semiconductor device is divided along the first direction into an IGBT region for forming an insulated gate bipolar transistor (IGBT), a diode region for forming a diode, and a MOSFET region for forming a metal oxide semiconductor field effect transistor (MOSFET); the semiconductor device further comprises a third semiconductor layer and a fourth semiconductor layer, the third semiconductor layer is arranged below the first semiconductor layer and located in the diode region and the MOSFET region, and the conductivity type of the third semiconductor layer is the first conductivity type; the fourth semiconductor layer is arranged below the first semiconductor layer and located in the IGBT region, and the conductivity type of the fourth semiconductor layer is the second conductivity type; the semiconductor device further comprises: at least one first conductive material region, the at least one first conductive material region being located in the diode region.

[0007] Optionally, the first conductivity type is different from the second conductivity type. For example, the first conductivity type may be N-type, and the second conductivity type may be P-type. For another example, the first conductivity type may be P-type, and the second conductivity type may be N-type. In combination with the above technical solution, it is assumed that the first conductivity type is N-type and the second conductivity type is P-type. When a forward voltage is applied to the diode region, the N-type cathode region of the diode is used to inject electrons from the cathode direction. If the conductive material region located in the diode is at the same potential as the emitter, the formation of a channel can be avoided. When a forward voltage is applied to the gate, holes can be injected from the second semiconductor layer into the N-type region of the first semiconductor layer, which can reduce the voltage drop in the synchronous rectification mode, thereby improving the synchronous rectification performance of the semiconductor device.

[0008] Furthermore, the ratio of the diode area to the total area (i.e., the diode area + MOSFET area + IGBT area) affects the current conduction characteristics of the diode under reverse bias conditions and the current conduction characteristics of the IGBT and MOSFET under forward bias conditions. The larger the ratio of the diode area to the total area, the smaller the forward voltage drop under high current during reverse conduction. The larger the ratio of the diode area to the total area, the larger the forward voltage drop under high and low currents during forward conduction.

[0009] In combination with the first aspect, in a possible implementation of the first aspect, the semiconductor device further includes: at least one first semiconductor region, at least one second semiconductor region, at least one second conductive material region, and at least one third conductive material region, wherein the at least one third conductive material and the at least one first semiconductor region are located in the IGBT region; the at least one second conductive material region and the at least one second semiconductor region are located in the MOSFET region, and the conductivity type of the first semiconductor region and the second semiconductor region is the first conductivity type.

[0010] In combination with the first aspect, in a possible implementation of the first aspect, the first conductive material region includes a first trench, the first trench is filled with the first conductive material, the first trench passes through the second semiconductor layer and contacts the first semiconductor layer and / or the column located in the diode region; the second conductive material region includes a second trench, the second trench is filled with the second conductive material, the second trench passes through the second semiconductor layer and contacts the first semiconductor layer and / or the column located in the MOSFET region; the third conductive material region includes a third trench, the third trench is filled with the third conductive material, the third trench passes through the second semiconductor layer and contacts the first semiconductor layer and / or the column located in the IGBT region.

[0011] In combination with the first aspect, in a possible implementation of the first aspect, the semiconductor device further includes: at least one fourth conductive material region, and the at least one fourth conductive material region is located in the IGBT region.

[0012] In combination with the first aspect, in a possible implementation of the first aspect, the semiconductor device further includes: at least one fifth conductive material region, and the at least one fifth conductive material region is located in the MOSFET region.

[0013] In combination with the first aspect, in a possible implementation of the first aspect, the first semiconductor layer is sequentially arranged with the IGBT region, the diode region, and the MOSFET region along the first direction.

[0014] In combination with the first aspect, in a possible implementation of the first aspect, the MOSFET region includes a first MOSFET region and a second MOSFET region, and the first semiconductor layer is arranged in sequence along the first direction with the IGBT region, the first MOSFET region, the diode region and the second MOSFET region.

[0015] In combination with the first aspect, in a possible implementation of the first aspect, the semiconductor device further includes at least one floating region, the at least one floating region corresponds one-to-one to at least one of the pillars, and the floating region penetrates the second semiconductor layer and contacts the corresponding pillar.

[0016] In combination with the first aspect, in a possible implementation manner of the first aspect, the first semiconductor region and the second semiconductor region are located in a region of the second semiconductor layer facing away from the first semiconductor layer.

[0017] In a second aspect, an embodiment of the present application provides a semiconductor device, comprising: the semiconductor device is divided into an IGBT region for forming an insulated gate bipolar transistor (IGBT) and a MOSFET region for forming a metal oxide semiconductor field effect transistor (MOSFET) along a first direction, the first direction, the second direction, and the third direction are perpendicular to each other, the second direction is the thickness direction of the semiconductor device, the MOSFET region comprises a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a fourth semiconductor layer, wherein the conductivity type of the first semiconductor layer is a first conductivity type, the first semiconductor layer comprises a plurality of pillars, the plurality of pillars are arranged along the first direction, and the conductivity type of the pillars is a second conductivity type; the conductivity type of the second semiconductor layer is the second conductivity type, the second semiconductor layer is arranged above the first semiconductor layer, and the conductivity type of the third semiconductor layer is the first conductivity type, The third semiconductor layer is arranged below the first semiconductor layer; the fourth semiconductor layer is arranged on the surface of the second semiconductor layer away from the first semiconductor layer, the fourth semiconductor layer includes: a first semiconductor region and a second semiconductor region arranged in parallel on both sides of the fourth semiconductor layer, a plurality of conductive material regions arranged in parallel, and a plurality of third semiconductor regions arranged in parallel, the first semiconductor region and the second semiconductor region are parallel to the first direction, the conductivity type of the first semiconductor region and the second semiconductor region is the first conductivity type, the conductive material region is parallel to the third direction, the third semiconductor region is parallel to the third direction, the conductivity type of the third semiconductor region is the second conductivity type, the fourth semiconductor layer also includes a fourth semiconductor region, the fourth semiconductor region is located between the third semiconductor region and the conductive material region, and the conductivity type of the fourth semiconductor region is the second conductivity type.

[0018] For the above-mentioned semiconductor device, when electrons are injected upward from the bottom of the MOSFET region. After the electrons are injected into the fourth semiconductor layer, they continue to be injected into the first semiconductor region and the second semiconductor region arranged in parallel. Therefore, the electron transmission path is greater than the lateral length of the drift region. In this case, a lateral voltage drop is generated. The lateral voltage drop causes the PN junction of the channel substrate (CS) layer to be forward biased. Holes are injected from the fourth semiconductor region between the first semiconductor region and the second semiconductor region arranged in parallel, so that the body diode of the MOSFET region has a lower voltage drop in the synchronous rectification mode, which can improve the synchronous rectification performance of the semiconductor device.

[0019] In combination with the second aspect, in a possible implementation of the second aspect, the first semiconductor region is divided into multiple first sub-semiconductor regions by the multiple parallel third semiconductor regions and the multiple parallel conductive material regions; the second semiconductor region is divided into multiple second sub-semiconductor regions by the multiple parallel third semiconductor regions and the multiple parallel conductive material regions.

[0020] In combination with the second aspect, in a possible implementation manner of the second aspect, the conductive material region includes a trench, the trench is filled with a conductive material, and the trench penetrates the second semiconductor layer.

[0021] In combination with the second aspect, in a possible implementation of the second aspect, an impurity concentration of the third semiconductor region is different from an impurity concentration of the fourth semiconductor region.

[0022] In combination with the second aspect, in a possible implementation of the second aspect, the MOSFET region further includes a fifth semiconductor layer, the conductivity type of the fifth semiconductor layer is the first conductivity type, and the fifth semiconductor layer is located between the first semiconductor layer and the second semiconductor layer.

[0023] In combination with the second aspect, in a possible implementation of the second aspect, the semiconductor device further includes a sixth semiconductor layer, the sixth semiconductor layer is located between the first semiconductor layer and the third semiconductor layer, and the conductivity type of the sixth semiconductor layer is the first conductivity type.

[0024] In a third aspect, an embodiment of the present application provides a power conversion circuit, comprising at least one semiconductor device as in the first aspect or any possible implementation of the first aspect.

[0025] In a fourth aspect, an embodiment of the present application provides a power conversion circuit, comprising at least one semiconductor device as in the second aspect or any possible implementation of the second aspect.

[0026] In a fifth aspect, an embodiment of the present application provides a chip comprising at least one semiconductor device as in the first aspect or any possible implementation of the first aspect.

[0027] In a sixth aspect, an embodiment of the present application provides a chip comprising at least one semiconductor device as in the second aspect or any possible implementation of the second aspect.

[0028] In a seventh aspect, an embodiment of the present application provides an electronic device comprising at least one semiconductor device according to the first aspect or any possible implementation of the first aspect.

[0029] In an eighth aspect, an embodiment of the present application provides an electronic device comprising at least one semiconductor device according to the second aspect or any possible implementation of the second aspect.

[0030] In a ninth aspect, an embodiment of the present application provides a vehicle comprising at least one semiconductor device according to the first aspect or any possible implementation of the first aspect. The vehicle may be a car, such as an electric car, a hybrid car, an electric bicycle, or the like.

[0031] In a tenth aspect, an embodiment of the present application provides a vehicle comprising at least one semiconductor device according to the second aspect or any possible implementation of the second aspect. The vehicle may be a car, such as an electric car, a hybrid car, an electric bicycle, or the like.

[0032] In the eleventh aspect, an embodiment of the present application provides a control method, which includes: when the current direction of the semiconductor device is from emitter to collector as in the first aspect or any possible implementation of the first aspect, monitoring the current value of the main current of the semiconductor device during the dead time; when the current value of the main current is greater than a preset value, keeping the gate of the semiconductor device in a closed state; when the current value of the main current is less than or equal to the preset value, opening the gate of the semiconductor device after the dead time.

[0033] In the twelfth aspect, an embodiment of the present application provides a control method, the method comprising: when the current direction of the semiconductor device is from emitter to collector as in the second aspect or any possible implementation of the second aspect, monitoring the current value of the main current of the semiconductor device during the dead time; when the current value of the main current is greater than a preset value, keeping the gate of the semiconductor device in a closed state; when the current value of the main current is less than or equal to the preset value, opening the gate of the semiconductor device after the dead time.

[0034] In the thirteenth aspect, an embodiment of the present application provides a control method, the method comprising: in a case where the current direction of the semiconductor device is from the emitter to the collector as in the first aspect or any possible implementation of the first aspect, determining a first voltage value and a second voltage value, the first voltage value being the voltage value of the terminal voltage of the semiconductor device during the dead time, and the second voltage value being the voltage value of the terminal voltage after the gate of the semiconductor device is opened; when the difference between the second voltage value and the first voltage value is greater than a preset value, closing the gate of the semiconductor device; and when the difference between the second voltage value and the first voltage value is not greater than the preset value, keeping the gate of the semiconductor device in an open state.

[0035] In the fourteenth aspect, an embodiment of the present application provides a control method, the method comprising: in a case where the current direction of the semiconductor device is from the emitter to the collector as in the second aspect or any possible implementation of the second aspect, determining a first voltage value and a second voltage value, the first voltage value being the voltage value of the terminal voltage of the semiconductor device during the dead time, and the second voltage value being the voltage value of the terminal voltage after the gate of the semiconductor device is opened; when the difference between the second voltage value and the first voltage value is greater than a preset value, closing the gate of the semiconductor device; and when the difference between the second voltage value and the first voltage value is not greater than the preset value, keeping the gate of the semiconductor device in an open state.

[0036] In a fifteenth aspect, an embodiment of the present application provides a method for manufacturing a semiconductor device, wherein the semiconductor device is divided into an IGBT region for forming an insulated gate bipolar transistor (IGBT), a diode region for forming a diode, and a MOSFET region for forming a metal oxide semiconductor field effect transistor (MOSFET) along the first direction, manufacturing a first semiconductor layer, wherein the conductivity type of the first semiconductor layer is the first conductivity type, the first semiconductor layer includes a plurality of columns, the plurality of columns are arranged along the first direction, the first direction is perpendicular to the thickness direction of the semiconductor device, and the conductivity type of the columns is the second conductivity type; manufacturing a second semiconductor layer, wherein the second semiconductor layer is located on the first surface of the first semiconductor layer, and the conductivity type of the second semiconductor layer is the second conductivity type; manufacturing a third semiconductor layer, wherein the third semiconductor layer is located below the second surface of the first semiconductor layer and located in the diode region and the MOSFET region, and the conductivity type of the third semiconductor layer is the first conductivity type; manufacturing a fourth semiconductor layer, wherein the fourth semiconductor layer is located below the second surface of the first semiconductor layer and located in the IGBT region, and the conductivity type of the fourth semiconductor layer is the second conductivity type; manufacturing at least one first conductive material region, wherein the at least one first conductive material region is located in the diode region.

[0037] In combination with the fifteenth aspect, in a possible implementation of the fifteenth aspect, the method also includes: producing at least one first semiconductor region, at least one second semiconductor region, at least one second conductive material region, and at least one third conductive material region, wherein the at least one third conductive material region and the at least one first semiconductor region are located in the IGBT region, the at least one second conductive material region and the at least one second semiconductor region are located in the MOSFET region, and the conductivity type of the first semiconductor region and the second semiconductor region is the first conductivity type.

[0038] In combination with the fifteenth aspect, in a possible implementation of the fifteenth aspect, the production of the first conductive material region includes: forming a first trench, which penetrates the second semiconductor layer and contacts the first semiconductor layer and / or column located in the diode region, and filling the first conductive material in the first trench; the production of the second conductive material region includes: forming a second trench, which penetrates the second semiconductor layer and contacts the first semiconductor layer and / or column located in the MOSFET region, and filling the second conductive material in the second trench; the production of the third conductive material region includes: forming a third trench, which penetrates the second semiconductor layer and contacts the first semiconductor layer and / or column located in the IGBT region, and filling the third trench with a third conductive material.

[0039] In combination with the fifteenth aspect, in a possible implementation of the fifteenth aspect, the method further includes: producing at least one fourth conductive material region, and the at least one fourth conductive material region is located in the IGBT region.

[0040] In combination with the fifteenth aspect, in a possible implementation of the fifteenth aspect, the method further includes: producing at least one fifth conductive material region, and the at least one fifth conductive material region is located in the MOSFET region.

[0041] In combination with the fifteenth aspect, in a possible implementation of the fifteenth aspect, the first semiconductor layer is arranged in sequence along the first direction with the IGBT region, the diode region, and the MOSFET region.

[0042] In combination with the fifteenth aspect, in a possible implementation of the fifteenth aspect, the MOSFET region includes a first MOSFET region and a second MOSFET region, and the first semiconductor layer is arranged in sequence along the first direction with the IGBT region, the first MOSFET region, the diode region and the second MOSFET region.

[0043] In combination with the fifteenth aspect, in a possible implementation of the fifteenth aspect, the method further includes: producing at least one floating region, the at least one floating region corresponding one-to-one to at least one of the pillars, the floating region penetrating the second semiconductor layer and contacting the corresponding pillar.

[0044] In combination with the fifteenth aspect, in a possible implementation of the fifteenth aspect, the first semiconductor region and the second semiconductor region are fabricated in a region of the second semiconductor layer away from the first semiconductor layer.

[0045] In the sixteenth aspect, an embodiment of the present application provides a method for manufacturing a semiconductor device, comprising: the semiconductor device is divided into an IGBT region for forming an insulated gate bipolar transistor IGBT and a MOSFET region for forming a metal oxide semiconductor field effect transistor MOSFET along a first direction, the first direction, the second direction and the third direction are perpendicular to each other, the second direction is the thickness direction of the semiconductor device, a first semiconductor layer is manufactured, wherein the first semiconductor layer is located in the MOSFET region, the conductivity type of the first semiconductor layer is a first conductivity type, the first semiconductor layer includes a first surface and a second surface relative to each other, the first semiconductor layer also includes a plurality of columns, the plurality of columns are arranged along the first direction, the conductivity type of the columns is a second conductivity type, a second semiconductor layer is manufactured, wherein the second semiconductor layer is located in the MOSFET region, the conductivity type of the second semiconductor layer is the second conductivity type, the second semiconductor layer is arranged on the first surface of the first semiconductor layer, a third semiconductor layer is manufactured, wherein the third semiconductor layer is located in the MOSFET region, the conductivity type of the second semiconductor layer is the second conductivity type, and the second semiconductor layer is arranged on the first surface of the first semiconductor layer region, the conductivity type of the third semiconductor layer is the first conductivity type, the third semiconductor layer is arranged under the second surface of the first semiconductor layer, and a fourth semiconductor layer is manufactured, wherein the fourth semiconductor layer is located in the MOSFET region, the fourth semiconductor layer is arranged on the surface of the second semiconductor layer away from the first semiconductor layer, the fourth semiconductor layer includes: a first semiconductor region and a second semiconductor region arranged in parallel on both sides of the fourth semiconductor layer, a plurality of parallel conductive material regions, and a plurality of parallel third semiconductor regions, the first semiconductor region and the second semiconductor region are parallel to the first direction, the conductivity type of the first semiconductor region and the second semiconductor region is the first conductivity type, the conductive material region is parallel to the third direction, the third semiconductor region is parallel to the third direction, the conductivity type of the third semiconductor region is the second conductivity type, the fourth semiconductor layer also includes a fourth semiconductor region, the fourth semiconductor region is located between the third semiconductor region and the conductive material region, and the conductivity type of the fourth semiconductor region is the second conductivity type.

[0046] In combination with the sixteenth aspect, in a possible implementation of the sixteenth aspect, the first semiconductor region is divided into multiple first sub-semiconductor regions by the multiple parallel third semiconductor regions and the multiple parallel conductive material regions; the second semiconductor region is divided into multiple second sub-semiconductor regions by the multiple parallel third semiconductor regions and the multiple parallel conductive material regions.

[0047] In combination with the sixteenth aspect, in a possible implementation of the sixteenth aspect, manufacturing the conductive material area includes: forming a trench, the trench penetrating the second semiconductor layer, and filling the trench with a conductive material.

[0048] In combination with the sixteenth aspect, in a possible implementation of the sixteenth aspect, the production of the fourth semiconductor layer includes: doping the third semiconductor region with impurities of a first concentration, and doping the fourth semiconductor region with impurities of a second concentration, the first concentration being different from the second concentration.

[0049] In combination with the sixteenth aspect, in a possible implementation of the sixteenth aspect, the method also includes: producing a fifth semiconductor layer, the fifth semiconductor layer is located in the MOSFET region, the conductivity type of the fifth semiconductor layer is the first conductivity type, and the fifth semiconductor layer is located between the first semiconductor layer and the second semiconductor layer.

[0050] In combination with the sixteenth aspect, in a possible implementation of the sixteenth aspect, the method further includes: producing a sixth semiconductor layer, the sixth semiconductor layer being located between the first semiconductor layer and the third semiconductor layer, and the conductivity type of the sixth semiconductor layer being the first conductivity type.

[0051] In the seventeenth aspect, an embodiment of the present application provides a computer device, which includes a unit for implementing the fifteenth aspect or any possible implementation method of the fifteenth aspect.

[0052] In the eighteenth aspect, an embodiment of the present application provides a computer device, which includes a processor, which is used to couple with a memory, read and execute instructions and / or program codes in the memory to execute the fifteenth aspect or any possible implementation of the fifteenth aspect.

[0053] In the nineteenth aspect, an embodiment of the present application provides a chip system, which includes a logic circuit, which is used to couple with an input / output interface and transmit data through the input / output interface to execute the fifteenth aspect or any possible implementation method of the fifteenth aspect.

[0054] In the twentieth aspect, an embodiment of the present application provides a computer-readable storage medium storing a program code. When the program code stored in the computer storage medium runs on a computer, the computer executes the fifteenth aspect or any possible implementation of the fifteenth aspect.

[0055] In aspect 21, an embodiment of the present application provides a computer program product, which includes: computer program code, which, when the computer program code runs on a computer, enables the computer to execute aspect 15 or any possible implementation of aspect 15.

[0056] In aspect 22, an embodiment of the present application provides a computer device comprising a unit for implementing aspect 16 or any possible implementation method of aspect 16.

[0057] In aspect twenty-third, an embodiment of the present application provides a computer device comprising a processor, which is used to couple with a memory, read and execute instructions and / or program codes in the memory to execute aspect sixteen or any possible implementation of aspect sixteen.

[0058] In aspect 24, an embodiment of the present application provides a chip system, which includes a logic circuit, which is used to couple with an input / output interface and transmit data through the input / output interface to execute aspect 16 or any possible implementation method of aspect 16.

[0059] In aspect 25, an embodiment of the present application provides a computer-readable storage medium, which stores program code. When the program code stored in the computer storage medium is run on a computer, the computer executes aspect 16 or any possible implementation of aspect 16.

[0060] In aspect 26, an embodiment of the present application provides a computer program product, which includes: computer program code, which, when the computer program code runs on a computer, enables the computer to execute aspect 16 or any possible implementation of aspect 16. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] FIG1 is a schematic diagram of an inverter circuit in an electric vehicle charging pile.

[0062] Figure 2 is a schematic diagram of dead time.

[0063] FIG3 is a schematic structural diagram of a semiconductor device provided according to an embodiment of the present application.

[0064] FIG4 is a schematic diagram of another semiconductor device provided according to an embodiment of the present application.

[0065] FIG5 is a schematic diagram of another semiconductor device provided according to an embodiment of the present application.

[0066] FIG6 is a schematic diagram of another semiconductor device provided according to an embodiment of the present application.

[0067] FIG7 is a schematic diagram of another semiconductor device provided according to an embodiment of the present application.

[0068] FIG8 is a schematic diagram of electron injection directions and hole injection directions.

[0069] FIG9 is a schematic diagram of a volt-ampere characteristic curve.

[0070] FIG10 is a schematic block diagram of another semiconductor device provided according to an embodiment of the present application.

[0071] FIG11 is a three-dimensional schematic diagram of a semiconductor device provided according to an embodiment of the present application.

[0072] FIG12 is a top view of a semiconductor device provided according to an embodiment of the present application.

[0073] FIG13 is a schematic diagram showing the arrangement of semiconductor regions.

[0074] FIG14 is a schematic diagram of another semiconductor device provided according to an embodiment of the present application.

[0075] FIG15 is a schematic diagram showing the electron injection direction and the hole injection direction.

[0076] FIG16 is a schematic diagram of a volt-ampere characteristic curve.

[0077] FIG17 is a schematic diagram of a control method provided according to an embodiment of the present application.

[0078] FIG18 is a schematic diagram of a control method provided according to an embodiment of the present application.

[0079] FIG19 is a volt-ampere characteristic curve. DETAILED DESCRIPTION

[0080] The technical solution in this application will be described below with reference to the accompanying drawings.

[0081] First, some key terms involved in the embodiments of the present application are explained.

[0082] (1) N-type semiconductor.

[0083] N-type semiconductors are electron-based semiconductors. Doping an intrinsic semiconductor with a donor impurity creates an N-type semiconductor. For example, doping pure silicon with a trace amount of a pentavalent element (phosphorus or arsenic) creates a covalent bond between the phosphorus and the surrounding tetravalent silicon atoms, creating an additional free electron. N-type semiconductors can be further divided into N+ (high-electron) and N- (low-electron) types. The impurity concentration of N+ semiconductors is greater than that of N-type semiconductors. It should be understood that the terms N+ (high-electron) and N- (low-electron) are relative.

[0084] (2) P-type semiconductor.

[0085] P (Positive) type, or hole type, is a semiconductor that conducts primarily through holes. P-type semiconductors are formed by doping an intrinsic semiconductor with acceptor impurities. For example, when a trace amount of a trivalent element (boron or indium, etc.) is doped into pure silicon, the boron forms a covalent bond with the surrounding tetravalent silicon atoms, resulting in a missing electron, forming a hole. P-type can be further divided into P+ type (high-hole type) and P- type (low-hole type). The impurity concentration of P+ type semiconductors is greater than that of P- type semiconductors.

[0086] (3) Insulated gate bipolar transistor (IGBT).

[0087] An IGBT is a fully controlled, voltage-driven, composite power semiconductor device consisting of a bipolar junction transistor (BJT) and an insulated-gate field-effect transistor (MOSFET). IGBTs are suitable for applications in power conversion systems with DC voltages of 600V and above, such as AC motors, inverters, switching power supplies, lighting circuits, and traction drives.

[0088] (4) Freewheeling diode (FWD) and fast recovery diode (FRD).

[0089] A FWD is a diode that provides freewheeling current when the IGBT is turned off in an inductive load switching circuit. A FRD is a diode with a fast reverse recovery speed.

[0090] (5), reverse conduction IGBT (reverse conduction IGBT, RC-IGBT).

[0091] RC-IGBT is an IGBT structure with an integrated diode, which can provide freewheeling when the IGBT is turned off.

[0092] (6) IGBT type and parameters.

[0093] The development of IGBT has gone through different stages. The first generation of IGBT is punch-through IGBT (PT-IGBT), which adopts a planar gate structure, a thick P-type substrate with a high doping concentration, and an epitaxially grown N-type buffer and drift region. The electric field has a trapezoidal distribution during reverse blocking. However, the device has a low withstand voltage rating and a negative temperature characteristic for the forward conduction voltage drop, which is not conducive to parallel application.

[0094] The second generation is the non-punch through IGBT (NPT-IGBT), which is characterized by a trench gate structure. It uses a lightly doped N-type substrate as the drift layer, and the back collector layer is formed by P-type impurity injection. When reverse blocking occurs, the electric field is distributed in a triangular shape, and the device's voltage rating is greatly improved. However, the substrate thickness also continues to increase, and the on-state voltage drop and switching loss are very large.

[0095] The third generation is the field stop IGBT (FS-IGBT), which adds an N-type field stop layer to the second generation structure. During reverse blocking, the electric field is distributed in a trapezoidal shape, thereby reducing the substrate thickness while ensuring sufficient device voltage resistance. This significantly reduces the on-state voltage drop and switching loss, and improves the compromise between the on-state voltage drop Vcesat and the turn-off loss Eoff.

[0096] The fourth generation is a refined FS-IGBT, which further reduces the substrate thickness by reducing the cell size, optimizing the back buffer distribution (for example, using hydrogen implantation to form a deep buffer), and achieving a higher power density and a better compromise between the on-state voltage drop Vcesat and the turn-off loss Eoff.

[0097] IGBTs and diodes are key components in inverter circuits. Inverter circuits convert direct current (DC) into alternating current (AC). They are widely used in electric vehicles, power systems, and other fields. For example, inverter circuits can be used in electric vehicle electronic control systems, driving the vehicle's motor through high-power DC / AC inversion. Inverter circuits can also be used in electric vehicle low-voltage systems and charging stations. Inverter circuits can also be used in flexible AC transmission systems (FACT) for ultra-high voltage direct current (UHVDC), power conditioning systems (PCS) for wind and photovoltaic power generation, and uninterruptible power supplies (USPs).

[0098] In addition, there is also a large demand for IGBTs in household white appliances and light-emitting diode (LED) lighting drivers.

[0099] FIG1 is a schematic diagram of an inverter circuit in an electric vehicle charging pile.

[0100] The inverter circuit shown in FIG1 includes six IGBTs (ie, IGBT 101 to IGBT 106 ) and six diodes (ie, diode 111 to diode 116 ).

[0101] As shown in Figure 1, each IGBT has an anti-parallel diode. For example, the anti-parallel diode of IGBT 101 is diode 111, and the anti-parallel diode of IGBT 102 is diode 112. When the IGBT is turned off, the anti-parallel diode can quickly absorb the current generated by the IGBT and limit the change in reverse voltage. Therefore, the anti-parallel diode can protect the IGBT from overvoltage and loss, ensuring the normal operation and lifespan of the IGBT. In addition, the IGBT anti-parallel diode can also shorten the IGBT's turn-off time and reduce the sudden current change (also known as di / dt) when the IGBT is turned off, thereby further reducing the device's energy consumption and failure risk. This reverse diode can also be called a freewheeling diode.

[0102] (7) Dead time

[0103] If the upper IGBT (e.g., IGBT 101, IGBT 103, and IGBT 105 in Figure 1) and the lower IGBT (e.g., IGBT 102, IGBT 104, and IGBT 106 in Figure 1) of the inverter circuit are turned on simultaneously, the DC power supply will short-circuit. Therefore, to prevent the upper and lower IGBTs of the inverter circuit from being turned on simultaneously, the IGBT switching device has a period of time during which both the upper and lower IGBTs are turned off. This period is called the dead time. In other words, one of the upper and lower IGBTs is turned off first, and then the other IGBT is turned on after the dead time expires.

[0104] Figure 2 is a schematic diagram of dead time.

[0105] As shown in Figure 2, IGBT 101 is turned off first. When IGBT 101 switches from on to off (i.e., time t1), IGBT 102 is also in the off state. IGBT 102 is turned on when the dead time ends (i.e., time t2).

[0106] In some embodiments of the present application, the first conductivity type may be N-type and the second conductivity type may be P-type. In other embodiments of the present application, the first conductivity type may be P-type and the second conductivity type may be N-type. If the channel type is N-type, then the first conductivity type is N-type and the second conductivity type is P-type; if the channel type is P-type, then the first conductivity type is P-type and the second conductivity type is N-type.

[0107] An embodiment of the present application provides a semiconductor device. The semiconductor device includes: a first semiconductor layer and a second semiconductor layer, wherein the first semiconductor layer has a first conductivity type and includes a plurality of pillars arranged along a first direction perpendicular to the thickness direction of the semiconductor device, and the pillars have a second conductivity type; a second semiconductor layer disposed above the first semiconductor layer and having the second conductivity type; the semiconductor device is divided along the first direction into an IGBT region for forming an insulated gate bipolar transistor (IGBT), a diode region for forming a diode, and a MOSFET region for forming a metal oxide semiconductor field effect transistor (MOSFET); the semiconductor device also includes a third semiconductor layer and a fourth semiconductor layer, the third semiconductor layer disposed below the first semiconductor layer and located in the diode region and the MOSFET region, and having the first conductivity type; a fourth semiconductor layer disposed below the first semiconductor layer and located in the IGBT region, and having the second conductivity type; and the semiconductor device also includes: at least one first conductive material region, the at least one first conductive material region being located in the diode region.

[0108] Optionally, the first conductivity type is different from the second conductivity type. For example, the first conductivity type may be N-type, and the second conductivity type may be P-type. For another example, the first conductivity type may be P-type, and the second conductivity type may be N-type. In conjunction with the above technical solution, assume that the first conductivity type is N-type and the second conductivity type is P-type.

[0109] Optionally, the semiconductor device further includes: at least one first semiconductor region, at least one second semiconductor region, at least one second conductive material region, and at least one third conductive material region, wherein the at least one third conductive material and the at least one first semiconductor region are located in the IGBT region; the at least one second conductive material region and the at least one second semiconductor region are located in the MOSFET region, and the conductivity type of the first semiconductor region and the second semiconductor region is the first conductivity type.

[0110] The semiconductor device provided in the embodiments of the present application is introduced below with reference to the accompanying drawings.

[0111] FIG3 is a schematic structural diagram of a semiconductor device provided according to an embodiment of the present application.

[0112] As shown in FIG. 3( a ), the semiconductor device may include a first semiconductor layer 310 , a second semiconductor layer 320 , a third semiconductor layer 330 and a fourth semiconductor layer 340 .

[0113] The first semiconductor layer 310 includes a first surface 311 and a second surface 312. The first surface 311 is an upper surface of the first semiconductor layer 310, and the second surface 312 is a lower surface of the first semiconductor layer 310.

[0114] Referring to FIG. 3( b ), FIG. 3( b ) is for more clearly illustrating the first semiconductor layer 310 , the second semiconductor layer 320 , the third semiconductor layer 330 , the fourth semiconductor layer 340 , the first surface 311 and the second surface 312 .

[0115] The second semiconductor layer 320 is located above the first surface 311, and the third and fourth semiconductor layers 330 and 340 are located below the second surface. In other words, the second semiconductor layer 320 is located above the first semiconductor layer 310, and the third and fourth semiconductor layers 330 and 340 are located below the first semiconductor layer.

[0116] The first semiconductor layer 310 has a first conductivity type. The first semiconductor layer 310 also includes a plurality of pillars 313. The pillars 313 are arranged along a first direction. The first direction is perpendicular to the thickness of the semiconductor device. The pillars 313 have a second conductivity type. In other words, in addition to regions of the first conductivity type, the first semiconductor layer 310 also includes regions of the second conductivity type. The regions of the second conductivity type are pillars 313, as shown in FIG3(a). The regions of the first conductivity type are regions 314, as shown in FIG3(a). It can be seen that the regions of the first conductivity type are also pillars arranged along the first direction. Therefore, pillars 313 can also be referred to as first pillars, and regions 314 can also be referred to as second pillars. In other words, the first semiconductor layer 310 can include a plurality of first pillars arranged along the first direction and a plurality of second pillars arranged along the second direction, with the first pillars and second pillars arranged alternately. If the first conductivity type is N-type and the second conductivity type is P-type, the first pillars can also be referred to as P-pillars, and the second pillars can also be referred to as N-pillars. Pillar 313 and region 314 need to maintain charge balance.

[0117] Referring to FIG. 3 ( a ), the semiconductor device can be divided into an IGBT region, a diode region, and a MOSFET region along a first direction.

[0118] The second semiconductor layer in the IGBT region includes at least one conductive material region. The second semiconductor layer in the MOSFET region also includes at least one conductive material region. To facilitate the distinction between the conductive material regions located in the IGBT region and the conductive material regions located in the MOSFET region, the conductive material regions located in the IGBT region may be referred to as third conductive material regions, and the conductive material regions located in the MOSFET region may be referred to as second conductive material regions. FIG3(a) shows five third conductive material regions 321 included in the IGBT region and eight second conductive material regions 324 included in the MOSFET region.

[0119] The second semiconductor layer in the IGBT region includes at least one semiconductor region. The second semiconductor layer in the MOSFET region also includes at least one semiconductor region. To facilitate the distinction between the semiconductor region located in the IGBT region and the semiconductor region located in the MOSFET region, the semiconductor region located in the IGBT region can be referred to as the first semiconductor region, and the semiconductor region located in the MOSFET region can be referred to as the second semiconductor region. The conductivity type of the first semiconductor region and the second semiconductor region are both the first conductivity type. (a) in FIG3 shows the 10 first semiconductor regions 322 included in the IGBT region and the 14 second semiconductor regions 325 included in the MOSFET region. As shown in (a) in FIG3, the first semiconductor regions 322 and the second semiconductor regions 325 are located on the side of the second semiconductor layer 320 facing away from the first semiconductor region. In some embodiments, the first semiconductor regions 322 and the second semiconductor regions 325 can serve as emitter regions.

[0120] Unlike the IGBT and MOSFET regions, the second semiconductor layer of the diode region includes at least one conductive material region. For ease of distinction, the conductive material regions in the second semiconductor layer of the diode region can be referred to as first conductive material regions. As shown in FIG3(a), the second semiconductor layer of the diode region includes six first conductive material regions 323.

[0121] The conductivity type of the second semiconductor layer 320 is the second conductivity type, the conductivity type of the third semiconductor layer 330 is the first conductivity type, and the conductivity type of the fourth semiconductor layer 340 is the second conductivity type.

[0122] In some embodiments, the impurity concentration of the third semiconductor layer 330 is different from the impurity concentration of the first semiconductor layer 310. For example, in some embodiments, the impurity concentration of the third semiconductor layer 330 is greater than the impurity concentration of the first semiconductor layer 310.

[0123] The third semiconductor layer 330 is located in the diode and MOSFET regions. The fourth semiconductor layer 340 is located in the IGBT region. In other words, for the IGBT, from top to bottom, they are: the second semiconductor layer 320, the first semiconductor layer 310, and the fourth semiconductor layer 340. For the MOSFET and diode regions, from top to bottom, they are: the second semiconductor layer 320, the first semiconductor layer 310, and the fourth semiconductor layer 340.

[0124] The third conductive material region, the second conductive material region, and the first conductive material region include conductive materials. For ease of description, the conductive material in the first conductive material region may be referred to as the first conductive material, the conductive material in the second conductive material region may be referred to as the second conductive material, and the conductive material in the third conductive material region may be referred to as the third conductive material. Although the names of the conductive materials in different conductive material regions are not exactly the same, this does not mean that different conductive materials are used in different conductive material regions. In other words, the conductive materials in different conductive material regions may be the same or different. The embodiments of the present application do not limit the conductive material. For example, the conductive material may be polysilicon, polysilicon deposited with metal or metal silicide, or metal, etc.

[0125] The conductive material region can adopt a planar structure (also known as a planar gate) or a trench structure (also known as a trench gate). However, in order to avoid unnecessary repetition, the embodiment of the present application takes the trench structure as an example to introduce the semiconductor device provided by the present application. As shown in Figure 3, the third conductive material region 321 includes a third trench, the third trench is filled with a third conductive material, the third trench penetrates the second semiconductor layer, the third trench is in contact with the first semiconductor layer, and / or the third trench is disconnected from the pillar 313 in the first semiconductor layer. Similarly, the second conductive material region 324 includes a second trench, the second trench is filled with a second conductive material, the second trench penetrates the second semiconductor layer, the second trench is in contact with the first semiconductor layer, and / or the second trench is in contact with the pillar 313 in the first semiconductor layer; the first conductive material region 323 includes a first trench, the first trench is filled with a first conductive material, the first trench penetrates the second semiconductor layer, the first trench is in contact with the first semiconductor layer, and / or the first trench is in contact with the pillar 313 in the first semiconductor layer.

[0126] In some embodiments, a metal layer may be further provided below the fourth semiconductor layer and the third semiconductor layer as a collector electrode.

[0127] In some embodiments, the conductive material regions (i.e., the first conductive material region, the second conductive material region, and the third conductive material region) located above the semiconductor device can be divided into three categories: the first conductive material region is in contact only with the pillar 313; the second conductive material region is in contact only with the region of the first conductivity type in the first semiconductor layer (i.e., region 314); and the third conductive material region is in contact with both the pillar 313 and region 314. For example, the first conductive material region from the left in FIG3 is the second conductive material region, the second conductive material region from the left is the first conductive material region, and the third electrode from the left is the third conductive material region. The conductive material region contacting the pillar 313 and / or region 314 referred to here means that the trench of the conductive material region extends to the first semiconductor layer 310 and is released from the pillar 313 and / or region 314 located in the first semiconductor layer.

[0128] In some other embodiments, the conductive material region located above the semiconductor device may not contact the first semiconductor layer. In other words, the trench of the conductive material region may not extend to the first semiconductor layer 310 .

[0129] FIG4 is a schematic diagram of another semiconductor device provided according to an embodiment of the present application.

[0130] The semiconductor device shown in FIG4 includes: a first semiconductor layer 410, a second semiconductor layer 420, a third semiconductor layer 430, and a fourth semiconductor layer 440. The semiconductor device shown in FIG4 also includes a third conductive material region 421, a second conductive material region 424, a first conductive material region 423, a first semiconductor region 422, and a second semiconductor region 424.

[0131] Similar to the first semiconductor layer 310 in the semiconductor device shown in FIG3 , the first semiconductor layer 410 in the semiconductor device shown in FIG4 also includes a plurality of pillars 413 (also referred to as first pillars) arranged along a first direction and regions 414 (also referred to as second pillars) having the first conductivity type. The pillars 413 have the second conductivity type.

[0132] Different from the semiconductor device shown in FIG. 3, the semiconductor device shown in FIG. 4 has a fifth semiconductor layer 450 added above the first surface 411 and a sixth semiconductor layer 460 added below the second surface 412. In other words, the fifth semiconductor layer 450 is included between the first semiconductor layer 410 and the second semiconductor layer 420; the sixth semiconductor layer 460 is also included between the first semiconductor layer 410 and the third semiconductor layer 430 and the fourth semiconductor layer 440. For the IGBT region, from top to bottom, it sequentially includes: the second semiconductor layer 420, the fifth semiconductor layer 450, the first semiconductor layer 410, the sixth semiconductor layer 460, and the fourth semiconductor layer 440. For the diode region and the MOSFET region, from top to bottom, it sequentially includes: the second semiconductor layer 420, the fifth semiconductor layer 450, the first semiconductor layer 410, the sixth semiconductor layer 460, and the third semiconductor layer 430.

[0133] The conductivity type of the fifth semiconductor layer 450 can be the same as that of the first semiconductor layer 410. In other words, the conductivity type of the fifth semiconductor layer 450 can be the first conductivity type.

[0134] In some embodiments, the impurity concentration of the fifth semiconductor layer 450 is different from that of the first semiconductor layer 410. For example, in some embodiments, the impurity concentration of the fifth semiconductor layer 450 is higher than that of the first semiconductor layer 410.

[0135] In the embodiments of the present application, the same impurity concentration of two semiconductor layers may include that the impurity concentrations are exactly the same, that is, Conc1 - Conc2 = 0, where Conc1 represents the impurity concentration of one semiconductor layer and Conc2 represents the impurity concentration of the other semiconductor layer. In the embodiments of the present application, the same impurity concentration of two semiconductors may also include that the impurity concentrations are approximately the same. In other words, the difference between the impurity concentrations of two semiconductor layers is less than a preset value, that is, Conc1 - Conc2 < TH, where Conc1 represents the impurity concentration of one semiconductor layer, Conc2 represents the impurity concentration of the other semiconductor layer, and TH represents the preset value. Correspondingly, if the difference between the impurity concentrations of two semiconductor layers is greater than or equal to the preset value, then it can be said that the impurity concentrations of these two semiconductor layers are different.

[0136] The conductivity type of the sixth semiconductor layer 460 can also be the same as that of the first semiconductor layer 410. In other words, the conductivity type of the sixth semiconductor layer 460 can be the first conductivity type.

[0137] In some embodiments, the impurity concentration of the sixth semiconductor layer 460 is different from that of the first semiconductor layer 410. For example, in some embodiments, the impurity concentration of the sixth semiconductor layer 460 is higher than that of the first semiconductor layer 410.

[0138] In some other embodiments, the impurity concentration of the sixth semiconductor layer 460 is the same as the impurity concentration of the first semiconductor layer 410. This structure may also be referred to as a semi-superjunction structure.

[0139] The conductivity type of the third semiconductor layer 430 is the first conductivity type. In other words, the conductivity type of the third semiconductor layer 430 is the same as the conductivity type of the sixth semiconductor layer 460. Similarly, in some embodiments, the impurity concentration of the third semiconductor layer 430 may be greater than the impurity concentration of the sixth semiconductor layer 460.

[0140] Similar to the semiconductor device shown in FIG3 , the second semiconductor layer of the IGBT region of the semiconductor device shown in FIG4 also includes a third conductive material region 421 and a first semiconductor region 422. The second semiconductor layer of the diode region of the semiconductor device shown in FIG4 includes a first conductive material region 423. The second semiconductor layer of the MOSFET region of the semiconductor device shown in FIG4 includes a second conductive material region 424 and a second semiconductor region 425. Unlike the semiconductor device shown in FIG3 , the first conductive material region, the second conductive material region, and the third conductive material region in the semiconductor device shown in FIG4 penetrate the second semiconductor layer 420 and the fifth semiconductor layer 450 and contact the first semiconductor layer 410 and / or the pillar 413. For other features of the third conductive material region 421, the second conductive material region 424, the first semiconductor region 422, the second semiconductor region 425, and the first conductive material region 423, reference can be made to the description of the embodiment shown in FIG3 . For the sake of brevity, these features are not further described here. Similarly, a metal layer may be provided below the fourth semiconductor layer 440 and the third semiconductor layer 430 as a collector electrode (not shown).

[0141] In some scenarios, the fifth semiconductor layer 450 can be referred to as a carrier storage (CS) layer. The sixth semiconductor layer 460 can be referred to as a buffer layer. The semiconductor device shown in Figure 4 is provided with both a CS layer and a buffer layer. In some embodiments, only one CS layer can be provided above the first surface of the first semiconductor layer of the semiconductor device. In other words, the semiconductor layer in the semiconductor device can include only the first semiconductor layer 410, the second semiconductor layer 420, the third semiconductor layer 430, the fourth semiconductor layer 440, and the fifth semiconductor layer 450 as shown in Figure 4. In other embodiments, only one buffer layer can be provided below the second surface of the first semiconductor layer of the semiconductor device. In other words, the semiconductor layer of the semiconductor device can include only the first semiconductor layer 410, the second semiconductor layer 420, the third semiconductor layer 430, the fourth semiconductor layer 440, and the sixth semiconductor layer 460 as shown in Figure 4.

[0142] The conductive materials in the first conductive material region, the second conductive material region, and the third conductive material region in the semiconductor devices shown in Figures 3 and 4 can be at the same potential as the gate or the emitter. If the conductive material region is at the same potential as the gate, then the conductive material region can be called a gate electrode; if the conductive material region is at the same potential as the emitter, then the conductive material region can be called an emitter electrode.

[0143] For example, in some embodiments, the conductive materials of the third conductive material region and the second conductive material region may be at the same potential as the gate. In this case, the third conductive material region may also be referred to as the first gate electrode, and the second conductive material region may also be referred to as the second gate electrode. For another example, in some embodiments, the first conductive material region is at the same potential as the emitter. In this case, the third conductive region may be referred to as the emitter electrode.

[0144] For another example, in some other embodiments, some of the plurality of third conductive material regions are at the same potential as the gate, and another portion of the third conductive material regions are at the same potential as the emitter.

[0145] For another example, in some other embodiments, some of the plurality of second conductive material regions are at the same potential as the gate, and another portion of the plurality of second conductive material regions are at the same potential as the emitter.

[0146] FIG5 is a schematic diagram of another semiconductor device provided according to an embodiment of the present application. The semiconductor device shown in FIG5 includes: a first semiconductor layer 510, a second semiconductor layer 520, a third semiconductor layer 530, and a fourth semiconductor layer 540. The first semiconductor layer 530 includes: a pillar 513, and a region 514 of the first conductivity type. The second semiconductor layer 520 includes: a third conductive material region 521, a second conductive material region 524, a first semiconductor region 522, and a second semiconductor region 525. In addition, the second semiconductor layer 520 also includes a first conductive material region 523, a fourth conductive material region 526, and a fifth conductive material region 527. Similarly, a metal layer can be provided below the fourth semiconductor layer 540 and the third semiconductor layer 530 as a collector electrode (not shown in the figure).

[0147] In some embodiments, the third conductive material region 521 and the second conductive material region 522 are at the same potential as the gate, and the first conductive material region, the fourth conductive material region, and the fifth conductive material region are at the same potential as the emitter. In this case, the third conductive material region 521 and the second conductive material region 522 can also be referred to as the first gate electrode and the second gate electrode, respectively, and the first conductive material region 523, the fourth conductive material region 526, and the fifth conductive material region 527 can be referred to as the first emitter electrode, the second emitter electrode, and the third emitter electrode, respectively. For ease of description, in this case, the IGBT region of the semiconductor device shown in Figure 5 includes multiple gate electrodes (first gate electrodes) and multiple emitter electrodes (second emitter electrodes). The electrodes included in the diode region are all emitter electrodes (first emitter electrodes). The MOSFET region includes multiple gate electrodes (second gate electrodes) and multiple emitter electrodes (third emitter electrodes).

[0148] The structure of the semiconductor device shown in FIG3 is the same as the structure of the semiconductor device shown in FIG5 . The conductivity type of each component in the semiconductor device shown in FIG5 is the same as the conductivity type of the semiconductor device shown in FIG3 . For example, the conductivity type of region 513 is the first conductivity type, and the conductivity type of pillar 514 is the second conductivity type. In addition, in some embodiments, a CS layer may be provided above the first surface 511 and / or a buffer layer may be provided below the second surface 512.

[0149] The semiconductor devices shown in Figures 3 to 5 have an IGBT region, a diode region, and a MOSFET region sequentially arranged along a first direction. For ease of description, this arrangement is referred to as a first arrangement or a boundary arrangement.

[0150] Figure 6 is a schematic diagram of another semiconductor device according to an embodiment of the present application. The semiconductor device shown in Figure 6 comprises an IGBT region, a first MOSFET region, a diode region, and a second MOSFET region, arranged sequentially along a first direction. For ease of description, this arrangement will be referred to as the second arrangement or internal arrangement.

[0151] The semiconductor device shown in Figure 6 includes a first semiconductor layer 610, a second semiconductor layer 620, a third semiconductor layer 630 and a fourth semiconductor layer 640, wherein the second semiconductor layer 620 is located above the first surface 611 of the first semiconductor layer 610, and the third semiconductor layer 630 and the fourth semiconductor layer 640 are located below the second surface 612 of the first semiconductor layer 610.

[0152] The conductivity type of the first semiconductor layer 610 is the first conductivity type. The first semiconductor layer 610 preferably includes a plurality of pillars 613. The pillars 613 are arranged along the first direction. The conductivity type of the pillars 613 is the second conductivity type. In other words, in addition to the region of the first conductivity type, the first semiconductor layer 610 also includes a region of the second conductivity type. The region of the second conductivity type is the pillar 613, and the region of the first conductivity type is the region 614. The pillar 613 can also be referred to as the first pillar, and the region 614 can also be referred to as the second pillar. In other words, the first semiconductor layer 610 includes a plurality of first pillars and a plurality of second pillars arranged along the first direction, the conductivity type of the first pillars is the second conductivity type, and the conductivity type of the second pillars is the first conductivity type. The first pillars and the second pillars are arranged alternately.

[0153] The second semiconductor layer of the IGBT region includes a plurality of third conductive material regions 621 and a plurality of first semiconductor regions 622 .

[0154] The second semiconductor layer of the diode region includes a plurality of first conductive material regions 623 .

[0155] Comparing the first MOSFET region and the second MOSFET region reveals that the structure and components of the first MOSFET region are identical to those of the second MOSFET region. For example, from top to bottom, the first MOSFET region and the second MOSFET region comprise, in order, a second semiconductor layer 620, a first semiconductor layer 610, and a third semiconductor layer 630. Both the first MOSFET region and the second MOSFET region include multiple second semiconductor regions 625 and multiple second conductive material regions 624. As can be seen in FIG6 , the number of second conductive material regions 624 included in the first MOSFET region is greater than the number of second conductive material regions 624 included in the second MOSFET region. However, in other embodiments, the number of second conductive material regions included in the first MOSFET region may be equal to or less than the number of second conductive material regions included in the second MOSFET region. Similarly, in FIG6 , the number of second semiconductor regions 625 included in the first MOSFET region is greater than the number of second semiconductor regions 625 included in the second MOSFET region. However, in other embodiments, the number of second semiconductor regions included in the first MOSFET region may be equal to or less than the number of second semiconductor regions included in the second MOSFET region. Similar to FIG3 , the third conductive material region and the second conductive material region are merely used to distinguish between conductive material regions located in the IGBT region and conductive material regions located in the MOSFET region. Similarly, the first semiconductor region and the second semiconductor region are also used to distinguish between the semiconductor region located in the IGBT region and the semiconductor region located in the MOSFET region.

[0156] As can be seen from FIG3 , the semiconductor device shown in FIG6 is equivalent to the MOSFET region shown in FIG3 being divided into two by the diode region, thereby obtaining two MOSFET regions.

[0157] The conductivity type of each component of the semiconductor device shown in FIG6 is the same as the conductivity type of the corresponding component of the semiconductor device shown in FIG3 , and will not be described again for the sake of brevity.

[0158] Similarly, in some embodiments, the semiconductor device shown in FIG. 6 may also include a CS layer disposed above the first surface 611 and / or a buffer layer inserted below the second surface 612 .

[0159] In the first arrangement, the conductive material regions in the second semiconductor layer of the IGBT region may be entirely gate electrodes (i.e., at the same potential as the gate), or may include part of the gate electrode and part of the emitter electrode (i.e., at the same potential as the emitter). Similarly, in the second arrangement, the conductive material regions in the second semiconductor layer of the IGBT region may be entirely gate electrodes, or may include part of the gate electrode and part of the emitter electrode. Similarly, in the first arrangement, the conductive material regions in the second semiconductor layer of the MOSFET region may be entirely gate electrodes, or may include part of the gate electrode and part of the emitter electrode. In the second arrangement, the conductive material regions in the second semiconductor layer of the first IGBT region may be entirely gate electrodes, or may include part of the gate electrode and part of the emitter electrode. The conductive material regions in the second semiconductor layer of the second IGBT region may be entirely gate electrodes, or may include part of the gate electrode and part of the emitter electrode.

[0160] FIG7 is a schematic diagram of another semiconductor device according to an embodiment of the present application. The semiconductor device shown in FIG7 includes a first semiconductor layer 710 , a second semiconductor layer 720 , a third semiconductor layer 730 and a fourth semiconductor layer 740 .

[0161] The structure of the first semiconductor layer 710 is the same as that of the first semiconductor layer in Figures 3 to 6. The first semiconductor layer 710 includes a plurality of pillars 713 and regions 714 arranged along a first direction.

[0162] Similarly, the second semiconductor layer 720 is located above the first surface 711 of the first semiconductor layer 710 , and the third semiconductor layer 730 and the fourth semiconductor layer 740 are located below the second surface 712 of the first semiconductor layer 710 .

[0163] Along the first direction, the semiconductor device includes an IGBT region, a diode region, and a MOSFET region in sequence. The second semiconductor layer 720 in the IGBT region includes a third conductive material region 722 and a first semiconductor region 721. The second semiconductor layer 720 in the diode region includes a first conductive material region 323. The second semiconductor layer 720 in the MOSFET region includes a second conductive material region 724 and a second semiconductor region 725. Similarly, the third conductive material region and the second conductive material region here are only used to distinguish the conductive material region located in the IGBT region from the conductive material region located in the MOSFET region. Similarly, the first semiconductor region and the second semiconductor region are also used to distinguish the semiconductor region located in the IGBT region from the semiconductor region located in the MOSFET region.

[0164] The conductivity type of each component of the semiconductor device shown in FIG. 7 is the same as the conductivity type of the corresponding component of the semiconductor device shown in FIG. 3 , and will not be described again for the sake of brevity.

[0165] Compared to the semiconductor device shown in FIG3 , the semiconductor device shown in FIG7 further includes a plurality of floating regions 726. The floating regions in the semiconductor device shown in FIG7 correspond one-to-one with the pillars 713, with each floating region penetrating the second semiconductor layer and contacting a corresponding pillar. The conductivity type of the floating region is the same as the conductivity type of the corresponding pillar. In other words, the conductivity type of the floating region is the second conductivity type.

[0166] Alternatively, in other embodiments, only some of the pillars in the semiconductor device may have corresponding floating regions. Similar to the semiconductor device shown in FIG7 , the floating regions corresponding to these pillars also penetrate the second semiconductor layer and contact the corresponding pillars.

[0167] Similarly, a CS layer may be added above the first surface 711 of the first semiconductor layer 710 of the semiconductor device shown in FIG7 and / or a buffer layer may be added below the second surface 712. In addition, the conductive material regions in the second semiconductor layer of the IGBT region and the MOSFET region of the semiconductor device shown in FIG7 are all equipotential with the gate. In other embodiments, some of the conductive material regions in the second semiconductor layer of the IGBT region and the MOSFET region of the semiconductor device shown in FIG7 may also be equipotential with the emitter. In other words, similar to the above embodiment, the conductive material regions in the second semiconductor layer of the IGBT region and the MOSFET region shown in FIG7 may include a conductive material region equipotential with the emitter and a conductive material region equipotential with the gate.

[0168] Similarly, the semiconductor device shown in FIG. 7 may further include a metal layer below the third semiconductor layer 730 and the fourth semiconductor layer 740 as a collector electrode.

[0169] As can be seen, the semiconductor device shown in FIG7 is a semiconductor device of the first arrangement. The semiconductor device of the second arrangement shown in FIG6 may also include a floating region. For example, in some embodiments, each pillar 613 in the semiconductor device shown in FIG6 has a corresponding floating region. For another example, in other embodiments, some pillars 613 in the semiconductor device shown in FIG6 have corresponding floating regions. The floating region penetrates the second semiconductor layer and contacts the corresponding pillar.

[0170] As described above, in some embodiments, the semiconductor device shown in Figures 5 to 7 may include a buffer layer above the first surface of the first semiconductor layer. In this case, the conductive material region needs to penetrate the second semiconductor layer and the buffer layer. Accordingly, if the semiconductor device also includes a floating region, the floating region also needs to penetrate the second semiconductor layer and the buffer layer.

[0171] In some embodiments, if the conductivity type of the floating region is P-type, the floating region may also be referred to as a floating P-type region.

[0172] FIG8(a) shows the electron injection direction (solid arrows) and the hole injection direction (dashed arrows) of the semiconductor device in the first arrangement mode (edge ​​arrangement).

[0173] FIG8(b) shows the electron injection direction (solid arrows) and the hole injection direction (dashed arrows) of the semiconductor device in the second arrangement (inner arrangement).

[0174] Assume that the first conductivity type is N-type and the second conductivity type is P-type. Then, as shown in (a) of Figure 8 and (b) of Figure 8, when a forward voltage is applied to the diode region, the N-type cathode region of the diode is used to inject electrons from the cathode direction. If the conductive material region located in the diode is at the same potential as the emitter, the formation of a channel can be avoided. When a forward voltage is applied to the gate, holes can be injected from the second semiconductor layer to the N-type region of the first semiconductor layer, which can reduce the voltage drop in the synchronous rectification mode, thereby improving the synchronous rectification performance of the semiconductor device.

[0175] In some embodiments, the second semiconductor layer of the diode region may not be provided with semiconductor regions that can serve as emitter regions, such as the first semiconductor region and the second semiconductor region, so as to prevent electron current from flowing to the emitter.

[0176] The ratio of the diode area to the total area (i.e., the diode area + MOSFET area + IGBT area) affects the current conduction characteristics of the diode under reverse bias conditions and the current conduction characteristics of the IGBT and MOSFET under forward bias conditions. The larger the ratio of the diode area to the total area, the smaller the forward voltage drop at high currents during reverse conduction. The larger the ratio of the diode area to the total area, the larger the forward voltage drop at both high and low currents during forward conduction.

[0177] The diode formed by the diode region in the semiconductor device of FIG. 3 to FIG. 8 and the body diode of the MOSFET region may constitute a FWD.

[0178] FIG9 shows a reverse current (IR)-reverse voltage (VR) characteristic curve of a semiconductor element provided according to the technical solution of the present application.

[0179] As shown in Figure 9, when a forward voltage is applied to the gate, the reverse voltage drops significantly due to hole injection from the diode. Furthermore, the downward trend in reverse voltage becomes more pronounced as the ratio of the diode area to the total area increases.

[0180] In some embodiments, it can be considered that what is shown in Figures 3 to 8 is a cell of the semiconductor device provided by the embodiment of the present application, wherein the IGBT region, the MOSFET region, and the diode region are three sub-cells of the cell. Similarly, the first MOSFET region and the second MOSFET region can also be considered as two sub-cells. The semiconductor device provided by the embodiment of the present application may include one or more cells. The embodiment of the present application does not limit the number of cells included in a semiconductor device.

[0181] FIG10 is a schematic block diagram of another semiconductor device according to an embodiment of the present application. The semiconductor device includes an IGBT region, a diode region, and a MOSFET region along a first direction. The first, second, and third directions of the semiconductor device are perpendicular to each other, with the second direction being the thickness direction of the semiconductor device.

[0182] The MOSFET region of the semiconductor device includes a first semiconductor layer 1010 , a second semiconductor layer 1020 , a third semiconductor layer 1030 , a fourth semiconductor layer 1040 , a fifth semiconductor layer 1050 and a sixth semiconductor layer 1060 .

[0183] The conductivity type of the first semiconductor layer 1010 is the first conductivity type. The first semiconductor layer includes a first surface 1011 and a second surface 1012 relative to each other. The first semiconductor layer also includes a plurality of pillars 1013, which are arranged along a first direction and have a conductivity type of the second conductivity type. In addition to the pillars 1013, the first semiconductor layer 1010 also includes a region 1014 of the first conductivity type. As shown in FIG10 , the region 1014 can also be a pillar. Therefore, the pillar 1013 can also be referred to as the first pillar 1013, and the region 1014 can also be referred to as the second pillar 1014. If the first conductivity type is N-type and the second conductivity type is P-type, then the first pillar can also be referred to as a P-pillar and the second pillar can also be referred to as an N-pillar.

[0184] The conductivity type of the second semiconductor layer 1020 is the second conductivity type. The second semiconductor layer 1020 is disposed on the first surface 1011 of the first semiconductor layer 1010. As shown in FIG10 , a fifth semiconductor layer 1050 is further included between the second semiconductor layer 1020 and the first semiconductor layer 1010. The conductivity type of the fifth semiconductor layer 1050 is the first conductivity type.

[0185] The conductivity type of the third semiconductor layer 1030 is the first conductivity type. The third semiconductor layer 1030 is disposed below the second surface 1012 of the first semiconductor layer 1010. As shown in FIG10 , a sixth semiconductor layer 1060 is further included between the third semiconductor layer 1030 and the first semiconductor layer 1010. The conductivity type of the sixth semiconductor layer 1060 is the first conductivity type.

[0186] In some embodiments, the fifth semiconductor layer 1050 and the sixth semiconductor layer 1060 may also be referred to as buffer layers. The semiconductor device shown in FIG10 includes two buffer layers (i.e., the fifth semiconductor layer 1050 and the sixth semiconductor layer 1060). Other semiconductor devices provided in embodiments of the present application may include only one buffer layer. For example, in some embodiments, the semiconductor device may include only the fifth semiconductor layer 1050 or the sixth semiconductor layer 1060 as shown in FIG10. Other semiconductor devices provided in embodiments of the present application may not include a buffer layer. In other words, in some embodiments, the semiconductor device may not include the fifth semiconductor layer 1050 and the sixth semiconductor layer 1060 as shown in FIG10.

[0187] The fourth semiconductor layer 1040 is disposed on the surface of the second semiconductor layer 1020 facing away from the first semiconductor layer. The fourth semiconductor layer 1040 includes: a first semiconductor region 1041 and a second semiconductor region (not shown in FIG. 10 ) disposed in parallel on either side of the fourth semiconductor layer; a plurality of parallel conductive material regions 1045; and a plurality of parallel third semiconductor regions 1043. In some embodiments, the conductive material regions 1045 can be at the same potential as the gate electrode. In this case, the conductive material regions 1045 can also be referred to as gate electrodes.

[0188] The first semiconductor region 1041 and the second semiconductor region are parallel to the first direction and have the first conductivity type.

[0189] The conductive material region 1045 is parallel to the third direction.

[0190] The third semiconductor region 1043 is parallel to the third direction and has the second conductivity type.

[0191] The fourth semiconductor layer 1040 further includes a fourth semiconductor region (not shown in the figure). The fourth semiconductor region is located between the third semiconductor region 1043 and the conductive material region 1045. The conductivity type of the fourth semiconductor region is the second conductivity type.

[0192] The semiconductor device may be a planar gate structure semiconductor device or a trench gate structure semiconductor device. For ease of description, the semiconductor device provided by the present application is introduced below using a trench gate as an example.

[0193] The conductivity type of the second pillar 1014, the fifth semiconductor layer 1050, the sixth semiconductor layer 1060, the third semiconductor layer 1030, the first semiconductor region 1041, and the second semiconductor region in the first semiconductor layer 1010 are all the first conductivity type. For ease of description, these regions of the first conductivity type may be referred to as first-category regions. Similarly, the conductivity type of the first pillar 1013, the second semiconductor layer 1020, the third semiconductor region 1043, the fourth semiconductor region, and the seventh semiconductor layer 1070 in the IGBT region are all the second conductivity type. Similarly, for ease of description, these regions of the second conductivity type may be referred to as second-category regions.

[0194] In some embodiments, the impurity concentrations of the first type of regions may be completely identical. In other words, the impurity concentrations of any two semiconductor layers (semiconductor regions) in the first semiconductor layer 1010, including the second pillar 1014, the fifth semiconductor layer 1050, the sixth semiconductor layer 1060, the third semiconductor layer 1030, the first semiconductor region 1041, or the second semiconductor region, may be completely identical.

[0195] In other embodiments, the impurity concentrations of the first type of regions are completely different. In other words, the impurity concentrations of any two semiconductor layers (semiconductor regions) in the second pillar 1014, the fifth semiconductor layer 1050, the sixth semiconductor layer 1060, the third semiconductor layer 1030, the first semiconductor region 1041, or the second semiconductor region in the first semiconductor layer 1010 are completely different.

[0196] In other embodiments, the impurity concentrations of the first type of regions may not be completely the same. The term "not completely the same" herein includes: the impurity concentrations in certain semiconductor layers and / or regions are the same, but the impurities in these semiconductor layers and / or regions are different from the impurity concentrations in other semiconductor regions and / or semiconductor layers. For example, in some embodiments, the impurity concentrations of the first semiconductor region and the second semiconductor region are the same; the impurity concentrations of the fifth semiconductor layer 1050 and the sixth semiconductor layer 1060 are the same, but the impurity concentration of the sixth semiconductor layer 1060 is different from the impurity concentration of the second pillar 1014, and the impurity concentration of the sixth semiconductor layer 1060 is also different from the impurity concentration of the third semiconductor layer 1030.

[0197] Similarly, in some embodiments, the impurity concentrations of the second type of regions may be completely identical. In other words, the impurity concentrations of any two semiconductor layers (semiconductor regions) among the first pillar 1013, the second semiconductor layer 1020, the third semiconductor region 1043, the fourth semiconductor region, or the seventh semiconductor layer 1070 may be completely identical.

[0198] In other embodiments, the impurity concentrations of the second type regions are completely different. In other words, the impurity concentrations of any two semiconductor layers (semiconductor regions) among the first pillar 1013, the second semiconductor layer 1020, the third semiconductor region 1043, the fourth semiconductor region, or the seventh semiconductor layer 1070 are completely different.

[0199] In other embodiments, the impurity concentrations of the second-type regions may not be completely the same. The term "not completely the same" herein includes: the impurity concentrations in some semiconductor layers and / or regions are the same, but the impurities in these semiconductor layers and / or regions are different from the impurity concentrations in other semiconductor regions and / or semiconductor layers. For example, in some embodiments, the impurity concentrations of the second semiconductor layer 1020 and the fourth semiconductor region are the same, but the impurity concentration of the second semiconductor layer 1020 is different from the impurity concentration of the third semiconductor layer 1043.

[0200] It can be understood that the semiconductor device provided in the embodiment of the present application can be a semiconductor device with a trench gate structure as shown in FIG10 , or a semiconductor device with a planar gate structure.

[0201] The semiconductor device shown in FIG10 includes a MOSFET region and an IGBT region in a first direction. It should be understood that FIG10 represents a single cell of the semiconductor device. The semiconductor device may also include multiple cells as shown in FIG10 . Furthermore, since the MOSFET region and the IGBT region appear alternately in the semiconductor device, it can also be considered that a single cell includes the IGBT region and the MOSFET region in sequence.

[0202] Optionally, in some embodiments, the cell of the semiconductor device may further include regions other than the MOSFET region and the IGBT region shown in FIG10 . For example, in some embodiments, the semiconductor device may further include a diode region. For example, the MOSFET region of the semiconductor device shown in FIG3 to FIG5 may also employ the same structure as the MOSFET region shown in FIG10 . For another example, at least one of the first MOSFET region or the second MOSFET region in the semiconductor device shown in FIG6 may also employ the same structure as the MOSFET shown in FIG10 .

[0203] Figure 11 is a three-dimensional schematic diagram of a semiconductor device provided according to an embodiment of the present application. The semiconductor device shown in Figure 11 is a three-dimensional schematic diagram of the region 1080 shown in Figure 10 .

[0204] The semiconductor device shown in FIG. 11 includes a first semiconductor layer 1010 , a second semiconductor layer 1020 , a third semiconductor layer 1030 , a fourth semiconductor layer 1040 , a fifth semiconductor layer 1060 and a sixth semiconductor layer 1060 .

[0205] The first semiconductor layer 1010 includes a first surface 1011 and a second surface 1012. The first semiconductor layer also includes a region 1014 of the first conductivity type (also referred to as a second pillar 1014) and a pillar 1013 of the second conductivity type (also referred to as a first pillar 1013).

[0206] For relevant information about the second semiconductor layer 1020 , the third semiconductor layer 1030 , the fifth semiconductor layer 1050 and the sixth semiconductor layer 1060 , reference may be made to the description of the above embodiments, which will not be elaborated here for the sake of brevity.

[0207] 11 shows a fourth semiconductor region 1044 and a second semiconductor region 1042 which are not shown in FIG 10. In addition, the fourth semiconductor layer 1040 further includes a first semiconductor region 1041, a third semiconductor region 1043 and a conductive material region 1045.

[0208] As shown in Figure 11, the first semiconductor region 1041 and the second semiconductor region 1042 are arranged in parallel on both sides of the fourth semiconductor layer 1040. The first semiconductor region 1040 and the second semiconductor region 1042 are parallel to a first direction. The first direction is perpendicular to the second direction, and the second direction is the thickness direction of the semiconductor device. The third direction is also perpendicular to the first and second directions. In other words, the first, second, and third directions are perpendicular to each other. In some embodiments, the first direction may also be referred to as the x-direction, the second direction may also be referred to as the y-direction, and the third direction may also be referred to as the z-direction.

[0209] FIG. 11 shows two third semiconductor regions 1043 , where the two third semiconductor regions 1043 are arranged in parallel, and the third semiconductor regions are parallel to the third direction.

[0210] As shown in FIG. 11 , the fourth semiconductor region 1044 is located between the conductive material region 1045 and the third semiconductor region 1043 .

[0211] Figure 11 shows only one conductive material region 1045. However, as described above, the conductive material region 1045 shown in Figure 11 is also arranged in parallel with the third direction in the fourth semiconductor region 1040 along with other conductive material regions. Figure 12 is a top view of the semiconductor device shown in Figure 10. The top view shown in Figure 12 shows the conductive material regions 1045 arranged in parallel. Two conductive material regions 1045 are shown in Figure 12. For ease of description, these two conductive material regions are labeled as 1045-1 and 1045-2 in Figure 12. As shown in Figure 12, the conductive material region 1045-1 is parallel to the conductive material region 1045-2, and the conductive material region 1045-1 is parallel to the third direction. In addition to the conductive material regions, Figure 12 also shows three third semiconductor regions. Also for ease of description, the three third semiconductor regions shown in Figure 12 are labeled as 1043-1, 1043-2, and 1043-3, respectively. 12 , the third semiconductor device 1043 - 1 is parallel to the third semiconductor region 1043 - 2 , and the third semiconductor region 1043 - 2 is parallel to the third semiconductor region 1043 - 3 . Furthermore, these three third semiconductor regions are parallel to the third direction.

[0212] The third semiconductor region and the conductive material region divide the first semiconductor region into a plurality of first sub-semiconductor regions. As shown in FIG12 , the third semiconductor region and the conductive material region divide the first semiconductor region 1041 into six first sub-semiconductor regions, namely, first sub-semiconductor regions 1041-1 through 1041-6. Similarly, the third semiconductor region and the conductive material region divide the second semiconductor region into a plurality of second sub-semiconductor regions. As shown in FIG12 , the third semiconductor region and the conductive material region divide the second semiconductor region 1042 into six second sub-semiconductor regions, namely, second sub-semiconductor regions 1042-1 through 1042-2.

[0213] FIG12 also shows six fourth semiconductor regions, namely, fourth semiconductor regions 1044-1 through 1044-6. As shown in FIG12 , the fourth semiconductor regions are located between the conductive material region and the third semiconductor region. For example, fourth semiconductor region 1044-2 is located between third semiconductor region 1043-1 and conductive material region 1045-1. Furthermore, fourth semiconductor region 1044-2 is located within the region enclosed by third semiconductor region 1043-1, conductive material region 1045-2, first sub-semiconductor region 1041-2, and second sub-semiconductor region 1042-2. For another example, fourth semiconductor region 1044-5 is located between conductive material region 1045-2 and third semiconductor region 1043-3. Furthermore, fourth semiconductor region 1044-5 is located within the region enclosed by conductive material region 1045-2, third semiconductor region 1043-3, first sub-semiconductor region 1041-5, and second sub-semiconductor region 1042-5.

[0214] FIG. 13 shows another arrangement of the semiconductor regions included in the fourth semiconductor layer.

[0215] As shown in FIG13(a), a first semiconductor region 1141 and a second semiconductor region 1142 are arranged in parallel on both sides of the fourth semiconductor layer, and the first semiconductor region 1141 and the second semiconductor region 1142 are parallel to the third direction. The first semiconductor region 1141 is divided into a plurality of first sub-semiconductor regions, namely, first sub-semiconductor regions 1141-1 to 1141-6, by the third semiconductor regions 1143-1 to 1143-3, the conductive material region 1145-1, and the conductive material region 1145-2. Each of the fourth semiconductor regions 1144-1 to 1144-6 corresponds to a third semiconductor region and a conductive material region, and each conductive material region is between the corresponding third semiconductor region and conductive material region. The plurality of third semiconductor regions are arranged in parallel and parallel to the third direction, and the plurality of conductive material regions are arranged in parallel and parallel to the third direction.

[0216] As shown in FIG13(b), a first semiconductor region 1141 and a second semiconductor region 1142 are arranged parallel to each other on either side of the fourth semiconductor layer, and the first semiconductor region 1141 and the second semiconductor region 1142 are parallel to the third direction. The first semiconductor region 1141 includes multiple recesses, each of which corresponds to a third semiconductor region or a conductive material region, and each recess contains a portion of a corresponding third semiconductor region or conductive material region. For example, the first recess from left to right corresponds to the third semiconductor region 1143-1, in which a portion of the third semiconductor region 1143-1 is disposed; the second recess from left to right corresponds to the conductive material region 1145-1, in which a portion of the conductive material region 1145-1 is disposed. FIG13(b) also shows third semiconductor regions 1143-1 through 1143-3. These third semiconductor regions are arranged in parallel and parallel to the third direction; the conductive material regions 1145-1 and 1145-2 are arranged in parallel and parallel to the third direction. Each of the fourth semiconductor regions 1141 - 1 to 1144 - 6 corresponds to one third semiconductor region and one conductive material region, and each conductive material region is between the corresponding third semiconductor region and the conductive material region.

[0217] As shown in FIG13(c), the first semiconductor region 1141 and the second semiconductor region 1142 are arranged parallel to each other on both sides of the fourth semiconductor layer, and the first semiconductor region 1141 and the second semiconductor region 1142 are parallel to the third direction. The first semiconductor region 1141 is divided into a plurality of first sub-semiconductor regions, namely, first sub-semiconductor regions 1141-1 to 1141-4, by the third semiconductor regions 1143-1 to 1143-3. The first semiconductor region 1141 also includes two recesses, which are respectively used to accommodate a portion of the conductive material region 1145-1 and the conductive material region 1145-2. Similarly, the second semiconductor region 1142 is also divided into a plurality of second sub-semiconductor regions, namely, second sub-semiconductor regions 1142-1 to 1142-2, by the third semiconductor regions 1143-1 to 1143-3. The second semiconductor region 1142 also includes two recesses, here, the two recesses are respectively used to accommodate a portion of the conductive material region 1145-1 and the conductive material region 1145-2. FIG13(c) also shows third semiconductor regions 1143-1 to 1143-3. These third semiconductor regions are arranged in parallel and parallel to the third direction; conductive material regions 1145-1 and 1145-2 are arranged in parallel and parallel to the third direction. Each of the fourth semiconductor regions 1141-1 to 1144-6 corresponds to a third semiconductor region and a conductive material region, with each conductive material region being between the corresponding third semiconductor region and conductive material region.

[0218] The arrangements of the semiconductor regions and the conductive material regions shown in FIG13(a), FIG13(b), and FIG13(c) are only some possible arrangements provided by the embodiments of the present application. Based on the disclosure of the present application, those skilled in the art may also derive other arrangements, which shall be within the scope of protection of the present application.

[0219] As described above, the fifth semiconductor layer 1050 shown in Figures 10 and 11 is a CS layer, and the sixth semiconductor layer 1060 is a buffer layer. In some embodiments, the semiconductor device may include only one of the CS layer and the buffer layer (for example, only the fifth semiconductor layer 1050 or the sixth semiconductor layer 1060). In other embodiments, the semiconductor device may not include either the CS layer or the buffer layer.

[0220] FIG14 is a schematic diagram of another semiconductor device provided according to an embodiment of the present application.

[0221] The semiconductor device shown in FIG. 14 includes a first semiconductor layer 1410 , a second semiconductor layer 1420 , a third semiconductor layer 1430 , and a fourth semiconductor layer 1440 .

[0222] First semiconductor layer 1410 includes a region 1414 (also referred to as a second pillar 1414) having a first conductivity type and a pillar 1413 (also referred to as a first pillar 1413) having a second conductivity type. Region 1414 and pillar 1413 are arranged along a first direction, which is perpendicular to a second direction, which is the thickness direction of the semiconductor device.

[0223] The second semiconductor layer 1420 is located on the first surface 1411 of the first semiconductor layer 1410 , and the third semiconductor layer 1430 is located under the second surface 1412 of the first semiconductor layer 1410 .

[0224] The conductivity type of the second semiconductor layer 1420 is the second conductivity type, and the conductivity type of the third semiconductor layer is the first conductivity type.

[0225] The fourth semiconductor layer 1440 is disposed on a surface of the second semiconductor layer 1420 facing away from the first semiconductor layer 1410 . The fourth semiconductor layer 1440 includes a first semiconductor region 1441 , a second semiconductor region 1442 , a third semiconductor region 1443 , a fourth semiconductor region 1444 and a conductive material region 1445 .

[0226] It can be seen that, compared with the semiconductor devices shown in Figures 10 and 11, the semiconductor device shown in Figure 14 does not include a buffer layer (i.e., the fifth semiconductor layer 1050) between the second semiconductor layer and the first semiconductor layer, and a buffer layer (i.e., the sixth semiconductor layer 1060) between the first semiconductor layer and the third semiconductor layer. Apart from this, the other components of the two semiconductor devices are arranged in the same manner. For the sake of brevity, they will not be described in detail here.

[0227] In the semiconductor devices shown in Figures 10 to 14, the conductive material regions in the fourth semiconductor layer are all at the same potential as the gate. In other embodiments, the fourth semiconductor layer may also include a conductive material region at the same potential as the emitter. In other words, the fourth semiconductor layer may include a conductive material region at the same potential as the emitter and a conductive material region at the same potential as the gate. The two adjacent conductive material regions are arranged in parallel and parallel to the third direction.

[0228] FIG15 shows the hole direction and electron direction of the semiconductor device shown in FIG11. As shown in FIG15, electrons are injected upward from the bottom of the MOSFET region. After the electrons are injected into the fourth semiconductor layer, they continue to be injected into the first semiconductor region and the second semiconductor region arranged in parallel. Therefore, the electron transmission path is greater than the side length of the drift region (i.e., Len in FIG15). D In this case, a lateral voltage drop is generated. This lateral voltage drop causes the PN junction of the channel-substrate (CS) layer to be forward biased. Holes are injected from the fourth semiconductor region between the first and second parallel semiconductor regions, resulting in a lower voltage drop across the body diode of the MOSFET region in synchronous rectification mode, thereby improving the synchronous rectification performance of the semiconductor device.

[0229] Fig. 16 is a volt-ampere characteristic curve of the body diode of the MOSFET region of the semiconductor device shown in Fig. 11. As can be seen from Fig. 16, when the voltage is less than 0, the voltage drop is small.

[0230] The present application also provides a control method that can be used to control a circuit including a semiconductor device as described in the above embodiments. The method includes: monitoring the current value of the main current of the semiconductor device during a dead time when the current direction of the semiconductor device is from emitter to collector; maintaining the gate of the semiconductor device in a closed state when the current value of the main current is greater than a preset value; and opening the gate of the semiconductor device after the dead time when the current value of the main current is less than or equal to the preset value. This method can select a smaller reverse voltage in both bidirectional and unidirectional modes, thereby reducing power loss in the reverse conduction state.

[0231] FIG17 is a schematic diagram of a control method provided according to an embodiment of the present application.

[0232] The semiconductor device 1701 and the semiconductor device 1702 shown in FIG17 are equivalent circuit diagrams of semiconductor devices provided according to embodiments of the present application. Assume that the current direction of the semiconductor device 1702 is from the emitter to the collector. In this case, the main current (i.e., I F ) (i.e. monitoring starts from time t1). If the main current value is greater than the preset value (i.e. I set ), the semiconductor device 1702 is kept in the off state (i.e., bidirectional mode); if the main current value is less than or equal to the preset value, the gate of the semiconductor device 1702 is opened after the dead time (i.e., time t2) (i.e., unidirectional mode).

[0233] The present application also provides a control method that can be used to control a circuit including a semiconductor device as described in the above embodiments. The method includes: when the current direction of the semiconductor device is from emitter to collector, determining a first voltage value and a second voltage value, wherein the first voltage value is the terminal voltage of the semiconductor device during dead time, and the second voltage value is the terminal voltage after the gate of the semiconductor device is opened; when the difference between the second voltage value and the first voltage value is greater than a preset value, closing the gate of the semiconductor device; and when the difference between the second voltage value and the first voltage value is not greater than the preset value, keeping the gate of the semiconductor device open. This method can select a smaller reverse voltage in both bidirectional mode and unidirectional mode, thereby reducing power loss in the reverse conduction state.

[0234] FIG18 is a schematic diagram of a control method provided according to an embodiment of the present application.

[0235] The semiconductor device 1801 and the semiconductor device 1802 shown in FIG18 are equivalent circuit diagrams of semiconductor devices provided according to embodiments of the present application. Assume that the current direction of the semiconductor device 1802 is from the emitter to the collector. In this case, the voltage value of the terminal voltage of the semiconductor device 1802 during the dead time (i.e., V1) and the voltage value of the terminal voltage of the semiconductor device 1802 after the gate of the semiconductor device 1802 is opened (i.e., V2) can be monitored. If V2-V1 is greater than the preset value (i.e., V set ), the gate of the semiconductor device 1802 is turned off (i.e., bidirectional mode); if V2-V1 is not greater than V set , then after the dead time (ie, time t2), the gate of the semiconductor device 1802 is kept open (ie, unidirectional mode).

[0236] FIG19 shows the IR-VR characteristic curve of the semiconductor element provided according to the technical solution of the present application.

[0237] As shown in Figure 19, when the current is greater than IR' or the voltage is greater than VR', the bidirectional mode can maintain a smaller reverse voltage. When the current is less than IR' or the voltage is less than VR', the unidirectional mode can maintain a smaller reverse voltage.

[0238] An embodiment of the present application also provides a method for manufacturing a semiconductor device, which is used to manufacture any of the above-mentioned semiconductor devices.

[0239] In some embodiments, the semiconductor device fabricated by the fabrication method is divided along a first direction into an IGBT region for forming an insulated gate bipolar transistor (IGBT), a diode region for forming a diode, and a MOSFET region for forming a metal oxide semiconductor field effect transistor (MOSFET). The fabrication method comprises: fabricating a first semiconductor layer, wherein the first semiconductor layer has a first conductivity type, the first semiconductor layer comprises a plurality of pillars, the plurality of pillars are arranged along a first direction perpendicular to the thickness direction of the semiconductor device, and the pillars have a second conductivity type; fabricating a second semiconductor layer, wherein the second semiconductor layer is located above the first semiconductor layer and has a second conductivity type; fabricating a third semiconductor layer, wherein the third semiconductor layer is located below the first semiconductor layer and is located in the diode region and the MOSFET region, and has a first conductivity type; fabricating a fourth semiconductor layer, wherein the fourth semiconductor layer is located below the first semiconductor layer and is located in the IGBT region, and has a second conductivity type; and fabricating at least one first conductive material region, wherein the at least one first conductive material region is located in the diode region.

[0240] Optionally, the manufacturing method also includes: at least one first semiconductor region, at least one second semiconductor region, at least one second conductive material region, and a third conductive material region, wherein the at least one third conductive material region and the at least one first semiconductor region are located in the IGBT region, the at least one second conductive material region and the at least one second semiconductor region are located in the MOSFET region, and the conductivity type of the first semiconductor region and the second semiconductor region is the first conductivity type.

[0241] Optionally, the manufacturing method further includes: manufacturing at least one fourth conductive material region, where the at least one fourth conductive material region is located in the IGBT region.

[0242] Optionally, the manufacturing method further includes: manufacturing at least one fifth conductive material region, where the at least one fifth conductive material region is located in the MOSFET region.

[0243] Optionally, the first semiconductor layer is sequentially arranged with the IGBT region, the diode region, and the MOSFET region along the first direction.

[0244] Optionally, the MOSFET region includes a first MOSFET region and a second MOSFET region, and the first semiconductor layer is sequentially arranged with the IGBT region, the first MOSFET region, the diode region and the second MOSFET region along the first direction.

[0245] Optionally, the manufacturing method further includes: manufacturing at least one floating region, the at least one floating region corresponding to at least one of the pillars one by one, the floating region penetrating the second semiconductor layer and contacting the corresponding pillar.

[0246] Optionally, making the third conductive material region includes: forming a third trench, which penetrates the second semiconductor layer and contacts the first semiconductor layer and / or pillar located in the IGBT region, and filling the third trench with a third conductive material; making the second conductive material region includes: forming a second trench, which penetrates the second semiconductor layer and contacts the first semiconductor layer and / or pillar located in the MOSFET region, and filling the second trench with a second conductive material; making the first conductive material region includes: forming a first trench, which penetrates the second semiconductor layer and contacts the first semiconductor layer and / or pillar located in the diode region, and filling the first trench with a first conductive material.

[0247] Optionally, the first semiconductor region and the second semiconductor region are fabricated in a region of the second semiconductor layer away from the first semiconductor layer.

[0248] In other embodiments, the semiconductor device manufactured by the manufacturing method is divided into an IGBT region for forming an insulated gate bipolar transistor (IGBT) and a MOSFET region for forming a metal oxide semiconductor field effect transistor (MOSFET) along a first direction, the first direction, the second direction, and the third direction are perpendicular to each other, and the second direction is the thickness direction of the semiconductor device. The manufacturing method includes: manufacturing a first semiconductor layer, wherein the first semiconductor layer is located in the MOSFET region, the conductivity type of the first semiconductor layer is a first conductivity type, the first semiconductor layer includes a plurality of columns, the plurality of columns are arranged along the first direction, the conductivity type of the columns is a second conductivity type, manufacturing a second semiconductor layer, wherein the second semiconductor layer is located in the MOSFET region, the conductivity type of the second semiconductor layer is the second conductivity type, and the second semiconductor layer is arranged above the first semiconductor layer, manufacturing a third semiconductor layer, wherein the third semiconductor layer is located in the MOSFET region, the conductivity type of the third semiconductor layer is the first conductivity type, and the third semiconductor layer is arranged below the first semiconductor layer, manufacturing a fourth semiconductor layer, wherein the fourth semiconductor layer is located in the MOSFET region, and the fourth semiconductor layer is located in the MOSFET region. A fourth semiconductor layer is arranged on a surface of the second semiconductor layer facing away from the first semiconductor layer. The fourth semiconductor layer includes: a first semiconductor region and a second semiconductor region arranged in parallel on both sides of the fourth semiconductor layer, a plurality of conductive material regions arranged in parallel, and a plurality of third semiconductor regions arranged in parallel. The first semiconductor region and the second semiconductor region are parallel to the first direction, and the conductivity type of the first semiconductor region and the second semiconductor region is the first conductivity type. The conductive material region is parallel to the third direction, and the third semiconductor region is parallel to the third direction. The conductivity type of the third semiconductor region is the second conductivity type. The fourth semiconductor layer also includes a fourth semiconductor region. The fourth semiconductor region is located between the third semiconductor region and the conductive material region. The conductivity type of the fourth semiconductor region is the second conductivity type.

[0249] Optionally, the first semiconductor region is divided into multiple first sub-semiconductor regions by the multiple parallel third semiconductor regions and the multiple parallel conductive material regions; the second semiconductor region is divided into multiple second sub-semiconductor regions by the multiple parallel third semiconductor regions and the multiple parallel conductive material regions.

[0250] Optionally, manufacturing the conductive material region includes: forming a trench, the trench penetrating the second semiconductor layer, and filling the trench with a conductive material.

[0251] Optionally, the fabrication of the fourth semiconductor layer includes: doping the third semiconductor region with impurities of a first concentration, and doping the fourth semiconductor region with impurities of a second concentration, wherein the first concentration is different from the second concentration.

[0252] In some embodiments, the manufacturing method further includes: manufacturing a fifth semiconductor layer, the fifth semiconductor layer is located in the MOSFET region, the conductivity type of the fifth semiconductor layer is the first conductivity type, and the fifth semiconductor layer is located between the first semiconductor layer and the second semiconductor layer.

[0253] In some embodiments, the manufacturing method further includes: manufacturing a sixth semiconductor layer, where the sixth semiconductor layer is located between the first semiconductor layer and the third semiconductor layer, and the conductivity type of the sixth semiconductor layer is the first conductivity type.

[0254] An embodiment of the present application also provides a power conversion circuit, which includes at least any one or more of the above-mentioned semiconductor devices.

[0255] An embodiment of the present application further provides an inverter or an inverter circuit, which includes at least any one or more of the above-mentioned semiconductor devices.

[0256] An embodiment of the present application also provides a chip, which includes at least any one or more of the above-mentioned semiconductor devices.

[0257] Embodiments of the present application also provide an electronic device. In some embodiments, the electronic device includes at least one or more of the aforementioned semiconductor devices. In other embodiments, the electronic device includes the aforementioned power conversion circuit. In other embodiments, the electronic device includes the aforementioned inverter or inverter circuit. In other embodiments, the electronic device includes the aforementioned chip.

[0258] Embodiments of the present application also provide a vehicle. In some embodiments, the vehicle includes any one or more of the aforementioned semiconductor devices. In other embodiments, the vehicle includes the aforementioned power conversion circuit. In other embodiments, the vehicle includes the aforementioned inverter or inverter circuit. In other embodiments, the vehicle includes the aforementioned chip. The vehicle can be a car, an electric bicycle, or the like. The car can be an electric car, a hybrid car, or the like.

[0259] The present application also provides an electric power device. In some embodiments, the electric power device includes any one or more of the above-mentioned semiconductor devices. In other embodiments, the electric power device includes the above-mentioned power conversion circuit. In other embodiments, the electric power device includes the above-mentioned inverter or inverter circuit. In other embodiments, the electric power device includes the above-mentioned chip. The electric power device can be a solar power device (such as a solar power generation device, a photovoltaic water pump, a solar signal light), a charging pile, a charger, etc.

[0260] According to the method provided in the embodiments of the present application, the present application also provides a computer program product, which includes: computer program code, which, when running on a computer, enables the computer to execute each step in the above embodiments.

[0261] According to the method provided in the embodiment of the present application, the present application also provides a computer-readable medium, which stores program code. When the program code is run on a computer, the computer executes the various steps in the above embodiments.

[0262] According to the method provided in an embodiment of the present application, an embodiment of the present application provides a chip system, which includes a logic circuit, which is used to couple with an input / output interface and transmit data through the input / output interface to execute the various steps in the above embodiments.

[0263] An embodiment of the present application provides an electronic device, which includes a processor and a memory. The processor can be a chip. For example, the processor can be a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a graphics processing unit (GPU), a system on chip (SoC), a central processing unit (CPU), a network processor (NP), a digital signal processing circuit (DSP), a microcontroller unit (MCU), a programmable logic device (PLD), other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or other integrated chips.

[0264] During implementation, each step of the above method can be completed by an integrated logic circuit of the hardware in the processor or by instructions in the form of software. The steps of the method disclosed in conjunction with the embodiments of the present application can be directly embodied as being executed by a hardware processor, or can be executed by a combination of hardware and software modules in the processor. The software module can be located in a storage medium mature in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory, and the processor reads the information in the memory and completes the steps of the above method in conjunction with its hardware. To avoid repetition, it will not be described in detail here.

[0265] It should be noted that the processor in the embodiment of the present application can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method embodiment can be completed by an integrated logic circuit of the hardware in the processor or by instructions in the form of software. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the method disclosed in the embodiment of the present application can be directly embodied as being executed by a hardware decoding processor, or can be executed by a combination of hardware and software modules in the decoding processor. The software module can be located in a mature storage medium in the art, such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.

[0266] It is understood that the memory in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct RAM bus RAM (DR RAM). It should be noted that the memory of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0267] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0268] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0269] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0270] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0271] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0272] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0273] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A semiconductor device, characterized in that: include: A first semiconductor layer and a second semiconductor layer, wherein The first semiconductor layer has a first conductivity type, comprises a plurality of columns, and the plurality of columns are arranged along a first direction perpendicular to a thickness direction of the semiconductor device. The columns have a second conductivity type. The second semiconductor layer is disposed above the first semiconductor layer, and the conductivity type of the second semiconductor layer is the second conductivity type; The semiconductor device is divided into an IGBT region for forming an insulated gate bipolar transistor (IGBT), a diode region for forming a diode, and a MOSFET region for forming a metal oxide semiconductor field effect transistor (MOSFET) along the first direction. The semiconductor device further includes a third semiconductor layer and a fourth semiconductor layer, The third semiconductor layer is disposed below the first semiconductor layer and located in the diode region and the MOSFET region, and the conductivity type of the third semiconductor layer is the first conductivity type; The fourth semiconductor layer is disposed below the first semiconductor layer and located in the IGBT region, and the conductivity type of the fourth semiconductor layer is the second conductivity type; The semiconductor device further includes: at least one first conductive material region, wherein the at least one first conductive material region is located in the diode region.

2. The semiconductor device according to claim 1, wherein The semiconductor device further includes: at least one first semiconductor region, at least one second semiconductor region, at least one second conductive material region, and at least one third conductive material region, wherein: The at least one third conductive material and the at least one first semiconductor region are located in the IGBT region; The at least one second conductive material region and the at least one second semiconductor region are located in the MOSFET region, The conductivity type of the first semiconductor region and the second semiconductor region is the first conductivity type.

3. The semiconductor device according to claim 2, wherein The first conductive material region includes a first trench filled with a first conductive material, the first trench penetrates the second semiconductor layer and contacts the first semiconductor layer and / or pillar in the diode region; The second conductive material region includes a second trench filled with a second conductive material, the second trench penetrates the second semiconductor layer and contacts the first semiconductor layer and / or pillar located in the MOSFET region; The third conductive material region includes a third trench filled with a third conductive material. The third trench penetrates the second semiconductor layer and contacts the first semiconductor layer and / or pillar in the IGBT region.

4. The semiconductor device according to any one of claims 1 to 3, wherein: The semiconductor device further includes: at least one fourth conductive material region, and the at least one fourth conductive material region is located in the IGBT region.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that The semiconductor device further includes: at least one fifth conductive material region, wherein the at least one fifth conductive material region is located in the MOSFET region.

6. The semiconductor device according to any one of claims 1 to 5, wherein: The first semiconductor layer is sequentially arranged with the IGBT region, the diode region, and the MOSFET region along the first direction.

7. The semiconductor device according to any one of claims 1 to 6, characterized in that The MOSFET region includes a first MOSFET region and a second MOSFET region. The first semiconductor layer is sequentially arranged with the IGBT region, the first MOSFET region, the diode region and the second MOSFET region along the first direction.

8. The semiconductor device according to any one of claims 1 to 7, wherein: The semiconductor device further includes at least one floating region, the at least one floating region corresponding to at least one pillar in a one-to-one manner, and the floating region penetrates the second semiconductor layer and contacts the corresponding pillar.

9. The semiconductor device according to any one of claims 2 to 8, wherein: The first semiconductor region and the second semiconductor region are located in a region of the second semiconductor layer facing away from the first semiconductor layer.

10. A semiconductor device, characterized in that: include: The semiconductor device is divided into an IGBT region for forming an insulated gate bipolar transistor (IGBT) and a MOSFET region for forming a metal oxide semiconductor field effect transistor (MOSFET) along a first direction, wherein the first direction, the second direction and the third direction are perpendicular to each other, and the second direction is the thickness direction of the semiconductor device. The MOSFET region includes a first semiconductor layer, a second semiconductor layer, a third semiconductor layer and a fourth semiconductor layer, wherein: The first semiconductor layer has a first conductivity type, and the first semiconductor layer includes a plurality of columns, the plurality of columns are arranged along the first direction, and the conductivity type of the columns is a second conductivity type; The conductivity type of the second semiconductor layer is the second conductivity type, and the second semiconductor layer is arranged above the first semiconductor layer. The conductivity type of the third semiconductor layer is the first conductivity type, and the third semiconductor layer is arranged below the first semiconductor layer; The fourth semiconductor layer is provided on a surface of the second semiconductor layer facing away from the first semiconductor layer, and the fourth semiconductor layer includes: a first semiconductor region and a second semiconductor region provided in parallel on both sides of the fourth semiconductor layer, a plurality of conductive material regions provided in parallel, and a plurality of third semiconductor regions provided in parallel. The first semiconductor region and the second semiconductor region are parallel to the first direction, and the conductivity type of the first semiconductor region and the second semiconductor region is the first conductivity type. The conductive material region is parallel to the third direction, The third semiconductor region is parallel to the third direction, and the conductivity type of the third semiconductor region is the second conductivity type. The fourth semiconductor layer further includes a fourth semiconductor region. The fourth semiconductor region is located between the third semiconductor region and the conductive material region. The conductivity type of the fourth semiconductor region is the second conductivity type.

11. The semiconductor device according to claim 10, wherein: The first semiconductor region is divided into a plurality of first sub-semiconductor regions by the plurality of third semiconductor regions arranged in parallel and the plurality of conductive material regions arranged in parallel; The second semiconductor region is divided into a plurality of second sub-semiconductor regions by the plurality of parallel third semiconductor regions and the plurality of parallel conductive material regions.

12. The semiconductor device according to claim 10 or 11, characterized in that The conductive material region includes a trench filled with a conductive material, and the trench penetrates the second semiconductor layer.

13. The semiconductor device according to any one of claims 10 to 12, characterized in that The impurity concentration of the third semiconductor region is different from the impurity concentration of the fourth semiconductor region.

14. The semiconductor device according to any one of claims 10 to 13, wherein: The MOSFET region further includes a fifth semiconductor layer. The conductivity type of the fifth semiconductor layer is the first conductivity type. The fifth semiconductor layer is located between the first semiconductor layer and the second semiconductor layer.

15. The semiconductor device according to any one of claims 10 to 14, characterized in that The semiconductor device further includes a sixth semiconductor layer located between the first semiconductor layer and the third semiconductor layer. The conductivity type of the sixth semiconductor layer is the first conductivity type.

16. A power conversion circuit, characterized in that: At least one semiconductor device according to any one of claims 1 to 15 is included.

17. A chip, characterized in that: At least one semiconductor device according to any one of claims 1 to 15 is included.

18. An electronic device, characterized in that: Comprising at least one semiconductor device according to claims 1 to 15.

19. A control method, characterized in that: The method comprises: In a case where the current direction of the semiconductor device according to any one of claims 1 to 15 is from the emitter to the collector, monitoring the current value of the main current of the semiconductor device during the dead time; When the current value of the main current is greater than a preset value, keeping the gate of the semiconductor device in a closed state; When the current value of the main current is less than or equal to the preset value, the gate of the semiconductor device is turned on after the dead time.

20. A control method, characterized in that: The method comprises: In a case where a current direction of the semiconductor device according to any one of claims 1 to 15 is from the emitter to the collector, determining a first voltage value and a second voltage value, wherein the first voltage value is a voltage value of a terminal voltage of the semiconductor device during a dead time, and the second voltage value is a voltage value of a terminal voltage after a gate of the semiconductor device is opened; When the difference between the second voltage value and the first voltage value is greater than a preset value, turning off the gate of the semiconductor device; When the difference between the second voltage value and the first voltage value is not greater than the preset value, the gate of the semiconductor device is kept in an open state.

21. A method for manufacturing a semiconductor device, characterized in that: The semiconductor device is divided into an IGBT region for forming an insulated gate bipolar transistor (IGBT), a diode region for forming a diode, and a MOSFET region for forming a metal oxide semiconductor field effect transistor (MOSFET) along the first direction. Fabricating a first semiconductor layer, wherein the first semiconductor layer has a first conductivity type, comprises a plurality of pillars, the plurality of pillars are arranged along a first direction perpendicular to a thickness direction of the semiconductor device, and the pillars have a second conductivity type; Manufacturing a second semiconductor layer, wherein the second semiconductor layer is located above the first semiconductor layer and has a conductivity type of the second conductivity type; A third semiconductor layer is fabricated, wherein the third semiconductor layer is located below the first semiconductor layer and located in the diode region and the MOSFET region, and the conductivity type of the third semiconductor layer is the first conductivity type. Fabricating a fourth semiconductor layer, wherein the fourth semiconductor layer is located below the first semiconductor layer and in the IGBT region, and the conductivity type of the fourth semiconductor layer is the second conductivity type; At least one first conductive material region is formed, wherein the at least one first conductive material region is located in the diode region.

22. The manufacturing method according to claim 21, characterized in that: The method further comprises: forming at least one first semiconductor region, at least one second semiconductor region, at least one second conductive material region, and at least one third conductive material region, wherein: The at least one third conductive material region and the at least one first semiconductor region are located in the IGBT region, The at least one second conductive material region and the at least one second semiconductor region are located in the MOSFET region, The conductivity type of the first semiconductor region and the second semiconductor region is the first conductivity type.

23. The production method according to claim 21 or 22, characterized in that: The method further includes: manufacturing at least one fourth conductive material region, wherein the at least one fourth conductive material region is located in the IGBT region.

24. The production method according to any one of claims 21 to 23, characterized in that: The method further includes: forming at least one fifth conductive material region, wherein the at least one fifth conductive material region is located in the MOSFET region.

25. The production method according to any one of claims 21 to 24, characterized in that: The first semiconductor layer is sequentially arranged with the IGBT region, the diode region, and the MOSFET region along the first direction.

26. The production method according to any one of claims 21 to 25, characterized in that: The MOSFET region includes a first MOSFET region and a second MOSFET region. The first semiconductor layer is sequentially arranged with the IGBT region, the first MOSFET region, the diode region and the second MOSFET region along the first direction.

27. The production method according to any one of claims 21 to 26, characterized in that: The method further includes: manufacturing at least one floating region, wherein the at least one floating region corresponds to at least one of the pillars in a one-to-one manner, and the floating region penetrates the second semiconductor layer and contacts the corresponding pillar.

28. A method for manufacturing a semiconductor device, characterized in that: include: The semiconductor device is divided into an IGBT region for forming an insulated gate bipolar transistor (IGBT) and a MOSFET region for forming a metal oxide semiconductor field effect transistor (MOSFET) along a first direction, wherein the first direction, the second direction and the third direction are perpendicular to each other, and the second direction is the thickness direction of the semiconductor device. A first semiconductor layer is fabricated, wherein the first semiconductor layer is located in the MOSFET region, the conductivity type of the first semiconductor layer is a first conductivity type, the first semiconductor layer includes a plurality of pillars, the plurality of pillars are arranged along the first direction, and the conductivity type of the pillars is a second conductivity type, A second semiconductor layer is fabricated, wherein the second semiconductor layer is located in the MOSFET region, the conductivity type of the second semiconductor layer is the second conductivity type, and the second semiconductor layer is disposed above the first semiconductor layer. A third semiconductor layer is fabricated, wherein the third semiconductor layer is located in the MOSFET region, the conductivity type of the third semiconductor layer is the first conductivity type, and the third semiconductor layer is disposed below the first semiconductor layer. A fourth semiconductor layer is fabricated, wherein the fourth semiconductor layer is located in the MOSFET region, the fourth semiconductor layer is disposed on a surface of the second semiconductor layer facing away from the first semiconductor layer, and the fourth semiconductor layer comprises: a first semiconductor region and a second semiconductor region disposed in parallel on both sides of the fourth semiconductor layer, a plurality of conductive material regions disposed in parallel, and a plurality of third semiconductor regions disposed in parallel. The first semiconductor region and the second semiconductor region are parallel to the first direction, and the conductivity type of the first semiconductor region and the second semiconductor region is the first conductivity type. The conductive material region is parallel to the third direction, The third semiconductor region is parallel to the third direction, and the conductivity type of the third semiconductor region is the second conductivity type. The fourth semiconductor layer further includes a fourth semiconductor region. The fourth semiconductor region is located between the third semiconductor region and the conductive material region. The conductivity type of the fourth semiconductor region is the second conductivity type.

29. The manufacturing method according to claim 28, characterized in that: The first semiconductor region is divided into a plurality of first sub-semiconductor regions by the plurality of third semiconductor regions arranged in parallel and the plurality of conductive material regions arranged in parallel; The second semiconductor region is divided into a plurality of second sub-semiconductor regions by the plurality of parallel third semiconductor regions and the plurality of parallel conductive material regions.

30. The production method according to claim 28 or 29, characterized in that: Producing the conductive material region includes forming a trench that penetrates the second semiconductor layer and filling the trench with a conductive material.

31. The production method according to any one of claims 28 to 30, characterized in that The manufacturing of the fourth semiconductor layer comprises: doping the third semiconductor region with impurities of a first concentration, The fourth semiconductor region is doped with impurities at a second concentration, wherein the first concentration is different from the second concentration.

32. The production method according to any one of claims 28 to 31, characterized in that The method further includes: manufacturing a fifth semiconductor layer, wherein the fifth semiconductor layer is located in the MOSFET region, the conductivity type of the fifth semiconductor layer is the first conductivity type, and the fifth semiconductor layer is located between the first semiconductor layer and the second semiconductor layer.

33. The production method according to any one of claims 28 to 32, characterized in that The method further includes: manufacturing a sixth semiconductor layer, wherein the sixth semiconductor layer is located between the first semiconductor layer and the third semiconductor layer, and the conductivity type of the sixth semiconductor layer is the first conductivity type.

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