Manufacturing method for a semiconductor device and semiconductor device

Abstract

The invention relates to a method for manufacturing a semiconductor device (20, 32), comprising the steps of - providing a structure (10) comprising a wide-bandgap semiconductor layer (12) having a top surface (14) and an insulating layer (16) formed on the top surface (14) of the wide-bandgap semiconductor layer (12), and - treating the insulating layer (16) of the structure (10) by plasma-immersion ion implantation or by ion implantation for the implementation of oxygen ions (22) into the insulating layer (16). Furthermore, the invention relates to a semiconductor device (20, 32) obtained by the above method. Additionally, the invention relates to a semiconductor device (20, 32) having a structure (10) comprising a wide-bandgap semiconductor layer (12) having a top surface (14) and an insulating layer (16) formed on the top surface (14) of the wide-bandgap semiconductor layer (12), wherein the insulating layer (16) is silicon dioxide layer or a metal oxide layer and wherein the insulating layer (16) comprises oxygen vacancies in the oxidation state +II and further comprises oxygen vacancies in the oxidation state -II.

Description

[0001] Description

[0002] Manufacturing method for a semiconductor device and semiconductor device

[0003] Technical Field

[0004] The invention relates to a method for manufacturing a semiconductor device.

[0005] Furthermore, the invention relates to a semiconductor device obtained by the above method.

[0006] Additionally, the invention relates to a semiconductor device having a structure comprising a wide-bandgap semiconductor layer having a top surface and an insulating layer formed on the top surface of the wide-bandgap semiconductor layer, wherein the insulating layer is silicon dioxide layer or a metal oxide layer.

[0007] Background Art

[0008] Power semiconductor devices are used as switches controlling the current flow through various electronic systems. Many power semiconductor devices make use of a metal-oxide-sem iconductor (MOS) structure. Devices that comprise a MOS structure are for example a power MOS field-effect transistor (MOSFET) designed to handle significant power levels or an insulated-gate bipolar transistor (IGBT).

[0009] While silicon (Si) is a very common semiconductor material for power semiconductor devices, power semiconductor devices formed with wide-bandgap semiconductor materials as substrate such as a silicon carbide substrate (SiC substrate) composed of silicon (Si) and carbon (C) bonded to each other at a composition ratio of 1 :1 are becoming more and more important.

[0010] For example, SiC offers a number of attractive characteristics for high-voltage power semiconductors when compared to commonly used Si. Exemplarily the much higher breakdown field strength and a high thermal conductivity of SiC in principle allow creating devices which outperform by far the corresponding Si devices and enable reaching otherwise unattainable efficiency levels. SiC based power MOSFETs may offer superior dynamic performance over conventional Si based power MOSFETs.

[0011] However, a major problem for wide-bandgap semiconductor materials and in particular for SiC based power semiconductor devices are various crystal defects. As a result, devices based on SiC display poorer performances as expected base on theoretical calculations.

[0012] In particular defects at the interface between SiC and the silicon dioxide (SiO2) used as insulating layer, as well as defects in the first few nanometers of the SiC material below the insulating layer dramatically affect the behaviour of the SiC based power semiconductor devices. In particular, the defects modify the threshold voltage, reduce the steepness of the subthreshold slope, increase leakage in the off-state and reduce the amount of current in the on-state. Efforts in the prior art focus on avoiding such defects at or close to the interface between the insulating layer and the SiC material of a channel region below.

[0013] Summary of invention

[0014] It is an object of the invention to provide means to improve the performance of power semiconductor devices based on wide-bandgap semiconductor materials. Furthermore, it is an object of the invention to improve the performance of silicon carbide (SiC) based power semiconductor devices. In particular, it is an object of the present invention to improve the threshold voltage and / or the channel mobility in power semiconductor devices such as MOSFET and IGBT.

[0015] The object of the invention is solved by the features of the independent claims. Modified embodiments are detailed in the dependent claims.

[0016] Thus, the object is solved by a method for manufacturing a semiconductor device, comprising the steps of

[0017] - providing a structure comprising a wide-bandgap semiconductor layer having a top surface and an insulating layer formed on the top surface of the wide- bandgap semiconductor layer, and

[0018] - treating the insulating layer of the structure by plasma-immersion ion implantation or by ion implantation for the implementation of oxygen ions into the insulating layer.

[0019] Furthermore, the object is also solved by a semiconductor device obtained by the above method.

[0020] Additionally, the object is solved by a semiconductor device having a structure comprising a wide-bandgap semiconductor layer having a top surface and an insulating layer formed on the top surface of the wide-bandgap semiconductor layer, wherein the insulating layer comprises oxygen vacancies in the oxidation state +11 and further comprises oxygen vacancies in the oxidation state -II.

[0021] One aspect of the invention is that oxygen ions are implanted into the insulating layer. This is achieved by plasma-immersion ion implantation or by ion implantation. Even though plasma-immersion ion implantation and ion implantation are generally known to increase the number of defects, it was surprisingly found that the threshold voltage for field effect transistors, the flat band voltage for metal-oxide-sem iconductor (MOS) structures, and the channel mobility are improved when implanting oxygen ions into the insulating layer. Without being bound to a specific theory, it is believed that the implanted oxygen ions diffuse to the interface between insulating layer and the wide-bandgap semiconductor layer and reduce the defect density at said interface.

[0022] The implantation of the oxygen ions into the insulating layer changes the nature of the defects and in particularly the oxygen vacancies in the insulating layer. While the oxidation state of the oxygen vacancy in the insulating layer is +11, the implantation of the oxygen ion into the insulating layer changes the oxidation state of the oxygen vacancy to -II. Thus, after performing the step of treating the insulating layer of the structure by plasma-immersion ion implantation or by ion implantation for the implementation of oxygen ions into the insulating layer, the insulation layer comprises in addition to the oxygen vacancy in the insulating layer is +11 also oxygen vacancy in the insulating layer is -II. The flat band voltage of a metal-oxide-sem iconductor (MOS) structure defines the voltage value at which there is no depletion layer at the junction between the semiconductor and the insulator. In other words, when applying the flat band voltage to the MOS structure the applied voltage compensates the natural band bending of the conduction and valence bands, that occur due to the different fermi levels of the semiconductor and conductor on the other side of the insulator.

[0023] The flat band voltage for MOS structures is strongly correlated to the threshold voltage for field-effect transistors such as MOSFETs and IGBTs. The threshold voltage defines the minimum gate-to-source-voltage that is needed to create a conducting path between the source and drain terminals.

[0024] A wide-bandgap semiconductor is a semiconductor having a bandgap greater than the bandgap of silicon. Preferably, the bandgap of the semiconductor layer is greater than 1 .5 eV and further preferably greater 2 eV.

[0025] The insulating layer of the structure is an electrically non-conductive layer. Preferably, the electrical conductance of the insulating layer is less than 10’8S.

[0026] Preferably the semiconductor device is a power semiconductor device. Further preferably the power semiconductor device is a 1 .2 kV to 6.5 kV volt class power semiconductor device. Further preferably the power semiconductor device is configured for current ratings of 5 A to 600 A in a temperature range of 25 °C to 175 °C.

[0027] Regarding the material of the wide-bandgap semiconductor layer and according to a preferred embodiment of the invention, the wide-bandgap semiconductor layer is preferably a silicon carbide layer (SiC layer), a gallium nitride layer, or a gallium(lll) oxide layer. Preferably, the wide-bandgap semiconductor layer is a silicon carbide layer or a gallium nitride layer, and further preferably the wide-bandgap semiconductor layer is a silicon carbide layer.

[0028] Regarding the material of the insulating layer and according to another preferred embodiment of the invention, the insulating layer is a silicon dioxide layer (SiO2 layer), a metal oxide layer, or an aluminum(lll) oxide layer. Further possible materials for the insulating layer are hafnium(IV) oxide or zirconium(IV) oxide.

[0029] Further preferably in case the wide-bandgap semiconductor layer is a silicon carbide layer, the insulating layer is preferably a silicon dioxide layer. In connection to this and according to another preferred embodiment a method for manufacturing a silicon carbide semiconductor device is provided, comprising the steps of

[0030] - providing the structure comprising the silicon carbide layer having the top surface and the silicon dioxide layer formed on the top surface of the silicon carbide layer, and

[0031] - treating the silicon dioxide layer of the structure by plasma-immersion ion implantation or by ion implantation for the implementation of oxygen ions into the silicon dioxide layer.

[0032] In a further preferred alternative embodiment the wide-bandgap semiconductor layer is a gallium nitride layer, the insulating layer is preferably a silicon dioxide layer. In connection to this and according to another preferred embodiment a method for manufacturing a gallium nitride semiconductor device is provided, comprising the steps of

[0033] - providing the structure comprising the gallium nitride layer layer having the top surface and the silicon dioxide layer formed on the top surface of the gallium nitride layer, and

[0034] - treating the silicon dioxide layer of the structure by plasma-immersion ion implantation or by ion implantation for the implementation of oxygen ions into the silicon dioxide layer.

[0035] Still in a further preferred alternative embodiment the wide-bandgap semiconductor layer is a gallium(lll) oxide layer, the insulating layer is preferably an aluminum(lll) oxide layer. In connection to this and according to another preferred embodiment a method for manufacturing a gallium(lll) oxide semiconductor device is provided, comprising the steps of

[0036] - providing the structure comprising the gallium (111) oxide layer having the top sur- face and the aluminum(lll) oxide layer formed on the top surface of the gal- lium(lll) oxide layer, and

[0037] - treating the aluminum(lll) oxide layer of the structure by plasma-immersion ion implantation or by ion implantation for the implementation of oxygen ions into the aluminum(lll) oxide layer.

[0038] Independent of the method used for the implantation of the oxygen ions into the insulating layer, and according to a preferred embodiment of the invention, the step of treating the insulating layer is performed at temperatures from -60 °C to +60 °C and preferably at room temperature. This has the advantage that the method is easy to perform and cost efficient as no heating to high temperatures is necessary as for example compared to an annealing step. In the context of this invention room temperature denominates a temperature range from 10 °C to 40 °C. Furthermore, it was also found that compared to annealing at high temperatures, the treatment at low temperature leads to less variation in the interface state density.

[0039] According to another preferred embodiment of the invention, the step of treating the insulating layer by plasma-immersion ion implantation is performed with energies of 5 keV to 10 keV. Plasma-immersion ion implantation is a surface modification technique of extracting accelerated ions from a plasma by applying a high voltage pulsed direct current or pure direct current power supply and targeting the ions into the insulatinglayer in order to implant the ions within the insulating layer. It was found that the energies of the ions can be chosen to be low, as only a small implantation depth is needed.

[0040] Preferably a plasma is generated in vacuum chamber with a plasma source such as an electron cyclotron resonance plasma source, a helicon plasma source, a capacitively coupled plasma source, or an inductively coupled plasma source. The vacuum chamber can be of the diode type or the triode type depending upon whether a power supply is applied to the structure comprising the silicon carbide layer and the silicon dioxide layer, or to a perforated grid.

[0041] Preferably an applied voltage for the step of treating the insulating layer by plasmaimmersion ion implantation is 1 kV to 50 kV for pulsed DC biasing and / or 1 kV to 30 kV for DC biasing. Further preferably in case of pulsed DC biasing an on time of the DC pulse is 0.1 ps to 100 ps, and an off time of the DC pulse is is 0.1 ms to 100 ms. Further preferably a pressure of the vacuum chamber is 10’12mbar to 10’3mbar.

[0042] According to another preferred embodiment of the invention, the step of treating the insulating layer by plasma-immersion ion implantation is performed with ion doses of 101° cm-2to 1018cm-2. It was found that such ion doses are sufficient to improve the threshold voltage of the semiconductor device.

[0043] Also, in connection to plasma-immersion ion implantation and according to a further preferred embodiment of the invention, it is preferred that the step of treating the insulating layer by plasma-immersion ion implantation comprises generating a plasma that comprises oxygen ions. Further preferably, the generated plasma is free of nitrogen ions, or free of nitrogen containing ions such as NOx ions. Further preferably, the generated plasma is free of nitrogen ions, and free of nitrogen containing ions.

[0044] As already mentioned, the oxygen ions can also be implanted into the insulating layer by ion implantation. Ion implantation is a process by which ions of the desired element - i.e. oxygen ions - are accelerated into a solid target - i.e. the insulating layer. Ion implantation is preferably performed with an ion source, where the ions are produced, an accelerator, where the ions are accelerated, and a target chamber, where the ions impinge on insulating layer.

[0045] In connection to ion implantation and according to another preferred embodiment of the invention, the step of treating the insulating layer by ion implantation is performed with ion beam energies of 1 keV to 50 keV, preferably 1 keV to 10 keV. As only a small penetration of the oxygen ions into the usually rather thin insulating layer is required, low beam energies can be used. This makes the process very cost efficient.

[0046] According to another preferred embodiment of the invention, the step of treating the insulating layer by ion implantation is performed with ion doses of 1014crrr2to 1018cnr2. It was found that such ion doses are sufficient to improve the threshold voltage of the semiconductor device when using ion implantation.

[0047] In connection with ion implantation and according to another preferred embodiment of the invention, the step of treating the insulating layer by ion implantation comprises generating oxygen ions with an ion source. Particularly preferably the oxygen ions are accelerated to the required ion beam energies and separated by a magnetic field. Further preferably, only ions with a specific value of the product of mass and velocity / charge are used for implantation into the insulating layer.

[0048] According to another preferred embodiment of the invention, the step of providing the structure comprising the wide-bandgap semiconductor layer having the top surface and the insulating layer formed on the top surface of the wide-bandgap semiconductor layer comprises the steps of forming the insulating layer on a surface of a substrate and forming the insulating layer on the top surface of the wide-bandgap semiconductor layer. Preferably the wide-bandgap semiconductor layer and in particularly the silicon carbide layer is epitaxially grown. This ensures that the wide- bandgap semiconductor layer has a well-defined orientation.

[0049] In connection to the embodiment, where the wide-bandgap semiconductor layer is a silicon carbide layer and the insulating layer is a silicon dioxide layer, it is further preferred that the step of forming the silicon dioxide layer on the top surface of the silicon carbide layer is performed by heating said silicon carbide layer in an atmosphere containing oxygen. In other words, the silicon dioxide layer is formed on the silicon carbide layer by thermal oxidation. Preferably, thermal oxidation is carried out at 800 °C to 1400 °C, and preferably at 1250 °C to 1400 °C.

[0050] Alternatively chemical vapor deposition may be used for forming the silicon dioxide layer, or for forming the metal oxide layer, or the aluminum(lll) oxide layer. Thermal oxidation may be preferred over chemical vapor deposition as it generates a higher- quality oxide with a cleaner interface. However, when manufacturing a MOSFET thermal oxidation is usually not performed after the source region and / or drain regions are generated by doping, as the high temperature required for thermal oxidation may disturb the placement of the dopants. According to a further preferred embodiment of the invention the wide-bandgap semiconductor layer is of n-type. In connection to the wide-bandgap semiconductor layer being the silicon carbide layer it is further preferred that the silicon carbide layer is a 4H-SiC polytype. 4H-SiC is the preferred polytype for silicon carbide semiconductor devices, such as SiC power MOSFETs, due to the advances in 4H-SiC growth technology as well as its attractive electronic properties such as larger band gap and higher carrier mobility over other polytypes, such as 6H-SiC or 3C-SiC.

[0051] Alternatively or additionally the silicon carbide layer is a {0001 } oriented layer. Particularly preferred, the silicon carbide layer is a {0001 } oriented 4H-SiC layer epitaxially grown on a {0001 } oriented 4H-SiC substrate.

[0052] In connection with the insulating layer and according to another preferred embodiment of the invention, the insulating layer has a thickness less than 100 nm, and preferably less than 80 nm. Furthermore, the insulating layer preferably has a thickness of at least 30 nm, and further preferably of at least 45 nm. It is believed that the low layer thickness of the insulating layer of around 50 nm makes it possible that only a small penetration depth of the implanted oxygen ions is needed in order to improve the threshold voltage of the semiconductor device.

[0053] According to another preferred embodiment of the invention, the method may further comprise the step of annealing the structure comprising the wide-bandgap semiconductor layer and the insulating layer, after having treated the insulating layer by plasma-immersion ion implantation or by ion implantation. The optional annealing step may be carried out at 600 °C ± 100 °C. This may further improve the threshold voltage and / or the channel mobility of the semiconductor device.

[0054] In particular when considering a MOSFET as semiconductor device and according to another preferred embodiment of the invention, the method further comprises the step of implanting a source structure into the wide-bandgap semiconductor layer by forming a well region, a source region, and a contact region in the wide-bandgap semiconductor layer before forming the insulating layer on the top surface of the wide-bandgap semiconductor layer. According to another preferred embodiment of the invention, the insulating layer of the structure is preferably a gate insulating layer in a gate structure of the semiconductor device.

[0055] Further characteristics and advantages of the method for manufacturing the semiconductor device are evident to the skilled person by the following description of the semiconductor device and the further description of the specific embodiments.

[0056] As already mentioned, the invention is also directed to the semiconductor device obtained by the above-described method. Due to the implantation of oxygen ions into the insulating layer, the semiconductor device has improved threshold voltage and / or channel mobilities.

[0057] As also already mentioned, the the invention is also directed to the semiconductor device having the structure comprising the wide-bandgap semiconductor layer having the top surface and the insulating layer formed on the top surface of the wide- bandgap semiconductor layer, wherein the insulating layer comprises oxygen vacancies in the oxidation state +11 and further comprises oxygen vacancies in the oxidation state -II. Due to the implantation of oxygen ions into the insulating layer, oxidation state of some of the oxygen vacancies in the insulating layer changes from +11 to -II.

[0058] Further preferably the semiconductor device has an altered structure of the insulating layer and / or the interface between the insulating layer and the wide-bandgap semiconductor layer due to the oxygen ion implantation. Preferably, the altered structure may be a reduced defect concentration at the interface. Further preferably, the isotope ratio of the oxygen isotopes 0-16, 0-17, and 0-18 in the insulating layer is altered by the implantation of oxygen ions into the insulating layer. Thus, preferably the insulating layer of the semiconductor device comprises an isotope ratio of the oxygen isotopes 0-16, 0-17, and 0-18 different to the natural occurring isotope ratio of oxygen. To determine the isotope ratio of the insulating layer, secondary-ion mass spectrometry (SIMS) may be used in order to analyse the composition of the insulating layer.

[0059] Additionally, or alternatively, X-ray photoelectron spectroscopy (XPS) may be used for analysis of the insulating layer, and in particular for determining the defect concentration in the insulating layer and / or at the interface. The defect concentration may also be determined with positron annihilation spectroscopy.

[0060] Regarding the amount of oxygen vacancies in the insulating layer that change their nature by oxygen ion implantation, it was found the semiconductor device has an improved threshold voltage and / or channel mobilities when at least 50% of the oxygen vacancies are in the oxidation state -II. In other words, and according to a preferred embodiment of the invention a semiconductor device is provided wherein a ratio of oxygen vacancies in the oxidation state +11 to -II is at least 50:50, and preferably 20:80.

[0061] According to another preferred embodiment of the invention the semiconductor device is a silicon carbide semiconductor device. In other words, preferably a semiconductor device is provided wherein the wide-bandgap semiconductor layer is a silicon carbide layer. Particularly preferably the insulating layer of the silicon carbide semiconductor device is a silicon dioxide layer.

[0062] Regarding the semiconductor device and according to another preferred embodiment of the invention, the insulating layer of the structure is preferably a gate insulating layer in a gate structure of the semiconductor device.

[0063] Further preferably the semiconductor device may further comprise an electrically conductive layer on top of the insulating layer. Due to the electrically conductive layer a MOS structure (metal - oxide - semiconductor structure) is formed. As the insulating layer is made of a dielectric material, the MOS structure is equivalent to a planar capacitor, with one of the electrodes replaced by a semiconductor.

[0064] According to another preferred embodiment of the invention the semiconductor device is preferably a Schottky diode, an insulated-gate bipolar transistor (IGBT), a metal oxide semiconductor field effect transistor (MOSFET), in particular a power MOSFET, a gate turn-off thyristor (GTO), an integrated gate-commutated thyristor (IGCT), or a bipolar junction transistor (BJT).

[0065] Further preferably the semiconductor device may comprise a source structure implanted into the wide-bandgap semiconductor layer, the source structure comprising a well region, a source region, and a contact region. Furthermore, the semiconductor device may also comprise a drain structure formed at a bottom surface of the substrate. Furthermore, or alternatively the semiconductor device may comprise a collector structure.

[0066] These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.

[0067] In the drawings:

[0068] Fig. 1 schematically shows the steps of a method for manufacturing a semiconductor device according to a preferred embodiment of the invention,

[0069] Fig. 2 schematically shows a capacitance-voltage diagram of a MOS structure according to a preferred embodiment of the invention, in comparison to a comparative embodiment according to prior art, and

[0070] Fig. 3 schematically shows results of a TCAD simulation of a MOSFET structure simulating a MOSFET according to a preferred embodiment of the invention, in comparison to a comparative embodiment according to prior art.

[0071] Description of embodiments

[0072] Figure 1 schematically shows the steps of a method for manufacturing a semiconductor device according to a preferred embodiment of the invention. In this embodiment the semiconductor device is a silicon carbide semiconductor device. In a first step of the method, which is shown in Figure 1 a) a structure 10 comprising a wide- bandgap semiconductor layer 12 - in this preferred embodiment a silicon carbide layer 12 - having a top surface 14 and an insulating layer 16 - in this preferred embodiment a silicon dioxide layer 16 - formed on the top surface 14 of the wide- bandgap semiconductor layer 12 is provided.

[0073] In this preferred embodiment the structure 10 shown in Figure 1 a) is formed by epitaxially growing a {0001 } oriented 4H-SiC layer 12 on a {0001 } oriented 4H-SiC n- type substrate 18, followed by a thermal oxidation step for forming the silicon dioxide layer 16. The silicon dioxide layer 16 later acts as insulating layer of a MOS structure 20.

[0074] Afterwards, and as shown in Figure 1 b), the silicon dioxide layer 16 of the structure 10 is treated by plasma-immersion ion implantation for the implementation of oxygen ions 22 into the silicon dioxide layer 16.

[0075] In order to provide the MOS structure 20, in a further step shown in figure 1 c) an electrically conductive layer 24 on top of the treated silicon dioxide layer 16 is formed.

[0076] Figure 2 schematically shows a capacitance-voltage diagram 26 of a MOS structure 20 according to a preferred embodiment of the invention, in comparison to a comparative embodiment according to prior art.

[0077] In order to show the improvement of the threshold voltage and / or the channel mobility in SiC based power semiconductor devices, a MOS structure 20 that was manufactured as previously described for Figure 1 was compared to a MOS structure 20’ that was manufactured in the same way, except that no treatment of the silicon dioxide layer 16 by plasma-immersion ion implantation for the implementation of oxygen ions 22 into the silicon dioxide layer 16 was performed. In other words, for the MOS structure 20’ no step according to Figure 1 b) was performed.

[0078] The diagram 26 in Figure 2 showing the voltage in volts on the x-axis 28, and the capacitance in picofarads on the y-axis 30 shows that treating the silicon dioxide layer 16 by plasma immersion ion implantation for the implementation of oxygen ions 22 leads to an improvement of the flat band voltage of the MOS structure 20 in comparison to the MOS structure 20’ from approximately 10 V to approximately - 0.5 V.

[0079] Figure 3 schematically shows results of a technology computer-aided design (TOAD) simulation of a MOSFET structure 32 according to a preferred embodiment of the invention, in comparison to a comparative MOSFET structure 32’.

[0080] The TOAD simulation were carried out on a SiC MOSFET. At first, a SiC MOSFET with a fixed charge concentration of 1016cm’3was simulated as reference MOSFET structure 32’. In Figure 3 simulation results achieved with the MOSFET structure 32’ with the standard concentration are compared with results achieved with a MOSFET structure 32 having a lower fixed charge concentration. Figure 3a) shows the drain to source current IDS in ampers per square centimetres on the y-axis 34, as a function of the gate to source voltage VGS in volts on the x-axis 36 at 25 °C and with a drain to source voltage VDS of 10 V. Figure 3a) shows that the lower fixed charge concentration leads to an improvement of the transfer characteristics.

[0081] Figure 3b) shows the output characteristics of the same MOSFET structures 32, 32’ as in Figure 3a) and shows on the y-axis 38 the drain to source current IDS in ampers per square centimetres as a function of the drain to source voltage VDS in volts on the x-axis 40 at 25 °C and with a gate to source voltage VGS of 15 V. It can be seen that the curve of the MOSFET structure 32 with lower fixed charge concentration shows an improvement with respect to the reference MOSFET 32’, meaning that the on-state resistance F?DS(on) has decreased.

[0082] While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive; the invention is not limited to the disclosed embodiments. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosed, and the appended claims. In the claims, the word “comprising” does not exclude other elements or steps, and the indefinite article “a” or “an” does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. Any reference signs in the claims should not be construed as limiting scope.

[0083] Reference signs list

[0084] 10 structure

[0085] 12 wide-bandgap semiconductor layer, silicon carbide layer, 4H-

[0086] SiC layer

[0087] 14 top surface

[0088] 16 insulating layer, silicon dioxide layer, SiO2

[0089] 18 substrate, SiC substrate

[0090] 20 MOS structure

[0091] 20’ MOS structure according to prior art

[0092] 22 oxygen ions

[0093] 24 electrically conductive layer

[0094] 26 capacitance-voltage diagram

[0095] 28 x-axis in figure 2, voltage in V

[0096] 30 y-axis in figure 2, capacitance in pF

[0097] 32 MOSFET structure

[0098] 32’ MOSFET structure according to prior art

[0099] 34 y-axis in figure 3a, drain to source current IDS in A / cm2

[0100] 36 x-axis in figure 3a, gate to source voltage VGS in V

[0101] 38 y-axis in figure 3b, drain to source current IDS A / cm2

[0102] 40 x-axis in figure 3b, drain to source voltage VDS in V

Claims

Claims1. Method for manufacturing a semiconductor device (20, 32), comprising the steps of- providing a structure (10) comprising a wide-bandgap semiconductor layer (12) having a top surface (14) and an insulating layer (16) formed on the top surface (14) of the wide-bandgap semiconductor layer (12), and- treating the insulating layer (16) of the structure (10) by plasma-immersion ion implantation or by ion implantation for the implementation of oxygen ions (22) into the insulating layer (16).

2. Method according to the previous claim, wherein the wide-bandgap semiconductor layer (12) is a silicon carbide layer (12), a gallium nitride layer, or a gal- lium(lll) oxide layer.

3. Method according to any of the previous claims, wherein the insulating layer (16) is a silicon dioxide layer (16), a metal oxide layer, or an aluminum(lll) oxide layer.

4. Method according to any of the previous claims, wherein the step of treating the insulating layer (16) is performed at temperatures from -60 °C to +60 °C, and preferably at room temperature.

5. Method according to any of the previous claims, wherein the step of treating the insulatinglayer (16) by plasma-immersion ion implantation is performed with energies of 5 keV to 10 keV.

6. Method according to any of the previous claims, wherein the step of treating the insulatinglayer (16) by plasma-immersion ion implantation is performed with ion doses of 1010cm-2to 1018cm-2.

7. Method according to any of the previous claims, wherein the step of treating the insulatinglayer (16) by plasma-immersion ion implantation comprises generating a plasma that comprises oxygen ions (22).

8. Method according to any of the previous claims, wherein the step of treating the insulatinglayer (16) by ion implantation is performed with ion beam energies of 1 keV to 50 keV.

9. Method according to any of the previous claims, wherein the step of treating the insulatinglayer (16) by ion implantation is performed with ion doses of 1014cm’2to 1018cm’2.

10. The according to any of the previous claims, wherein the step of treating the insulatinglayer (16) by ion implantation comprises generating oxygen ions (22) with an ion source.11 . Method according to any of the previous claims, wherein the step of providing the structure (10) comprising the wide-bandgap semiconductorlayer (12) having the top surface (14) and the insulatinglayer (16) formed on the top surface (14) of the wide-bandgap semiconductorlayer (12) comprises the steps of forming the wide-bandgap semiconductor (12) on a surface of a substrate (18) and forming the insulating layer (16) on the top surface (14) of the wide-bandgap semiconductorlayer (12).

12. Method according to the previous claim, wherein the wide-bandgap semiconductor layer (12) is a silicon carbide layer and the insulating layer (16) is a silicon dioxide layer, and wherein forming the insulating layer (16) on the top surface (14) of the wide-bandgap semiconductor layer (12) is performed by heating said wide-bandgap semiconductor layer (12) in an atmosphere containing oxygen.

13. Method according to any of the previous claims, wherein the wide-bandgap semiconductor layer (12) is of n-type.

14. Method according to any of the previous claims, wherein the wide-bandgap semiconductor layer (12) is a silicon carbide layer (12) and a) is a 4H-SiC polytype, and / or b) is a {0001 } oriented layer.

15. Method according to any of the previous claims, wherein the insulating layer (16) has a thickness less than 100 nm and / or wherein the insulating layer (16) has a thickness of at least 30 nm.

16. Semiconductor device (20, 32) obtained by the method according to any of the preceding claims.

17. Semiconductor device (20, 32) having a structure (10) comprising a wide- bandgap semiconductor layer (12) having a top surface (14) and an insulating layer (16) formed on the top surface (14) of the wide-bandgap semiconductor layer (12), wherein the insulating layer (16) comprises oxygen vacancies in the oxidation state +II and further comprises oxygen vacancies in the oxidation state -II.

18. Semiconductor device (20, 32) according to any of claims 16 or 17, wherein a ratio of oxygen vacancies in the oxidation state +II to -II is at least 50:50, and preferably 20:80.

19. Semiconductor device (20, 32) according to any of claims 16 to 18, wherein the wide-bandgap semiconductor layer (12) is a silicon carbide layer and / or wherein the insulating layer (16) is a silicon dioxide layer.

20. Semiconductor device (20, 32) according to any of claim 16 to 19, wherein the insulting layer (16) is a gate insulating layer in a gate structure of the semiconductor device (20, 32).21 . Semiconductor device (20, 32) according to any of claim 16 to 20, wherein the semiconductor device (20,32) further comprises an electrically conductive layer (24) on top of the insulating layer (16).

22. Semiconductor device (20, 32) according to any of claims 16 to 21 , wherein the semiconductor device (20, 32) is a Schottky diode, an insulated-gate bipolar transistor, a metal oxide semiconductor field effect transistor, in particular a power MOSFET, a gate turn-off thyristor, an integrated gate-commutated thy- ristor, or a bipolar junction transistor.

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