Power semiconductor module

Abstract

There is provided a power semiconductor module 100 comprising: a power semiconductor device 50 comprising first and second power electrodes; and a substrate 10. The substrate 10 comprises first and second electrically insulating layers 1, 2 stacked with first and second electrically conductive layers 11, 12, wherein the first electrically insulating layer 1 is arranged between the first and second electrically conductive layers 11, 12, and the second electrically conductive layer 12 is arranged between the first and second electrically insulating layers 1, 2. The first electrically conductive layer comprises first and second conductive tracks 11-1, 11-2 which are spaced apart from one another. The first electrically insulating layer comprises a first conductive via 40-1 which electrically connects the first conductive track 11-2 to at least a part of the second electrically conductive layer 12-1, and a second conductive via 40- 2 which electrically connects the second conductive track 11-2 to the at least a part of the second electrically conductive layer 12-1. One of the first and second power electrodes is electrically connected to the first conductive track 11-1.

Description

[0001] Power Semiconductor Module

[0002] Technical Field

[0003] This disclosure relates to a power semiconductor module and a method of manufacturing the same. More particularly, but not exclusively, this disclosure relates to a double-side cooled power semiconductor module which uses an internal conductive layer of a multi-layered substrate to realise electrical interconnections within the module.

[0004] Power semiconductor modules have been considered as one of the most delicate components in electric drive systems of electric vehicles (EVs) and hybrid electric vehicles (HEVs). For such applications, there has been an increasing demand for power semiconductor modules with increased efficiency (in terms of reduction of losses and of removal of heat generated through those losses), increased power density, improved electrical and thermal performance, high reliability and reduced volume and costs.

[0005] The conventional power semiconductor module typically uses a patterned copper-clad ceramic substrate on which power chips are mounted. Copper clips and / or wire bonds are commonly used to make the interconnections between electrodes of the power chips and copper tracks of the substrate. The known structure and technologies are generally difficult to meet HEV / EV requirements in efficiency, power density, electrical and thermal performance, as well as in the reliability, volume and costs.

[0006] It is generally desirable to further improve the performance of known power semiconductor modules in EV and HEV electric drive applications. It is an object of the present disclosure, among others, to provide such an improved power semiconductor module. According to a first aspect of the present disclosure, there is provided a power semiconductor module comprising: a power semiconductor device comprising first and second power electrodes; and a substrate comprising first and second electrically insulating layers stacked with first and second electrically conductive layers, wherein the first electrically insulating layer is arranged between the first and second electrically conductive layers, and the second electrically conductive layer is arranged between the first and second electrically insulating layers, and wherein: the first electrically conductive layer comprises first and second conductive tracks which are spaced apart from one another; the first electrically insulating layer comprises a first conductive via which electrically connects the first conductive track to at least a part of the second electrically conductive layer, and a second conductive via which electrically connects the second conductive track to the at least a part of the second electrically conductive layer; and one of the first and second power electrodes is electrically connected to the first conductive track.

[0007] The substrate used in conventional power modules typically includes a single electrically insulating layer laminated with two conductive layers at both sides of the insulating layer. In contrast, the substrate used in the present power semiconductor module includes two electrically insulating layers with an internal (second) electrically conductive layer therebetween. The internal (second) electrically conductive layer, together with conductive vias formed within the first electrically insulating layer, allows a power electrode of the power semiconductor device to be easily connected to a power electrode of other power device(s) or a power terminal of the module (which may be electrically connected to the second conductive track). The use of the second electrically conductive layer and the first and second conductive vias to route a power current of the module significantly improves the flexibility in the layout design (e.g., the arrangement of conductive traces on the substrate and the positioning of terminals) of the power semiconductor module, and allows the footprint of the substrate to be greatly reduced as compared to conventional power modules. In particular, the first electrically conductive layer is no longer required to provide all of the electrical connections and thus can be simplified and down-sized.

[0008] It would be understood that the electrically insulating layers are thermally conductive. The first and second electrically insulating layers may be stacked with the first and second electrically conductive layers along a stacking direction. The stacking direction may be perpendicular to a surface of the first electrically insulating layer.

[0009] Within the present disclosure, the term “electrically connected” describes a permanent low-ohmic connection between electrically connected elements, for example a direct contact between the concerned elements or a low-ohmic connection via metal conductor(s) (such as a metal spacer).

[0010] The first electrically conductive layer may be arranged on a surface of the first electrically insulating layer that faces the power semiconductor device.

[0011] The substrate may further comprise a third electrically conductive layer, and the second electrically insulating layer may be arranged between the second and third electrically conductive layers. The third electrically conductive layer may be exposed to an exterior of the power semiconductor module for thermally coupling to a heat removal structure.

[0012] One or more of the first and second electrically insulating layers may comprise a ceramic material. The ceramic material may be silicon nitride ceramic.

[0013] One or more of the first and second electrically conductive layers may comprise copper.

[0014] The substrate may be a first substrate, and the power semiconductor module may further comprise a second substrate having a third electrically insulating layer and a fourth electrically conductive layer which is arranged on a surface of the third electrically insulating layer that faces the power semiconductor device. The power semiconductor device may be arranged between the first substrate and the second substrate. The other of the first and second power electrodes is electrically connected to at least a part of the fourth electrically conductive layer.

[0015] By having first and second substrates, the power semiconductor module may be a double-side cooled module. In particular, the second substrate may comprise a fifth electrically conductive layer, and the fourth and fifth electrically conductive layers may be provided on opposite surfaces of the third electrically insulating layer. The fifth electrically conductive layer may be exposed to an exterior of the power semiconductor module for thermally coupling to a further heat removal structure.

[0016] The first and second power electrodes may be arranged on opposite surfaces of the power semiconductor device. In other words, the power semiconductor device may be a vertical power device.

[0017] The power semiconductor device may comprise a power MOSFET.

[0018] The power semiconductor device may be a wide bandgap power MOSFET. The body diode of a power MOSFET may be used as a fast recovery diode, and therefore the power MOSFET no longer requires a separate diode to form a power switch. Consequently, using power MOSFETs are useful for reducing the overall number of power semiconductor devices within the power semiconductor module, thereby reducing the footprint or increasing the power density of the power semiconductor module.

[0019] The power semiconductor device may comprise a silicon carbide MOSFET.

[0020] The power semiconductor device may be a first power semiconductor device, and the power semiconductor module may further comprise: a second power semiconductor device comprising third and fourth power electrodes, wherein the third power electrode is electrically connected to the second power electrode of the first power semiconductor device.

[0021] In other words, the first and second power semiconductor devices may be connected to form a half bridge circuit. The power semiconductor module may further comprise: a first power terminal electrically connected to the first power electrode; a second power terminal electrically connected to the second and third power electrodes; and a third power terminal electrically connected to the fourth power electrode.

[0022] One of the first and second power semiconductor devices may be directly mounted on the fourth electrically conductive layer of the second substrate; and the other one of the first and second power semiconductor devices may be directly mounted on the first electrically conductive layer of the first substrate.

[0023] With the expression “directly mounted”, it is meant that no other structure (such as a spacer) is between a surface of the power electrode and a surface of the conductive track (except a small amount of bonding / interface material for joining the two surfaces). The power electrode may be directly mounted on the respective conductive track by soldering or sintering.

[0024] The power semiconductor module may further comprise: a first conductive spacer arranged between and electrically connecting the one of the first and second power semiconductor devices and the first substrate; and a second conductive spacer arranged between and electrically connecting the other one of the first and second power semiconductor devices and the second substrate.

[0025] One or more of the first and second conductive spacers may be of a composition of 60% molybdenum and 40% copper.

[0026] The first power semiconductor device may be configured to block a voltage with a higher potential at the second power electrode than at the first power electrode. The second power semiconductor device may be configured to block a voltage with a higher potential at the fourth power electrode than at the third power electrode. One of the second and fourth power electrodes may be directly mounted on the fourth electrically conductive layer of the second substrate, and the other one of the second and fourth power electrodes may be directly mounted on the first electrically conductive layer of the first substrate.

[0027] In other words, the second / fourth power electrode may be the drain electrode and the first / third power electrode may be the source electrode if the first and second power semiconductor devices are power MOSFETs. By directly mounting the drain electrodes of the first and second power semiconductor devices on opposite substrates of the module, and also by using the internal (second) electrically conductive layer of the first substrate, the overall power current path for the switching operation can be drastically reduced and the need for inter-substrate conductive spacers are removed entirely. As a result, the parasitic inductance within the commutation loop of the half bridge circuit (formed by the first and second power semiconductor devices) is reduced. This is useful for improving the switching efficiency and reducing the switching loss of the power semiconductor module.

[0028] The second power electrode may be electrically connected to the first conductive track and the third power electrode may be electrically connected to the second conductive track.

[0029] Alternatively, the first power electrode may be electrically connected to the first conductive track, and the power semiconductor module may further comprise a first power terminal which is electrically connected to the second conductive track.

[0030] The first power semiconductor device may further comprise a first control electrode configured to control a power current flowing between the first power electrode and the second power electrode, and the second power semiconductor device may further comprise a second control electrode configured to control a power current flowing between the third power electrode and the fourth power electrode. The first electrically conductive layer may comprise a third conductive track spaced apart from the first and second conductive tracks, and the power semiconductor module may comprise a control terminal directly mounted on the third conductive track. The second electrically conductive layer may comprise fourth and fifth conductive tracks which are spaced apart from one another, the fourth conducting track being electrically connected to the first and second conductive vias. The first electrically insulating layer may comprise a third conductive via electrically coupling one of the first and second control electrodes to the fifth conductive track, and a fourth conductive via electrically connecting the fifth conductive track to the third conductive track.

[0031] In other words, the internal, second, electrically conductive layer can also be used to route a gate control signal, in addition to routing the power current of the module. This further improves the flexibility in forming the electrical connections within the power semiconductor module, and allows the footprint of the substrate to be minimised.

[0032] According to a second aspect of the present disclosure, there is provided a method of manufacturing a power semiconductor module. The method comprises: providing a power semiconductor device comprising first and second power electrodes; providing a substrate comprising first and second electrically insulating layers stacked with first and second electrically conductive layers, wherein: the first electrically insulating layer is arranged between the first and second electrically conductive layers, and the second electrically conductive layer is arranged between the first and second electrically insulating layers; the first electrically conductive layer comprises first and second conductive tracks which are spaced apart from one another; the first electrically insulating layer comprises a first conductive via which electrically connects the first conductive track to at least a part of the second electrically conductive layer, and a second conductive via which electrically connects the second conductive track to the at least a part of the second electrically conductive layer; and electrically connecting one of the first and second power electrodes to the first conductive track.

[0033] The term “about” or “approximately” used in the present disclosure indicate a degree of variability (e.g., 20%) in the stated numerical values.

[0034] It would also be understood that the terms “first” to “fifth” are simply used in the present disclosure to label the relevant elements (e.g., “power electrode”, “electrically conductive layer” etc.) for the ease of description, and do not imply any limitations to the sequence, locations or total number of the relevant elements.

[0035] The term “electrically coupled” includes that one or more intervening element(s) adapted for signal transmission may or may not exist between the electrically coupled elements. Similarly, the term “thermally coupled (or coupling)” includes that one or more intervening element(s) may or may not exist between the thermally coupled elements.

[0036] Where appropriate any of the optional features described above in relation to one of the aspects of the disclosure may be applied to another one of the aspects of the disclosure.

[0037] Brief Description of the Drawings

[0038] In order that the disclosure may be more fully understood, a number of embodiments of the disclosure will now be described, by way of example, with reference to the accompanying drawings, in which: Figure 1 schematically illustrates a circuit diagram of a half-bridge structure;

[0039] Figure 2 is a schematic representation of a perspective view of a power semiconductor module according to an embodiment of the present disclosure which implements the half-bridge structure of Figure 1;

[0040] Figure 3 schematically illustrates a side view of the power semiconductor module of Figure 2 (with the housing removed for clarity);

[0041] Figure 4 schematically illustrates a perspective view of a lower substrate in the power semiconductor module of Figure 2;

[0042] Figure 5 schematically illustrates a plan view of an internal metallisation layer within the lower substrate of Figure 4;

[0043] Figure 6 schematically illustrates a spatial relationship between a top metallisation layer and the internal metallisation layer within the lower substrate of Figure 4;

[0044] Figure 7 schematically illustrates a perspective view of an upper substrate in the power semiconductor module of Figure 2;

[0045] Figure 8 schematically illustrates the path of a commutation loop within the power semiconductor module of Figure 2;

[0046] Figure 9 schematically illustrates processing steps of a method for manufacturing a power semiconductor module according to the present disclosure.

[0047] In the figures, like parts are denoted by like reference numerals.

[0048] It will be appreciated that the drawings are for illustration purposes only and are not drawn to scale.

[0049] Detailed Description of the Preferred Embodiments Figure 1 shows a circuit diagram of a half-bridge structure 1000 which is commonly used in power electronic systems (e.g., EV and HEV applications). The half-bridge structure 1000 incudes a high-side power switch 1200 connected between a DC positive power terminal ‘DC+’ and an output power terminal ‘AC’, and a low-side power switch 1400 connected between the output power terminal ‘AC’ and a DC negative power terminal ‘DC-’.

[0050] The high-side power switch 1200 includes two power transistors T1, T2 in anti-parallel connection with two power diodes D1, D2. The low-side power switch 1400 includes two power transistors T3, T4 in anti-parallel connection with two power diodes D3, D4.

[0051] In use, the half-bridge structure 1000 provides one phase of a power converter. In the example of Figure 1, the power transistors T1 to T4 are insulated gate bipolar transistors (IGBT). The power diodes D1 to D4 may be fast recovery diodes (FRD) or Schottky diodes. The number of transistors and diodes within each power switch may be suitably varied to achieve a desired current rating.

[0052] The power transistor T1 has a pair of control terminals G1, E1 for switching on / off a power current flowing between a collector and an emitter (which are power electrodes) of the power transistor T1. Similarly, the transistors T2 to T4 have control terminals G2&E2, G3&E3, and G4&E4 respectively. The terminals G1 to G4 are gate terminals, while the terminals E1 to E4 are auxiliary emitter terminals.

[0053] Figures 2 to 7 schematically illustrates the structure of a power semiconductor module 100 (hereinafter, “module 100”) that implements the half-bridge structure 1000.

[0054] Figure 2 is a perspective view of the module 100. As shown in Figure 2, the module 100 includes power terminals 110 (DC+), 120 (DC-), 130 (AC), control terminals 140 to 190 and a housing 60. In this example, the power terminals 110 to 130 take the form of copper busbars, while the control terminals 140 to 190 take the forms of copper pins. Because the housing 60 is non-transparent, the internal structure of the module 100 is invisible in Figure 2.

[0055] As described below in more detail, the module 100 uses wide-bandgap (WBG) siliconcarbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) 30, 50 rather than IGBTs. In switching from IGBTs to MOSFETs, the body diodes of the MOSFETs may also be utilised in place of the separate, antiparallel, diodes (e.g., D1- D4) that is required in order to handle the reverse recovery period of power transistors during switching. Therefore, the use of SiC MOSFETs within the module 100 is beneficial for reducing the number of devices required to form each switch. As such, by using SiC MOSFETs, the overall number of switching devices themselves can be increased without the need to increase the module footprint. Accordingly, the power density of the module 100 is increased above the power density that can be achieved using contemporary silicon IGBT devices. It however would be appreciated that the module 100 may use other types of WBG power MOSFETs or non-WBG power MOSFETs to achieve similar effects.

[0056] The control terminals 140, 150 are the gate control terminal and Kevin source control terminal of the high-side power switch 30. The control terminals 160, 170 are the gate control terminal and Kevin source control terminal of the low-side power switch 50. The control terminals 180, 190 are the two nodes of a negative temperature coefficient (NTC) thermistor 60 (Figure 7) included within the module 100.

[0057] Figure 3 shows a side view of the module 100 (with the housing 60 completely omitted for clarity). The module 100 comprises a lower substrate 10 and an upper substrate 20. The role of the substrates 10, 20 is to provide the interconnections to form an electric circuit and to cool the power switching devices 30, 50. Compared to materials and techniques (e.g., printed circuit boards) used in lower power microelectronics, the substrates 10, 20 must carry higher currents and provide a higher voltage isolation (up to several thousand volts). They also must operate over a wide temperature range (up to 150 or 200 °C).

[0058] The lower substrate 10 has two electrically insulating layers (hereinafter, “insulating layers”) 1 and 2 stacked with three electrically conductive layers (hereinafter, “conductive layers”) 11, 12, 13 along a stacking direction Z. The stacking direction Z is generally perpendicular to the surfaces of the insulating layers 1, 2. The conductive layer 11 forms a top surface of the lower substrate 10 that faces the power devices 30, 50. The conductive layer 13 forms a bottom surface of the lower substrate 10. The conductive layer 12 is an internal layer of the lower substrate 10 and is sandwiched between the insulating layers 1, 2. Due to the existence of the insulating layers 1, 2, adjacent conductive layers 11 to 13 would not be electrically shorted to one another without the use of conductive through-layer vias. As described in more detail below, the insulating layer includes through-layer vias 40-1 to 40-6 (collectively referred to as conducive vias 40) which selectively connect the conductive layer 11 to the conductive layer 12. The upper substrate 20 has an insulating layer 3 laminated with conductive layers 14, 15 at both sides. The conductive layer 14 faces the power devices 30, 50. The substrates 10, 20 may be referred to as the “first substrate” and the “second substrate”, respectively. The electrically insulating layers 1, 2 and 3 may referred to as the first to third electrically insulating layers, respectively. The electrically conductive layer 11 to 15 may referred to as the first to fifth electrically conductive layers, respectively. As described in more detail below with reference to Figures 4 and 5, each of the conductive layers 11 , 12 and 14 are patterned to separate regions of different voltage potentials. The conductive layers 13, 15 are generally kept plain.

[0059] The insulating layers 1, 2 and 3 may be made of a ceramic material (such as silicon nitride ceramic with a thermal conductivity of around 90 W / m K). The thickness of each of the insulating layers 1 to 3 may be between around 0.25mm and around 0.65mm. The conductive layers 11 to 15 are typically made of copper. The thickness of each of the conductive layers 11 to 15 may be between around 0.2mm to 0.8mm. The substrates 10, 20 may be made by integrating a ceramic plate with copper plates through bonding by the active metal brazing (AMB) method or direct copper bonding (DCB) method. The substrates 10, 20 are equipped with a high thermal conductivity and a high electric conductivity of copper and a high insulation property of ceramic substrate.

[0060] Figure 4 shows a perspective view of the lower substrate 10. The top conductive layer 11 of the lower substrate 10 is patterned to form conductive tracks 11-1 to 11-7 which are spaced apart (hence electrically isolated) from one another. The DC- terminal 120 is directly bonded to the conductive track 11-2. The DC+ terminal 110 as well as the drain electrodes of a group of four SiC MOSFETs 30 are directly bonded to the conductive track 11-3. The four SiC MOSFETs 30 collectively function as the high-side power switch 1200 of the half-bridge circuit 1000. Conductive spacers 33 are bonded to the source electrodes of the SiC MOSFETs 30, which are further wire-bonded to the conductive track 11-5 using bonding wires 38. The gate electrodes of the SiC MOSFETs 30 are wire-bonded to gate resistors mounted on the conductive track 11-4 using bonding wires 36. The high-side gate control terminal 140 is directly mounted on the conductive track 11-7. The high-side Kelvin source control terminal 150 is directly mounted on the conductive track 11-6.

[0061] The internal conductive layer 12 of the lower substrate 10 is shown in Figure 5. The internal conductive layer 12 is patterned to form conductive tracks 12-1 to 12-3 which are spaced apart (hence electrically isolated) from one another. Figure 6 further shows how the internal conductive layer 12 corresponds to the top conductive layer 11, by making the insulating layer 1 transparent. In particular, there are groups of conductive vias 40-1 to 40-6 formed within the insulating layer 1. The conductive vias are copper filled holes drilled through the insulating layer 1 in such a way as to provide a conductive pathway for current. The group of conductive vias 40-1 are formed at the overlapping area between the conductive track 12-1 and the conductive track 11-1, thereby electrically connecting the conductive tracks 11-1 and 12-1. The group of conductive vias 40-2 are formed at the overlapping area between the conductive track 12-1 and the conductive track 11-2, thereby electrically connecting the conductive tracks 12-1 and 11-2. Similarly, the group of conductive vias 40-3 electrically connect the conductive track 11-7 to a top, right, end of the conductive track 12-3. The group of conductive vias 40-4 electrically connect the conductive track 11-4 to a bottom, left, end of the conductive track 12-3. The group of conductive vias 40-5 electrically connect the conductive track 11-6 to a top, right, end of the conductive track 12-2. The group of conductive vias 40-6 electrically connect the conductive track 11-5 to a bottom, left, end of the conductive track 12-2.

[0062] As a result, the conductive track 12-1 of the internal conductive layer 12 and the conductive vias 40-1 and 40-2 electrically connect the conductive track 11-1 (which is electrically connected to the source electrodes of the low-side SiC MOSFETs 50 as described below) to the DC- terminal 120. Because the conductive track 12-1 and the conductive vias 40-1 and 40-2 are part of a power circuit of the module 100, the conductive track 12-1 is designed to be very wide and occupies a majority of the conductive layer 12, and each group of the conductive via 40-1 or 40-2 includes a large number of conductive vias. This is beneficial for reducing the parasitic resistance and inductance between the conductive track 11-1 and the DC- terminal 120, thereby improving the electrical efficiency and thermal performance of the module 100. The conductive track 12-3 of the internal conductive layer 12 and the conductive vias 40-3 and 40-4 electrically connect the conductive track 11-4 (which is electrically coupled to the gate electrodes of the high-side SiC MOSFETs 30 via gate resistors) to the high-side gate control terminal 140. The conductive track 12-2 of the internal conductive layer 12 and the conductive vias 40-5 and 40-6 electrically connect the conductive track 11-5 (which is electrically connected to the source electrodes of the high-side SiC MOSFETs 30) to the high-side Kelvin source control terminal 150. Therefore, the conductive tracks 12-2, 12-3 and the conductive vias 40-3 o 40-6 are part of a gate control circuit loop of the module 100. The width of the conductive track 12-2, 12-3 is significantly narrower than that of the conductive track 12-1 , and less number of conductive vias are used than those associated with the conductive track 12-1. This is because the gate current is at a significantly lower level than the power current of the module 100. The conductive tracks 11-1, 11-2, 11-7, 12-1, 12-3 may be referred to as the first to fifth conductive tracks, respectively. The conductive vias 40-1 , 40-2, 40-4, 40-3 may be referred to as the first to fourth conductive vias, respectively.

[0063] The use of the internal conductive layer 12 and the conductive vias 40 significantly improves the flexibility in the layout design of the module 100. More specifically, the power terminal 120 is no longer required to be placed immediately adjacent to the conductive track 11-1, and the gate control terminals 140, 150 are no longer required to be placed immediately adjacent to the high-side SiC MOSFETs 30. Further, the layout design of conductive tracks on the top conductive layer 11 is greatly simplified, because the top conductive layer 11 is no longer required to provide all of the electrical connections between the power devices and the power and control terminals. Rather, the top conductive layer 11 and the internal conductive layer 12 collectively provide the required electrical connections. As a result, the footprint of the lower substrate 10 can be greatly reduced as compared to conventional substrates which use a single conductive layer to provide all of the required electrical connections.

[0064] Figure 7 shows a perspective view of the upper substrate 20. The bottom conductive layer 14 of the upper substrate 20 is patterned to form conductive tracks 14-1 to 14-6 which are spaced apart (hence electrically isolated) from one another. The AC terminal 130 as well as the drain electrodes of a group of four SiC MOSFETs 50 are directly bonded to the conductive track 14-1. The four SiC MOSFETs 50 collectively function as the low-side power switch 1400 of the half-bridge circuit 1000. Conductive spacers 53 are bonded to the source electrodes of the SiC MOSFETs 50, which are further wire- bonded to the conductive track 14-3 using bonding wires 58. The gate electrodes of the SiC MOSFETs 50 are wire-bonded to gate resistors mounted on the conductive track 14-2 using bonding wires 56. The low-side gate control terminal 160 is directly mounted on the conductive track 14-4, which is electrically connected to the conductive track 14- 2 by way of a bond wire. The low-side Kelvin source control terminal 170 is directly mounted on the conductive track 14-3. The two terminals 180, 190 of the NTC thermistor 60 are directly mounted on the conductive track 14-5, 14-6, respectively.

[0065] The conductive spacers 33, 53 may be of the composition of 60% molybdenum and 40% copper, where % means percent by weight. This particular composition of the spacer is chosen such that the spacer is electrically conductive enough to complete the half-bridge circuit without introducing undue resistance, whilst maintaining a coefficient of thermal expansion (CTE) low enough that it will not expand excessively under heating and, in doing so, introduce stress in to the module stack and limit its reliability.

[0066] The module 100 can be assembled in various different ways. In one example, the high- side SiC MOSFETs 30, the DC+ terminal 110, the DC- terminal 120, and the control terminals 140, 150 are bonded to the respective conductive tracks 11-3, 11-2, 11-7, 11- 6 of the lower substrate 10 using a conductive silver layer in a pressure-less silver sintering process. The spacers 33 may be bonded to the source electrodes of the SiC MOSFETs 30 using the same silver sintering process. The gate and source electrodes of the SiC MOSFETs 30 are bonded to the respective conductive tracks 11-4 and 11-5 of the lower substrate 10 using single ultrasonically welded wire-bond connections. In the meantime, the upper substrate 20 are processed similarly. In particular, the AC terminal 130, the low-side SiC MOSFETs 50 and the control terminals160 to 190 are bonded to the respective conductive tracks 14-1 , 14-4, 14-3, 14-5, 14-6 of the upper substrate 20 using a conductive silver layer in a pressure-less silver sintering process. The spacers 53 may be bonded to the source electrodes of the SiC MOSFETs 50 using the same silver sintering process. The gate and source electrodes of the SiC MOSFETs 50 are separately bonded to the conductive tracks 14-2 and 14-3 of the lower substrate 10 using single ultrasonically welded wire-bond connections.

[0067] Subsequently, the substrates 10, 20, complete with SiC MOSFETs 30, 50 and conductive spacers 33, 53, are joined face to face such that the spacers 33 forms an electrical contact with the upper substrate 20 and the spacers 53 forms an electrical contact with the lower substrate 10. The joined substrate stack is as shown in Figure 3. The purpose of the spacers 33, 53 is to selectively provide electrical connections between the upper substrate 20 and the lower substrate 10, while ensuring electrical isolation between the components (e.g., wire bonds, power terminals and control terminals) mounted on one substrate and the conductive tracks of the opposite substrate. The height of the spacers 33, 53 also determines the height of the substrate stack.

[0068] In the final substrate stack, the drain electrodes of the low-side SiC MOSFETs 50 are electrically connected to the source electrodes of the high-side SiC MOSFETs 30 by the spacers 33 and the conductive track 14-1 , which is further electrically connected to the AC terminal 130. The source electrodes of the low-side SiC MOSFETs 50 are electrically connected to the DC- terminal 120 by the spacers 53, the conductive track 11-1, the through-layer vias 40-1, the conductive track 12-1, the through-layer vias 40-2 and the conductive track 11-2. The drain electrodes of the high-side SiC MOSFETs 30 are electrically connected to the DC+ terminal 110 by the conductive track 11-3. In this way, the module 100 realises a half-bridge circuit.

[0069] The substrate stack (Figure 3) is then over-moulded with a high-temperature, electrically insulating, plastic material (e.g., epoxy moulding compound), in order to provide a mechanically and electrically stable package. The moulding compound becomes the housing 60 of the module 100. The power terminals 110-130 and the control terminals 140-190 are left to protrude from the housing 60 to enable external connections to the module 100. The outer surfaces of the substrate stack (i.e., the conductive layers 15, 13) are left free from the plastic material during the overmoulding process, and therefore are largely exposed to an exterior of the module 100 (as shown in Figure 2).

[0070] In use, the conductive layers 13, 15 provide thermally conductive surfaces that may be utilised to cool the module 100. In particular, cooling of the module 100 may be applied either through sandwiching the module 100 between two actively cooled heatsinks with an interface of thermally conductive material (e.g., grease based thermal interface material or otherwise), or by sandwiching the module 100 between two cooling baths such that each exposed side of the module 100 comes in to direct contact with the cooling fluid used. The overall effect is a power module that is cooled much more efficiently than would be possible using a more traditional, single side cooled, baseplate-based package.

[0071] In terms of the electrical performance, the module 100 has a reduced overall parasitic inductance in the switching loop and thus an improved switching efficiency as compared to known power modules. This is described below in more details.

[0072] With reference to Figure 1 , parameters indicating the switching performance of the halfbridge circuit 1000 include parasitic inductances of the commutation loops (i) DC+ — > T1&T2 D3&D4 DC- and (ii) DC+^ D1&D2 T3&T4 DC-. Ideally, the parasitic inductances should be minimised.

[0073] Figure 8 schematically illustrates the path of a commutation loop within the power module 100. Because the module 100 uses SiC MOSFETs 30, 50, each of which can be treated as a combination of a power transistor and a diode shown in Figure 1 , the commutation loops (i) and (ii) share substantially the same path. With reference to Figures 4 to 8, the path of the commutation loop is in the following order: DC+ terminal 110 -> the conductive track 11-3 of the conductive layer 11 -> the high-side SiC the conductive track 14-1 of the conductive layer 14 the spacers 53 the conductive track 11-1 of the conductive layer 11 -> the conductive vias 40-1 within the insulating layer 1 the conductive track 12-1 of the internal conductive layer 12 the conductive vias 40-2 within the insulating layer 1 the conductive track 11-2 of the conductive layer 11 -> the DC- terminal 120. As shown in Figure 8, due to the particular layout design of the module 100, the commutation loop generally loops around the right-side half of the module 100, and has a relatively small loop size. Further, the pathway of the commutation loop comprises two groups of conductive spacers 33, 53 and wide conductive tracks 11-3, 14-1 , 11-1 , 12-1 and 11-2, each of which has a relatively small resistance and inductance.

[0074] Known power modules typically mount both high-side and low-side power switches on the same substrate. This means that the drain electrodes (or the equivalent collector electrodes for IGBTs) of all devices are directly bonded to a surface conductive layer of one substrate. In the event that two substrates are used to achieve double-sided cooling, an additional group of large, inter-substrate, spacers would be required to complete the functional half-bridge circuit. The commutation loop would have a greater loop size than what is shown in Figure 8 because it shall pass through the intersubstrate spacers. Further, because the substrate on which all of the power devices are mounted would be a traditional substrate without any internal conductive layer similar to the layer 12, the surface conductive layer of the substrate would be required to provide all of the electrical connections. Thus, with the same substrate footprint, the conductive traces provided by the surface conductive layer would be narrower than those provided by the lower substrate 10. As a result, the known power modules often possess high parasitic inductance in its commutation loop, which leads to a relatively low switching efficiency.

[0075] In comparison, the module 100 has a better switching performance than known power modules. By mounting the high-side and low-side power switches 30, 50 to opposite substrates 10, 20, the module 100 does not require any inter- substrate spacers. Accordingly, the overall conductive path of the commutation loop within the module 100 can be drastically reduced as compared to known power modules. By routing some of the conductive pathway through the internal conductive layer 12 of the substrate 10, the conductive tracks (e.g., 11-3, 11-1, 12-1 and 11-2) provided by the substrate 10 would be significantly wider than those provided by the substrate of a known module under the same substrate footprint. Both of these two factors lead to a reduction in the parasitic inductance within the commutation loop of the module 100, thereby contributing to a reduction in switching losses and allowing the module 100 to operate faster and more efficiently.

[0076] The removal of the need for large, inter-substrate, spacers further reduces the required footprint for the module 100, which in turn increases the power density of the module 100 over that can be achieved by known power modules. This increase in power density is in conjunction with the aforementioned increase in power density that is achieved through the utilisation of the integrated body diodes of SiC MOSFETs in place of external antiparallel diodes that is required to operate with IGBTs.

[0077] In the module 100, each of the high-side and low-side power switches includes a group of four power devices. It would be understood that the number of power devises in the design could be altered in order to produce a module with the same functionality but rated to a higher or lower voltage and / or current output.

[0078] In the module 100, the internal conductive layer 12 of the lower substrate 10 is electrically connected between the source electrodes of the low-side power devices 50 and the DC- terminal 120 of the half-bridge circuit. It would be understood that the module 100 may be readily modified such that the internal conductive layer 12 is electrically connected between the source electrodes of the high-side power devices 30 and the drain electrodes of the low-side power devices 50 (i.e., to the AC terminal 130), or between the drain electrodes of the high-side power devices 30 and the DC+ terminal 110. The modification may be carried out by suitably modifying the layout of some of the conductive layers 11, 12, 14, and / or adjusting the positions of some of the terminals 110 to 180.

[0079] While the module 100 described above comprises both high-side and low-side power switches which form a half-bridge circuit, it would be appreciated that the module 100 may be modified to have a single switch configuration rather than a half-bridge. Likewise, the number of power devices within the module 100 could be increased to produce a different internal circuit configuration, e.g., a three-phase inverter, rather than a single-phase half bridge inverter. Further, the module 100 may be modified to be a single-side cooled power module with the lower substrate 10 alone. Indeed, the design of the substrate 10 (in particular, the provision of the internal conductive layer 12 and the conductive vias in the insulating layer 1) may benefit the layout design of any type of power modules. In addition, the upper substrate 20 (which has the structure of a conventional substrate) of the module 100 may be replaced by a substrate similar to the lower substrate 10 which has an internal conductive layer.

[0080] The module 100 is intended primarily for use in automotive inverter applications for the driving of electric motors intended for the propulsion of EVs or HEV. It would however be appreciated that the module 100 could conceivably be utilised in any industrial application calling for a similar, low volume, low voltage, switching device with an emphasis on reliability and low inductance.

[0081] Figure 9 describes processing steps of a method for manufacturing a power semiconductor module (e.g., the module 100). At step S1, a power semiconductor device (e.g., one or more of the low-side SiC MOSFETs 50) is provided. The power semiconductor device has first and second power electrodes (e.g., drain and source electrodes).

[0082] At step S2, a substrate (e.g., the lower substrate 10) is provided. The substrate comprises first and second electrically insulating layers (e.g., the insulating layers 1, 2) stacked with first and second electrically conductive layers (e.g., the conductive layers 11 , 12). The first electrically insulating layer (e.g., the insulating layer 1) is arranged between the first and second electrically conductive layers (e.g., the conductive layers 11 , 12), and the second electrically conductive layer (e.g., the conductive layer 12) is arranged between the first and second electrically insulating layers (e.g., the insulating layers 1, 2). The first electrically conductive layer comprises first and second conductive tracks (e.g., the conductive tracks 11-1 , 11-2) which are spaced apart from one another. The first electrically insulating layer (e.g., the insulating layer 1) comprises a first conductive via (e.g., the through-layer vias 40-1) which electrically connects the first conductive track (e.g., the conductive track 11-1) to at least a part of the second electrically conductive layer (e.g., the conductive track 12-1 of the layer 12), and a second conductive via (e.g., the through-layer vias 40-2) which electrically connects the second conductive track (e.g., the conductive track 11-2) to the at least a part of the second electrically conductive layer (e.g., the conductive track 12-1 of the layer 12).

[0083] At step S3, one of the first and second power electrodes (e.g., the source electrode) is electrically connected to the first conductive track (e.g., the conductive track 11-1). The electrical connection may be achieved by direct bonding or by inserting a conductive spacer (such as the spacers 53) between the first / second power electrodes and the first conductive track.

[0084] In the event that the module further comprises a second substrate (e.g., the upper substrate 20) having a third electrically insulating layer (e.g., the insulating layer 3) and a fourth electrically conductive layer (e.g., the conductive layer 14) arranged on a surface of the third electrically insulating layer that faces the power semiconductor device, the method may include the following optional step: At step S4, the other of the first and second power electrodes (e.g., the drain electrode) is electrically connected to at least a part of the fourth electrically conductive layer (e.g., the conductive layer 14).

[0085] In the event that the module has a further, second, power semiconductor device (e.g., one or more of the high-side SiC MOSFETs 30) comprising third and fourth power electrodes (e.g., source and drain electrodes), wherein the third power electrode (e.g., the source electrode) is electrically connected to the second power electrode (e.g., the drain electrode) of the power semiconductor device (e.g., one or more of the low-side SiC MOSFETs 50), the method may include the following optional steps:

[0086] At step S5, one of the first and second power semiconductor devices is directly mounted on the fourth electrically conductive layer of the second substrate, and the other one of the first and second power semiconductor devices is directly mounted on the first electrically conductive layer of the first substrate. In this way, the first and second power semiconductor devices are mounted on the opposite substrates of the module. Preferably, the drain electrodes (or collector electrodes for IGBTs) of the first and second power semiconductor devices are mounted on the opposite substrates.

[0087] At step S6, the first and second substrates are bonded to one another with the first electrically conductive layer facing the fourth electrically conductive layer. As such, the first and second power semiconductor devices are positioned and also electrically connected between the first and second substrates.

[0088] At step S7, the bonded first and second substrates are then encapsulated. The encapsulant forms a housing (e.g., the housing 60) of the power semiconductor module. The encapsulant may comprise epoxy moulding compound.

[0089] All joints in the module are made by a suitable technology, which may include sintering, soldering or bonding by conductive epoxy resin.

[0090] It would be appreciated that the steps may be performed in a temporal order that is different from the order of description. For example, step S3 (or S4) may be performed during step S5 or S6. The terms “having”, “containing”, “including”, “comprising” and the like are open and the terms indicate the presence of stated structures, elements or features but not preclude the presence of additional elements or features. The articles “a”, “an” and “the” are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

[0091] The skilled person will understand that in the preceding description and appended claims, positional terms such as ‘upper’, ‘lower’, ‘top’, ‘bottom’, ‘vertical’, etc. are made with reference to conceptual illustrations of a power semiconductor module, such as those showing standard cross-sectional perspectives and those shown in the appended drawings. These terms are used for ease of reference but are not intended to be of limiting nature. These terms are therefore to be understood as referring to a device when in an orientation as shown in the accompanying drawings.

[0092] Although the disclosure has been described in terms of preferred embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives in view of the disclosure which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may be incorporated in the disclosure, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein.

Claims

CLAIMS:

1. A power semiconductor module comprising: a power semiconductor device comprising first and second power electrodes; and a substrate comprising first and second electrically insulating layers stacked with first and second electrically conductive layers, wherein the first electrically insulating layer is arranged between the first and second electrically conductive layers, and the second electrically conductive layer is arranged between the first and second electrically insulating layers, and wherein: the first electrically conductive layer comprises first and second conductive tracks which are spaced apart from one another; the first electrically insulating layer comprises a first conductive via which electrically connects the first conductive track to at least a part of the second electrically conductive layer, and a second conductive via which electrically connects the second conductive track to the at least a part of the second electrically conductive layer; and one of the first and second power electrodes is electrically connected to the first conductive track.

2. The power semiconductor module of claim 1 , wherein: the substrate further comprises a third electrically conductive layer, and the second electrically insulating layer is arranged between the second and third electrically conductive layers; and the third electrically conductive layer is exposed to an exterior of the power semiconductor module for thermally coupling to a heat removal structure.

3. The power semiconductor module of claim 1 or 2, wherein one or more of the first and second electrically insulating layers comprise a ceramic material.

4. The power semiconductor module of any preceding claim, wherein one or more of the first and second electrically conductive layers comprise copper.

5. The power semiconductor module of any preceding claim, wherein:the substrate is a first substrate, and the power semiconductor module further comprises a second substrate having a third electrically insulating layer and a fourth electrically conductive layer arranged on a surface of the third electrically insulating layer that faces the power semiconductor device; the power semiconductor device is arranged between the first substrate and the second substrate; and the other of the first and second power electrodes is electrically connected to at least a part of the fourth electrically conductive layer.

6. The power semiconductor module of any preceding claim, wherein the first and second power electrodes are arranged on opposite surfaces of the power semiconductor device.

7. The power semiconductor module of any preceding claim, wherein the power semiconductor device comprises a power MOSFET.

8. The power semiconductor module of any preceding claim, wherein the power semiconductor device comprises a silicon carbide MOSFET.

9. The power semiconductor module of any preceding claim, wherein the power semiconductor device is a first power semiconductor device, and the power semiconductor module further comprises: a second power semiconductor device comprising third and fourth power electrodes, wherein the third power electrode is electrically connected to the second power electrode of the first power semiconductor device.

10. The power semiconductor module of claim 9 as dependent from claim 5, wherein: one of the first and second power semiconductor devices is directly mounted on the fourth electrically conductive layer of the second substrate; and the other one of the first and second power semiconductor devices is directly mounted on the first electrically conductive layer of the first substrate.

11. The power semiconductor module of claim 10, further comprising: a first conductive spacer arranged between and electrically connecting the one of the first and second power semiconductor devices and the first substrate; anda second conductive spacer arranged between and electrically connecting the other one of the first and second power semiconductor devices and the second substrate.

12. The power semiconductor module of claim 11 , wherein one or more of the first and second conductive spacers are of a composition of 60% molybdenum and 40% copper.

13. The power semiconductor module of any one of claims 9 to 12, wherein: the first power semiconductor device is configured to block a voltage with a higher potential at the second power electrode than at the first power electrode; the second power semiconductor device is configured to block a voltage with a higher potential at the fourth power electrode than at the third power electrode; and one of the second and fourth power electrodes is directly mounted on the fourth electrically conductive layer of the second substrate, and the other one of the second and fourth power electrodes is directly mounted on the first electrically conductive layer of the first substrate.

14. The power semiconductor module of any preceding claim as dependent from claim 9, wherein the second power electrode is electrically connected to the first conductive track and the third power electrode is electrically connected to the second conductive track.

15. The power semiconductor module of any of claims 1 to 13 as dependent from claim 9, wherein the first power electrode is electrically connected to the first conductive track and the power semiconductor module further comprises a first power terminal which is electrically connected to the second conductive track.

16. The power semiconductor module of any preceding claim as dependent from claim 9, wherein: the first power semiconductor device further comprises a first control electrode configured to control a power current flowing between the first power electrode and the second power electrode, and the second power semiconductor device further comprises a second control electrode configured to control a power current flowing between the third power electrode and the fourth power electrode;the first electrically conductive layer comprises a third conductive track spaced apart from the first and second conductive tracks, and the power semiconductor module comprises a control terminal directly mounted on the third conductive track; the second electrically conductive layer comprises fourth and fifth conductive tracks which are spaced apart from one another, and the fourth conducting track is electrically connected to the first and second conductive vias; and the first electrically insulating layer comprises a third conductive via electrically coupling one of the first and second control electrodes to the fifth conductive track, and a fourth conductive via electrically connecting the fifth conductive track to the third conductive track.

17. A method of manufacturing a power semiconductor module, comprising: providing a power semiconductor device comprising first and second power electrodes; providing a substrate comprising first and second electrically insulating layers stacked with first and second electrically conductive layers, wherein: the first electrically insulating layer is arranged between the first and second electrically conductive layers, and the second electrically conductive layer is arranged between the first and second electrically insulating layers; the first electrically conductive layer comprises first and second conductive tracks which are spaced apart from one another; the first electrically insulating layer comprises a first conductive via which electrically connects the first conductive track to at least a part of the second electrically conductive layer, and a second conductive via which electrically connects the second conductive track to the at least a part of the second electrically conductive layer; and electrically connecting one of the first and second power electrodes to the first conductive track.

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