Power semiconductor module

Abstract

There is provided a power semiconductor module (100) which comprises a substrate (1), a power semiconductor device (20) mounted on the substrate (1), and a circuit board assembly (8) overlying the substrate (1). The power semiconductor device (20) comprises a first power electrode (23), a second power electrode (22) and a control electrode (24). The circuit board assembly (8) comprises a main body (35) for receiving a control signal for controlling a power current flowing between the first and second power electrodes, and a projecting member (36). The projecting member (36) is directly attached to the power semiconductor device (20) so as to form an electrical connection to the control electrode (24). The main body (35) and the projecting member (36) are electrically coupled to one another so as to collectively provide a conductive pathway for the control signal to travel from the main body (35) to the control electrode (24).

Description

[0001] Power Semiconductor Module

[0002] Technical Field

[0003] This disclosure relates to a power semiconductor module and a method of manufacturing the same. More particularly, but not exclusively, this disclosure relates to a power semiconductor module which uses a circuit board assembly with a flexible projecting member to realise a direct electrical connection to a control electrode of a power semiconductor device within the module.

[0004] Wide bandgap (WBG) power semiconductor devices such as Gallium-Nitride High- electron-mobility transistors (GaN HEMT s) are capable of switching with faster slew rates than traditional silicon-based power semiconductor devices, such as metal-oxide- semiconductor field-effect transistors (MOSFETs) and insulated gate bipolar transistors (IGBTs). Energy loss during a switching transition is directly related to the time duration of the transition. Therefore, the ability to switch with faster slew rates leads to a reduction in switching energy loss and is a key advantage of power semiconductor devices made from WBG materials rather than silicon.

[0005] Traditional power modules, used for packaging silicon-based power semiconductor devices, are manufactured using patterned copper-clad ceramic substrates, wire bonds and auxiliary pins to make the interconnections between the copper tracks and the chips. This technology is mature, flexible, and suitable for mass production but it brings with it a number of issues. First, the wire bonds and auxiliary pins have high inductance due to their relatively small cross-sectional area and sub-optimal shape. Second, the two- dimensional planar nature of the patterned copper on the substrate limits the capability of the designer to minimise inductance by forcing the use of indirect paths. Third, magnetic flux cancellation techniques, such as closely coupling conductors with opposing current flow directions, are difficult to achieve due to the aforementioned two- dimensional planar nature of the patterned copper on the substrate.

[0006] High inductance is incompatible with switching at the faster slew rates enabled by WBG semiconductors, because the high current slew rates (di / df) interact with parasitic inductances generating voltage overshoots and oscillations. The present disclosure is mainly concerned with voltage overshoots and oscillations in the gate loop, however the issues presented can affect the power loop as well.

[0007] Voltage oscillations appearing between the gate and source, caused by the interaction between the current slew rate (di / dt) and the stray inductance of the gate loop, has two effects: (1) spurious voltages caused by parasitic inductances are opposite in polarity to the driving voltage. This slows down the switching transition, which in turn increases energy losses by increasing the V * I product of the drain-source voltage and drain current during the switching transition; (2) if the magnitude of the voltage oscillations exceeds or drops below the device’s threshold voltage, it can cause false turn-on or false turn-off, which can potentially damage the device.

[0008] GaN enhancement-mode HEMTs have maximum gate to source voltages of 5V or 6V, and very low threshold voltages, typically 1 ,5V. But the device requires 4 to 5V to be fully turned on. This leaves very small margins for the gate-source voltage, and increases the device sensitivity to false turn-on / turn-off when switching at faster slew rates.

[0009] The high inductance of the wire bonds and auxiliary pins in traditional power module designs limits the maximum performance of WBG-based semiconductor modules. To extract the ultimate performance of WBG semiconductors, packaging designs with reduced inductance are required.

[0010] High switching speeds also interact with parasitic capacitances and inductances to cause electromagnetic interference (EMI). High dv / dt transients interact with parasitic capacitances to produce displacement currents. High di / dt transients interact with parasitic inductances to produce fluctuations in voltages. Current loops can cause radiated EMI. To minimise EMI, physical current loop sizes should be as small as possible, and parasitic inductances should be minimised and balanced.

[0011] A known method for making the gate and Kelvin source connections between a chip within a power module and gate circuit terminals of the power module is described below with reference to Figures 1 to 4.

[0012] Figures 1 and 2 show a power semiconductor module 100’ which has a printed circuit board (PCB) 8’, a substrate T and power chips 20’. Source pads 23’ and drain pads 22’ of the chips 20’ are connected to conductive pads 3’ and 4’ of the substrate T by power connections 27’, 28’, respectively. The PCB 8’ sits above the chips 20’ and the power connections 27’, 28’, and is attached by solder to multiple auxiliary pins 25’ and 26’. The auxiliary pins 25’ and 26’ are in turn soldered or sintered to conductive pads 5’, 6’ of the substrate T, respectively. Bond wires 29’, 30’ connect the conductive pads 5’, 6’ to the respective gate pads 24’ and the source pads 23’ of the chips 20’. Gate circuit terminals of the module 100’ include a gate control terminal 3T and a Kelvin source control terminal (not labelled), which are attached to a top metal layer 1 T of the PCB 8’.

[0013] The current flow paths in the gate circuit of the module 100’ are shown in Figures 3 and 4. The current is picked up by the PCB 8’ from the gate control terminal 3T, and is routed on the top metal layer 1 T to a through-layer via 33’, which connects the signal to the auxiliary pin 25’. The current then travels through the conductive pad 5’ and the bond wire 29’ to the gate pad 24’ of each chip 20’. In Figure 4, dashed lines show the current flow from the gate control terminal 3T to the chips 20’, and solid lines show the current flow from the chips 20’ to the Kelvin source control terminal. The gate and Kelvin source currents overlap in the sectional view of Figure 3. The planar nature of this type of layout causes part of the current loop to lie in the XY plane (Figure 4), as well as in the YZ plane (Figure 3). This increases the size of the current loop, which in turn increases the loop inductance. Furthermore, the wire bonds and auxiliary pins have high inductance due to their relatively small cross-sectional area and sub-optimal shape, thus also contributing towards increasing the value of the gate circuit loop inductance.

[0014] It is an object of the present disclosure, among others, to provide an improved power semiconductor module that solves problems associated with conventional power semiconductor modules, whether identified herein or otherwise.

[0015] Summary

[0016] According to a first aspect of the present disclosure, there is provided a power semiconductor module comprising: a substrate; a power semiconductor device mounted on the substrate, wherein the power semiconductor device comprises a first power electrode, a second power electrode and a control electrode; and a circuit board assembly overlying the substrate, wherein: the circuit board assembly comprises a main body for receiving a control signal for controlling a power current flowing between the first and second power electrodes, and a projecting member; the projecting member is directly attached to the power semiconductor device so as to form an electrical connection to the control electrode; and the main body and the projecting member are electrically coupled to one another so as to collectively provide a conductive pathway for the control signal to travel from the main body to the control electrode.

[0017] It would be understood that each of the main body and the projecting member of the circuit board assembly may comprise at least one electrically insulating layer laminated with at least one electrically conductive layer. The circuit board assembly may also be referred to as a laminate structure or a laminate assembly.

[0018] Advantageously, by having the circuit board assembly overlying the substrate and by arranging the projecting member to directly attach to the power semiconductor device, the circuit board assembly makes a direct electrical connection to the control electrode of the power semiconductor device. As compared to lengthy and thin bond wires and auxiliary pins conventionally used in known power modules, this direct electrical connection, combined with the use of relatively wide conductive layers within the circuit board assembly, provides a significant reduction in the parasitic resistance and inductance of the conductive pathway of the control signal. Further, the direct electrical connection between the circuit board assembly and the power semiconductor device has the effect of reducing the size of the control current loop which is further helpful for reducing the inductance of the conductive pathway of the control signal.

[0019] Further still, with the circuit board assembly overlying the substrate, the control signal can be connected as close as possible to the power semiconductor device, thereby reducing the need for lengthy conductive traces on the substrate and bond wires with small cross-sectional areas (i.e. lengthy high-inductance current path for the control signal as used in prior power modules).

[0020] Having the circuit board assembly overlying the substrate also allows the footprint of the power semiconductor module to be reduced, because auxiliary traces, pins and bond wires are no longer required at the substrate level.

[0021] Therefore, the present disclosure provides a more compact power semiconductor module which allows the parasitics of the control current loop to be significantly reduced as compared to prior modules. The power semiconductor module is particularly suitable for use with wide bandgap power semiconductor devices.

[0022] The main body may be generally planar. The projecting member may project (or protrude) from the main body.

[0023] The main body may have a larger area than the projecting member. A footprint of the main body may be substantially the same as a footprint of the substrate.

[0024] With the expression “directly attached”, it is meant that no other structure is between the projecting member and the power semiconductor device (except a small amount of bonding material used). The projecting member may be directly attached to the control electrode of the power semiconductor device by sintering, soldering or bonding by conductive epoxy resin. The expression “directly mounted” has a similar meaning in the present disclosure.

[0025] The term “electrically coupled” includes that one or more intervening element(s) adapted for signal transmission may or may not exist between the electrically coupled elements.

[0026] The power semiconductor device may be arranged between the substrate and the circuit board assembly.

[0027] It would be understood that the power semiconductor device may comprise more than one power semiconductor die which are electrically connected together in any suitable manner (e.g., in series or in parallel).

[0028] The power semiconductor module may be a single-side cooled module. In other words, the power semiconductor module may comprise a single substrate thermally coupled to a heat removal structure (such as a heat sink).

[0029] The projecting member may be flexible.

[0030] The projecting member may be more flexible than the main body. The projecting member may comprise a first end region and a second end region. The first end region may be mechanically and electrically coupled to the main body. The second end region may be directly attached to the power semiconductor device so as to form the electrical connection to the control electrode.

[0031] The main body may extend along a first plane. At least a part of the projecting member may extend away from the first plane and towards the control electrode of the power semiconductor device.

[0032] The first plane may be parallel to a surface of the substrate.

[0033] At least a part of the projecting member may extend along a direction which forms an angle with respect to the first plane, and the angle is between 0° and 90°.

[0034] The main body may comprise a cut-out region, and the projecting member may project from an edge of the cut-out region.

[0035] The main body may comprise an electrically conductive layer which forms a surface of the main body that faces the power semiconductor device. The electrically conductive layer may be isolated from voltage potentials of the electrodes of the power semiconductor device.

[0036] Advantageously, the electrically conductive layer may be used as a shielding layer, to shield the sensitive control circuitry from any radiated EMI emissions from the power circuit of the power semiconductor device.

[0037] The power semiconductor module may further comprise a housing which encloses the power semiconductor device and an entirety of the circuit board assembly.

[0038] The power semiconductor module may further comprise a control terminal for receiving the control signal, wherein the control terminal is electrically connected to the main body of the circuit board assembly, and at least a part of the control terminal is exposed to an exterior of the power semiconductor module. In other words, the control terminal may protrude beyond the housing of the power semiconductor module, for receiving an external control signal from an electronic environment of the power semiconductor module.

[0039] Within the present disclosure, the term “electrically connected” describes a permanent low-ohmic connection between electrically connected elements, for example a direct contact between the concerned elements or a low-ohmic connection via a metal.

[0040] The control terminal may be a first control terminal, and the power semiconductor module may further comprise a second control terminal which is electrically coupled to the first power electrode by the circuit board assembly.

[0041] The control signal may be applied across the first and second control terminals.

[0042] It would be appreciated that the power semiconductor device would be configured to block a voltage with a higher potential at the second power electrode than at the first power electrode. The second control terminal may have similar features to the first control terminal as described above.

[0043] The main body may be rigid. The rigid main body is useful for supporting control terminal(s) of the power semiconductor module. In particular, the control terminal(s) of the power semiconductor module may be directly mounted on the rigid main body.

[0044] The projecting member may comprise a first electrically insulating layer and first and second electrically conductive layers arranged on opposite sides of the first electrically insulating layer. At least a part of the first electrically conductive layer may be electrically connected to the control electrode, and at least a part of the second electrically conductive layer may be electrically connected to the first power electrode.

[0045] At least a part of the first electrically conductive layer may be electrically coupled to the first control terminal, and at least a part of the second electrically conductive layer may be electrically coupled to the second control terminal. The circuit board assembly may further comprise a connector which mechanically and electrically couples the projecting member and the main body. The connector may be a flexible printed circuit connector.

[0046] The main body may comprise a second electrically insulating layer and third and fourth electrically conductive layers arranged on opposite sides of the second electrically insulating layer. The connector may electrically connect at least a part of the first electrically conductive layer of the projecting member to at least a part of the third electrically conductive layer, and may further electrically connect at least a part of the second electrically conductive layer of the projecting member to at least a part of the fourth electrically conductive layer.

[0047] Alternatively, the main body and the projecting member may be integrally formed.

[0048] The main body may comprise a second electrically insulating layer and third and fourth electrically conductive layers arranged on opposite sides of the second electrically insulating layer. The first and second electrically insulating layers may be integrally formed. The first and third electrically conductive layers may be integrally formed. The second and fourth electrically conductive layers may be integrally formed.

[0049] The main body may further comprise: third and fourth electrically insulating layers which sandwich the second electrically insulating layer and the third and fourth electrically conductive layers; fifth and sixth electrically conductive layers which sandwich the second to fourth electrically insulating layers and the third and fourth electrically conductive layers, wherein the fifth electrically conductive layer comprises first and second conductive tracks which are spaced apart from one another and supports the first and second control terminals, respectively; a first conductive via which electrically connects at least a part of the third electrically conductive layer to the first conductive track; and a second conductive via which electrically connects at least a part of the fourth electrically conductive layer to the second conductive track. The sixth electrically conductive layer may face the power semiconductor device, and is not electrically connected to the third or fourth electrically conductive layers. In other words, the sixth electrically conductive layer is isolated from voltage potentials of the electrodes of the power semiconductor device, and may be used as a shielding layer to shield the sensitive control circuitry from radiated EMI emissions.

[0050] The first and second control terminals may be bonded between the main body and the substrate. The first control terminal may be electrically connected to at least a part of the third electrically conductive layer. The second control terminal may be electrically connected to at least a part of the fourth electrically conductive layer.

[0051] The power semiconductor module may further comprise a spacer which maintains a clearance between the substrate and the circuit board assembly along a direction perpendicular to a surface of the substrate.

[0052] The power semiconductor device may comprise a wide bandgap power semiconductor device.

[0053] According to a second aspect of the present disclosure, there is provided a method of manufacturing a power semiconductor module, comprising: mounting a power semiconductor device on a substrate, wherein the power semiconductor device comprises a first power electrode, a second power electrode and a control electrode; positioning a circuit board assembly above the substrate, wherein the circuit board assembly comprises a main body for receiving a control signal for controlling a power current flowing between the first and second power electrodes, and a projecting member; and directly attaching the projecting member to the power semiconductor device so as to form an electrical connection to the control electrode; wherein the main body and the projecting member are electrically coupled to one another so as to collectively provide a conductive pathway for the control signal to travel from the main body to the control electrode.

[0054] The term “about” or “approximately” used in the present disclosure indicate a degree of variability (e.g., 20%) in the stated numerical values.

[0055] It would also be understood that the terms “first” to “sixth” are simply used in the present disclosure to label the relevant elements (e.g., “power electrode”, “electrically conductive layer” etc.) for the ease of description, and do not imply any limitations to the sequence, locations or total number of the relevant elements.

[0056] Where appropriate any of the optional features described above in relation to one of the aspects of the disclosure may be applied to another one of the aspects of the disclosure.

[0057] Brief of the

[0058] In order that the disclosure may be more fully understood, a number of embodiments of the disclosure will now be described, by way of example, with reference to the accompanying drawings, in which:

[0059] Figure 1 is a schematic representation of a cross-sectional view of a known power semiconductor module;

[0060] Figure 2 is a schematic representation of a top plan view of the power semiconductor module of Figure 1 (with the PCB removed for clarity);

[0061] Figures 3 and 4 schematically illustrate paths of gate circuit currents within the power semiconductor module of Figure 1 ;

[0062] Figure 5 is a schematic representation of a cross-sectional view of a power semiconductor module according to a first embodiment of the present disclosure;

[0063] Figure 6 is a schematic representation of a top plan view of the power semiconductor module of Figure 5 (with part of the circuit board assembly cut away for clarity);

[0064] Figure 7 is a schematic representation of a top plan view of the circuit board assembly used within the power semiconductor module of Figure 5;

[0065] Figure 8 is a schematic representation of a cross-sectional view of the circuit board assembly used within the power semiconductor module of Figure 5;

[0066] Figure 9 schematically illustrates paths of gate circuit currents within the power semiconductor module of Figure 5; Figure 10 a schematic representation of a cross-sectional view of a power semiconductor module according to a second embodiment of the present disclosure;

[0067] Figure 11 a schematic representation of a cross-sectional view of a power semiconductor module according to a third embodiment of the present disclosure.

[0068] Figure 12 schematically illustrates processing steps of a method for manufacturing a power semiconductor module according to the present disclosure.

[0069] In the figures, like parts are denoted by like reference numerals.

[0070] It will be appreciated that the drawings are for illustration purposes only and are not drawn to scale.

[0071] Detailed Description of the Preferred Embodiments

[0072] Figures 5 and 6 schematically illustrate the structure of a power semiconductor module 100 (hereinafter, “module 100”) according to a first embodiment of the present disclosure. Figure 5 is a cross-sectional view of the module 100 along a Y-Z plane when the module 100 is cut along a line V-V’ in Figure 6.

[0073] As shown in Figures 5 and 6, the module 100 includes a substrate 1 , power semiconductor devices (hereinafter, “devices”) 20-1 , 20-2 (collectively referred to as 20) mounted on the substrate 1 , and a circuit board assembly 8 overlying the substrate 1 and the devices 20.

[0074] The substrate 1 includes an electrically insulating body 2, a patterned electrically conductive layer 5 arranged on its top surface, and another electrically conductive layer 7 arranged on its opposite bottom surface. The electrically insulating body 2 is typically made of ceramic or a suitable polymer. The conductive layers 5, 7 may be made of copper or other suitable conducting material such aluminum, copper-molybdenum alloy, or copper-tungsten alloy etc. The substrate may be a direct bonded copper (DBG) substrate, a directed bonded aluminium (DBA) substrate or an active metal brazed (AMB) substrate. The top electrically conductive layer 5 is patterned to separate regions of difference potentials, i.e., conductive tracks 3, 4. The conductive tracks 3, 4 are spaced apart from one another.

[0075] As shown in Figure 6, the devices 20-1 , 20-2 are mounted on the substrate 1. In an example, the devices 20-1 , 20-2 are GaN transistors (e.g., GaN HEMTs). Each of the devices 20-1 , 20-2 has a gate electrode 24, a source electrode 23 and a drain electrode 22, all of which are formed at the top surface of the device. The gate electrode 24 is a control electrode, and the source and drain electrodes 23, 22 are power electrodes. In particular, a voltage difference between the gate electrode 24 and the source electrode 23 determines the on / off status of a power current path between the drain electrode 22 and the source electrode 23. The bottom surfaces of the devices 20-1 , 20-2 are semiconductor substrates and are directly bonded to the conductive track 3 by bonding materials 21 (e.g., solder or sintering paste). Therefore, the devices 20-1 , 20-2 are thermally coupled to the substrate 1. The source and drain electrodes 23, 22 may be referred to as “first power electrode” and “second power electrode” of the devices 20, respectively.

[0076] Power connections 27 (e.g., copper clips) are used to connect the source electrodes 23 of the devices 20 to the conductive track 3. Power connections 28 (e.g., copper clips) are used to connect the drain electrodes 22 of the devices 20 to the conductive track 4. Therefore, the devices 20 are electrically connected in parallel with each other and collectively form a power switch. It would be understood that the number of the devices 20 included within the module 100 can be suitably varied depending upon the required current rating of the power switch. The devices 20 may be pre-packaged bare dies or packaged chips.

[0077] The circuit board assembly 8 is suspended above the substrate 1 by spacers 19 (also called PCB standoffs). In this example, the spacers 19 are press-fit into holes 37 (Figure 7) formed within the circuit board assembly 8 and rest on the top surface of the substrate 1. The spacers 19 maintain a clearance D between the substrate 1 and the circuit board assembly 8 along a vertical direction Z. The vertical direction Z is generally perpendicular to surfaces of the substrate 1. In the example of Figure 5, the devices 20 and the power connections 27, 28 are positioned between the substrate 1 and the circuit board assembly 8. The clearance D ensures the electrical isolation between the power connections 27, 28 and the circuit board assembly 8. The spacers 19 are typically made of an electrically insulating material (such as plastic).

[0078] Gate circuit terminals of the module 100 include a gate control terminal 31 and a Kelvin source control terminal 32, which are directly mounted to a top metal layer 11 of the circuit board assembly 8. The gate control terminal 31 and the Kelvin source control terminal 32 may be referred to as “first control terminal” and “second control terminal”, respectively. The circuit board assembly 8 is used to realise the electrical connections between the gate and source electrodes 24, 23 of the devices 20, and the gate circuit terminals 31 , 32 of the module 100. This is described in more detail below.

[0079] Figure 7 shows a top plan view of the circuit board assembly 8 while Figure 8 shows a cross-sectional view of the circuit board assembly 8 when it is cut along a line VI ll-VI IT in Figure 7. With reference to Figures 7 and 8, the circuit board assembly 8 has a main body 35 which is generally planar, and two projecting members 36-1 , 36-2 (collectively referred to as 36) which project from the main body 35. The main body 35 has a larger area than each of the projecting members 36. The footprint of the main body 35 is substantially the same as the footprint of the substrate 1. The main body 35 includes two cut-out regions (i.e. , holes) 38-1 , 38-2 (collectively referred to as 38). The cut-out regions 38 are designed such that when the main body 35 (with the spacers 19 inserted) is placed on top of the substrate 1 in position, the gate electrodes 24 and at least a part of the source electrodes 23 of the devices 20 are accessible through the cut-out regions 38. In other words, when the module 100 is viewed from the top along the Z- direction (as shown in Figure 6), the gate electrodes 24 and at least a part of the source electrodes 23 of the devices 20 fall within the boundaries of the cut-out regions 38. This arrangement allows a user to subsequently bend down the projecting members 36 and bond the projecting members 36 to the gate and source electrodes 24, 23 of the devices 20. It would be understood that the number of the cut-out regions 38 corresponds to the number of the devices 20.

[0080] With reference to Figures 7 and 8, each of the projecting members 36 projects from a right-side edge of a respective cut-out region 38-1 or 38-2. In other words, a right-end region of each projecting member 36 is mechanically and electrically coupled to the main body 35, and an opposite left-end region of the same projecting member 36 is a free end for bonding with a respective device 20 (by way of soldering, sintering, or conductive epoxy).

[0081] As shown in Figure 6, the projecting members 36 and the power connections 27 do not overlap along the X direction. Therefore, the projecting members 36 do not interfere with the power connections 27. As a result, the gate circuit of the devices 20 is electrically isolated from the power circuit of the devices 20.

[0082] The main body 35 is generally rigid, and the projecting members 36 are flexible. In other words, the projecting members 36 bend easily without breaking, while the main body 35 generally maintains its shape during use without experiencing noticeable deformation. The rigidity of the main body 35 allows the main body 35 to support the gate circuit terminals 31 , 32 of the module 100. The flexibility of the projecting members 36 allows the projecting members 36 to make a direct connection to the gate and source electrodes 24, 23 of the devices 20, as described in more detail below.

[0083] Each of the main body 35 and the projecting members 36 is a laminate structure, and includes one or more electrically insulating layer stacked with electrically conductive layers. With reference to Figure 8, each of projecting members 36 includes an electrically insulating layer 9 clad with two electrically conductive layers 12, 13 (such as, copper layers) on opposite sides. The electrically insulating layer 9 and the electrically conductive layers 12, 13 may be referred to as “first electrically insulating layer” and “first and second electrically conductive layers”, respectively. In an example, the electrically insulating layer 9 is made of polyimide and has a thickness of around 25.4pm. In this way, the electrically insulating layer 9 is flexible. The electrically conductive layers 12, 13 may be made of copper and each has a thickness of around 35pm. The main body 35 has the same layers 9, 12, 13 which extend continuously from the corresponding layers of the projecting members 36. In other words, the main body 35 and the projecting members 36 are integrally formed as a unitary structure. The main body 35 further comprises another two electrically insulating layers 10-1 , 10-2 which sandwich the layers 9, 12, 13, and are further clad with electrically conductive layers 11 , 14 on the outer surfaces of the main body 35. The electrically insulating layers 10-1 , 10-2 may be referred to as “third and fourth electrically insulating layers”, respectively, and the electrically conductive layers 11 , 14 may be referred to as “fifth and sixth electrically conductive layers”, respectively. In an example, the electrically insulating layers 10-1 , 10-2 are made of a glass-reinforced epoxy laminate material such as FR-4, and each has a thickness of around 0.8mm. In this way, the electrically insulating layers 10-1 , 10- 2 are generally rigid. The electrically conductive layers 11 , 14 may be made of copper and each has a thickness of around 35pm. Due to the extra layers 10-1 , 10-2, 11 and 14, the main body 35 is more rigid than the projecting members 36. The circuit board assembly 8 may be manufactured by patterning each layer separately followed by stacking the patterned layers. The layers of the circuit board assembly 8 may adopt other thicknesses depending on the application, but thick conductive layers and thin insulating layers are preferred where possible.

[0084] With reference to Figure 7, the top electrically conductive layer 11 of the main body 35 is patterned into spaced-apart conductive tracks, which includes a conductive track 15 on which the gate control terminal 31 is mounted, and a conductive track 16 on which the Kelvin source control terminal 32 is mounted. The use of the Kelvin source control terminal 32 is beneficial for reducing common-source inductances of the devices 20, which is important to minimise for successful switching of GaN HEMTs.

[0085] Due to the existence of the electrically insulating layers 9, 10-1 , 10-2, adjacent conductive layers within the circuit board assembly 8 would not be electrically shorted to one another without the use of conductive through-layer vias. With reference to Figures 7 and 8, the main body 35 further includes through-layer vias 17-1 to 17-4 (collectively referred to as 17). The through-layer via 17-3 electrically connects the conductive layer 12 of the projecting member 36-1 to a small conductive track of the conductive layer 13 which is bonded to the gate electrode 24 of the device 20-1. The remaining of the conductive layer 13 of the projecting member 36-1 is electrically connected to the source electrode 23 of the device 20-1 by direct bonding. Similarly, the through-layer via 17-4 electrically connects the conductive layer 12 of the projecting member 36-2 to a small conductive track of the conductive layer 13 which is bonded to the gate electrode 24 of the device 20-2. The remaining of the conductive layer 13 of the projecting member 36- 2 is electrically connected to the source electrode 23 of the device 20-2 by direct bonding. The through-layer via 17-1 electrically connects the conductive track 16 (and the Kelvin source control terminal 32) to the conductive layer 13. The through-layer via 17-2 electrically connects the conductive track 15 (and the gate control terminal 31) to the conductive layer 12. Therefore, the gate and source electrodes 24, 23 of the devices 20 are electrically connected to the gate and Kelvin source control terminals 31 , 32, respectively, by the projecting members 36 and the main body 35 of the circuit board assembly 8.

[0086] In Figures 5 to 8, the through layer vias 17 are shown in defined locations for clarity. However, in reality their locations would be dependent on the layout and distribution that best minimises the resistance and inductance of the gate and Kelvin source current paths.

[0087] Once the module 100 is assembled (Figure 5), the main body 35 extends along a plane P which is generally parallel to a surface of the substrate 1 (i.e., XY plane), and the projecting members 36 extend away from the plane P and downwards to the devices 20. As shown in Figure 5, the projecting member 36-1 extends along a direction which forms an angle 0 with respect to the XY plane. The angle 0 is between 0° and 90° (excluding the end nodes).

[0088] Figure 9 shows paths of gate circuit currents within a cross-section of the module 100 as shown in Figure 5. In Figure 9, the solid lines show the gate circuit current flowing from the gate control terminal 31 to the gate electrode 24 of the device 20-1 . In particular, the gate circuit current is picked up by the main body 35 from the gate control terminal 31 , and is then routed on the conductive track 15 of the top conductive layer 11 to the through-layer via 17-2. The gate circuit current then flows laterally along the conductive layer 12 shared by the main body 35 and the projecting member 36-1 , before flowing downwards to the gate electrode 24 of the device 20-1. The dashed lines show the gate circuit current flowing from the source electrode 23 of the device 20-1 to the Kelvin source control terminal 32. In particular, the gate circuit current flows from the source electrode 23 to the conductive layer 13 of the projecting member 36-1 due to the direct bonding therebetween, and is then routed on the conductive layer 13 of the main body 35 to the through-layer via 17-1. The gate circuit current then flows along the conductive track 16 of the top conductive layer 11 to the Kelvin source control terminal 32. The above description similarly applies to the gate circuit current paths of the device 20-2.

[0089] Therefore, the module 100 uses the circuit board assembly 8 alone to make the electrical connection between the gate and source electrodes 24, 23 of the devices 20, and the gate circuit terminals 31 , 32 of the module 100. This is achieved by directly bonding the flexible projecting members 36 of the circuit board assembly 8 to the gate and source electrodes 24, 23 of the devices 20, and by directly bonding the gate circuit terminals 31 , 32 to the main body 35 of the circuit board assembly 8. In contrast to the prior module 100’, the module 100 does not require any bond wires or auxiliary pins to make the gate circuit connections.

[0090] The gate circuit loop inductance within the module 100 (i.e. , the inductance between the gate circuit terminals 31 , 32 along the current path as shown in Figure 9) is significantly lower than that within the module 100’ as shown in Figure 3. This is attributed to several factors as described below:

[0091] Firstly, the module 100 uses large-area conductive layers (e.g., the layers 12, 13) within the circuit board assembly 8 to make the gate circuit connections. In particular, the gate control layer (e.g., the layer 12) and the Kelvin source control layer (i.e., the layer 13) are separately provided. By comparing Figures 2 and 6, it can be seen that the width of the layer 12 or 13 in a protruding member 36 along the X direction is much greater than the width of each conductive pad 5’ or 6’ of the substrate T. Therefore, the cross-sectional area (along the XZ plane) of the layer 12 or 13 in a projecting member 36 can be greater than that of the conductive pad 5’ or 6’ used in the known module 100’. Further, the cross-sectional area of the layer 12 or 13 in a projecting member 36 is much greater than that of the bonding wire 29’ or 30’ used in the module 100’. Accordingly, the module 100 has a reduced gate circuit loop inductance than the module 100’ due to the use of relatively wide conductive layers in the projecting members 36. Further, the majority of the conductive layers 12 and 13 within the main body 35 have an area similar to that of the substrate 1. This allows the conductive layers 12, 13 of the main body 35 to have a lower inductance than the auxiliary pins 25’, 26’ used in the module 100’, and further reduces the gate circuit loop inductance of the module 100.

[0092] Secondly, suspending the circuit board assembly 8 above the devices 20 and the power connections 27, 28 allows the gate and Kelvin source signals to be connected as close as possible to the devices 20, thereby reducing the need for lengthy substrate traces and bond wires with small cross-sectional areas, i.e., lengthy high-inductance current paths. In addition, the projecting members 36 of the circuit board assembly 8 are directly connected to the electrodes 23, 24 of the devices 20 without any intermediary interconnections. This arrangement allows a low inductance path directly to the devices 20. Thirdly, by suspending the circuit board assembly 8 above the devices 20 and the power connections 27, 28, and also by using the flexible projecting members 36 to achieve a direct connection to the devices 20, the size of the gate current loop within the module 100 has been reduced significantly as compared to that within the module 100’. This is because the flexible projecting members 36 provide a short-cut as compared to the use of bonding wires and auxiliary pins within the YZ plane (Figures 3 and 9). The thin insulating layer 9 within the projecting members 36 and the main body 35 also contribute to the reduction in the size of the gate current loop. Reducing the size of the gate current loop in turn reduces the gate circuit loop inductance.

[0093] Fourthly, the arrangement of the gate circuit current paths within the module 100 promotes flux cancellation. With reference to Figure 9, it can be seen that, in regions R1 (within the projecting member 36) and R2 (within part of the main body 35), the gate circuit currents flow in opposite directions in the conductive layer 12 and the conductive layer 13, which are separated by a single electrical insulating layer 9. As described above, the electrical insulating layer 9 is relatively thin (e.g., 25.4pm) to provide flexibility to the projecting member 36. Therefore, this arrangement allows the opposite current flows of the gate circuit to be closely coupled, thereby promoting flux cancellation and causing a further reduction of parasitic inductances of electrical connections between the gate control terminal 31 and the gate electrode 24, and between the Kelvin source control terminal 32 and the source electrode 23.

[0094] Advantageously, the reduced parasitic inductance of the gate circuit loop within the module 100 improves the switching speed of the devices 20, and also reduce the risks of falsely triggering the devices 20, thereby allowing full exploitation of fast-switching capabilities of WBG power semiconductor devices (e.g., GaN HEMTs) within the module 100.

[0095] In addition, suspending the circuit board assembly 8 above the devices 20 and the power connections 27, 28 also provides the opportunity to reduce the module footprint, since auxiliary traces, pins and bond wires are no longer required at the substrate level.

[0096] The use of the circuit board assembly 8 also allows the capacitance between the gate and Kelvin source potentials to be tailored, by varying the area of mutual overlap (e.g., the overlap between the conductive layers 12, 13) and insulation thickness (e.g., the thickness of the insulating layer 9). Tailoring the capacitance between the gate and Kelvin source potentials allows the adjustment of the gate drive circuit impedance, which can help improve dv / dt immunity.

[0097] Further, the bottom conductive layer 14 of the main body 35, which faces the devices 20, is not connected to any voltage potential of the electrodes 23, 22, 24 of the devices 20. The conductive layer 14 functions as a shielding layer, to shield the sensitive gate circuit from any radiated EMI emissions from the power connections 27, 28. The conductive layer 14 may be connected to a stable voltage supply, the ground, or be left floating, depending upon various applications.

[0098] The module 100 can be assembled in various different ways. In one example, the gate electrodes 24 and the source electrodes 23 of the devices 20 are directly attached to the projecting members 36 of the circuit board assembly 8 by a flip-chip process. The backsides of the devices 20 are then bonded to the substrate 1 by way of either soldering or sintering. Simultaneously, the power connections 27, 28 are bonded to the devices 20 and substrate 1 , again by either soldering or sintering processes. Finally, the spacers 19 are inserted into the holes 37 of the main body 35 to raise the circuit board assembly 8 above the devices 20 and the power connections 27, 28. In another example, the devices 20 and the power connections 27, 28 are bonded to the substrate 1 , by way of either soldering or sintering processes. The circuit board assembly 8 with the spacers 19 inserted, is placed on top of the substrate 1 in position. The projecting members 36 of the circuit board assembly 8 are then bonded to the gate electrodes 24 and the source electrodes 23 of the devices 20 using a conductive epoxy. It would be appreciated that these examples are in no way limiting, and the module 100 may be assembled by any suitable process.

[0099] In the examples described above, the devices 20 are GaN transistors (e.g., GaN HEMTs). It would be appreciated that the devices 20 may be other types of WBG power transistors, or may be based upon non-WBG semiconductor materials (e.g., Silicon). For example, the devices 20 may comprise one or more of insulated gate bipolar transistors (IGBT), power metal-oxide-semiconductor field-effect transistors (MOSFET), injection enhanced gate transistors (IEGT), and power bipolar junction transistors (BJT), etc. In the event that the devices 20 are IGBT-based, the Kelvin source control terminals 32 may be referred to as auxiliary emitter terminals. While it is not shown in any of the figures, it would be appreciated that the module 100 typically includes a housing which encloses the devices 20 and an entirety of the circuit board assembly 8. In this way, the circuit board assembly 8 would not be exposed to the exterior of the module 100. The gate circuit terminals 31 , 32 protrude outside of the housing to provide connections to an electrical environment of the module 100. This arrangement provides flexibility for a user of the module 100 in terms of gate driver design and selection. The bottom conductive layer 7 of the substrate 1 is typically bonded to an external heat sink, and therefore is not covered by the housing. In other words, the module 100 may be a single-side cooled power module. The housing may take the form of a plastic frame with insulating material (such as silicone gel) used to fill the space between the circuit board assembly 8 and the substrate 1. Alternatively, the housing may be made by a moulding compound in a transfer moulding process.

[0100] Within the module 100, each of the devices 20 is a lateral power device, meaning that its power electrodes are formed on the same side (e.g., the top surface) of the device and that a power current flows laterally between the power electrodes. It would be appreciated that the devices 20 may be replaced by vertical power devices.

[0101] The module 100 described above contains a single power switch. It would further be appreciated that the module 100 may comprise power semiconductor devices that are suitably interconnected to form a circuit structure (e.g., one or more half-bridge structures, at least one phase of a three-level neutral point clamped inverter, etc.). In particular, this may be achieved by suitably patterning the conductive layers included within the projecting members 36 and the main body 35 of the circuit board assembly 8, and / or by increasing the number of conductive layers within the projecting members 36 and the main body 35.

[0102] Further, as described above, the gate circuit terminals 31 , 32 of the module 100 protrude outside of the housing of the module 100 and receive gate control signals (e.g., a gate voltage signal and a Kelvin source voltage signal) from external gate drive circuitry. It would be appreciated that the module 100 may be modified such that the main body 35 of the circuit board assembly 8 carries gate drive circuitry which generates internal control signals for driving the devices 20. The control signals would still be routed to the gate electrodes 24 and the source electrodes 23 of the devices by the main body 35 and the projecting members 36 alone, without utilizing any wire bonds or auxiliary pins. The gate drive circuitry may be housed completely within the module 100.

[0103] Figures 10 to 11 schematically illustrate power semiconductor modules 100A, 100B according to second and third embodiments of the present disclosure. Elements of the modules 100A, 100B that are identical to those of the module 100 are identified using the same labels. Elements of the modules 100A, 100B that correspond to, but are different from those of the module 100 are labelled using the same numerals but with a letter ‘A’ or ‘B’ for differentiation. The features and advantages described above with reference to the first embodiment are generally applicable to the second and third embodiments.

[0104] The module 100A differs from the module 100 in that the main body 35A and the projecting members 36A of the circuit board assembly 8A are separately provided and then coupled together, but are not integrally formed. Figure 10 shows only one projecting member 36A-1 , but it would be understood that other projecting members within the module 100A take a similar form to the projecting member 36A-1 .

[0105] Similar to the projecting member 36, the projecting member 36A includes an electrically insulating layer 9 clad with two electrically conductive layers 12, 13 (such as, copper layers) on opposite sides. However, the projecting member 36A takes the form of a circuit board strip and is a standalone circuit board.

[0106] The main body 35A comprises an electrically insulating layer 10A clad with two electrically conductive layers 11A and 34 (such as, copper layers) on opposite sides. The electrically insulating layer 10A and the electrically conductive layers 11A and 34 may be referred to as “second electrically insulating layer” and “third and fourth electrically conductive layers”, respectively. The electrically insulating layer 10A may be similar to the layer 10-1 or 10-2 of the module 100. In an example, the electrically insulating layer 10A is made of a glass-reinforced epoxy laminate material such as FR- 4, and has a thickness of around 0.8mm. The electrically conductive layers 11A, 34 may be made of copper and each has a thickness of around 35pm. Due to the material choice and the thickness, the electrically insulating layer 10A is generally rigid and gives rigidity to the main body 35A, thereby allowing the main body 35A to support the gate circuit terminals 31 , 32. A connector 40 is used to mechanically and electrically couple the projecting member 36A-1 to the main body 35A within the circuit board assembly 8A. In an example, the connector 40 is a flexible printed circuit (FPC) connector. More specifically, the right-end region of the projecting member 36A-1 is inserted into the connector 40 which forms separate electrical connections with the conductive layers 12, 13. The connector 40 is then bonded to the main body 35A (e.g., by way of soldering) and forms separate electrical connections with the conductive layers 11A, 34. Therefore, the connector 40 electrically connects the conductive layer 12 to the conductive layer 11A, and also electrically connects the conductive layer 13 to the conductive layer 34. Similar to the module 100, the left-end region of the projecting member 36A-1 is directly bonded to the gate electrode and the source electrode of the power device 20, by way of soldering, sintering, or conductive epoxy.

[0107] The conductive layer 11 A may be patterned to form two spaced-apart conductive tracks on which the gate circuit terminals 31 , 32 are mounted The conductive track supporting the Kelvin source control terminal 32 may be connected to the bottom conductive layer 34 using a through-layer via (not shown in Figure 10) of the main body 35A. As a result, the conductive layer 12 is electrically connected to a conductive track of the conductive layer 11A (on which the gate control terminal 31 is mounted), and the conductive layer 13 is electrically connected to the conductive layer 34 (which is electrically connected to the Kelvin source control terminal 32).

[0108] The module 100A can be assembled in various different ways. By way of an example, the standalone projecting members 36A is directly bonded to the devices 20 by way of soldering, sintering or conductive epoxy. This is followed by bonding the devices 20 and the power connections 27, 28 to the substrate 1 by either soldering or sintering. The standalone rigid main body 35 is then positioned above devices 20 and the power connections 27, 28, and rests on the substrate 1 via the spacers 19. The projecting members 36 are then raised and inserted into the connector 40, which is then locked in place on the main body 35.

[0109] The module 100A is useful for overcoming any restrictions in the compatibility of the rigid main body 35A of the circuit board assembly 8A with the necessary high temperatures used for soldering and sintering. It would be appreciated that the main body 35A may be modified to add an extra insulating layer and an extra conductive layer at its bottom surface (similar to the layers 10-2, 14 of the module 100). The extra conductive layer may be used as a shielding layer similar to the layer 14.

[0110] The module 100B differs from the module 100 in that the main body 35B is not a rigid circuit board. The projecting members 36 of the module 100B have an identical structure to those of the module 100. The main body 35B is integrally formed with the projecting members 36. However, the main body 35B does not include any layers in addition to those of the projecting members 36. Therefore, the main body 35B remains as flexible as the projecting members 36.

[0111] To manufacture the module 100B, the gate circuit terminals 31 , 32 of the module 100B are bonded directly to conductive tracks 45 formed in the top conductive layer 5B of the substrate 1 B. Subsequently, the circuit board assembly 8B is attached by directly bonding the projecting members 36 to the gate electrodes and the source electrodes of the devices 20, and by bonding the main body 35B to the top surfaces of the gate circuit terminals 31 , 32. The main body 35B has a through-layer via 17-1 B which electrically connects the conductive layer 12 (i.e., gate control layer) to the gate control terminal 31. The conductive layer 13 of the main body is directly bonded to the Kelvin source control terminal 32.

[0112] It would be understood that the main body 35B would have large cut-out regions (such as, 38-1 B) to provide clearance for the devices 20 and the power connections 27, 28. The area of the cut-out region 38-1 B is greater than that of the cut-out region 38-1 in the module 100 or 100A. This embodiment would be beneficial for reducing the overall height of the power module 100B.

[0113] Figure 12 schematically illustrates processing steps of a method for manufacturing a power semiconductor module (e.g., either of the modules 100, 100A and 100B).

[0114] At step S1 , a power semiconductor device (e.g., the devices 20) are mounted on a substrate (e.g., the substrate 1). The power semiconductor device comprises a first power electrode (e.g., the source electrode 23), a second power electrode (e.g., the drain electrode 22) and a control electrode (e.g., the gate electrode 24). The power semiconductor device may be bonded to the substrate by either soldering or sintering processes.

[0115] At step S2, a circuit board assembly (e.g., the circuit board assembly 8, 8A, 8B) is positioned above (i.e., overlying) the substrate 1. The circuit board assembly comprises a main body (e.g., the main body 35, 35A, 35B) for receiving a control signal to control a power current flowing between the first and second power electrodes of the power semiconductor device, and a projecting member (e.g., the projecting member(s) 36, 36A).

[0116] At step S3, the projecting member (e.g., the projecting member(s) 36, 36A) is directly attached to the power semiconductor device so as to form an electrical connection to the control electrode. The main body and the projecting member are electrically coupled to one another so as to collectively provide a conductive pathway for the control signal to travel from the main body to the control electrode.

[0117] The projecting member may be attached to the power semiconductor device, by way of soldering, sintering, or conductive epoxy in a flip-chip process.

[0118] It would be appreciated that the steps may be performed in a temporal order that is different from the order of description. For example, the module 100 or 100A may alternatively be manufactured by following an order of S3, S1 and S2.

[0119] The method may include a further processing step of bonding a control terminal to the main body of the circuit board assembly (e.g., in the module 100, 100A) or to the substrate (e.g., in the module 100B). The control terminal is for receiving the control signal, and may extend beyond a housing of the power semiconductor module.

[0120] In the event that the projecting member and the main body of the circuit board assembly are not integrally formed, the method may include a further processing step of electrically and mechanically coupling the projecting member to the main body (e.g., by using a connector).

[0121] The terms “having”, “containing”, “including”, “comprising” and the like are open and the terms indicate the presence of stated structures, elements or features but not preclude the presence of additional elements or features. The articles “a”, “an” and “the” are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

[0122] The skilled person will understand that in the preceding description and appended claims, positional terms such as ‘left’, ‘right’, ‘top’, ‘bottom’, ‘above’, ‘vertical’, etc. are made with reference to conceptual illustrations of a power semiconductor module, such as those showing standard cross-sectional perspectives and those shown in the appended drawings. These terms are used for ease of reference but are not intended to be of limiting nature. These terms are therefore to be understood as referring to a device when in an orientation as shown in the accompanying drawings.

[0123] Although the disclosure has been described in terms of preferred embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives in view of the disclosure which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may be incorporated in the disclosure, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein.

Claims

CLAIMS:1 . A power semiconductor module comprising: a substrate; a power semiconductor device mounted on the substrate, wherein the power semiconductor device comprises a first power electrode, a second power electrode and a control electrode; and a circuit board assembly overlying the substrate, wherein: the circuit board assembly comprises a main body for receiving a control signal for controlling a power current flowing between the first and second power electrodes, and a projecting member; the projecting member is directly attached to the power semiconductor device so as to form an electrical connection to the control electrode; and the main body and the projecting member are electrically coupled to one another so as to collectively provide a conductive pathway for the control signal to travel from the main body to the control electrode.

2. A power semiconductor module according to claim 1 , wherein the projecting member is more flexible than the main body.

3. A power semiconductor module according to claim 1 or 2, wherein: the projecting member comprises a first end region and a second end region; the first end region is mechanically and electrically coupled to the main body; and the second end region is directly attached to the power semiconductor device so as to form the electrical connection to the control electrode.

4. A power semiconductor module according to any preceding claim, wherein the main body extends along a first plane, and at least a part of the projecting member extends away from the first plane and towards the control electrode of the power semiconductor device.

5. A power semiconductor module according to claim 4, wherein at least a part of the projecting member extends along a direction which forms an angle with respect to the first plane, and the angle is between 0° and 90°.

6. A power semiconductor module according to any preceding claim, wherein the main body comprises a cut-out region, and the projecting member projects from an edge of the cut-out region.

7. A power semiconductor module according to any preceding claim, wherein the main body comprises an electrically conductive layer which forms a surface of the main body that faces the power semiconductor device, and the electrically conductive layer is isolated from voltage potentials of the electrodes of the power semiconductor device.

8. A power semiconductor module according to any preceding claim, further comprising a housing which encloses the power semiconductor device and an entirety of the circuit board assembly.

9. A power semiconductor module according to any preceding claim, further comprising a control terminal for receiving the control signal, wherein the control terminal is electrically connected to the main body of the circuit board assembly, and at least a part of the control terminal is exposed to an exterior of the power semiconductor module.

10. A power semiconductor module according to claim 8 or 9, wherein the control terminal is a first control terminal, and the power semiconductor module further comprises a second control terminal which is electrically coupled to the first power electrode by the circuit board assembly.

11. A power semiconductor module according to any preceding claim, wherein the main body is rigid.

12. A power semiconductor module according to any preceding claim, wherein the projecting member comprises a first electrically insulating layer and first and second electrically conductive layers arranged on opposite sides of the first electrically insulating layer, and wherein at least a part of the first electrically conductive layer is electrically connected to the control electrode, and at least a part of the second electrically conductive layer is electrically connected to the first power electrode.

13. A power semiconductor module according to any preceding claim, wherein the circuit board assembly further comprises a connector which mechanically and electrically couples the projecting member and the main body.

14. A power semiconductor module according to claim 13, wherein the main body comprises a second electrically insulating layer and third and fourth electrically conductive layers arranged on opposite sides of the second electrically insulating layer, and wherein the connector electrically connects at least a part of the first electrically conductive layer of the projecting member to at least a part of the third electrically conductive layer, and further electrically connects at least a part of the second electrically conductive layer of the projecting member to at least a part of the fourth electrically conductive layer.

15. A power semiconductor module according to any of claims 1 to 12, wherein the main body and the projecting member are integrally formed.

16. A power semiconductor module according to claim 15 as dependent from claim 12, wherein the main body comprises a second electrically insulating layer and third and fourth electrically conductive layers arranged on opposite sides of the second electrically insulating layer, and wherein: the first and second electrically insulating layers are integrally formed; the first and third electrically conductive layers are integrally formed; and the second and fourth electrically conductive layers are integrally formed.

17. A power semiconductor module according to claim 16 as dependent from claim 10, wherein the main body further comprises: third and fourth electrically insulating layers which sandwich the second electrically insulating layer and the third and fourth electrically conductive layers; fifth and sixth electrically conductive layers which sandwich the second to fourth electrically insulating layers and the third and fourth electrically conductive layers, wherein the fifth electrically conductive layer comprises first and second conductive tracks which are spaced apart from one another and supports the first and second control terminals, respectively; a first conductive via which electrically connects at least a part of the third electrically conductive layer to the first conductive track; anda second conductive via which electrically connects at least a part of the fourth electrically conductive layer to the second conductive track; wherein the sixth electrically conductive layer faces the power semiconductor device, and is not electrically connected to the third or fourth electrically conductive layers.

18. A power semiconductor module according to claim 16 as dependent from claim 10, wherein: the first and second control terminals are bonded between the main body and the substrate; the first control terminal is electrically connected to at least a part of the third electrically conductive layer; and the second control terminal is electrically connected to at least a part of the fourth electrically conductive layer.

19. A power semiconductor module according to any one of claims 1 to 17, further comprising a spacer which maintains a clearance between the substrate and the circuit board assembly along a direction perpendicular to a surface of the substrate.

20. A power semiconductor module according to any preceding claim, wherein the power semiconductor device comprises a wide bandgap power semiconductor device.21 . A method of manufacturing a power semiconductor module, comprising: mounting a power semiconductor device on a substrate, wherein the power semiconductor device comprises a first power electrode, a second power electrode and a control electrode; positioning a circuit board assembly above the substrate, wherein the circuit board assembly comprises a main body for receiving a control signal for controlling a power current flowing between the first and second power electrodes, and a projecting member; and directly attaching the projecting member to the power semiconductor device so as to form an electrical connection to the control electrode; wherein the main body and the projecting member are electrically coupled to one another so as to collectively provide a conductive pathway for the control signal to travel from the main body to the control electrode.

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