Method for testing insulated gate-type sic semiconductor element, and insulated gate-type sic semiconductor element

Abstract

The present invention provides a testing method, for an insulated gate type SiC semiconductor element, capable of highly accurate sorting of substandard products which are difficult to be distinguished by conventional testing methods.　This testing method for an insulated gate-type SiC semiconductor element is characterized by comprising: (a) a step for incorporating an element under test into an H-bridge type circuit having an inductance load; and (b) a step for using a gate voltage signal of the H-bridge type circuit to repeatedly perform ON / OFF switching so as to cause a bidirectional current to flow to the element under test, wherein the element under test satisfies the relational expression dv / dt > 0.06 × t × Vav, where Vav [kV] is the interruption rated breakdown voltage, t [nm] is the thickness of a gate insulating film, and dv / dt [kV / us] is the rate of change in voltage during the ON / OFF switching.

Description

Test method for insulated gate SiC semiconductor device, insulated gate SiC semiconductor device

[0001] The present invention relates to a semiconductor device testing method and a semiconductor device to be tested, and in particular to a technique that is effective when applied to screening tests of insulated gate SiC semiconductor devices.

[0002] Silicon carbide (SiC) has been attracting attention as a semiconductor material that can be used to manufacture power semiconductor elements with low resistance, high voltage resistance, heat resistance, and excellent high-speed characteristics. Power semiconductor elements using SiC include Schottky barrier diodes (SBDs), PN diodes (PNDs), metal-oxide-semiconductor field-effect transistors (MOSFETs), and insulated gate bipolar transistors (IGBTs).

[0003] Since SiC has a dielectric breakdown field strength approximately 10 times higher than that of Si (silicon), it is possible to fabricate high-voltage power semiconductor elements of several hundred to several thousand volts with a higher impurity concentration and thinner drift layer than Si semiconductor elements, thereby realizing high-voltage elements with extremely low on-resistance per unit area.

[0004] In addition, with Si, minority carrier devices such as IGBTs are mainly used to improve the increase in on-resistance that accompanies higher breakdown voltages, but they have the problem of large switching losses, and the resulting heat generation limits high-frequency operation. On the other hand, with SiC, high breakdown voltages can be achieved using majority carrier devices such as SBDs and MOSFETs, which have high-speed device structures, so it is possible to simultaneously achieve three performance characteristics: high breakdown voltage, low on-resistance, and high speed.

[0005] Furthermore, since the band gap is about three times wider than that of Si, it is possible to realize a power semiconductor element that can operate even at high temperatures.

[0006] As background art in this technical field, there is, for example, a technique such as that disclosed in Patent Document 1. Patent Document 1 discloses "a method for screening silicon carbide semiconductor devices capable of screening silicon carbide semiconductor devices that do not deteriorate in reliability even when used at high temperatures for a long period of time in an inverter circuit in which a diode is connected in antiparallel to a silicon carbide semiconductor device."

[0007] Japanese Patent Application Laid-Open No. 2018-205251

[0008] In a power semiconductor device (e.g., a power MOSFET), a voltage is repeatedly and intermittently applied between the drain and source during switching. When a MOSFET switches from a conductive state (on) to a non-conductive state (off), the voltage applied to the MOSFET's drain electrode increases rapidly. This change in drain voltage generates a displacement current via the depletion layer capacitance between the source and drain. This displacement current flows through the P-well and into the source electrode, generating a voltage in the P-well proportional to the magnitude of the current (see Figure 1, described below). In the area where the gate oxide is sandwiched between the P-well and the gate electrode, the high voltage applies a high electric field to the gate oxide, potentially damaging it. In particular, in high-voltage devices that handle high power supply voltages, the displacement current generated during switching is large, and the electric field applied to the gate oxide is also large. This raises concerns that damage will accumulate over long-term use, leading to device destruction.

[0009] Although there are ways to prevent damage caused by internal electric fields through the design of element structures, it is inevitable that elements that are easily damaged will be included due to variations in the manufacturing process or foreign matter that cannot be completely removed, and such vulnerable elements must be selected and removed through stress testing.

[0010] Furthermore, the breakdown resistance of high-voltage elements is closely related to the interrupting rated breakdown voltage and gate insulating film thickness of the element in question, and is also affected by the switching speed during stress testing, so stress testing must take these factors into consideration.

[0011] In the above-mentioned Patent Document 1, these parameters are not taken into consideration, and there is room for improvement in terms of highly accurate sorting.

[0012] Therefore, an object of the present invention is to provide a testing method for insulated gate SiC semiconductor elements that enables highly accurate sorting of non-standard products that are difficult to distinguish using conventional testing methods, and an insulated gate SiC semiconductor element using the same.

[0013] In order to solve the above problems, the present invention provides a method for testing an insulated gate SiC semiconductor device, comprising the steps of: (a) incorporating a device under test into an H-bridge circuit having an inductance load; and (b) repeatedly performing on / off switching using a gate voltage signal of the H-bridge circuit to pass a bidirectional current through the device under test, wherein the device under test satisfies the relational expression dv / dt>0.06×t×Vav, where Vav [kV] is a rated interrupting withstand voltage, t [nm] is a gate insulating film thickness, and dv / dt [kV / us] is a voltage change rate during on / off switching.

[0014] The present invention also provides an insulated gate SiC semiconductor device comprising a gate terminal, a source terminal, and a drain terminal, and controlling a current flowing between the source terminal and the drain terminal by applying a voltage to the gate terminal, the device being incorporated into an H-bridge circuit having an inductance load, and having a history of repeatedly performing on / off switching by a gate voltage signal of the H-bridge circuit to cause a bidirectional current to flow through the device under test, the device satisfying the relational expression dv / dt>0.06×t×Vav, where Vav is an interrupting rated withstand voltage, t is a gate insulating film thickness, and dv / dt is a voltage change rate during on / off switching.

[0015] According to the present invention, it is possible to realize a testing method for insulated gate SiC semiconductor devices that enables highly accurate sorting of non-standard products that are difficult to distinguish using conventional testing methods, and an insulated gate SiC semiconductor device using the same.

[0016] This can contribute to improving the reliability and extending the life of the insulated gate SiC semiconductor device.

[0017] Problems, configurations, and effects other than those described above will become apparent from the following description of the embodiments.

[0018] FIG. 1 is a diagram schematically showing a cross-sectional structure of a SiC-MOSFET according to Example 1 of the present invention. FIG. 2 is a diagram showing the relationship between the rated breakdown voltage of an element and the voltage change rate dv / dt required for defect screening. FIG. 3 is a diagram showing the relationship between the gate insulating film thickness and the voltage change rate dv / dt required for defect screening. FIG. 4 is a diagram showing an H-bridge type test circuit according to Example 1 of the present invention. FIG. 5 is a diagram showing an example of test waveforms by the H-bridge type test circuit of FIG. 3. FIG. 6 is a diagram showing the temperature of an element during testing by the H-bridge type test circuit of FIG. 3. FIG. 7 is a flowchart showing a method for testing a SiC semiconductor element according to Example 1 of the present invention.

[0019] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the drawings, the same components are designated by the same reference numerals, and detailed description of overlapping parts will be omitted.

[0020] A method for testing a SiC semiconductor device according to a first embodiment of the present invention and a SiC semiconductor device to be tested will be described with reference to FIGS. 1 to 6. FIG.

[0021] FIG. 1 is a diagram showing a schematic cross-sectional structure of a SiC-MOSFET according to this embodiment, and shows an example of a planar MOSFET.

[0022] As shown in FIG. 1, the SiC-MOSFET 1 of this embodiment has an n+ type SiC substrate 2 and an n type drift layer 3 made of SiC provided on the main surface of the substrate 2.

[0023] Near the surface of the drift layer 3, a p-type body region 4, an n+ type source region 5 containing an n-type dopant at a higher concentration than the n-type drift layer 3, and a p+ type contact region 6 containing a p-type dopant at a higher concentration than the p-type body region 4 are formed.

[0024] A source electrode 7 is formed in contact with at least a part of the n+ type source region 5 and the p+ type contact region 6 near the surface of the drift layer 3 .

[0025] A gate insulating film 8 and a gate electrode 9 are formed in contact with the p-type body region 4 near the surface of the drift layer 3 .

[0026] A drain electrode 10 is provided on the back surface of the SiC substrate 2 .

[0027] When the gate electrode 9 is biased to a certain voltage or higher (threshold voltage VGSth) with respect to the source electrode 7, the portion of the p-type body region 4 that is in contact with the gate insulating film 8 on the surface side is inverted to n-type, forming a conductive channel. In this state, when the drain electrode 10 is positively biased with respect to the source electrode 7, electrons flow from the n+ type source region 5 toward the drain electrode 10 through the conductive channel.

[0028] When the gate voltage is equal to or lower than the threshold voltage VGSth, no conductive channel is formed, and when a high drain voltage is applied, a depleted region is formed in the drift layer 3, causing only a very small leakage current to flow through the drain electrode 10.

[0029] In this way, by controlling the voltage applied to the gate electrode 9, it is possible to control the on / off of the current (switching operation).

[0030] The method for testing the SiC semiconductor device of this embodiment will be described with reference to the flowchart of FIG.

[0031] First, in step S1, a target SiC semiconductor device is incorporated into an H-bridge circuit having an inductance load (see FIG. 3 described later). Next, in step S2, a gate voltage signal is input to repeatedly switch the SiC semiconductor device on and off, causing a bidirectional current to flow through the SiC semiconductor device, thereby applying stress to the SiC semiconductor device.

[0032] During this switching, the operating conditions are set so that the relational expression (1) is satisfied.

[0033] dv / dt>0.06×t×Vav (1) Here, Vav [kV] is the rated interruption voltage of the SiC semiconductor element, t [nm] is the thickness of the gate insulating film, and dv / dt [kV / us] is the rate of voltage change during switching.

[0034] Subsequently, in step S3, the SiC semiconductor device is removed from the H-bridge circuit.

[0035] Next, in step S4, the gate leakage current of the SiC semiconductor device taken out of the H-bridge circuit is measured.

[0036] Next, in step S5, it is determined whether the gate leakage current value is within a predetermined value. If the gate leakage current value is within the predetermined value (Yes), the process proceeds to step S6, where the device is classified as a non-defective product. On the other hand, if the gate leakage current value is outside the predetermined value (No), the process proceeds to step S7, where the device is classified as a defective product.

[0037] According to the test method of this embodiment, by setting the operating conditions in the H-bridge circuit so that the above relational expression (1) is satisfied, weak elements will malfunction or be destroyed, and will be screened out as defective products.

[0038] Since a device with a higher rated breakdown voltage has a larger stress applied to the gate oxide film, efficient screening is possible if the rated breakdown voltage is 2 kV or more.

[0039] As will be described later with reference to Figure 5, since a higher stress can be applied by raising the temperature inside the element due to self-heating caused by current flow, the maximum value of the current flowing during testing is 1 / 5 or more (preferably 1 / 2 or more) of the rated current of the element, and it is desirable that the junction temperature of the element be heated to 100°C or higher.

[0040] The voltage change rate dv / dt required for screening out defective products will be described with reference to FIGS. 2A and 2B.

[0041] FIG. 2A is a diagram showing the relationship between the rated breakdown voltage of an element and the voltage change speed (voltage change rate) dv / dt required for defect screening, and FIG. 2B is a diagram showing the relationship between the gate insulating film thickness and the voltage change speed (voltage change rate) dv / dt required for defect screening.

[0042] The voltage change rate dv / dt at which a weak element can be classified as a defective product was calculated, and the relationship shown in FIGS. 2A and 2B was obtained.

[0043] As shown in Figure 2A, the voltage change rate dv / dt required for screening increases in proportion to the device's rated breakdown voltage (rated interruption voltage). This is because the higher the rated voltage, the smaller the capacitance of the depletion layer and the smaller the displacement current associated with the capacitance change.

[0044] Furthermore, as shown in FIG. 2B, the thinner the gate insulating film, the lower the withstand voltage, and therefore the voltage change rate dv / dt required for sorting becomes smaller.

[0045] From the voltage change rate dv / dt shown in these two figures, the relationship shown in the above formula (1) can be obtained.

[0046] FIG. 3 shows the state in which the device under test (SiC semiconductor device) is incorporated into an H-bridge type test circuit.

[0047] In addition to SW1, which is the device under test (DUT), four switch elements SW2, SW3, and SW4 are also included, forming an H-bridge circuit, along with a DC power supply 11 and an inductance load 12. A gate driver GD is connected to each of the switch elements SW1 to SW4 to input a gate signal to each switch element.

[0048] When the switching element has a rated break-down voltage of 3.3 kV and a rated current capacity of 1000 A, for example, the voltage of the DC power supply 11 is 1.8 kV and the inductance load 12 is 2 mH.

[0049] In this embodiment, switch element SW1 is the device under test (DUT), and switch elements SW2 to SW4 are auxiliary elements for configuring an H-bridge circuit, but in order to apply sufficient stress to switch element SW1, which is the device under test (DUT), it is desirable that the interrupting rated voltage and rated current capacity of switch elements SW2 to SW4 be larger than those of switch element SW1. Alternatively, switch elements SW2 to SW4 can also be incorporated with the same element as switch element SW1, and all four can be tested as devices under test (DUT).

[0050] Furthermore, if the product to be the device under test (DUT) is a type in which two switch elements are mounted in one package (2-in-1 type), the switch elements SW1 and SW2 in FIG. 3 may be incorporated into a circuit as one package product and tested.

[0051] To control the switching speed (speed of voltage change) dv / dt, the gate voltage when turned on / off and the resistance value connected between the gate driver output and the gate terminal of the device under test are adjusted. To apply high stress more efficiently, it is necessary to increase the gate-on voltage, decrease the gate-off voltage, and reduce the gate resistance value.

[0052] The signal input to the gate of each switch element of the H-bridge circuit can be output by comparing the magnitude of a sine wave modulating wave and a sawtooth wave carrier wave, which is known as pulse width modulation (PWM) control.

[0053] FIG. 4 shows an example of a test waveform obtained by the H-bridge type test circuit of FIG.

[0054] Figure 4 shows the gate voltage signal input to the device under test (DUT) when PWM control is performed using a 50 Hz modulating wave and a 1 kHz carrier wave, as well as the waveforms of the drain voltage of the device under test (DUT) and the current flowing through the device under test (DUT) at that time.

[0055] The drain voltage applied to the device under test also changes repeatedly according to the on / off signal input to the gate. If the switching speed (voltage change rate) dv / dt at this time falls within the range specified by equation (1) above, stress can be applied to the device under test efficiently. In the H-bridge test circuit shown in Figure 3, the current reverses positive and negative within one cycle, indicating that it flows in both directions. With such an H-bridge circuit, it is possible to test all operating modes, including on and off of the switching element, as well as forward and reverse recovery.

[0056] FIG. 5 shows the temperature of the element during testing using the H-bridge type test circuit of FIG.

[0057] Figure 5 shows the change in the junction temperature of the device under test during the test. The temperature of the switching element gradually rises due to Joule heat generated by the current flow during the test. The temperature rise at this time depends on the thermal characteristics determined by the switching element structure and the method of cooling the switching element, but it generally takes several seconds to several tens of seconds for the switching element to reach a nearly constant steady temperature.

[0058] The test is preferably performed by repeatedly passing current for a sufficient time to reach such a steady state, and at that time the temperature reaches 100°C or higher. In order to reach that temperature, the current applied to the device under test must be at least 1 / 5 (preferably at least 1 / 2) of its maximum rated current. If the current is low and the maximum temperature reached is low, the stress may be insufficient.

[0059] As described above, the method for testing SiC semiconductor devices in this example includes the steps of: (a) incorporating the device under test into an H-bridge circuit having an inductance load; and (b) repeatedly performing on / off switching using a gate voltage signal of the H-bridge circuit to pass a bidirectional current through the device under test. The device under test satisfies the relational expression dv / dt>0.06×t×Vav, where Vav [kV] is the rated interrupting withstand voltage, t [nm] is the gate insulating film thickness, and dv / dt [kV / us] is the voltage change rate during on / off switching.

[0060] Moreover, the SiC semiconductor element of this example is an insulated gate SiC semiconductor element that includes a gate terminal, a source terminal, and a drain terminal, and that controls a current flowing between the source terminal and the drain terminal by applying a voltage to the gate terminal, is incorporated into an H-bridge circuit having an inductance load, and has a history of being repeatedly switched on / off by a gate voltage signal of the H-bridge circuit, causing a bidirectional current to flow through the insulated gate SiC semiconductor element, and satisfies the relational expression dv / dt>0.06×t×Vav, where Vav is the rated interrupting withstand voltage, t is the gate insulating film thickness, and dv / dt is the rate of voltage change during on / off switching.

[0061] This makes it possible to accurately sort out non-standard products that are difficult to identify using conventional testing methods, contributing to improved reliability and longer life of insulated gate SiC semiconductor elements.

[0062] The present invention is not limited to the above-described embodiments, but includes various modifications. For example, the above-described embodiments have been described in detail to clearly explain the present invention, and the present invention is not necessarily limited to those including all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, or to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is possible to add, delete, or replace part of the configuration of each embodiment with other configurations.

[0063] 1...SiC-MOSFET 2...SiC substrate (n+ type) 3...Drift layer (n type) 4...Body region (p type) 5...Source region (n+ type) 6...Contact region (p+ type) 7...Source electrode 8...Gate insulating film 9...Gate electrode 10...Drain electrode 11...DC power supply 12...Inductance load GD...Gate driver SW1 to SW4...Switch elements.

Claims

1. A method for testing an insulated gate SiC semiconductor device, comprising: (a) incorporating the device under test into an H-bridge circuit having an inductance load; and (b) repeatedly switching the device under test on and off using a gate voltage signal of the H-bridge circuit to pass a bidirectional current through the device under test, wherein the device under test satisfies the following relationship: dv / dt>0.06×t×Vav, where Vav is the rated interrupting voltage rating, t is the gate insulating film thickness, and dv / dt is the rate of voltage change during on / off switching.

2. A method for testing an insulated gate SiC semiconductor device according to claim 1, wherein the device under test has an interrupting rated withstand voltage of 2 kV or more.

3. A method for testing an insulated gate SiC semiconductor device according to claim 1, characterized in that in step (b), the junction temperature of the device under test is heated to 100°C or higher due to self-heating caused by current flow.

4. A method for testing an insulated gate SiC semiconductor device as set forth in claim 1, characterized in that in step (b), the maximum value of the bidirectional current flowing through the device under test is 1 / 5 or more of the maximum rated current of the device under test.

5. A method for testing an insulated gate SiC semiconductor device according to claim 1, characterized in that in step (b), the maximum value of the bidirectional current flowing through the device under test is equal to or greater than half the maximum rated current of the device under test.

6. An insulated gate SiC semiconductor element comprising a gate terminal, a source terminal, and a drain terminal, wherein a current flowing between the source terminal and the drain terminal is controlled by applying a voltage to the gate terminal, the insulated gate SiC semiconductor element being incorporated into an H-bridge circuit having an inductance load, and having a history of repeatedly performing on / off switching using a gate voltage signal from the H-bridge circuit to cause a bidirectional current to flow through the insulated gate SiC semiconductor element, wherein the insulated gate SiC semiconductor element satisfies the following relational expression: dv / dt>0.06×t×Vav, where Vav is the rated interrupting voltage rating, t is the gate insulating film thickness, and dv / dt is the voltage change rate during on / off switching.

7. An insulated gate SiC semiconductor device according to claim 6, characterized in that the interrupting rated withstand voltage is 2 kV or more.

8. An insulated gate SiC semiconductor element according to claim 6, wherein the junction temperature is heated to 100°C or higher due to self-heating caused by current flow during the repeated on / off switching.

9. An insulated gate SiC semiconductor element according to claim 6, wherein the maximum value of the bidirectional current flowing through said insulated gate SiC semiconductor element during said repeated on / off switching is 1 / 5 or more of the maximum rated current of said insulated gate SiC semiconductor element.

10. An insulated gate SiC semiconductor element according to claim 6, wherein the maximum value of the bidirectional current flowing through said insulated gate SiC semiconductor element during said repeated on / off switching is equal to or greater than half of the maximum rated current of said insulated gate SiC semiconductor element.

Images