Selector material, storage chip, and memory

Abstract

Embodiments of the present application provide a selector material, a storage chip, and a memory, applied to the technical field of semiconductors. The selector material is a compound comprising a first element, a second element, a third element, selenium (Se), and tellurium (Te). The first element is germanium (Ge) or silicon (Si). The second element is any one or a combination of any two or more of non-metallic elements having an atomic number less than 20. The third element is any one or a combination of any two or more of elements having an atomic number greater than or equal to 30 in the third or fourth main group. Selectors made of the selector material provided by the embodiments of the present application have excellent characteristics of low electric leakage, high thermal stability, high adaptability to other devices, long service life, low threshold voltage shifts, etc.

Description

A gate tube material, memory chip and memory

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on February 7, 2024, with application number 202410175645.2 and application name “A strobe material, storage chip and memory”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a gate tube material, a memory chip, and a memory. Background Art

[0003] The development of big data, cloud computing, and the Internet of Things (IoT) is accompanied by an explosion of information. Efficient data storage and convenient data transfer have become the goals of contemporary storage technology. Consequently, various new high-performance storage technologies have emerged, such as crossbar array storage.

[0004] To address leakage current issues in crossbar array memory structures, a gate transistor is typically used to select the memory cells. Specifically, each memory cell in a memory chip is connected in series with a gate transistor. When an electrical signal is applied to the gate transistor, the gate material changes from a high-resistance state to a low-resistance state, turning the gate transistor on and selecting the memory cell. When the electrical signal is removed, the gate material changes from a low-resistance state to a high-resistance state, turning the gate transistor off and preventing the memory cell from being selected.

[0005] Existing gate materials are typically compounds containing silicon (Si), germanium (Ge), arsenic (As), and selenium (Se) (Si-Ge-As-Se system). This type of gate material has poor stability during the manufacturing process and is prone to device damage. Furthermore, since As is highly toxic, its presence renders the process very unfriendly. Therefore, how to obtain a gate material that does not contain As, so that the gate manufactured from it has strong thermal stability, a suitable threshold voltage, a long erase and write life, and the excellent characteristics of low threshold voltage drift, has become an urgent problem to be solved.

[0006] Summary of the Invention

[0007] The present invention provides a gate material, a memory chip, and a memory device. In the present invention, the gate material comprises at least five elements. A gate transistor fabricated from this gate material exhibits excellent properties, including low leakage, high thermal stability, high compatibility with other devices, long switching life, and low threshold voltage drift.

[0008] In a first aspect, an embodiment of the present application provides a gate material, wherein the gate material includes at least five elements. Specifically, it includes a first element, a second element, a third element, selenium Se, and tellurium Te. The first element can be germanium Ge or silicon Si, and the second element is any one or a combination of any two or more non-metallic elements with an atomic number less than 20. The third element is any one or a combination of any two or more elements in the third or fourth main group with an atomic number greater than or equal to 30.

[0009] Among them, the gate tube material is used to prepare the gate tube material layer of the gate tube. The addition of Te element to the gate tube material can greatly increase the stability of the gate tube material layer to ensure the switching characteristics of the gate tube. The addition of Se element can make the gate tube have a suitable threshold voltage, so that the threshold voltage of the gate tube can be adapted to the storage unit, peripheral circuit, etc. At the same time, the addition of non-metallic elements with an atomic number less than 20 can provide small atoms for the gate tube material layer, further inhibit the material crystallization and element drift of the gate tube material layer, and thus improve the switching life of the gate tube. The addition of the third and fourth main group elements can further improve the structural stability of the gate tube material layer, thereby reducing the threshold voltage drift. In this way, the gate tube prepared by this gate tube material has excellent characteristics such as low leakage, high thermal stability, high compatibility with other devices, long switching life and low threshold voltage drift.

[0010] In some possible implementations, the chemical formula of the gate tube material is:

[0011] (Ge x Se y Te z ) a M b X c Or (Si x Se y Te z ) a M b X c

[0012] Wherein, M represents a second element with an atomic number less than 20 and is a non-metallic element, and X represents a third element in the third or fourth main group with an atomic number greater than or equal to 30. x Se y Te zis the main body of the material of the gate tube material layer. Among them, the ratio of x to y is greater than 1 and less than 3, and the ratio of y to z is greater than 1 and less than 10. A, b and c represent the content of each part respectively, among which the content b and c of the non-main element (the second element and the third element) cannot exceed the maximum threshold value of 15% to avoid affecting the threshold voltage of the gate tube. The content a of the main element needs to be greater than 70%. In a multi-component compound, a specific element ratio can reduce homogeneous bonds (such as Ge-Ge bonds, etc.) and band gap changes introduced by relaxation phenomena, thereby suppressing the threshold voltage rise of the prepared gate tube and improving the reliability of the gate tube.

[0013] In an optional embodiment, in the gate tube material, Si(Ge) x Se y Te z The content a is between 80% and 94%, while the contents b and c of the doped non-main elements (second element and third element) are between 3% and 10%, further improving the stability and reliability of the gate tube.

[0014] In some possible implementations, the chemical formula of the material of the gate tube layer is:

[0015] (Ge x Se y Te z ) a M1 b1 M2 b2 X c or (Si x Se y Te z ) a M1 b1 M2 b2 X c

[0016] Wherein, M1 and M2 represent two second elements with atomic numbers less than 20 and which are non-metallic elements, respectively, and X represents a third element in the third or fourth main group with an atomic number greater than or equal to 30. The ratio of x to y is greater than 1 and less than 3, and the ratio of y to z is greater than 1 and less than 10.

[0017] Where a, b1, b2, and c represent the content of each component, respectively. The content of the non-main element (secondary and tertiary elements) b1, b2, and c must not exceed a maximum threshold of 15% to avoid affecting the threshold voltage of the fabricated gate transistor. The content of the main element a must be greater than 55%.

[0018] In this embodiment, the main element Si (Ge) x Se y Te zTwo second elements with atomic numbers less than 20 and which are non-metallic elements can be doped into the gate tube, which can further suppress the crystallization of the gate tube material and the element drift, thereby improving the stability of the final gate tube and extending the switching life of the gate tube.

[0019] In an optional embodiment, in the gate tube material, Si(Ge) x Se y Te z The content a is between 70% and 91%, while the contents b1, b2 and c of the doped non-main elements (second element and third element) are between 3% and 10%, further improving the stability and reliability of the gate tube.

[0020] In some optional embodiments, the chemical formula of the material of the gate tube layer may also be:

[0021] (Ge x Se y Te z ) a M b X1 c1 X2 c2 or (Si x Se y Te z ) a M b X1 c1 X2 c2

[0022] Wherein, M represents a second element with an atomic number less than 20 and is a non-metallic element, and X1 and X2 represent two third elements from the third or fourth main groups with an atomic number greater than or equal to 30. The ratio of x to y is greater than 1 and less than 3, and the ratio of y to z is greater than 1 and less than 10.

[0023] Where a, b, c1, and c2 represent the content of each component, respectively. The content of the non-main element (secondary and tertiary elements) b, c1, and c2 cannot exceed the maximum threshold of 15% to avoid affecting the threshold voltage of the fabricated gate transistor. The content of the main element a must be greater than 55%.

[0024] In this embodiment, the main element Si (Ge) x Se y Te z Two elements with atomic numbers greater than or equal to 30 in the third or fourth main group can be doped to further improve the structural stability of the gate tube material layer made of the gate tube material, thereby reducing the threshold voltage drift of the gate tube.

[0025] In an optional embodiment, in the gate tube material, Si(Ge) x Sey Te z The content a is between 70% and 91%, while the contents b, c1 and c2 of the doped non-main elements (second element and third element) are between 3% and 10%, further improving the stability and reliability of the gate tube.

[0026] In a second aspect, an embodiment of the present application provides a method for preparing a gate tube, the method comprising:

[0027] First, a first electrode layer is formed. Then, a gate material layer is formed on one side of the first electrode layer. The material of the gate material layer includes at least five elements. Specifically, it includes a first element, a second element, a third element, selenium Se, and tellurium Te. The first element can be germanium Ge or silicon Si, and the second element is any one or a combination of any two or more non-metallic elements with an atomic number less than 20. The third element is any one or a combination of any two or more elements in the third or fourth main group with an atomic number greater than or equal to 30. Finally, a second electrode layer is formed on the side of the gate material layer away from the first electrode layer.

[0028] Among them, the addition of Te element can greatly increase the material stability of the gate tube material layer and ensure the switching characteristics of the manufactured gate tube. The addition of Se element can ensure that the gate tube has a suitable threshold voltage, so that the threshold voltage of the gate tube can be adapted to the storage unit and the peripheral circuit. The addition of non-metallic elements with an atomic number less than 20 can provide small atoms for the gate tube material layer, further inhibit its material crystallization and element drift, thereby improving the switching life of the gate tube. At the same time, the addition of the third and fourth main group elements can further improve the structural stability of the gate tube material layer, thereby reducing the threshold voltage drift. In this way, a gate tube with excellent characteristics such as low leakage, high thermal stability, high adaptability to external devices, long switching life and low threshold voltage drift can be obtained. At the same time, no toxic substances are stored in the entire process, the process environment is friendly and reduces environmental pollution.

[0029] In an optional embodiment, when preparing the gate tube, a first buffer layer may be added to the structure. Specifically, after forming the first electrode layer, the first buffer layer is first formed on one side of the first electrode layer, and then the gate tube material layer is formed on the side of the first buffer layer facing away from the first electrode layer. Then, the second electrode layer is formed on the side of the gate tube material layer facing away from the first buffer layer. The material of the first buffer layer can be any one or more of amorphous carbon, SiC, CS, TeC, TeCS, MoTe2, MoS2, MnTe, HfO2 / TaO, WTe2, and WS2.

[0030] Specifically, adding a buffer layer can further alleviate the leakage problem of the gate transistor and improve the switching characteristics of the gate transistor. At the same time, the first buffer layer contacts one surface of the gate transistor layer, and the interface formed can further prevent element migration, thereby improving the stability of the gate transistor and the switching life of the gate transistor.

[0031] In an optional embodiment, a second buffer layer may be added between the gate tube layer and the second electrode layer to form a double-sided buffer layer structure. Specifically, after forming the first electrode layer, a first buffer layer is first formed on one side of the first electrode layer, and then a gate tube material layer is formed on the side of the first buffer layer facing away from the first electrode layer. Then, a second buffer layer is formed on the side of the gate tube material layer facing away from the first buffer layer, and finally, a second electrode layer is formed on the side of the second buffer layer facing away from the gate tube material layer. The material of the second buffer layer may also be any one or more of amorphous carbon, SiC, CS, TeC, TeCS, MoTe2, MoS2, MnTe, HfO2 / TaO, WTe2, and WS2.

[0032] Specifically, this double-sided buffer layer structure can further alleviate the leakage problem of the gate transistor and improve the switching characteristics of the gate transistor. At the same time, the first and second buffer layers contact the two surfaces of the gate transistor layer respectively, and the interface formed can further prevent element migration, thereby improving the stability of the gate transistor and the switching life of the gate transistor.

[0033] In a third aspect, embodiments of the present application provide a memory chip. The memory chip includes multiple memory cells, each of which includes a storage layer and a gate layer. The gate layer acts on the storage layer to perform read and write operations on the memory cell. The gate layer includes a gate material layer, which is made from the gate material provided in the first aspect and any embodiment of the first aspect.

[0034] The gate tube layer is used to select the storage layer. When the gate tube layer is turned on, the memory cells connected to it will be selected. When the gate tube layer is turned off, the memory cells will also be turned off and cannot be selected. In this way, the leakage current problem in the memory chip can be solved, preventing the gate current from flowing through the surrounding memory cells and causing the unselected cells to malfunction. The gate tube material affects the performance of the gate tube layer. The gate tube layer made of the gate tube material provided in the embodiment of the present application has excellent characteristics such as low leakage, high thermal stability, high compatibility with other devices, long switching life, and low threshold voltage drift. Therefore, this type of gate tube layer can greatly increase the storage reliability of the memory cell, thereby improving the storage performance of the entire memory chip.

[0035] In some optional embodiments, the gate tube layer further includes a first buffer layer. This first buffer layer is stacked with the gate tube material layer. The addition of the buffer layer can further alleviate leakage issues in the gate tube layer, thereby improving the switching characteristics of the gate tube layer. Furthermore, the first buffer layer contacts a surface of the gate tube material layer, and the interface formed therewith can further prevent element migration in the gate tube material layer, thereby improving the stability of the gate tube layer and extending the switching life of the gate tube layer.

[0036] In some optional embodiments, the gate tube layer may further include a second buffer layer, wherein the first buffer layer, the gate tube material layer, and the second buffer layer are stacked in sequence, with the second buffer layer located on the side of the gate tube material layer facing away from the first buffer layer. This double-sided buffer layer structure can further alleviate leakage issues in the gate tube layer and improve its switching characteristics. Furthermore, the first and second buffer layers, respectively contacting the two surfaces of the gate tube material layer, form an interface that further prevents element migration, thereby improving the stability of the gate tube layer and extending its switching life.

[0037] In some optional embodiments, the first buffer layer and the second buffer layer include any one or more of amorphous carbon, SiC, CS, TeC, TeCS, MoTe2, MoS2, MnTe, HfO2 / TaO, WTe2, and WS2.

[0038] In a fourth aspect, embodiments of the present application provide a memory chip. The memory chip includes multiple memory cells, each of which includes a gate transistor layer. The gate transistor layer not only has switching characteristics but also utilizes its switching characteristics to implement a storage function. Specifically, the gate transistor layer generates two different turn-on voltages after being operated with positive and negative polarity pulses. Therefore, the positive and negative polarity pulse operations can be defined as write and erase operations, respectively, to implement the storage of "0" and "1." For example, after a positive polarity pulse operation, the threshold voltage of the gate transistor layer becomes Vth1, while after a negative polarity pulse operation, the threshold voltage becomes Vth2. During a read operation on the gate transistor layer, the gate transistor layer is tested using Vth between Vth1 and Vth2. If Vth turns on the gate transistor layer, the threshold voltage of the gate transistor layer is Vth1, indicating that the data stored in the gate transistor is "0." If Vth does not turn on the gate transistor layer, the threshold voltage of the gate transistor layer is Vth2, indicating that the data stored in the gate transistor is "1." The gate tube layer is made from the gate tube material provided by the first aspect and any of the embodiments of the first aspect. While the gate tube material affects the performance of the gate tube layer, a gate tube layer made from the gate tube material provided by the embodiments of the present application exhibits excellent properties such as low leakage, high thermal stability, high compatibility with other devices, long switching life, and low threshold voltage drift. Therefore, using the gate tube layer for data storage can improve the storage reliability and stability of the memory cell, and significantly increase the lifespan of the memory cell.

[0039] At the same time, the storage mechanism of the selection tube layer is based on the effect of positive and negative electrical polarity. Compared with the traditional storage cell structure, it is no longer limited by the nucleation and growth limitations in crystallization dynamics, so it has faster read and write speeds. At the same time, its read and write process does not involve a high-temperature melting process, so it reduces thermal crosstalk while also reducing erase and write power consumption.

[0040] In some optional embodiments, the gate tube layer further includes a first buffer layer. This first buffer layer is stacked with the gate tube material layer. The addition of the buffer layer can further alleviate leakage issues in the gate tube layer, thereby improving the switching characteristics of the gate tube layer. Furthermore, the first buffer layer contacts a surface of the gate tube material layer, and the interface formed therewith can further prevent element migration in the gate tube material layer, thereby improving the stability of the gate tube layer and extending the life of the gate tube layer.

[0041] In some optional embodiments, the gate tube layer may further include a second buffer layer, wherein the first buffer layer, the gate tube material layer, and the second buffer layer are stacked in sequence, with the second buffer layer located on the side of the gate tube material layer facing away from the first buffer layer. This double-sided buffer layer structure can further alleviate leakage issues in the gate tube layer and improve the switching characteristics of the gate tube layer. Furthermore, the first and second buffer layers, respectively, contact the two surfaces of the gate tube material layer, forming an interface that further prevents element migration, thereby improving the stability of the gate tube layer and extending its lifespan.

[0042] In some optional embodiments, the first buffer layer and the second buffer layer include any one or more of amorphous carbon, SiC, CS, TeC, TeCS, MoTe2, MoS2, MnTe, HfO2 / TaO, WTe2, and WS2.

[0043] In a fifth aspect, an embodiment of the present application provides a memory comprising the memory chip as described in any one of the third aspect or the fourth aspect and a controller, wherein the controller is configured to perform data read and write operations on the memory chip.

[0044] In a sixth aspect, embodiments of the present application provide an electronic device comprising the memory and processor described in the fifth aspect, wherein the processor is configured to store data generated by the electronic device in the memory. The electronic device may be a desktop computer, laptop computer, smartphone, tablet computer, wearable device, smart speaker, television, drone, vehicle, or robot, without limitation. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] FIG1 is a structural diagram of an electronic device provided in an embodiment of the present application;

[0046] FIG2 is a structural diagram of a memory provided in an embodiment of the present application;

[0047] FIG3 is a schematic structural diagram of a memory chip provided in an embodiment of the present application;

[0048] FIG4 is a schematic structural diagram of a storage unit provided in an embodiment of the present application;

[0049] FIG5 is a schematic diagram of the structure of another memory chip provided in an embodiment of the present application;

[0050] FIG6 is a schematic structural diagram of another storage unit provided in an embodiment of the present application;

[0051] FIG7 is a schematic structural diagram of a gate tube layer provided in an embodiment of the present application;

[0052] FIG8 is a schematic structural diagram of another gate tube layer provided in an embodiment of the present application;

[0053] FIG9 is a schematic flow chart of a method for preparing a gate tube according to an embodiment of the present application;

[0054] FIG10 is a schematic flow chart of another method for preparing a gate tube according to an embodiment of the present application;

[0055] FIG11 is a DC IV curve diagram of the gate tube provided in an embodiment of the present application after annealing at 400 degrees;

[0056] FIG12 is an IV curve diagram of the gate tube provided in an embodiment of the present application after annealing at 400 degrees;

[0057] FIG13 is a diagram showing the resistance change of the gate transistor provided in an embodiment of the present application after annealing at 450 degrees;

[0058] FIG14 is a schematic diagram showing how the threshold voltage of a gate transistor provided by an embodiment of the present application changes with the number of cycles after annealing at 400 degrees Celsius;

[0059] FIG15 is a schematic diagram showing the threshold voltage drift of the gate transistor provided in an embodiment of the present application after annealing at 400 degrees. DETAILED DESCRIPTION

[0060] The present invention provides a gate material, a memory chip, and a memory device. In the present invention, the gate material comprises at least five elements. A gate transistor fabricated from this gate material exhibits excellent properties, including low leakage, high thermal stability, high compatibility with other devices, long switching life, and low threshold voltage drift.

[0061] To make the objectives, technical solutions, and advantages of this application more clear, the technical solutions in this application will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0062] The terms "first", "second", etc. in the specification, embodiments, claims, and drawings of this application are only used for the purpose of distinguishing descriptions and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying an order. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one (item)" means one or more, and "multiple" means two or more. "Installation", "connection", "connected", etc. should be understood in a broad sense, for example, it can be an electrical connection or a mechanical connection; it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, an indirect connection through an intermediate medium, or a connection between two elements. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, including a series of steps or units. Methods, systems, products, or devices are not necessarily limited to the steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to the processes, methods, products, or devices. "Up," "down," "left," "right," etc. are used only with respect to the orientation of components in the drawings. These directional terms are relative concepts and are used for relative description and clarification. They may change accordingly depending on the orientation of the components in the drawings.

[0063] The technical solutions provided in the embodiments of the present application are described below with reference to the accompanying drawings.

[0064] The present application provides an electronic device, which may be a terminal device, a server device, or the like. Taking a terminal device as an example, the terminal may be a mobile phone, a computer, a tablet computer, a personal digital assistant (PDA), a smart wearable device, a smart home device, or other device including a chip, although this is not limited to this embodiment of the present application. For ease of explanation, the following description uses a mobile phone as an example.

[0065] As shown in Figure 1, a mobile phone may include a circuit board, a display screen, a battery, a camera, etc. The circuit board may include a processor, internal memory, a charging circuit, etc. Of course, the mobile phone may also include other components, and the circuit board may also include other circuit structures, which are not limited in this embodiment of the present application.

[0066] A processor may include one or more processing units, for example, an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a memory, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU). Different processing units may be independent devices or integrated into one or more processors.

[0067] The GPU is a microprocessor for image processing that connects the display and application processor. It performs mathematical and geometric calculations for graphics rendering. This allows the phone to achieve display functionality through the GPU, display, and application processor.

[0068] The mobile phone's charging circuitry includes a power management circuit and a charge management circuit. The power management circuit connects the battery, the charge management circuit, and the processor. The charge management circuit receives charging input from the charger to charge the battery. While the charge management circuit charges the battery, it also provides power to the mobile phone through the power management circuit. The power management circuit receives input from the battery and / or the charge management module to power the processor, internal memory, display, camera, and other components.

[0069] Mobile phones can also achieve shooting functions through cameras, GPUs, displays, and application processors.

[0070] The internal memory in a mobile phone can be used to store computer-executable program code, which includes instructions. The processor executes the instructions stored in the internal memory to perform various functions and data processing in the mobile phone. The following is an introduction to memory.

[0071] FIG2 is a structural framework diagram of a memory provided in an embodiment of the present application. As shown in FIG2 , the memory 200 includes a controller 201 and a memory chip 202. The memory chip 202 includes multiple memory cells, and the controller 201 can communicate with each memory cell in the memory chip 202. In other words, the controller 201 can implement read and write operations and other operations for the memory cells. For example, the controller 201 can control the data writing process of each memory cell, and can also control the data reading process of each memory cell.

[0072] Figure 3 is a schematic diagram of the structure of a memory chip provided in an embodiment of the present application. As shown in Figure 3, the memory chip can be a crossbar array memory structure, which can achieve 3D stacking of memory cells, ensuring high storage density of the memory chip. Each memory cell in the memory chip includes a stacked memory layer and a gate tube layer, wherein the gate tube layer has a switching characteristic, which is used to open or close the memory layer to enable reading and writing of the memory cell.

[0073] Referring to Figure 3 , WL stands for word line and BL for bit line, both of which are used to identify the location of each memory cell in the crossbar array. For example, the location of memory cell 30 can be represented as (BL0, WL1), and the locations of gate layer 301 and storage layer 302 are also (BL0, WL1). Specifically, word line WL1 and bit line BL0 work together to select memory cell 30, thereby enabling reading and writing of memory cell 30.

[0074] The storage layer is used to store and access data. The storage layer involved in the embodiments of the present application can be a phase change memory unit, a resistive memory unit, a magnetic memory unit, or a ferroelectric memory unit, etc., without specific limitation.

[0075] Among them, the gate tube layer is used to solve the leakage current problem in the memory chip. In order to prevent the gate current from flowing through the surrounding memory cells and causing the unselected cells to malfunction, each memory cell must contain a gate tube layer. The following is a brief introduction to the working principle of the gate tube layer: the gate tube layer realizes the gating of the memory layer connected in series with it. Specifically, WL and BL provide electrical signals for the gate tube layer. When an electrical signal is applied to the gate tube layer, the gate tube material changes from a high-resistance state to a low-resistance state, the gate tube layer is in an on state, the memory layer connected to it is selected, and then the memory layer can perform subsequent read and write operations. When the electrical signal is removed, the gate tube material will change from a low-resistance state to a high-resistance state, the gate tube layer is in an off state, and the memory layer connected to it will also be closed and cannot be selected, making it impossible to read and write data.

[0076] As shown in Figure 4, it is a schematic diagram of the structure of a memory cell provided in an embodiment of the present application. According to the above description, each memory cell includes a gate tube layer and a storage layer, and the storage layer and the gate tube layer are stacked in sequence. Taking the phase change memory as an example, the stacking structure of the storage layer and the gate tube includes a lower electrode layer 401, a gate tube material layer 402, an intermediate electrode layer 403, a first buffer layer 404, a phase change layer 405, a second buffer layer 406, and an upper electrode layer 407 in sequence. Among them, the lower electrode layer 401, the gate tube material layer 402 and the intermediate electrode layer 403 constitute the gate tube layer, and the intermediate electrode layer 403, the first buffer layer 404, the phase change layer 405, the second buffer layer 406, and the upper electrode layer 407 constitute the storage layer. The lower electrode layer 401 of the gate tube layer is connected to the bit line BL in the memory, and the upper electrode layer 407 of the storage layer is connected to the word line WL in the memory. Among them, the insulating layer 408 is used for insulation isolation.

[0077] It is understandable that the gate material forming the gate material layer 402 needs to meet certain performance requirements in order to be better applied in low-latency, high-life, and high-density 3D memories.

[0078] 1. The gating tube material needs to have good stability.

[0079] During the manufacturing process of the gate tube layer, the gate tube material needs to undergo a series of processing processes such as heat treatment and etching. This requires that the gate tube material can maintain a high degree of stability during the process, and will not lose the switching characteristics of the final gate tube layer or cause serious leakage due to crystallization or element segregation.

[0080] 2. The gate tube material needs to match the storage layer.

[0081] To achieve high integration density and minimize peripheral circuit modifications, the gate tube material must meet the matching requirements of high integration density on leakage density, threshold voltage, drive current density, etc. For example, the gate tube material must ensure that the final gate tube layer has a suitable threshold voltage.

[0082] 3. The material of the gate tube needs to ensure that the gate tube layer has a long erase and write life.

[0083] Specifically, the gate tube material must match the low latency and high fatigue requirements of the storage layer. The erase and write life of the gate tube layer must be 1-2 orders of magnitude higher, reaching over 1E10. This means that the gate tube layer must maintain good switching characteristics under a certain number of on-off cycles.

[0084] 4. The material of the gate tube needs to ensure the reliability of the gate tube.

[0085] Specifically, it is necessary to ensure that the threshold voltage of the gate tube layer drifts as little as possible over time, that is, the threshold voltage needs to be stable within a certain range to ensure a sufficient read margin range.

[0086] FIG5 is a schematic diagram of the structure of another memory chip provided in an embodiment of the present application. As shown in FIG5A , the memory chip may have a crossbar array memory structure, which enables 3D stacking of memory cells, ensuring a high storage density of the memory chip. For example, as shown in FIG5B , the memory chip may also have a vertical stacked memory structure, which enables multiple layers of memory cells to be stacked in a vertical direction, further increasing the storage density of the memory chip.

[0087] In the embodiment of the present application, each memory cell in the memory chip only includes a gate tube layer, wherein the gate tube layer has not only switching characteristics but also storage characteristics. The storage principle of the gate tube layer is introduced below.

[0088] The gate layer primarily utilizes two different threshold voltages, Vth1 and Vth2, generated by positive and negative polarity pulses to store "0" and "1." Specifically, under the action of electric fields of different polarities, the localized migration of atoms in the gate layer varies, shifting the energy band structure and causing corresponding changes in its threshold voltage. This allows one of the positive and negative polarity pulses to be used as a write operation, and the other as an erase operation. Simultaneously, a voltage, Vth0, between Vth1 and Vth2, can be used to determine a read operation.

[0089] For example, a positive polarity pulse operation can be performed on the memory cell, so that the turn-on voltage of the memory cell becomes Vth1. At this time, the data stored in the memory cell is data "1". When the memory cell is read using voltage Vth0, Vth0 is greater than Vth1, the gate tube layer is turned on, and a read current flows. Next, a reverse polarity pulse operation can be performed on the memory cell, so that the turn-on voltage of the memory cell becomes Vth2. At this time, the data stored in the memory cell will become data "0". When the memory cell is read using voltage Vth0, Vth0 is less than Vth2, the gate tube layer is turned off, and no read current flows.

[0090] According to the above description, the memory cell provided by the embodiment of the present application removes the memory layer compared to the traditional memory cell, and the core functional layer of the memory cell is simplified from a 7-layer stack to a 3-layer stack, which greatly reduces the aspect ratio and etching difficulty of the column after etching, effectively avoids the collapse problem in the miniaturization process, and improves the yield of the entire silicon wafer. In addition, the transformation of the memory cell provided by the embodiment of the present application does not come from the crystallization and amorphization process, but from the effect of positive and negative electrode polarity. Therefore, the memory cell is no longer limited by the nucleation and growth limitations in the crystallization dynamics, has a faster transformation speed, and its read and write delay is greatly reduced. In addition, the transformation process does not involve a high-temperature melting process, which can reduce the erase and write power consumption while reducing thermal crosstalk. Therefore, the storage performance of the memory cell using the gate tube layer is better.

[0091] 5A , WL stands for word line and BL stands for bit line, which can be used to identify the location of each memory cell in the crossbar array. Specifically, WL and BL work together to select a memory cell, thereby enabling reading and writing of the memory cell.

[0092] FIG6 is a schematic diagram of the structure of a memory cell according to an embodiment of the present application. As described above, each memory cell includes a gate tube layer. The gate tube layer includes, in sequence, a lower electrode layer 401, a gate tube material layer 402, and an upper electrode layer 403. The lower electrode layer 401 of the gate tube layer is connected to the bit line BL in the memory, and the upper electrode layer 403 of the gate tube layer is connected to the word line WL in the memory.

[0093] It is understandable that the gate material forming the gate material layer 402 needs to meet certain performance requirements to achieve good storage performance. For example, the gate material needs to have excellent stability, the gate material needs to ensure that the ultimately formed gate layer has a suitable threshold voltage, the gate material needs to ensure that the gate layer has a long erase and write life, and the gate material needs to ensure that the threshold voltage of the gate layer drifts as little as possible over time. In other words, the threshold voltage needs to be stable within a certain range to ensure a sufficient read margin range.

[0094] The existing gate tube material is usually a compound containing silicon Si, germanium Ge, arsenic As, and selenium Se (Si-Ge-As-Se system). This type of gate tube material has weak stability during the process and is prone to device damage. If the stability is increased by increasing the concentration of Si, the threshold voltage of the gate tube will be too high. And because the As element is highly toxic, its presence makes the process very unfriendly. Therefore, how to obtain a gate tube material that does not contain the As element, so that the gate tube made of it has strong thermal stability, suitable threshold voltage, high erase and write life and excellent characteristics of low threshold voltage drift, has become a problem that needs to be solved urgently.

[0095] Based on the above description, the embodiment of the present application provides a new gate tube material. The gate tube made of the gate tube material has strong thermal stability, appropriate threshold voltage, long erase and write life, and low threshold voltage drift.

[0096] Figure 7 is a schematic structural diagram of a gate tube layer provided in an embodiment of the present application. As shown in Figure 7 , the gate tube layer 700 includes a second electrode layer 401 , a gate tube material layer 402 , and a first electrode layer 403 stacked in sequence.

[0097] The first electrode layer 403 and the second electrode layer 401 are both made of conductive materials and are connected to the outside to provide electrical signals for the gate transistor.

[0098] Exemplarily, the first electrode layer 403 and the second electrode layer 401 can both be inert electrodes, and their materials can be one of platinum Pt, tungsten W, gold Au, ruthenium Ru, aluminum Al, titanium tungsten TiW, titanium nitride TiN, tantalum nitride TaN, ruthenium oxide IrO2, nano indium tin metal oxide ITO and indium zinc oxide IZO, or an alloy material synthesized from the above multiple materials.

[0099] The gate tube material layer 402 includes at least five elements. Schematically, the gate tube material used to make the gate tube material layer 402 is a compound including a first element, a second element, a third element, selenium Se, and tellurium Te.

[0100] The first element is germanium Ge or silicon Si, forming a Ge-Se-Te or Si-Se-Te system.

[0101] The second element is any one or more non-metallic elements with an atomic number less than 20. For example, the second element can be any one of boron B, carbon C, nitrogen N, oxygen O, and sulfur S, or a combination of any two or more thereof.

[0102] The third element is any one or more elements in the third or fourth main group with an atomic number greater than or equal to 30. For example, the third element can be any one of germanium Ge, gallium Ga, indium In, thallium Tl, tin Sn, and lead Pb, or a combination of any two or more thereof.

[0103] The performance of the above-mentioned gating tube is described below:

[0104] 1. The addition of Te significantly increases the stability of the gate tube material. This is because Te atoms are large, chemically stable, and less susceptible to segregation. This more stable gate tube material prevents severe local structural changes, such as crystallization or element migration, after high-temperature processing, thereby ensuring the switching characteristics of the resulting gate tube.

[0105] 2. Since the threshold voltage of Te-based devices is generally low, adding Se elements can increase the threshold voltage of the gate tube, so that the threshold voltage of the gate tube can be adapted to the memory cell or peripheral circuit.

[0106] 3. The addition of elements such as boron (B), carbon (C), nitrogen (N), oxygen (O), and sulfur (S) provides small atoms for the gate tube layer material, which further inhibits material crystallization and element drift. This allows the gate tube to have a higher cycle count, extending its lifespan and, in turn, ensuring a longer lifespan for the memory chip.

[0107] 4. The addition of Group III and Group IV elements can form bonds with Se and Te, further improving structural stability and thus reducing threshold voltage drift. Furthermore, the material of the gate tube layer is a multi-element compound comprising at least five elements. Within this multi-element compound, a specific element ratio can reduce homogeneous bonds (such as Ge-Ge bonds) and band gap variations introduced by relaxation phenomena, thereby suppressing the rise in the threshold voltage of the gate tube and improving its reliability.

[0108] Therefore, the gate transistor provided by the embodiment of the present application has excellent characteristics such as low leakage, high thermal stability, high compatibility with external devices, long switch life, and low threshold voltage drift. In addition, its material does not contain toxic elements, and the process is environmentally friendly.

[0109] The following is an explanation of the material of the gate tube layer based on the chemical molecular formula:

[0110] Schematically, the chemical formula of the material of the gate tube layer can be a five-element formula:

[0111] (Ge x Se y Te z ) a M b X c or (Si x Se y Te z ) a M b X c

[0112] Among them, M is used to indicate the second element, and X is used to indicate the third element. x Se y Te zThe aforementioned Ge-Se-Te or Si-Se-Te system is the primary material of the gate tube layer. For example, the ratio of x to y is greater than 1 and less than 3, and the ratio of y to z is greater than 1 and less than 10. For example, x can be 8, y can be 4, and z can be 2. It is understood that the values ​​of x, y, and z only need to satisfy the aforementioned ratio constraints and are not specifically limited.

[0113] a, b and c represent the contents of each part respectively, wherein the contents b and c of the non-main elements (secondary element and tertiary element) need to be less than 15%, and the content of the main element needs to be greater than 70%.

[0114] The content of non-main elements cannot exceed the maximum threshold to avoid affecting the threshold voltage of the gate transistor. Within the maximum threshold range, the higher the content of non-main elements doped in the material, the higher the thermal stability of the gate transistor device, the lower the leakage current, and the more stable the threshold voltage.

[0115] Preferably, among the gate tube materials, Si(Ge) x Se y Te z The content a is between 80% and 94%, while the contents b and c of the doped non-main elements (secondary element and tertiary element) are between 3% and 10% to improve the reliability of the gate tube.

[0116] Exemplarily, the combination of elements in the five-membered molecular formula includes but is not limited to the following examples:

[0117] Ge(Si)SeTeCGa, Ge(Si)SeTeCIn, Ge(Si)SeTeBGa, Ge(Si)SeTeBIn, Ge(Si)SeTeNGa, Ge(Si)SeTeNIn, etc. are not specifically limited.

[0118] Illustratively, the chemical formula of the material of the gate tube layer can also be a six-element formula, that is, a material based on the Ge-Se-Te or Si-Se-Te system is doped with two second elements (non-metallic elements with an atomic number less than 20) or two third elements (elements in the third and fourth main groups with an atomic number greater than or equal to 30). The six-element formula is:

[0119] (Ge x Se y Te z ) a M1 b1 M2 b2 X c or (Ge x Se y Te z ) a Mb X1 c1 X2 c2 ;

[0120] (Si x Se y Te z ) a M1 b1 M2 b2 X c or (Si x Se y Te z ) a M b X1 c1 X2 c2 .

[0121] The values ​​of x, y, and z refer to the values ​​of x, y, and z in the above five-membered molecular formula and are not described in detail here.

[0122] M1 indicates the first secondary element, M2 indicates the second secondary element, X1 indicates the first tertiary element, and X2 indicates the second tertiary element. When doping with two secondary elements, b1 and b2 represent the concentrations of each secondary element. b1, b2, and c must all be less than 15% to minimize impact on the gate threshold voltage. When doping with two tertiary elements, c1 and c2 represent the concentrations of each tertiary element. b, c1, and c2 must all be less than 15% to minimize impact on the gate threshold voltage.

[0123] Preferably, among the gate tube materials, Si(Ge) x Se y Te z The content a is between 70% and 91%, and the content of each doped non-main element (second element and third element) is between 3% and 10% to improve the reliability of the gate tube.

[0124] For example, the combination of elements in the six-membered molecular formula includes but is not limited to the following examples:

[0125] Ge(Si)SeTeCBGa, Ge(Si)SeTeCBGaIn, Ge(Si)SeTeCNGa, Ge(Si)SeTeCNIn, Ge(Si)SeTeBNGa, Ge(Si)SeTeBNIn, GeSiSeTeNGa, GeSiSeTeNIn, etc. are not specifically limited.

[0126] It is understandable that the number and combination of non-main elements doped in the gate tube material can be varied, and this application does not limit this.

[0127] Based on the above description, Figure 8 is a schematic diagram of the structure of another gate tube layer provided in an embodiment of the present application. As shown in Figure 8, the gate tube layer 800 includes a second electrode layer 401, a second buffer layer 501, a gate tube material layer 402, a first buffer layer 502, and a first electrode layer 403 stacked in sequence.

[0128] Among them, the first electrode layer 403, the second electrode layer 401 and the gate tube material layer 402 are the same as the first electrode layer 403, the second electrode layer 401 and the gate tube material layer 402 in the embodiment shown in Figure 4. The description of each layer refers to the description of each layer in the embodiment shown in Figure 4 and is not repeated here.

[0129] The first buffer layer 502 and the second buffer layer 501 can be amorphous carbon layers, and their materials can also be compounds of C-Si, CS, or can be one or more compounds including molybdenum ditelluride MoTe2, molybdenum disulfide MoS2, manganese telluride MnTe, hafnium dioxide HfO2, hafnium zirconium oxide HfZrO, tantalum oxide TaO, aluminum oxide Al2O3, tungsten ditelluride WTe2, tungsten disulfide WS2, titanium nitride TiNO, etc., which are not limited here.

[0130] For example, the materials of the first buffer layer 502 and the second buffer layer 501 may be the same or different, which is not limited here.

[0131] The addition of the first buffer layer 502 and the second buffer layer 501 can further alleviate the leakage problem of the gate tube layer and improve the switching and storage characteristics of the gate tube layer. At the same time, the first buffer layer 502 and the second buffer layer 501 are in contact with the two surfaces of the gate tube material layer 402 respectively. The interface formed by them can further prevent element migration, thereby improving the stability of the gate tube layer and extending the life of the gate tube.

[0132] FIG9 is a flow chart of a method for preparing a gate tube according to an embodiment of the present application. As shown in FIG9 , the preparation method includes:

[0133] 901. Form a second electrode layer.

[0134] As shown, the second electrode layer can be an inert electrode, and its material can be one of platinum Pt, tungsten W, gold Au, ruthenium Ru, aluminum Al, titanium tungsten TiW, titanium nitride TiN, tantalum nitride TaN, ruthenium oxide IrO2, nano indium tin metal oxide ITO and indium zinc oxide IZO, or an alloy material synthesized from the above materials.

[0135] 902. Form a gate material layer on the first surface of the second electrode layer.

[0136] Indicatively, the gate material layer includes at least five elements. Indicatively, the gate material of the gate material layer is a compound including a first element, a second element, a third element, selenium Se and tellurium Te. Among them, the first element is germanium Ge or silicon Si, forming a Ge-Se-Te or Si-Se-Te system. The second element is any one or more of the non-metallic elements with an atomic number less than 20. Exemplarily, the second element can be any one of boron B, carbon C, nitrogen N, oxygen O, sulfur S, or a combination of any two or more. The third element is any one or more of the elements in the third or fourth main group with an atomic number greater than or equal to 30. Exemplarily, the third element can be any one of germanium Ge, gallium Ga, indium In, thallium Tl, tin Sn, lead Pb, or a combination of any two or more.

[0137] Specifically, for the description of the material of the gating layer, please refer to the description of the relevant contents of the above embodiment, which will not be repeated here.

[0138] The thickness of the gate tube material layer is 5 to 100 nanometers. Preferably, the thickness of the gate tube material layer is about 20 nanometers.

[0139] 903. Form a first electrode layer on a side of the gating material layer away from the second electrode layer.

[0140] As shown, the first electrode layer can be an inert electrode, and its material can be one of platinum (Pt), tungsten (W), gold (Au), ruthenium (Ru), aluminum (Al), titanium tungsten (TiW), titanium nitride (TiN), tantalum nitride (TaN), ruthenium oxide (IrO2), nano-indium tin oxide (ITO), and indium zinc oxide (IZO), or an alloy material synthesized from multiple of the above materials. The material of the first electrode layer can be the same as or different from the material of the second electrode layer.

[0141] In the above-mentioned preparation method, the preparation process of each layer can adopt deposition methods such as physical vapor deposition, chemical vapor deposition, molecular beam epitaxy, atomic layer deposition or metal organic deposition, without limitation.

[0142] The gate transistor fabrication method provided in the embodiments of the present application exhibits excellent characteristics such as low leakage, high thermal stability, high compatibility with external devices, long switching life, and low threshold voltage drift. Furthermore, the process is free of toxic elements, which not only helps reduce process costs but also poses a significant risk to the environment.

[0143] FIG10 is a flow chart of another method for preparing a gate tube according to an embodiment of the present application. As shown in FIG7 , the preparation method includes:

[0144] 1001. Form a second electrode layer.

[0145] It can be understood that this step is similar to step 601 in the above embodiment and will not be described in detail here.

[0146] 1002. Form a second buffer layer on the first surface of the second electrode layer.

[0147] Among them, the second buffer layer can be an amorphous carbon layer, and its material can also be a compound of C-Si, CS, or it can be one or more compounds including molybdenum ditelluride MoTe2, molybdenum disulfide MoS2, manganese telluride MnTe, hafnium dioxide HfO2, hafnium zirconium oxide HfZrO, tantalum oxide TaO, aluminum oxide Al2O3, tungsten ditelluride WTe2, tungsten disulfide WS2, titanium oxynitride TiNO, etc., which are not limited here.

[0148] 1003. Form a gate material layer on a side of the second buffer layer away from the second electrode layer.

[0149] The gate tube material of the gate tube material layer is consistent with the material of the gate tube material layer in the embodiment shown in FIG6 , and will not be described in detail here.

[0150] 1004. Form a first buffer layer on a side of the gate tube material layer away from the second buffer layer.

[0151] The first buffer layer may be an amorphous carbon layer, and its material may be a compound of C-Si, CS, or one or more compounds including molybdenum ditelluride MoTe2, molybdenum disulfide MoS2, manganese telluride MnTe, hafnium dioxide HfO2, hafnium zirconium oxide HfZrO, tantalum oxide TaO, aluminum oxide Al2O3, tungsten ditelluride WTe2, tungsten disulfide WS2, titanium oxynitride TiNO, etc., without limitation herein. The materials of the first buffer layer and the second buffer layer may be the same or different, without limitation herein.

[0152] 1005. Form a first electrode layer on a side of the first buffer layer away from the gate material layer.

[0153] Specifically, this step is similar to step 603 in the above embodiment and will not be described in detail here.

[0154] The gate transistor fabricated by the method provided in the embodiments of the present application comprises a first buffer layer and a second buffer layer. The addition of the first and second buffer layers can further alleviate leakage issues in the gate transistor and improve its switching characteristics. Furthermore, the first and second buffer layers contact two surfaces of the gate transistor layer, respectively, forming an interface that further prevents element migration, thereby improving the stability of the gate transistor and extending its switching life.

[0155] Figures 11 to 15 show the test results of the gate tube provided in the embodiment of the present application. As shown in Figure 11, it is a DC IV curve diagram of the gate tube provided in the embodiment of the present application after annealing at 400 degrees. Among them, the horizontal axis is the voltage value and the vertical axis is the current value. The current value corresponding to 1 / 2Vth (1 / 2 threshold voltage) is the leakage current of the gate tube. Referring to Figure 11, 1 / 2Vth is 1.5V, and the leakage current corresponding to 1.5V is about 3nA (nanoamperes), which indicates that the gate tube has a small leakage current when it is turned off and has very good switching characteristics.

[0156] Figure 12 shows the IV curve of the gate transistor provided in the embodiment of the present application after annealing at 400 degrees. As can be seen from Figure 12, the threshold voltage of the gate transistor is around 3.5V, which has good switching characteristics and a threshold voltage that matches the external environment.

[0157] Figure 13 shows the resistance change of the gate transistor provided in the embodiment of the present application after annealing at 450 degrees. As shown in Figure 13, the gate transistor can still maintain a high resistance state after annealing, and has high stability.

[0158] Figure 14 shows a schematic diagram of the threshold voltage of a gate transistor provided by an embodiment of the present application after annealing at 400 degrees Celsius and the change in cycle number. As shown in Figure 14, as the number of cycles (switching times) of the gate transistor increases, the gate transistor can still be opened and closed normally, and has a long service life.

[0159] Figure 15 is a schematic diagram showing the threshold voltage drift of the gate transistor provided by the present invention after annealing at 400 degrees Celsius. As shown in Figure 15, the threshold voltage region of the gate transistor is stable, the threshold voltage drift is small, and the performance is high.

[0160] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0161] For other relevant contents in the above-mentioned deposition method, you can refer to the corresponding parts in the above-mentioned deposition equipment embodiment, which will not be repeated here; for other setting structures in the above-mentioned deposition equipment embodiment, you can refer to the above-mentioned deposition method for adjustment, which will not be repeated here one by one.

[0162] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A gate tube material, characterized in that: The gate tube material is a compound including a first element, a second element, a third element, selenium Se and tellurium Te; Wherein, the first element is germanium Ge or silicon Si; The second element is any one or a combination of any two or more non-metallic elements with an atomic number less than 20; The third element is any one or a combination of any two or more elements in the third or fourth main group with an atomic number greater than or equal to 30.

2. The gate tube material according to claim 1, characterized in that: The molecular formula of the compound is: (Ge x Se y Te z ) a M b X c or (Si x Se y Te z ) a M b X c ; Wherein, the M is used to indicate the second element, and the X is used to indicate the third element; The ratio of x to y is greater than 1 and less than 3; the ratio of y to z is greater than 1 and less than 10; The a is used to indicate the (Ge x Se y Te z ) or (Si x Se y Te z ) content; said b is used to indicate the content of said M, said c is used to indicate the content of said X; wherein said a is greater than 70%, said b and said c are greater than 0 and less than 15%.

3. The gate tube material according to claim 2, characterized in that: The a is greater than 80% and less than 94%, and the b and c are both greater than 3% and less than 10%.

4. The gate tube material according to claim 1, characterized in that: The molecular formula of the compound is: (Ge x Se y Te z ) a M1 b1 M2 b2 X c or (Si x Se y Te z ) a M1 b1 M2 b2 X c ; Wherein, the M1 is used to indicate the first type of the second element, the M2 is used to indicate the second type of the second element; and the X is used to indicate the third element. The ratio of x to y is greater than 1 and less than 3; the ratio of y to z is greater than 1 and less than 10; The a is used to indicate the (Ge x Se y Te z ) or (Si x Se y Te z ), the b1 is used to indicate the content of the M1, the b2 is used to indicate the content of the M2, and the c is used to indicate the content of the X; wherein the a is greater than 55%, and the b1, the b2 and the c are all greater than 0 and less than 15%.

5. The gate tube material according to claim 4, characterized in that: The a is greater than 70% and less than 91%, and the b1, b2 and c are all greater than 3% and less than 10%.

6. The gate tube material according to claim 1, characterized in that: The molecular formula of the compound is: (Ge x Se y Te z ) a M b X1 c1 X2 c2 or (Si x Se y Te z ) a M b X1 c1 X2 c2 ; Wherein, the M is used to indicate the second element; the X1 is used to indicate the first type of the third element; and the X2 is used to indicate the second type of the third element; The ratio of x to y is greater than 1 and less than 3; the ratio of y to z is greater than 1 and less than 10; The a is used to indicate the (Ge x Se y Te z ) or (Si x Se y Te z ), the b is used to indicate the content of the M, the c1 is used to indicate the content of the X1, and the c2 is used to indicate the content of the X2; wherein the a is greater than 55%, and the b, the c1 and the c2 are all greater than 0 and less than 15%.

7. The gate tube material according to claim 4, characterized in that: The a is greater than 70% and less than 91%, and the b, c1, and c2 are all greater than 3% and less than 10%.

8. A memory chip, characterized in that: It comprises a plurality of storage units; wherein each storage unit comprises a storage layer and a gate tube layer, the gate tube layer is used to select the storage layer to perform read and write operations on the storage unit, the gate tube layer comprises a gate tube material layer; the gate tube material layer adopts the gate tube material described in any one of claims 1-7.

9. The memory chip according to claim 8, wherein: The gate tube layer further includes a first buffer layer; The first buffer layer and the gate tube material are stacked.

10. The memory chip according to claim 9, wherein: The gate tube layer further includes a second buffer layer; The first buffer layer, the gate tube material layer and the second buffer layer are stacked in sequence; the second buffer layer is located on a side of the gate tube material layer away from the first buffer layer.

11. The memory chip according to claim 10, wherein: The first buffer layer and / or the second buffer layer includes any one or more of amorphous carbon, SiC, CS, TeC, TeCS, MoTe2, MoS2, MnTe, HfO2 / TaO, WTe2, and WS2.

12. A memory chip, characterized in that: It comprises a plurality of storage units, each storage unit comprises a gate tube layer, the gate tube layer has both gating and storage functions, the gate tube layer comprises a gate tube material layer; the gate tube material layer adopts the gate tube material according to any one of claims 1-7.

13. The memory chip according to claim 12, wherein: The gate tube layer further includes a first buffer layer; The first buffer layer and the gate tube material are stacked.

14. The memory chip according to claim 13, wherein: The gate tube layer further includes a second buffer layer; The first buffer layer, the gate tube material layer and the second buffer layer are stacked in sequence; the second buffer layer is located on a side of the gate tube material layer away from the first buffer layer.

15. The memory chip according to claim 14, wherein: The first buffer layer and / or the second buffer layer includes any one or more of amorphous carbon, SiC, CS, TeC, TeCS, MoTe2, MoS2, MnTe, HfO2 / TaO, WTe2, and WS2.

16. A memory, characterized in that: The memory comprises a memory chip and a controller according to any one of claims 8 to 14; The controller is used to perform data reading and writing operations on the storage chip.

17. An electronic device, characterized in that: The electronic device comprises a processor and the memory as claimed in claim 16 , wherein the processor is configured to store data generated by the electronic device in the memory.

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