Load store unit, processor, and computer device

Abstract

The present application discloses a load store unit, a processor, and a computer device. The load store unit comprises an address calculation circuit, a prediction circuit, a store queue, and a store buffer. The address calculation circuit is connected to the prediction circuit, and the prediction circuit is separately connected to the store queue, the store buffer, and a data cache. The address calculation circuit is configured to: calculate a load data address corresponding to a load instruction and send the load data address to the prediction circuit. The prediction circuit is configured to: by comparing features of the load data address with features of addresses of data in the store queue and the store buffer, predict whether data corresponding to the load instruction is present in the store queue or the store buffer; and if the prediction indicates that the data corresponding to the load instruction is present in the store queue or the store buffer, trigger a query for the data corresponding to the load instruction in the store queue and the store buffer, while skipping a query for said data in the data cache.

Description

Loading storage units, processors, and computer devices This application claims priority to the Chinese patent application filed with the China Patent Office on February 7, 2024, with application number 202410175640.X and invention name “Loading storage unit, processor and computer device”, the entire contents of which are incorporated by reference into this application. Technical Field The present application relates to the field of chip technology, and in particular to a loading and storing unit, a processor, and a computer device. Background of the Invention In a processor, the Load Store Unit (LSU) is responsible for accessing memory and retrieving data. In related technologies, the LSU contains multiple buffers. When accessing memory, the LSU needs to simultaneously query data from multiple buffers and the data cache (DCache), and then merge the query results from multiple buffers and the DCache. Summary of the Invention The embodiments of the present application provide a loading storage unit, a processor, and a computer device, which can improve the processor's access efficiency to data and reduce the processor's power consumption. A load-store unit according to various embodiments includes: an address calculation circuit, a prediction circuit, a store queue, and a store buffer; The address calculation circuit is connected to the prediction circuit, and the prediction circuit is respectively connected to the storage queue, the storage buffer and the data cache; An address calculation circuit is used to calculate the load data address corresponding to the load instruction and send the load data address to the prediction circuit; A prediction circuit, configured to predict whether the data corresponding to the load instruction exists in the storage queue or the storage buffer by comparing characteristics of the load data address with characteristics of addresses of the data in the storage queue and the storage buffer; The prediction circuit is further configured to trigger a query for the data corresponding to the load instruction in the prediction circuit and the storage queue when it is predicted that the data corresponding to the load instruction exists in the storage queue or the storage buffer, and skip querying the data in the data cache. An instruction processing method according to various embodiments may be performed by a load-store unit, which may be the load-store unit described above. The method may include the following steps: Calculate the load data address corresponding to the load instruction and send the load data address to the prediction circuit; Predicting whether the data corresponding to the load instruction exists in the store queue or the store buffer by comparing a feature based on the load data address with features of addresses of the data in the store queue and the store buffer; When it is predicted that the data corresponding to the load instruction exists in the storage queue or the storage buffer, a query for the data corresponding to the load instruction is triggered in the storage queue and the storage buffer, and querying the data in the data cache is skipped. On the other hand, a processor is provided, comprising at least one load-store unit as described above. On the other hand, a computer device is provided. The computer device includes at least one processor, and the processor includes at least one load-store unit as described above. The embodiment of the present application sets a prediction circuit in the load-store unit of the processor. The prediction circuit can predict whether the data corresponding to the load instruction exists in the storage queue or the storage buffer by comparing the characteristics of the load data address corresponding to the load instruction with the characteristics of the address of the data in the storage queue and the storage buffer. If the data corresponding to the load instruction exists in the storage queue or the storage buffer, the data corresponding to the load instruction can be queried in the storage buffer and the storage queue, thereby skipping the query process in the data cache, thereby reducing invalid access to the data cache, improving data access efficiency, and reducing the power consumption of the processor. BRIEF DESCRIPTION OF THE DRAWINGS In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work. FIG1 is a schematic diagram of a load access pipeline; Figure 2 is an implementation structure of a cuckoo filter; FIG3 is a schematic diagram of a load storage unit according to an embodiment of the present application; FIG4 is a schematic diagram of a load storage unit according to an embodiment of the present application; FIG5 is a schematic diagram of a load storage unit provided in an embodiment of the present application; FIG6 is a schematic diagram of the structure of a prediction circuit according to an embodiment of the present application; FIG7 is a schematic diagram of the structure of another prediction circuit according to an embodiment of the present application; FIG8 is a schematic diagram of the structure of another prediction circuit according to an embodiment of the present application; FIG9 is a schematic diagram of a cache structure according to an embodiment of the present application; FIG10 is a schematic diagram of the structure of another prediction circuit according to an embodiment of the present application; FIG11 is a schematic diagram of the structure of a prediction circuit according to an embodiment of the present application; FIG12 is a schematic diagram of a load storage unit according to an embodiment of the present application; FIG13 is a schematic diagram of the structure of another prediction circuit according to an embodiment of the present application; FIG14 is a schematic diagram of a load access pipeline according to an embodiment of the present application; FIG15 is a schematic diagram of inserting a new address into a predictor according to an embodiment of the present application; FIG16 is a schematic diagram of another embodiment of the present application of inserting a new address into the predictor; FIG17 is a schematic diagram of an address in a query predictor according to an embodiment of the present application; FIG18 is a flowchart of an instruction processing method according to an embodiment of the present application. Modes for Carrying Out the Invention In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings. It should be understood that although the terms first, second, etc. may be used in this disclosure to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, a first parameter may also be referred to as a second parameter, and similarly, a second parameter may also be referred to as a first parameter without departing from the scope of this disclosure. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining". The following first introduces some concepts involved in this application: 1) Load Store Unit (LSU): The LSU (Low Storage Unit) of a processor (such as a central processing unit (CPU)) is responsible for accessing memory and retrieving data. The LSU contains multiple buffers, such as the Store Queue (SQ) and the Store Buffer (SB). The SQ buffers the execution results of uncommitted store instructions, while the SB buffers the execution results of committed instructions that have not yet been written to the data cache (Dcache). Store instructions instruct the storage of data in registers to external memory (the computer system's internal memory and the CPU's cache are collectively referred to as the CPU's external memory). Load instructions instruct the loading of data from external memory into the processor's registers. During the execution of a load instruction, the SQ and SB are checked for the required data (matching the address). If so, the data in those buffers is prioritized, discarding the data retrieved from the Dcache. From the perspective of the Load instruction, the priority for data retrieval is SQ > SB > Dcache. However, to prioritize performance, access to the SQ, SB, and Dcache is performed simultaneously. After all data is retrieved, data merging is performed. For example, if address matching data is found in the SQ, SB, and Dcache, the data in the SB and Dcache must be discarded. For example, refer to Figure 1, which shows a schematic diagram of a load access pipeline. 2) Cuckoo filter: Please refer to Figure 2, which shows an implementation structure of a Cuckoo filter. As shown in Figure 2, Cuckoo filters and Bloom filters are both probabilistic data structures used to efficiently check whether an element belongs to a set. They are very useful in many applications, such as network routing, caching, and databases. Although they have similar purposes, their implementation and performance characteristics differ. The insertion and deletion principles of Cuckoo filters are as follows: (1) Insertion principle: As shown in Figure 2, for the element x to be inserted, its hash value h(x) and fingerprint f(x) are calculated. The fingerprint is a shorter representation of the element, usually expressed in a few bits, and is generally taken from the last few bits of the element's hash value. For example, if the fingerprint of x in Figure 2 is 0101, then an attempt will be made to insert this fingerprint into the bucket. Two candidate locations i1 and i2 are calculated using two hash functions. Here, i1 = h(x) and i2 = h(x)xor h(f(x)). This means that element x can be stored in either location i1 or i2. Check if there is an empty space at positions i1 and i2. If there is an empty space, store f(x) in one of the positions and complete the insertion. If both positions i1 and i2 are full, then one of the positions (for example, i1) is selected, its current fingerprint f(y) is moved out, and f(x) is stored in that position. Calculate the new position for the element y that was removed using the method calculated previously. Then try to insert f(y) into the new position. If the new position is also full, continue to remove the existing element and try to insert f(y). If after a number of iterations (usually set to a fixed threshold), f(y) cannot be inserted, the Cuckoo Filter is considered full. At this time, you can choose to increase the size of the filter or report the insertion failure. (2) Deletion principle: For the element x to be deleted, calculate its hash value h(x) and fingerprint f(x). Use the hash value to calculate two candidate positions i1 and i2, where i1 = h(x) and i2 = i1⊕h(f(x)). Check if positions i1 and i2 contain fingerprint f(x). If f(x) is found, set the position where it is located to empty and complete the deletion. If f(x) is not found in both positions i1 and i2, then the element x is not in the Cuckoo Filter. In order to solve the problems of existing processors at least in terms of access efficiency and power consumption, an embodiment of the present application provides a load storage unit that can be applied to a processor, which can improve the processor's access efficiency to data and reduce the processor's power consumption. Please refer to FIG3 , which shows a schematic diagram of a load-store unit provided by an exemplary embodiment of the present application. The load-store unit includes: an address calculation circuit 310 , a prediction circuit 320 , a store queue 330 , and a store buffer 340 . The address calculation circuit 310 is connected to the prediction circuit 320 , and the prediction circuit 320 is connected to the store queue 330 , the store buffer 340 , and the data cache 350 , respectively. An input / output port of the address calculation circuit 310 is electrically connected to an input port of the prediction circuit 320 , and an output port of the prediction circuit 320 is electrically connected to an input port of each of the storage queue 330 , the storage buffer 340 , and the data cache 350 . The address calculation circuit 310 is used to calculate the load data address corresponding to the load instruction and send the load data address to the prediction circuit 320 . The address calculation circuit 310 may calculate the load data address based on the load instruction, and output the load data address to the input port of the prediction circuit 320 via the output port between the address calculation circuit 310 and the prediction circuit 320 . For example, the load instruction may include the base position / starting position (base) and offset (offset) of the data to be loaded. The address calculation circuit 310 may parse the base position and offset in the load instruction and calculate the loaded data address based on the base position and offset obtained by parsing. The prediction circuit 320 is used to predict whether the data corresponding to the load instruction exists in the storage queue or storage buffer based on the load data address. The prediction circuit 320 may determine whether data corresponding to the load data address exists in the store queue or store buffer based on the load data address input by the address calculation circuit 310. The prediction circuit 320 may predict whether the data corresponding to the load instruction exists in the store queue or store buffer by comparing characteristics of the load data address with characteristics of addresses of data in the store queue and the store buffer. For example, the prediction circuit 320 may store address information of all or part of the data in the storage queue and the storage buffer, and then compare the address information of the loaded data with the stored address information. If the stored address information contains information that is consistent with the address information of the loaded data, it can be considered that the data corresponding to the load instruction is present in the storage queue or the storage buffer. Conversely, if the stored address information does not contain information that is consistent with the address information of the loaded data, it can be considered that the data corresponding to the load instruction is not present in the storage queue or the storage buffer. For another example, the prediction circuit 320 may store fingerprints of addresses of all or part of the data in the storage queue and storage buffer, and compare the fingerprints of the loaded data address with the stored address information to predict whether the data corresponding to the load instruction exists in the storage queue or storage buffer. The prediction circuit 320 is further configured to trigger a query for the data corresponding to the load instruction in the storage queue 330 or storage buffer 340 when predicting that the data corresponding to the load instruction exists in the storage queue or storage buffer, and skip querying the data in the data cache. Among them, if the prediction circuit 320 predicts that the data corresponding to the load instruction exists in the storage queue or storage buffer, it can trigger the query of the corresponding data in the storage queue 330 and storage buffer 340. At this time, the process of querying the corresponding data in the data cache 350 may not be executed. In some embodiments, the prediction circuit 320 is further configured to trigger a query for the data corresponding to the load instruction in the storage queue 330 , the storage buffer 340 , and the data cache 350 when it is predicted that the data corresponding to the load instruction does not exist in the storage queue or the storage buffer. In the embodiment of the present application, the prediction circuit 320 predicts that the data corresponding to the load instruction does not exist in the storage queue or storage buffer, which can also be called the prediction circuit 320 failing to predict that the data corresponding to the load instruction exists in the storage queue or storage buffer. In an embodiment of the present application, a certain error is allowed in the prediction result of the prediction circuit 320. If the prediction circuit 320 predicts that the data corresponding to the load instruction does not exist in the storage queue or storage buffer, it can trigger a process of querying the corresponding data in parallel in the storage queue 330, the storage buffer 340 and the data cache 350 to ensure the accuracy of the data query process. To sum up, the solution shown in the embodiment of the present application is to set a prediction circuit in the load storage unit of the processor. The prediction circuit can predict whether the data corresponding to the load instruction exists in the storage queue or the storage buffer through the load data address corresponding to the load instruction. If it is predicted that the data corresponding to the load instruction exists in the storage queue or the storage buffer, the data corresponding to the load instruction can be queried in the prediction circuit and the storage queue, thereby skipping the query process in the data cache, thereby reducing invalid access to the data cache, and then improving the utilization rate of the data cache and reducing the power consumption of the processor. Based on the above embodiment, please refer to Figure 4, which shows a schematic diagram of a load storage unit provided by an exemplary embodiment of the present application. As shown in Figure 4, the prediction circuit 320 includes a cache circuit 322, and the cache circuit 322 is used to store the fingerprint information of the address of the data in the storage queue 330 and the storage buffer 340. Prediction circuit 320 is configured to calculate fingerprint information of the load data address, match the fingerprint information of the load data address with the fingerprint information stored in cache circuit 322, and, if the fingerprint information of the load data address successfully matches the fingerprint information stored in cache circuit 322, predict that the data corresponding to the load instruction exists in the store queue or store buffer. Here, prediction circuit 320 searches the fingerprint information stored in cache circuit 322 for fingerprint information that matches the fingerprint information of the load data address. If the fingerprint information stored in cache circuit 322 includes fingerprint information that matches the fingerprint information of the load data address, prediction circuit 320 determines that the data corresponding to the load instruction exists in the store queue or store buffer. Accordingly, when the fingerprint information of the loaded data address fails to match the fingerprint information stored in the cache circuit 322, that is, when there is no fingerprint information in the fingerprint information stored in the cache circuit 322 that is consistent with the fingerprint information of the loaded data address, it is determined that the data corresponding to the load instruction does not exist in the storage queue or storage buffer. The fingerprint information may be obtained by performing a hash calculation on the data address, or may be obtained by processing the data address using other algorithms (such as a secure hash algorithm, a message digest (MD) algorithm, etc.). That is, the data volume (or length) of the fingerprint information is smaller than the data volume of the corresponding address, and the fingerprint information of different data addresses is different. Among them, the above-mentioned cache circuit 322 can cache the fingerprint information of the addresses of all or part of the data in the storage queue 330 and the storage buffer 340. During the prediction process, the prediction circuit 320 matches the fingerprint information of the input address with the fingerprint information stored in the cache circuit 322. If the match is successful, it is determined that the data corresponding to the input address is present in the storage queue or the storage buffer. If the match is unsuccessful, it is determined that the data corresponding to the input address is not present in the storage queue or the storage buffer. Since the data volume of the above-mentioned fingerprint information is smaller than the data volume of the address, the storage queue 330 performs subsequent predictions by caching the fingerprint information of the data address. On the one hand, it can reduce the amount of data stored in the cache circuit 322 and simplify the structural complexity of the cache circuit 322. On the other hand, the matching speed between the fingerprint information of a small amount of data is faster, which can improve the efficiency of the prediction. Based on the above embodiment, please refer to Figure 5, which shows a schematic diagram of a load-store unit provided by an exemplary embodiment of the present application. As shown in Figure 5, the cache circuit 322 includes a first cache 322a and a second cache 322b; the first cache 322a and the second cache 322b each contain multiple entries. The prediction circuit 320 is configured to calculate a position of a first entry in the first cache 322 a and a position of a second entry in the second cache 322 b based on the load data address. The prediction circuit 320 is used to match (i.e., compare) the fingerprint information of the load data address with the fingerprint information in the first entry and the second entry respectively, and when the fingerprint information of the load data address successfully matches (i.e., is consistent with) the fingerprint information in the first entry or the second entry, determine that the data corresponding to the load instruction is present in the storage queue 330 or the storage buffer 340. In the embodiment of the present application, two caches may be provided in the cache circuit 322 , each of which may include multiple entries for caching fingerprint information, each entry being used to store fingerprint information corresponding to a segment of addresses (ie, each entry is shared by a segment of continuous addresses). Furthermore, for one address, corresponding entries can be found in both caches. When data is written to the storage queue, the fingerprint information of the address of the data can be cached in one entry of the two caches. Accordingly, for one address, the prediction circuit 320 can calculate the entry positions of the address in the two caches, and then match the fingerprint information of the address with the fingerprint information of the cache in the calculated entry positions. If the fingerprint information of the address matches the fingerprint information cached in any of the calculated entry positions of the two caches, it is determined that the data corresponding to the address exists in the storage queue 330 or the storage buffer 340. Conversely, if the fingerprint information of the address does not match (i.e., is consistent with) the fingerprint information in both calculated entry positions of the caches, it is determined that the data corresponding to the address does not exist in the storage queue 330 or the storage buffer 340 (or in other words, it is not predicted that the data corresponding to the address exists in the storage queue 330 or the storage buffer 340). Among them, since the above-mentioned one entry corresponds to a section of address, there may be a situation where the data of two addresses in the section of address corresponding to the same entry are both written into the storage queue. In this case, the entry can only store the fingerprint information of one of the addresses, which causes an address conflict, resulting in a reduction in the accuracy of subsequent predictions. In response to this, the solution shown in the embodiment of the present application sets up two caches, each of which contains multiple entries. In the case where the data of two addresses in the section of address corresponding to the same entry are both written into the storage queue, the fingerprint information of the two addresses can be cached in the entries corresponding to different caches respectively, thereby effectively reducing the situation of address conflicts. The solution shown in the above embodiment of the present application is to set up multiple entries in the cache, each entry corresponding to a segment of address. When the data of a certain address is written to the storage queue, the fingerprint information of the address is cached in the corresponding entry for matching in the subsequent prediction process. On the one hand, each entry is shared by a segment of address, and the largest possible address range can be covered with a lower number of entries. On the other hand, by storing the fingerprint information of two addresses in the same segment of address in two caches respectively, address conflicts can be reduced and prediction accuracy can be improved. In addition to setting two caches in the cache circuit 322, three or more caches can also be set in the cache circuit 322, each cache containing multiple entries. In this way, fingerprint information of three or more addresses in the same segment address can be cached in the cache circuit 322 at the same time, further reducing address conflicts and improving prediction accuracy. In some embodiments, the prediction circuit 320 is configured to perform a hash calculation on the address portion of the loaded data address that is higher than the cache line granularity to obtain fingerprint information of the loaded data address. In a computer system, a cache can be composed of multiple cache lines. A cache line is the smallest storage unit of cache management, also called a cache block. Each cache line can contain a flag, tag, and data. The flag and tag may be different for different processor models. A cache line is the smallest unit for exchanging data between the cache and RAM. The storage space of a cache line can be called the cache line granularity. For example, the cache line granularity can be 64 bytes. Based on spatial locality, that is, the possibility that adjacent data will be accessed in the future is high, when the processor loads data from the memory into the cache, it will put the adjacent 64-byte data into the same cache line. In an embodiment of the present application, a continuous address segment corresponding to a cache line granularity can be set to share an entry in the above-mentioned cache, and for a segment of addresses that share an entry in the above-mentioned cache, the address portion of this segment of addresses that is higher than the cache line granularity is the same; when calculating the fingerprint information of an address, the prediction circuit 320 can perform a hash calculation through the address portion of the address that is higher than the cache line granularity to obtain the corresponding fingerprint information. For example, taking the cache line granularity as 64B (i.e., 64Byte) and an address of 0x20000f74f8 (binary representation is 100000000000000000011110111010011111000) as an example, the address above 64B is 0x20000f74c0 (binary representation is 10000000000000000011110111010011000000), and the address within 64B is 0x38 (binary representation is 111000). At this time, the prediction circuit 320 can perform hash calculation on 0x20000f74c0 to obtain the corresponding fingerprint information. For example, please refer to Figure 6, which shows a schematic diagram of the structure of a prediction circuit involved in an embodiment of the present application. As shown in Figure 6, in addition to the cache circuit 322, the prediction circuit 320 also includes a fingerprint calculation circuit 323, which is connected to the address calculation circuit 310; the fingerprint calculation circuit 323 is used to perform a hash calculation on the address portion of the address input by the address calculation circuit 310 (i.e., the above-mentioned loaded data address) that is higher than the cache line granularity to obtain the fingerprint information of the loaded data address. The fingerprint information of the loaded data address can be matched with the fingerprint information in the first entry of the first cache 322a and the fingerprint information in the second entry of the second cache 322b respectively. If the fingerprint information of the loaded data address matches the fingerprint information in the first entry or the second entry, it can be determined that the data corresponding to the predicted load instruction exists in the storage queue 330 or the storage buffer 340. Conversely, if the fingerprint information of the loaded data address does not match the fingerprint information in the first entry or the second entry, it can be considered that the data corresponding to the unpredicted load instruction exists in the storage queue 330 or the storage buffer 340. In an embodiment of the present application, a hash calculation is performed on the address portion that is higher than the cache line granularity in the address to obtain fingerprint information, so that a segment of address corresponding to a cache line granularity shares one entry, and the hash value is used as the fingerprint information to reduce the amount of data represented by the address, thereby covering a sufficiently large address range with as little data as possible, reducing the complexity of storage and matching of address information in the prediction circuit 320, and improving matching efficiency. In some embodiments, the prediction circuit 320 is used to calculate the address portion of the loaded data address that is higher than the cache line granularity through the first position function of the cuckoo filter to obtain the position of the first entry; the prediction circuit 320 is used to calculate the address portion of the loaded data address that is higher than the cache line granularity through the second position function of the cuckoo filter to obtain the position of the second entry. For example, referring to FIG6 , prediction circuit 320 includes, in addition to cache circuit 322 and fingerprint calculation circuit 323, a first position calculation circuit 324 and a second position calculation circuit 325. First position calculation circuit 324 is configured with a first position function for calculating the portion of the load data address input by address calculation circuit 310 that is above the cache line granularity to obtain the position of the first entry in first cache 322a. Correspondingly, second position calculation circuit 325 is configured with a second position function for calculating the portion of the load data address input by address calculation circuit 310 that is above the cache line granularity to obtain the position of the second entry in second cache 322b. As shown in Figure 6, prediction circuit 320 also includes a fingerprint matching circuit 326, which is connected to cache circuit 322. Furthermore, fingerprint matching circuit 326 is connected to fingerprint calculation circuit 323. Based on the position of the first entry calculated by first position calculation circuit 324, cache circuit 322 queries the first cache 322a for the fingerprint information cached in the first entry. Based on the position of the second entry calculated by second position calculation circuit 325, cache circuit 322 queries the second cache 322b for the fingerprint information cached in the second entry. Both retrieved fingerprints are sent to fingerprint matching circuit 326. Fingerprint calculation circuit 323 also sends the calculated fingerprint information of the load data address to fingerprint matching circuit 326. Fingerprint matching circuit 326 is configured to match the fingerprint information of the load data address with the two fingerprints retrieved and sent by cache circuit 322. If the fingerprint information of the load data address matches one of the two fingerprints retrieved and sent by cache circuit 322, it is predicted that the data corresponding to the load instruction is present in store queue 330 or store buffer 340. On the contrary, if the fingerprint information of the load data address does not match the two fingerprint information queried and sent by the cache circuit 322 , it can be considered that the data corresponding to the load instruction is not predicted to exist in the storage queue 330 or the storage buffer 340 . In some embodiments, the fingerprint matching circuit 326 is connected to the storage queue 330, the storage buffer 340, and the data cache 350, respectively. When the fingerprint matching circuit 326 matches the fingerprint information of the loaded data address with one of the two fingerprint information queried and sent by the cache circuit 322, the fingerprint matching circuit 326 can trigger the storage queue 330 and the storage buffer 340 to query the data corresponding to the loaded data address. When the fingerprint matching circuit 326 matches the fingerprint information of the loaded data address with neither of the two fingerprint information queried and sent by the cache circuit 322, the fingerprint matching circuit 326 can trigger the storage queue 330, the storage buffer 340, and the data cache 350 to query the data corresponding to the loaded data address. For example, in FIG6 , the fingerprint matching circuit 326 is further connected to the address calculation circuit 310. The address calculation circuit 310 sends the load data address to the fingerprint matching circuit 326. When the fingerprint matching circuit 326 triggers the storage queue 330 and the storage buffer 340 to query the data corresponding to the load data address, the load data address can be sent to the storage queue 330 and the storage buffer 340. When the fingerprint matching circuit 326 triggers the storage queue 330, the storage buffer 340, and the data cache 350 to query the data corresponding to the load data address, the load data address can be sent to the storage queue 330, the storage buffer 340, and the data cache 350. Alternatively, the load data address may be provided to the storage queue 330, storage buffer 340, and data cache 350 via other circuits besides the fingerprint matching circuit 326. For example, the load data address may be cached in a register in the prediction circuit 320. When the fingerprint matching circuit 326 triggers the storage queue 330 and storage buffer 340 to query the data corresponding to the load data address, the storage queue 330 and storage buffer 340 may be triggered to read the load data address from the register. Correspondingly, when the fingerprint matching circuit 326 triggers the storage queue 330, storage buffer 340, and data cache 350 to query the data corresponding to the load data address, the storage queue 330, storage buffer 340, and data cache 350 may be triggered to read the load data address from the register. Among them, the above-mentioned first position function and second position function can be two different hash functions in the cuckoo filter, and these two different hash functions correspond to a cache respectively. For the same address, the first position function and the second position function can be used to calculate the different entry positions in the two caches, and the fingerprint information of two addresses in the same address segment can be stored in two caches respectively, thereby reducing address conflicts and improving prediction accuracy. In some embodiments, the prediction circuit 320 is further used to perform a hash calculation on the address portion of the first data that is higher than the cache line granularity in response to the first data being written to the storage queue, to obtain fingerprint information of the address of the first data; the prediction circuit 320 is further used to calculate the address portion of the first data that is higher than the cache line granularity through the first position function of the cuckoo filter, to obtain the position of the third entry in the first cache; the prediction circuit 320 is further used to store the fingerprint information of the address of the first data in the third entry. In an embodiment of the present application, when the first data is written to the storage queue, the prediction circuit 320 can calculate the fingerprint information of the address of the first data. At the same time, the position of the third entry in the first cache corresponding to the address of the first data is calculated by the first position function. Regardless of whether the fingerprint information already exists in the third entry, the fingerprint information of the address of the first data is stored in the third entry. Through the above scheme, the fingerprint information corresponding to the address of the data newly written to the storage queue can be cached in the prediction circuit 320 in a timely manner, so that the prediction circuit can subsequently accurately predict whether the data corresponding to the newly received load instruction exists in the storage queue or storage buffer, thereby ensuring the accuracy of the prediction. In some embodiments, the prediction circuit 320 is further used to remove the first fingerprint information from the third entry in response to the first fingerprint information already existing in the third entry; the prediction circuit 320 is further used to calculate the address portion of the data corresponding to the first fingerprint information that is higher than the cache line granularity through the second position function of the cuckoo filter to obtain the position of the fourth entry in the second cache; the prediction circuit is further used to store the first fingerprint information in the fourth entry. In which, the above-mentioned removing the first fingerprint information from the third entry in response to the first fingerprint information already existing in the third entry may mean removing the first fingerprint information from the third entry in response to the first fingerprint information already existing in the third entry and the first fingerprint information is different from the fingerprint information of the address of the first data. In the above embodiment of the present application, each entry is used to store the fingerprint information of an address. When the fingerprint information of the address of the first data is written into the third entry, the fingerprint information of the address of the first data will overwrite the original information in the third entry. At this time, if the fingerprint information of the address of the first data is different from the original information in the third entry, it will be impossible to predict the existence of data corresponding to the first fingerprint information in the storage queue 330 or storage buffer 340 based on the address in the third entry. At this time, the prediction circuit 320 can calculate the fourth entry in the second cache that can cache the first fingerprint information using the second position function, and then move the original first fingerprint information in the third entry to the fourth entry. Subsequently, based on the address in the fourth entry, it can be predicted that the data corresponding to the first fingerprint information exists in the storage queue 330 or storage buffer 340, thereby avoiding the problem that the old fingerprint information in the cache circuit 322 is overwritten by the new fingerprint information, resulting in the inability to accurately predict the corresponding old fingerprint information in the storage queue 330 or storage buffer 340, thereby improving the accuracy of the prediction. In some embodiments, the prediction circuit 320 is further configured to remove the second fingerprint information from the fourth entry in response to the second fingerprint information already existing in the fourth entry. In which, in response to the second fingerprint information already existing in the fourth entry, removing the second fingerprint information from the fourth entry may mean that in response to the second fingerprint information already existing in the fourth entry and the second fingerprint information is different from the first fingerprint information, the second fingerprint information is removed from the fourth entry. In an embodiment of the present application, if the second fingerprint information already exists in the fourth entry and the second fingerprint information is different from the first fingerprint information, the prediction circuit 320 may remove the second fingerprint information from the fourth entry before writing the first fingerprint information into the fourth entry, or during the process of writing the first fingerprint information into the fourth entry, thereby ensuring the accuracy of the fingerprint information stored in the fourth entry. For example, before writing the first fingerprint information into the fourth entry, the prediction circuit 320 may first clear the second fingerprint information already in the fourth entry; or, during the process of writing the first fingerprint information into the fourth entry, the prediction circuit 320 may write the first fingerprint information into the fourth entry by overwriting. For example, please refer to FIG7 , which shows a schematic structural diagram of another prediction circuit involved in an embodiment of the present application. As shown in Figure 7, the storage queue 330 is also connected to the prediction circuit 320. For example, the storage queue 330 is also directly or indirectly connected to the fingerprint calculation circuit 323, the first position calculation circuit 324, and the second position calculation circuit 325 in the prediction circuit 320; when the first data is written into the storage queue 330, the storage queue 330 (or other circuit components outside the storage queue 330) can send the address of the first data to the prediction circuit 320; the prediction circuit 320 first calculates the fingerprint information of the address of the first data through the fingerprint calculation circuit 323 based on the address of the first data, and calculates the third entry in the first cache 322a through the first position calculation circuit 324, and writes the fingerprint information of the address of the first data into the third entry; further, if the first fingerprint information exists in the third entry, the second position calculation circuit 325 is further used to calculate the fourth entry in the second cache 322b corresponding to the address of the data corresponding to the first fingerprint information, and writes the first fingerprint information into the fourth entry; at this time, if the second fingerprint information already exists in the fourth entry, the second fingerprint information will be cleared or overwritten. In some embodiments, the entry includes a fingerprint field and a bitmap field; the bitmap field includes N bits, each bit corresponds to an address range of cache line granularity / N; N is an integer greater than or equal to 2; the prediction circuit 320 is also used to determine the target bit in the bitmap field corresponding to the address portion of the first data that is lower than the cache line granularity when the fingerprint information of the address of the first data is stored in the third entry, and set the target bit in the third entry to the first value. For example, the first value may be 1, and the initial value (second value) of each bit in the bitmap field may be 0. Alternatively, the first value may be 0, and the initial value (second value) of each bit in the bitmap field may be 1. For example, please refer to Figure 8, which shows a schematic diagram of the structure of another prediction circuit involved in an embodiment of the present application. As shown in Figure 8, the prediction circuit 320 may also include a bit calculation circuit 327, which is connected to the cache circuit 322; the bit calculation circuit 327 can calculate the bit in the bitmap field corresponding to the address portion of the address below the cache line granularity based on the address input to the prediction circuit 320, and output the calculated bit to the cache circuit 322; for example, in the process of storing the fingerprint information of the address of the first data, the cache circuit 322 can receive the bit in the bitmap field corresponding to the address portion of the address below the cache line granularity calculated by the bit calculation circuit 327, thereby setting the target bit in the third entry to the first value. For example, please refer to Figure 9, which shows a schematic diagram of a cache structure involved in an embodiment of the present application. As shown in Figure 9, taking the value of N as 16 as an example, in the first cache 322a, each entry includes a fingerprint field 322a1 and a bitmap field 322a2. Among them, the fingerprint field 322a1 is used to cache fingerprint information. The bitmap field 322a2 contains 16 bits (numbered Bit0 to Bit15). Among them, each bit corresponds to an address range of 4Byte. For example, Bit0 corresponds to the address range of 0 to 3Byte, Bit1 corresponds to the address range of 4 to 7Byte, and so on. Taking the address portion of the first data above as 0x38 (in hexadecimal notation) below 64 bytes (this address portion can also be called the address offset within 64 bytes), converted to decimal notation is 56, which corresponds to the address range of 56 to 59 bytes corresponding to Bit 14. When the fingerprint information of the first data is stored in the third entry of the first cache 322a, the bit corresponding to Bit 14 in the bitmap field of the third entry is also set to 1 (the initial value of each bit is 0). Alternatively, the bit corresponding to Bit 14 in the bitmap field of the third entry can be set to 0 (the initial value of each bit is 1). In this case, the value in the bitmap field can represent the data corresponding to the fingerprint information in the fingerprint field. The address portion below 64 bytes is within the range of 56 to 59 bytes (0x38 to 0x3b in hexadecimal notation). Furthermore, suppose another piece of data is written into storage queue 330, and the portion of the address above 64 bytes of this data is the same as the portion of the address above 64 bytes of the first data, while the portion of the address below 64 bytes of this data is different from the portion of the address below 64 bytes of the first data. Assume that the portion of the address below 64 bytes of this data is 0X3E (in hexadecimal), which is converted to decimal as 62, corresponding to the address range of 60 to 63 bytes corresponding to Bit 15. At this time, fingerprint information already exists in the third entry, so the bit corresponding to Bit 15 in the bitmap field of the third entry is set to 1 (the initial value of each bit is 0) or 0 (the initial value of each bit is 1). As shown in Figure 9, through the above setting logic, a maximum of 16 addresses can be stored in one entry. Similarly, when the first fingerprint information is stored in the fourth entry, the address portion of the data corresponding to the first fingerprint information within 64 bytes is obtained, the bit corresponding to the address portion in the bitmap field is calculated, and then the bit in the fourth entry is set to the first value. In an embodiment of the present application, an entry can store fingerprint information of any address in an address range corresponding to a cache line granularity. That is, for an address range of a cache line granularity, the address portion of the address above the cache line granularity is the same. Accordingly, the fingerprint information calculated based on this address portion is also the same. In other words, it is impossible to further distinguish the addresses in an address range of a cache line granularity using only the fingerprint information. In this regard, in an embodiment of the present application, each entry can be divided into two fields, one of which is a fingerprint field for storing fingerprint information, and the other is a bitmap field. The bitmap field contains N bits, and the address range of a cache line granularity is divided into N small address ranges, each small address range corresponding to 1 bit. In the process of storing the fingerprint information of the address of the first data in the third entry, the prediction circuit 320 can also determine the small address range where the address portion of the address of the first data below the cache line granularity is located, and then determine the bit in the bitmap field corresponding to the address portion of the address of the first data below the cache line granularity, and then set the bit position to the first value. Through the above processing, the fingerprint information in an entry, combined with the bits in the bitmap field set to the first value, can be used to indicate a smaller address range (cache line granularity / N address ranges) within which the address of data in the store queue 330 or store buffer 340 is located. This further improves the accuracy of the address indicated by the information cached by each entry. Furthermore, a single entry can store addresses from N address ranges, thereby improving the accuracy of subsequent predictions of whether loaded data exists in the store queue 330 or store buffer 340 and conserving storage resources. In some embodiments, the prediction circuit 320 is further used to perform a hash calculation on the address portion of the second data that is higher than the cache line granularity in response to the second data being removed from the storage buffer to obtain fingerprint information of the address of the second data; the prediction circuit 320 is further used to calculate the position of the fifth entry in the first cache and the position of the sixth entry in the second cache based on the address of the second data; the prediction circuit 320 is used to match the fingerprint information of the address of the second data with the fingerprint information in the fifth entry and the sixth entry respectively, and if the fingerprint information of the address of the second data successfully matches the fingerprint information in the fifth entry or the sixth entry, remove the successfully matched fingerprint information. For example, please refer to Figure 10, which shows a schematic diagram of the structure of another prediction circuit involved in an embodiment of the present application. As shown in Figure 10, the prediction circuit 320 may also include a fingerprint removal circuit 328, which is connected to the cache circuit 322. In addition, the storage buffer 340 is also connected to the prediction circuit 320. Specifically, for example, the storage buffer 340 is also directly or indirectly connected to the fingerprint calculation circuit 323, the first position calculation circuit 324, the second position calculation circuit 325, and the bit calculation circuit 327 in the prediction circuit 320. When the second data is removed from storage buffer 340, storage buffer 340 (or another circuit component outside of storage buffer 340) may send the address of the second data to prediction circuit 320. Based on the address of the second data, prediction circuit 320 calculates fingerprint information of the address of the second data using fingerprint calculation circuit 323, calculates the fifth entry in first cache 322a using first position calculation circuit 324, and calculates the sixth entry in second cache 322b using second position calculation circuit 325. Fingerprint removal circuit 328 then matches the fingerprint information of the address of the second data with the fingerprint information in the fifth entry and the fingerprint information in the sixth entry, respectively. If the fingerprint information of the address of the second data matches the fingerprint information in the fifth entry, cache circuit 322 is triggered to remove the fingerprint information in the fifth entry. If the fingerprint information of the address of the second data matches the fingerprint information in the sixth entry, cache circuit 322 is triggered to remove the fingerprint information in the sixth entry. If the fingerprint information of the address of the second data does not match the fingerprint information in either the fifth entry or the sixth entry, the fingerprint information in the fifth entry and the fingerprint information in the sixth entry are not processed. Through the solution shown in the embodiment of the present application, the fingerprint information corresponding to the address of the data removed from the storage buffer can be promptly removed from the prediction circuit 320, thereby avoiding the prediction circuit from subsequently erroneously predicting that the second data is stored in the storage queue or storage buffer, thereby ensuring the accuracy of the prediction. In some embodiments, the prediction circuit 320 is configured to determine that the fingerprint information of the loaded data address successfully matches the fingerprint information in the first entry or the second entry if the fingerprint information of the loaded data address is identical to the fingerprint information in the first entry or the second entry, and the address range corresponding to the bits set to a specified value in the entry with the identical fingerprint information includes the address portion of the loaded data address below the cache line granularity. The prediction circuit 320 is configured to determine that the fingerprint information of the second data address successfully matches the fingerprint information in the fifth entry or the sixth entry if the fingerprint information of the second data address is identical to the fingerprint information in the fifth entry or the sixth entry, and the address range corresponding to the bits set to a specified value in the entry with the identical fingerprint information includes the address portion of the second data address below the cache line granularity. In an embodiment of the present application, when an entry includes a fingerprint field and a bitmap field, if the address portion of two data above the cache line granularity is the same, and the address portion below the cache line granularity is different, then the fingerprint information of the two addresses is the same, while the bits in the bitmap field corresponding to the address portion below the cache line granularity of the two addresses may be different. At this time, the addresses of the two data can be distinguished by the bits of the first value in the bitmap field. In this regard, in an embodiment of the present application, during the prediction process or during the fingerprint removal process, when matching the fingerprint information of an address with the fingerprint information in an entry in the cache circuit, in addition to checking whether the fingerprint information of the address is the same as the fingerprint information in the entry, it is also checked whether the bits in the bitmap field corresponding to the address portion below the cache line granularity are the same as the bits set to the first value in the entry. If the fingerprint information of the address is the same as the fingerprint information in the entry, and the bits in the bitmap field corresponding to the address portion below the cache line granularity are also the same as the bits set to the first value in the entry, then it means that the address and the address of the data cached in the entry are within the same address range of cache line granularity / N (for example, the above 4 bytes), and it can be considered that the fingerprint information of the address is successfully matched with the fingerprint information in the entry. In other words, the above scheme can match data addresses with cache line granularity / N as the address granularity, thereby reducing the amount of data represented by the address, improving matching efficiency, and ensuring the accuracy of address matching. For example, during the prediction process, as shown in FIG8 , the bit calculation circuit 327 further calculates the bit in the bitmap field corresponding to the address portion of the loaded data address that is lower than the cache line granularity, and sends the bit in the bitmap field corresponding to the address portion of the loaded data address that is lower than the cache line granularity to the fingerprint matching circuit 326. When the fingerprint matching circuit 326 matches the fingerprint information of the loaded data address with the fingerprint information in the first entry / second entry, in addition to checking whether the fingerprint information of the loaded data address is the same as the fingerprint information in the first entry / second entry, it also checks whether the bit in the bitmap field corresponding to the address portion of the loaded data address that is lower than the cache line granularity is the same as the bit set to the first value in the first entry / second entry. If the fingerprint information of the loaded data address is the same as the fingerprint information in the first entry / second entry, the fingerprint matching circuit 326 checks whether the bit in the bitmap field corresponding to the address portion of the loaded data address that is lower than the cache line granularity is the same as the bit set to the first value in the first entry / second entry. The fingerprint information of the loaded data address is the same as that of the first entry / second entry, and the bit in the bitmap field corresponding to the address portion below the cache line granularity in the loaded data address is also the same as the bit set to the first value in the first entry / second entry, then it is determined that the fingerprint information of the loaded data address successfully matches the fingerprint information of the address of the cached data in the first entry / second entry; accordingly, in the case where the second data is removed from the storage buffer, the bit calculation circuit 327 also calculates the bit in the bitmap field corresponding to the address portion below the cache line granularity in the second data address, and sends the bit in the bitmap field corresponding to the address portion below the cache line granularity in the address of the second data to the fingerprint removal circuit 328, so that the fingerprint removal circuit 328 matches the fingerprint information of the address of the second data with the fingerprint information in the fifth entry / sixth entry. In some embodiments, the above-mentioned prediction circuit is used to set the bits corresponding to the address portion of the second data below the cache line granularity in the bitmap field of the entry where the successfully matched fingerprint information is located to the second value when the fingerprint information of the address of the second data successfully matches the fingerprint information in the fifth entry or the sixth entry. In an embodiment of the present application, where an entry includes a fingerprint field and a bitmap field, and the bitmap field includes N bits, each bit corresponding to an address range of cache line granularity / N, removing the fingerprint information corresponding to the address of a data from an entry in the cache circuit 322 may refer to restoring the values of the bits in the bitmap field of the entry corresponding to the address portion below the cache line granularity to the initial second values. In some embodiments, if, after restoring the values of the bits in the bitmap field of the entry corresponding to the address portion below the cache line granularity to the initial second values, the values of all bits in the bitmap field of the entry are the second values, the fingerprint information in the fingerprint field of the entry may also be removed. For example, taking the cache structure shown in FIG. 9 as an example, assume that the second data and the first data are the same data. In this case, the third entry and the fifth entry are the same entry. When the second data is removed from the storage buffer 340, the fingerprint removal circuit 328 determines that the fingerprint information of the second data's address successfully matches the fingerprint information of the third entry. Simultaneously, it determines that the portion of the second data's address below the cache line granularity that corresponds to the bit numbered Bit 14 in the bitmap field of the third entry is Bit 14. At this point, the fingerprint removal circuit 328 can trigger the cache circuit 322 to restore Bit 14 in the third entry to its initial value. At this point, if the bitmap field of the third entry contains other bits with the first value (for example, in FIG. 9 , the initial value of the bit is 0 and the value of Bit 15 is 1), the cache circuit 322 maintains the fingerprint information in the fingerprint field of the third entry unchanged. Conversely, if all bits in the bitmap field of the third entry have the initial value, the cache circuit 322 can remove the fingerprint information from the fingerprint field of the third entry. Accordingly, the process of the prediction circuit 320 removing the first fingerprint information from the third entry may refer to removing the first fingerprint information from the fingerprint field of the third entry and setting each bit in the bitmap field of the third entry to the initial second value. Similarly, the process of the prediction circuit 320 removing the second fingerprint information from the fourth entry may refer to removing the second fingerprint information from the fingerprint field of the fourth entry and setting each bit in the bitmap field of the fourth entry to the initial second value. The embodiments shown in Figures 5 to 10 of the present application involve filtering prediction solutions based on the Cuckoo filter principle. In some embodiments, or in other embodiments, prediction can also be implemented based on other filter algorithms. For example, the prediction of whether data exists in a storage queue or storage buffer can be implemented based on the Bloom filter principle. In some embodiments, the prediction circuit 320 is used to calculate multiple positions of the load data address in the target array through a Bloom filter algorithm, and when the values of the multiple positions of the load data address in the target array are all specified values, it is determined that the data corresponding to the load instruction is predicted to exist in the storage queue or storage buffer. For example, based on the solution shown in FIG4 , please refer to FIG11 , which shows a schematic structural diagram of a prediction circuit involved in an embodiment of the present application. As shown in FIG11 , the prediction circuit 320 further includes a position calculation circuit 328 and a value check circuit 329. The cache circuit 322 includes a third cache 322 c, which caches a target array. For an address (e.g., the aforementioned load data address), the position calculation circuit 328 calculates the load data address using multiple hash algorithms in the Bloom filter algorithm to obtain multiple positions (e.g., three positions) corresponding to the load data address in the target array, and indicates the calculated three positions to the third cache 322 c. The third cache 322 c can read the values of the three positions in the target array and send the read values of the three positions to the value check circuit 329. If the value check circuit 329 detects that the values of the three positions are all specified values (e.g., the initial value of each position in the target array can be 0 and the specified value can be 1, or the initial value of each position in the target array can be 1 and the specified value can be 0), it is determined that the data corresponding to the predicted load instruction exists in the store queue or store buffer. Through the above scheme, it is only necessary to calculate the multiple positions of an address corresponding to the target array and check whether the values of the multiple positions are all specified values to complete the prediction. The prediction process is relatively simple and the prediction efficiency is high. In some embodiments, the prediction circuit 320 is further used to calculate the addresses of the third data at multiple positions in the target array through a Bloom filter algorithm in response to the third data being written into the storage queue 330, and set the values of the addresses of the third data at multiple positions in the target array to specified values. For example, as shown in Figure 11, the storage queue 330 is also connected to the prediction circuit 320. Specifically, the storage queue 330 can be connected to the position calculation circuit 328 in the prediction circuit 320. When the third data is written into the storage queue 330, the storage queue 330 sends the address of the third data to the position calculation circuit 328. The position calculation circuit 328 calculates the address of the third data through multiple hash algorithms in the Bloom filter algorithm, and can obtain the addresses of the third data corresponding to multiple positions (for example, 3 positions) in the target array, and indicates the calculated 3 positions to the third cache 322c; the third cache 322c can set the values of these three positions to specified values. Based on the above embodiment, please refer to FIG12, which shows a schematic diagram of a load-store unit provided by an exemplary embodiment of the present application. As shown in FIG12, the load-store unit further includes: a load reservation station 360 and a data merging circuit 370; the load reservation station 360 is connected to the address calculation circuit 310, the storage queue 330, the storage buffer 340 and the data cache 350 are respectively connected to the data merging circuit 370, and the data merging circuit 370 is also connected to the load reservation station; the load reservation station 360 is used to send a load instruction to the address calculation circuit; the storage queue 330 and the storage buffer 340 are used to predict When the circuit 320 predicts that the data corresponding to the load instruction exists in the storage queue or storage buffer, the queried data is sent to the data merging circuit 370; the data merging circuit 370 is used to merge the data sent by the storage queue 330 and the storage buffer 340, and perform an exception detection on the merged data, and when a data exception is detected, send an exception instruction to the load reservation station 360; the load reservation station 360 is used to resend the load instruction to the address calculation circuit 310; the prediction circuit 320 is used to trigger a query of the data corresponding to the load instruction in the data cache 350 based on the resent load instruction. For example, the prediction circuit 320 is used to trigger a query of the data corresponding to the load instruction in the store queue 330 , the store buffer 340 , and the data cache 350 based on the reissued load instruction. In some embodiments, the load reservation station 360 is used to reissue the load instruction to the address calculation circuit and set the value of the specified flag bit in the reissued load instruction to the specified flag value; the prediction circuit 320 is used to trigger the query of the data corresponding to the load instruction in the data cache 350 when the value of the specified flag bit in the reissued load instruction is the specified flag value. For example, based on the scheme shown in FIG6 , please refer to FIG13 , which shows a schematic diagram of the structure of another prediction circuit involved in an embodiment of the present application. As shown in FIG13 , before the fingerprint calculation circuit 323, the first position calculation circuit 324, and the second position calculation circuit 325, a flag bit check circuit 321 is also included. The input end of the flag bit check circuit 321 is connected to the output end of the address calculation circuit 310, and the output end of the flag bit check circuit 321 is respectively connected to the fingerprint calculation circuit 323, the first position calculation circuit 324, the second position calculation circuit 325 and the data cache 350; the address calculation circuit 310 sends the loaded data address to the flag bit check circuit 321, and the flag bit check circuit 321 checks the value of the specified flag bit in the loaded data address. If the specified flag bit is If the value of the flag bit is a specified flag value (for example, 1), the data cache 350 is directly triggered to query the data corresponding to the load instruction; for example, when the flag bit check circuit 321 checks that the value of the specified flag bit is the specified flag value, the loaded data address can be sent to the data cache 350, and the loaded data address will not be sent to the fingerprint calculation circuit 323, the first position calculation circuit 324 and the second position calculation circuit 325; on the contrary, if the value of the specified flag bit is not the specified flag value, the loaded data address can be sent to the fingerprint calculation circuit 323, the first position calculation circuit 324 and the second position calculation circuit 325 for subsequent prediction process. Through the above scheme, for a certain address, when the prediction circuit 320 makes an incorrect prediction, the data merging circuit 370 can trigger the load reservation station 360 to reissue the load instruction. Correspondingly, when the prediction circuit 320 receives the reissued load instruction, it can directly trigger the data cache 350 to perform data query, thereby ensuring the accuracy of the data query and avoiding the situation where data cannot be loaded due to prediction errors. The solution shown in the above embodiment of the present application can improve CPU performance and reduce CPU power consumption on the product side. Please refer to Figure 14, which shows a schematic diagram of the load access pipeline involved in this application. As shown in Figure 14, based on the solution shown in the above embodiment of the present application, if the predictor predicts that the data has hit in SQ or SB, there is no need to access Dcache. If the prediction is wrong, it will be found that the acquired data is incomplete in the step of merging data, and it will be fed back to Load RS to notify the instruction to re-emit and execute. During the second transmission after the prediction error, Dcache is forced to be accessed, so there will be no error that the data cannot be loaded after the prediction error. Please refer to Figure 15, which shows a schematic diagram of inserting a new address into the predictor involved in this application. As shown in Figure 15, the system designed in the embodiment of the present application uses cacheline (cache line) 64B as the granularity, and fingerprint bucket 1 (Bucket1, corresponding to the above-mentioned first cache 322a) and fingerprint bucket 2 (Bucket2, corresponding to the above-mentioned second cache 322b) have 16 entries respectively. Therefore, the fingerprint (fingerprint information) can be obtained by hashing the address part above 64B, and the address part above 64B is calculated through the Pos1=hash() function or the Pose2=Pos1 xor hash(f(x)) function to obtain the specific entry position pointing to the Bucket. The Bucket in this application is stored in the form of addr:bitmap. As shown in Figure 15, the addr of a Bucket entry in the embodiment of the present application can correspond to 16 bitmaps, which can cover the address range of 16*4B. Compared with the original cuckoo filter structure, more addresses can be stored. In this application, one bit in the bitmap represents a 4-byte data. If the data written by the store instruction is 2 bytes, it also occupies one bit. If it is 8 bytes, it needs to occupy two bits. When an instruction is issued from the store reservation station, its memory address is inserted into the predictor. Assuming the width of the data to be written is 4 bytes, the insertion method is shown in Figure 8. Assuming the address is 0x20000f74f8 (100000000000000000011110111010011111000), it is first divided into two parts according to the cacheline granularity. Taking a cacheline of 64B as an example, the address above 64B is 0x20000f74c0 (10000000000000000011110111010011000000), and the part within 64B is 0x38 (111000). 0x20000f74c0 is used for hash operations. A hash calculation is performed on 0x20000f74c0 (based on fp()) to obtain its fingerprint. If the fingerprint is 0x36, the insertion position is calculated using the formula Pos1 = hash(0x20000f74c0). For example, if the fingerprint is 0x7, the first attempt is to insert fingerprint 0x36 into entry 7 of bucket 1. If there is no conflict with entry 7 in bucket 1, the insertion is performed. If there is a conflict, the attempt is to insert it into bucket 2 at position Pose2 = Pos1 xor hash(f(x)). At this point, the insertion is not complete, and the bitmap needs to be set. Since the offset of address 0x20000f74f8 is 0x38, after processing at a 4-byte granularity, it corresponds to bit 14 of the 16 bits. Therefore, bitmap 14 of entry 7 of bucket 1 is set to 1, and the insertion is now complete. Please refer to Figure 16, which shows another schematic diagram of inserting a new address into the predictor involved in this application. As shown in Figure 16, if the new address 0x00000839f0 is inserted, the bucket1 position obtained after hash calculation is also entry 7, then the original fingerprint 0x36 and the corresponding bitmap need to be kicked out, and the new fingerprint 0xf and bitmap 12 need to be inserted into entry7. The kicked-out fingerprint and bitmap need to be recalculated to obtain a new insertion position Pos2 = Pose1xor hash(f(x)) = 7xor hash(0x36) = 11, so the 0x36 fingerprint and bitmap need to be recalculated to obtain a new insertion position Pos2 = Pose1xor hash(f(x)) = 7xor hash(0x36) = 11.

[0014] Insert into entry 11 in bucket 2. Please refer to Figure 17, which shows a schematic diagram of the address query predictor involved in this application. As shown in Figure 17, if the load instruction accesses the address 0x20000f74f8 during execution, the predictor is queried. Similarly, after processing the address, its pos1 (entry 7) and pos2 (entry 11) are obtained, along with the fingerprint 0x36. Simultaneously querying pos1 and pos2 reveals that the fingerprint of entry 7 in bucket 1 does not match, but the fingerprint of entry 11 in bucket 2 does match, so the address is a hit. At this time, when accessing address 0x20000f74f8, there is no need to access the DCache. To ensure the accuracy of the predictor, after the Store instruction is written from SBuffer to Dcache, it will be deleted from bucket1 and bucket2. The deletion process is similar to the above and will not be repeated here. After data analysis and statistics, about 16% of memory access instructions can obtain complete data from SQ or SB. Therefore, after using this application, assuming that the predictor prediction accuracy is 90% (according to historical design experience, 95% is easily achievable), a total of 16% * 90% = 14.4% of Load instructions accessing Dcache can be reduced. Compared with the original solution, Dcache access conflicts can be reduced and Dcache power consumption can be reduced by about 15%, thereby improving performance and reducing overall power consumption. Please refer to Figure 18, which shows a flow chart of an instruction processing method involved in an exemplary embodiment of the present application. As shown in Figure 18, the method can be performed by a load-store unit, which can be a load-store unit as described in any of Figures 3 to 5 and Figure 12. As shown in Figure 18, the method may include the following steps: Step 1801: Calculate the load data address corresponding to the load instruction through the address calculation circuit, and send the load data address to the prediction circuit. Step 1802 : Predicting whether the data corresponding to the load instruction exists in the store queue or store buffer based on the load data address by using a prediction circuit. Step 1803 : When the prediction circuit predicts that the data corresponding to the load instruction exists in the storage queue or the storage buffer, a query is triggered in the storage queue and the storage buffer for the data corresponding to the load instruction. In some embodiments, the method further includes: triggering, by the prediction circuit, to query the storage queue, storage buffer, and data cache for the data corresponding to the load instruction when it is predicted that the data corresponding to the load instruction does not exist in the storage queue or storage buffer. In some embodiments, the prediction circuit includes a cache circuit configured to store fingerprint information of addresses of data in the storage queue and the storage buffer; In some embodiments, the prediction circuit predicts whether the data corresponding to the load instruction exists in the store queue or the store buffer based on the load data address, including: The fingerprint information of the load data address is calculated by the prediction circuit, and the fingerprint information of the load data address is matched with the fingerprint information stored in the cache circuit. When the fingerprint information of the load data address successfully matches the fingerprint information stored in the cache circuit, it is determined that the data corresponding to the load instruction is predicted to exist in the storage queue or storage buffer. In some embodiments, the cache circuit includes a first cache and a second cache; the first cache and the second cache each include a plurality of entries; The above prediction circuit predicts whether the data corresponding to the load instruction exists in the store queue or store buffer based on the load data address, including: calculating, by the prediction circuit, a position of a first entry in the first cache and a position of a second entry in the second cache based on the load data address; The prediction circuit matches the fingerprint information of the load data address with the fingerprint information in the first entry and the second entry respectively. When the fingerprint information of the load data address successfully matches the fingerprint information in the first entry or the second entry, it is determined that the data corresponding to the load instruction is predicted to exist in the storage queue or the storage buffer. In some embodiments, the calculation of the fingerprint information of the load data address by the prediction circuit includes: The prediction circuit performs hash calculation on the address portion of the loaded data address that is higher than the cache line granularity to obtain fingerprint information of the loaded data address. In some embodiments, calculating the position of the first entry in the first cache and the position of the second entry in the second cache based on the load data address by the prediction circuit includes: The prediction circuit calculates the address portion of the loaded data address that is higher than the cache line granularity based on the first position function of the cuckoo filter to obtain the position of the first entry; The prediction circuit calculates the address portion of the loaded data address that is higher than the cache line granularity based on the second position function of the cuckoo filter to obtain the position of the second entry. In some embodiments, the above method further comprises: In response to the first data being written into the storage queue, the prediction circuit performs a hash calculation on an address portion of the first data that is higher than the cache line granularity to obtain fingerprint information of the address of the first data; By means of a prediction circuit, based on a first position function of a cuckoo filter, a portion of an address of the first data that is higher than a cache line granularity is calculated to obtain a position of a third entry in the first cache; The fingerprint information of the address of the first data is stored in the third entry through the prediction circuit. In some embodiments, the above method further comprises: removing, by the prediction circuit, the first fingerprint information from the third entry in response to the first fingerprint information already existing in the third entry; By using the prediction circuit, based on the second position function of the cuckoo filter, calculating the address portion of the data corresponding to the first fingerprint information that is higher than the cache line granularity, to obtain the position of the fourth entry in the second cache; In response, the first fingerprint information is stored in the fourth entry by the prediction circuit. In some embodiments, the above method further comprises: By the prediction circuit, in response to the second fingerprint information already existing in the fourth entry, the second fingerprint information is removed from the fourth entry. In some embodiments, the entry includes a fingerprint field and a bitmap field; the bitmap field includes N bits, each bit corresponding to an address range of cache line granularity / N; the above method further includes: Through the prediction circuit, when the fingerprint information of the address of the first data is stored in the third entry, it is determined that the address portion of the address of the first data that is lower than the cache line granularity corresponds to the target bit in the bitmap field, and the target bit in the third entry is set to the first value. In some embodiments, the above method further comprises: In response to the second data being removed from the storage buffer, the prediction circuit performs a hash calculation on an address portion of the second data that is higher than a cache line granularity to obtain fingerprint information of the address of the second data; calculating, by the prediction circuit, a position of a fifth entry in the first cache and a position of a sixth entry in the second cache based on the address of the second data; The fingerprint information of the address of the second data is matched with the fingerprint information in the fifth entry and the sixth entry respectively through the prediction circuit. If the fingerprint information of the address of the second data successfully matches the fingerprint information in the fifth entry or the sixth entry, the successfully matched fingerprint information is removed. In some embodiments, matching the fingerprint information of the address of the second data with the fingerprint information in the fifth entry and the sixth entry respectively by the prediction circuit includes: Through the prediction circuit, when the fingerprint information of the address of the second data is the same as the fingerprint information in the fifth entry or the sixth entry, and the address range corresponding to the bits set to the specified value in the entry with the same fingerprint information includes the address portion of the address of the second data that is lower than the cache line granularity, it is determined that the fingerprint information of the address of the second data successfully matches the fingerprint information in the fifth entry or the sixth entry. In some embodiments, the above-mentioned removing the successfully matched fingerprint information by the prediction circuit when the fingerprint information of the address of the second data successfully matches the fingerprint information in the fifth entry or the sixth entry includes: setting, by the prediction circuit, the bits of the address portion of the second data address that is lower than the cache line granularity in the bitmap field of the entry where the successfully matched fingerprint information is located to the second value when the fingerprint information of the address of the second data successfully matches the fingerprint information in the fifth entry or the sixth entry. In some embodiments, the prediction circuit predicts whether the data corresponding to the load instruction exists in the store queue or the store buffer based on the load data address, including: Through the prediction circuit, based on the Bloom filter algorithm, multiple positions of the load data address in the target array are calculated. When the values of the multiple positions of the load data address in the target array are all specified values, it is determined that the data corresponding to the load instruction is predicted to exist in the storage queue or storage buffer. In some embodiments, the above method further comprises: Through the prediction circuit, in response to the third data being written into the storage queue, the addresses of the third data at multiple locations in the target array are calculated through the Bloom filter algorithm, and the values of the addresses of the third data at multiple locations in the target array are set to specified values. In some embodiments, the load-store unit further includes: a load-reservation station and data merging circuitry; The load reservation station is connected to the address calculation circuit, the store queue, the store buffer and the data cache are respectively connected to the data merging circuit, and the data merging circuit is also connected to the load reservation station; The above method further includes: Sending a load instruction to the address calculation circuit via the load reservation station; Through the storage queue and the storage buffer, when the prediction circuit predicts that the data corresponding to the load instruction exists in the storage queue or the storage buffer, the queried data is sent to the data merging circuit; Merging the data sent from the storage queue and the storage buffer through a data merging circuit, performing an anomaly detection on the merged data, and sending an anomaly instruction to the load reservation station when a data anomaly is detected; Reissue the load instruction to the address calculation circuit via the load reservation station; The prediction circuit is used to trigger a query of the data corresponding to the load instruction in the data cache based on the reissued load instruction. In some embodiments, reissuing the load instruction to the address calculation circuit via the load reservation station includes: reissuing a load instruction to the address calculation circuit through the load reservation station, and setting a value of a specified flag bit in the reissued load instruction to a specified flag value; The above prediction circuit triggers the query of the data corresponding to the load instruction in the data cache based on the reissued load instruction, including: The prediction circuit is used to trigger a query of the data cache for data corresponding to the load instruction when the value of the designated flag bit in the reissued load instruction is the designated flag value. The solutions shown in the above embodiments of the present application can be applied to a processor. Specifically, the present application further provides a processor comprising at least one load-store unit as shown in the above embodiments. On the other hand, the present application further provides a computer device, which includes at least one processor, and the processor includes at least one load storage unit as shown in the above embodiments. Those skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware, or may be accomplished by a program to instruct the relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc. The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification. In conclusion, the scope of the claims should not be limited to the exemplary embodiments described above, but should be given the broadest interpretation of the specification as a whole.

Claims

1. A load store unit (LSU), characterized in that: The load storage unit includes: an address calculation circuit, a prediction circuit, a store queue (Store Queue, SQ) and a store buffer (Store Buffer, SB); The address calculation circuit is connected to the prediction circuit, and the prediction circuit is respectively connected to the storage queue, the storage buffer and the data cache (Dcache); The address calculation circuit is used to calculate the load data address corresponding to the load instruction and send the load data address to the prediction circuit; The prediction circuit is configured to predict whether the data corresponding to the load instruction exists in the storage queue or the storage buffer by comparing the characteristics of the load data address with the characteristics of the addresses of the data in the storage queue and the storage buffer; The prediction circuit is further configured to, when it is predicted that the data corresponding to the load instruction exists in the storage queue or the storage buffer, trigger a query for the data corresponding to the load instruction in the storage queue and the storage buffer, and skip querying the data in the data cache.

2. The load-store unit according to claim 1, wherein: The prediction circuit is further configured to trigger a query for the data corresponding to the load instruction in the storage queue, the storage buffer, and the data cache when it is predicted that the data corresponding to the load instruction does not exist in the storage queue or the storage buffer.

3. The load-store unit according to claim 1 or 2, characterized in that: The prediction circuit includes a cache circuit, and the cache circuit is used to store fingerprint information of addresses of data in the storage queue and the storage buffer; The prediction circuit is configured to calculate fingerprint information of the load data address, search for fingerprint information consistent with the fingerprint information of the load data address in the fingerprint information stored in the cache circuit, and determine that the data corresponding to the load instruction exists in the storage queue or the storage buffer when the fingerprint information stored in the cache circuit includes fingerprint information consistent with the fingerprint information of the load data address.

4. The load-store unit according to claim 3, wherein: The cache circuit includes a first cache and a second cache; the first cache and the second cache each include a plurality of entries; The prediction circuit is configured to calculate a position of a first entry in the first cache and a position of a second entry in the second cache based on the load data address; The prediction circuit is used to compare the fingerprint information of the load data address with the fingerprint information in the first entry and the second entry respectively, and when the fingerprint information of the load data address is consistent with the fingerprint information in the first entry or the second entry, determine that the data corresponding to the load instruction exists in the storage queue or the storage buffer.

5. The load-store unit according to claim 4, wherein: The prediction circuit is used to perform hash calculation on the address portion of the loaded data address that is higher than the cache line granularity to obtain fingerprint information of the loaded data address.

6. The load-store unit according to claim 4, wherein: The prediction circuit is configured to calculate the address portion of the load data address that is higher than the cache line granularity based on the first position function of the cuckoo filter to obtain the position of the first entry; The prediction circuit is configured to calculate the address portion of the load data address that is higher than the cache line granularity based on the second position function of the cuckoo filter to obtain the position of the second entry.

7. The load-store unit according to claim 4, wherein: The prediction circuit is further configured to, in response to first data being written into the storage queue, perform a hash calculation on an address portion of the first data that is higher than a cache line granularity to obtain fingerprint information of the address of the first data; The prediction circuit is further configured to calculate, by using a first position function of a cuckoo filter, an address portion of the first data that is higher than a cache line granularity, to obtain a position of a third entry in the first cache; The prediction circuit is further configured to store fingerprint information of the address of the first data into the third entry.

8. The load-store unit according to claim 7, wherein: The prediction circuit is further configured to remove the first fingerprint information from the third entry in response to the first fingerprint information already existing in the third entry; The prediction circuit is further configured to calculate, by using a second position function of a cuckoo filter, an address portion of the data corresponding to the first fingerprint information that is higher than a cache line granularity, to obtain a position of a fourth entry in the second cache; The prediction circuit is further configured to store the first fingerprint information in the fourth entry.

9. The load-store unit according to claim 8, wherein: The prediction circuit is further configured to remove the second fingerprint information from the fourth entry in response to the second fingerprint information already existing in the fourth entry.

10. The load-store unit according to claim 7, wherein: The entry includes a fingerprint field and a bitmap field; the bitmap field includes N bits, each bit corresponds to an address range of cache line granularity / N; N is an integer greater than or equal to 2; The prediction circuit is further configured to, when the fingerprint information of the address of the first data is stored in the third entry, determine that the address portion of the address of the first data that is lower than the cache line granularity corresponds to a target bit in the bitmap field, and set the target bit in the third entry to a first value.

11. The load-store unit according to claim 10, wherein: The prediction circuit is further configured to, in response to the second data being removed from the storage buffer, perform a hash calculation on an address portion of the second data that is higher than a cache line granularity to obtain fingerprint information of the address of the second data; The prediction circuit is further configured to calculate a position of a fifth entry in the first cache and a position of a sixth entry in the second cache based on an address of the second data; The prediction circuit is used to compare the fingerprint information of the address of the second data with the fingerprint information in the fifth entry and the sixth entry respectively, and if the fingerprint information of the address of the second data is consistent with the fingerprint information in the fifth entry or the sixth entry, remove the fingerprint information that successfully matches.

12. The load-store unit according to claim 11, wherein: the prediction circuit being configured to determine that the fingerprint information of the load data address is consistent with the fingerprint information in the first entry or the second entry, if the fingerprint information of the load data address is the same as the fingerprint information in the first entry or the second entry, and the address range corresponding to the bits set to the specified value in the entries with the same fingerprint information includes the address portion of the load data address that is lower than the cache line granularity; The prediction circuit is configured to determine that the fingerprint information of the address of the second data is consistent with the fingerprint information in the fifth entry or the sixth entry, when the fingerprint information of the address of the second data is the same as the fingerprint information in the fifth entry or the sixth entry, and an address range corresponding to bits set to a specified value in the entries with the same fingerprint information includes an address portion of the address of the second data that is lower than the cache line granularity.

13. The load-store unit according to claim 12, wherein: The prediction circuit is configured to, when the fingerprint information of the address of the second data is consistent with the fingerprint information in the fifth entry or the sixth entry, set the bits corresponding to the address portion of the address of the second data below the cache line granularity in the bitmap field of the entry where the consistent fingerprint information is located to a second value.

14. The load-store unit according to claim 1 or 2, characterized in that: The prediction circuit is used to calculate multiple positions of the load data address in the target array based on the Bloom filter algorithm, and when the values of the multiple positions of the load data address in the target array are all specified values, determine and predict that the data corresponding to the load instruction exists in the storage queue or the storage buffer.

15. The load-store unit according to claim 14, wherein: The prediction circuit is further configured to, in response to third data being written into the storage queue, calculate the addresses of the third data at multiple locations in the target array through the Bloom filter algorithm, and set the values of the addresses of the third data at multiple locations in the target array to the specified values.

16. The load-store unit according to claim 1 or 2, characterized in that: The load-store unit further includes: a load-reservation station and a data merging circuit; The load reservation station is connected to the address calculation circuit, the store queue, the store buffer and the data cache are respectively connected to the data merging circuit, and the data merging circuit is also connected to the load reservation station; The load reservation station is used to send the load instruction to the address calculation circuit; The storage queue and the storage buffer are configured to send the queried data to the data merging circuit when the prediction circuit predicts that the data corresponding to the load instruction exists in the storage queue or the storage buffer; The data merging circuit is used to merge the data sent by the storage queue and the storage buffer, perform an exception detection on the merged data, and send an exception instruction to the load reservation station when a data exception is detected; The load reservation station is used to resend the load instruction to the address calculation circuit; The prediction circuit is used to trigger a query in the data cache for data corresponding to the load instruction based on the reissued load instruction.

17. A method for processing an instruction, characterized in that: The method is performed by the load-store unit according to any one of claims 1 to 16, and the method includes: Calculating the load data address corresponding to the load instruction by the address calculation circuit, and sending the load data address to the prediction circuit; Predicting, by the prediction circuit, whether the data corresponding to the load instruction exists in the storage queue or the storage buffer based on the load data address; When the prediction circuit predicts that the data corresponding to the load instruction exists in the storage queue or the storage buffer, a query is triggered in the storage queue and the storage buffer for the data corresponding to the load instruction.

18. A processor, characterized in that: The processor comprises at least one load-store unit according to any one of claims 1 to 16.

19. A computer device, characterized in that: The computer device comprises at least one processor, and the processor comprises at least one load-store unit according to any one of claims 1 to 16.

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