Solid-state imaging device and electronic apparatus

Abstract

[PROBLEM] To provide an image sensor that is resilient to fluctuations in threshold voltage and that exhibits little variation in ranging. [SOLUTION] A solid-state imaging device includes a pixel comprising: a light-receiving element; one or a plurality of accumulation units; and a plurality of transfer gates. The one or plurality of accumulation units accumulate signals output by the light-receiving element. At a prescribed timing, the plurality of transfer gates transfer the signals output by the light-receiving element to the accumulation unit. In addition, the plurality of transfer gates are configured so that at least two of the transfer gates are used for transfer to the respective accumulation units, and if there are a plurality of accumulation units, at least one of the transfer gates is used for transfer to the plurality of accumulation units.

Description

Solid-state imaging device and electronic device

[0001] The present disclosure relates to a solid-state imaging device and an electronic device.

[0002] In image sensors, including time-of-flight (ToF) sensors, signals converted from received light are accumulated and transferred to a storage region, such as a floating diffusion layer, via a transfer gate at a predetermined timing. Generally, one transfer gate is provided for each storage region. However, in this configuration, performance differences due to individual differences in the threshold voltage of each transfer gate can affect the processing of image signals and ranging signals. To avoid this, a single transfer gate may be configured with multiple gate electrodes of the transistors that form the transfer gate. However, this configuration has the drawback of being inefficient in terms of area and difficult to miniaturize.

[0003] Patent Publication No. 2021-097214

[0004] Therefore, one non-limiting problem to be solved by the embodiments of the present disclosure is to provide an image sensor that is tolerant to variations in threshold voltage or has small variations in distance measurement. The problem to be solved by the embodiments of the present disclosure can also be, as some further non-limiting examples, a problem corresponding to the effects described in the embodiments. In other words, a problem corresponding to at least one of the effects described in the description of the embodiments of the present disclosure can be the problem to be solved by the present disclosure.

[0005] According to one embodiment, a solid-state imaging device has a pixel including a light-receiving element, one or more storage units, and multiple transfer gates. The one or more storage units store signals output by the light-receiving element. The multiple transfer gates transfer the signals output by the light-receiving element to the storage units at predetermined timing. Furthermore, at least two of the multiple transfer gates are used for transfer to each of the storage units, and when there are multiple storage units, at least one of the transfer gates is used for transfer to multiple of the storage units.

[0006] At least one of the plurality of storage portions may be a charge storage region.

[0007] At least one of the plurality of reservoirs may be a floating diffusion region.

[0008] The transfer gate may be formed by at least one vertical transistor.

[0009] At least two of the plurality of transfer gates may be turned on at the same timing.

[0010] The pixels may form an indirect Times of Flight (iToF) sensor.

[0011] At least one overflow drain may be provided.

[0012] At least one of the plurality of transfer gates may be an overflow gate that transfers a signal to the overflow drain.

[0013] The plurality of transfer gates may be arranged so that two transfer gates corresponding to each of the plurality of storage sections are arranged in line symmetry.

[0014] The plurality of transfer gates may be arranged at positions that form a polygon, and the plurality of storage sections may be arranged outside the plurality of transfer gates at positions where transfer of signals to each of the storage sections is controlled by two of the transfer gates.

[0015] The plurality of transfer gates may be turned on in a predetermined order.

[0016] The plurality of transfer gates may be turned on in a clockwise or counterclockwise order, with adjacent transfer gates being turned on at the same timing.

[0017] The plurality of transfer gates may be arranged such that the transfer gates located on the left and right of the pixel are alternately turned on.

[0018] The multiple transfer gates may share a driver.

[0019] The device may further include one or more photogates composed of electrodes in the region on the light receiving element side, which is the source of the signal transfer, and when at least two of the multiple transfer gates are turned on, the photogates corresponding to those two transfer gates are turned on, and a voltage is applied to assist the two transfer gates in transferring the signal.

[0020] The region on the storage section side, to which the signal is transferred, may further include one or more lateral gates composed of electrodes, and when at least two of the plurality of transfer gates are turned on, the lateral gates corresponding to those two transfer gates may be turned on, and a voltage may be applied to assist the transfer of signals by those two transfer gates.

[0021] According to one embodiment, an electronic device includes an imaging unit having a light-receiving element, one or more storage units, and multiple transfer gates. The one or more storage units store signals output by the light-receiving element. The multiple transfer gates transfer the signals output by the light-receiving element to the storage units at predetermined timing. Furthermore, at least two of the multiple transfer gates are used for transfer to each of the storage units, and when multiple storage units are provided, at least one of the transfer gates is used for transfer to multiple of the storage units.

[0022] 6 is a diagram schematically illustrating a solid-state imaging device according to an embodiment. FIG. 6 is a diagram schematically illustrating a solid-state imaging device according to an embodiment. FIG. 6 shows an example of a pixel circuit according to an embodiment. FIG. 6 is a diagram schematically illustrating an example of a transfer gate according to an embodiment. FIG. 6 is a perspective view schematically illustrating an example of a transfer gate according to an embodiment. FIG. 6 is a diagram schematically illustrating an example of a transfer gate according to an embodiment. FIG. 6 is a diagram schematically illustrating an example of a transfer gate according to an embodiment. FIG. 6 is a diagram schematically illustrating an example of a transfer gate according to an embodiment. FIG. 6 is a diagram schematically illustrating an example of a transfer gate according to an embodiment. FIG. 6 is a diagram schematically illustrating an example of a cross section along AA in FIG. 6. FIG. 6 is a diagram schematically illustrating an example of a cross section along BB in FIG. 6. FIG. 6 is a diagram showing an example of a cross section along AA in FIG. 6. FIG. 6 is a diagram schematically illustrating an example of a cross section along BB in FIG. 6. FIG. 6 shows an example of a timing chart for the configuration of FIG. 6. FIG. 6 is a diagram schematically illustrating an example of an arrangement of transfer gates according to an embodiment. FIG. 6 is a diagram schematically illustrating an example of an arrangement of transfer gates according to an embodiment. FIG. 6 is a diagram schematically illustrating an example of an arrangement of transfer gates according to an embodiment. FIG. 1 is a diagram schematically showing an example of an arrangement of transfer gates according to an embodiment. FIG. 1 is a diagram schematically showing an example of an arrangement of transfer gates according to an embodiment. FIG. 2 is a diagram schematically showing an example of an arrangement of transfer gates according to an embodiment. FIG. 3 is a diagram schematically showing an example of an arrangement of transfer gates according to an embodiment. FIG. 4 is a diagram schematically showing an example of an arrangement of transfer gates according to an embodiment. FIG. 5 is a diagram schematically showing an example of an arrangement of transfer gates according to an embodiment. FIG. 6 is a diagram showing an example of a timing chart of transfer gates according to an embodiment. FIG. 7 is a diagram showing an example of a timing chart of transfer gates according to an embodiment. FIG. 8 is a diagram showing an example of a timing chart of transfer gates according to an embodiment. FIG. 9 is a diagram showing an example of a connection of drivers of transfer gates according to an embodiment. FIG. 10 is a diagram showing an example of a connection of drivers of transfer gates according to an embodiment. FIG. 11 is a block diagram showing an example of a schematic configuration of a vehicle control system. FIG. 12 is an explanatory diagram showing an example of installation positions of an outside vehicle information detection unit and an imaging unit.

[0023] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. The drawings are used for explanation purposes, and the shape, size, and size ratio of each component in an actual device do not necessarily have to be the same as those shown in the drawings. Furthermore, since the drawings are simplified, components necessary for implementation other than those shown in the drawings are also assumed to be appropriately provided.

[0024] The present disclosure will be described in the following order: 1. Configuration example of a solid-state imaging device 2. Configuration example of a pixel 3. First embodiment (Example of transfer gate formation) 4. Second embodiment (Example of transfer gate layout and operation) 5. Third embodiment (Example of memory region layout) 6. Fourth embodiment (Example of transfer gate structure) 7. Fifth embodiment (Example of on-timing) 8. Sixth embodiment (Example of storage section and transfer gate layout) 9. Seventh embodiment (Example of storage section and transfer gate layout) 10. Eighth embodiment (Example of storage section and transfer gate layout) 11. Ninth embodiment (Example of storage section and transfer gate layout) 12. Tenth embodiment (Example of storage section and transfer gate layout) 13. Eleventh embodiment (Example of transfer gate on-timing) 14. Twelfth embodiment (Example of driver) 15. Thirteenth embodiment (Application example)

[0025] <1. Solid-state imaging device>

[0026] 1 is a diagram illustrating an example of a solid-state imaging device according to an embodiment. The solid-state imaging device 1 includes, for example, a solid-state imaging element 10, a control unit 16, a storage unit 17, an interface 18, and an optical system 19. The solid-state imaging device 1 includes pixels capable of acquiring at least one piece of information from various types of information related to light. As a non-limiting example, the solid-state imaging device 1 may include a light-receiving pixel that acquires light information related to ToF, but this does not exclude the inclusion of other light-receiving pixels.

[0027] The solid-state imaging device 10 is an element that outputs signals from pixels based on light acquired from the outside via an optical system 19. The signals output from the solid-state imaging device 10 are output to a memory unit 17 or an interface 18.

[0028] The control unit 16 is a circuit that controls the solid-state imaging device 1. The control unit 16 controls the solid-state imaging element 10, for example, based on a command received from the outside via the interface 18 or based on a signal received from the solid-state imaging element 10. This control may be, for example, control to select the type of signal to be output from the pixel.

[0029] The memory unit 17 includes a memory, storage, etc. that temporarily or non-temporarily stores signals acquired by the solid-state imaging device 1. The information stored in the memory unit 17 may be appropriately output to the outside via the interface 18. In addition, commands, information, etc. from the outside may be temporarily or non-temporarily stored in the memory unit 17.

[0030] When at least part of the processing in at least one of the solid-state imaging element 10 or the control unit 16 is realized by software information processing using hardware resources, programs, executable files, etc. for this information processing may be stored in the memory unit 17.

[0031] The interface 18 is an interface for connecting the inside of the solid-state imaging device 1 with an external device 2. The interface 18 may also have a display for displaying images and presenting data to the user, buttons for receiving commands from the user, a touch panel, or other user interfaces for exchanging information with the user.

[0032] The optical system 19 is an optical system that allows the solid-state imaging device 10 to appropriately acquire information on light, such as light reflected from or transmitted through a subject, etc. The optical system 19 may include, for example, one or more lenses, an aperture, and / or a shutter.

[0033] The external device 2 is a device provided outside the solid-state imaging device 1. Processing in the solid-state imaging device 1 can be implemented using some of the functions of the external device 2. In this case, in a broad sense, the configuration that executes the some of the functions of the external device 2 may be considered to be part of the solid-state imaging device 1. The external device 2 may include, for example, a processor for executing an application, and in this case, the processor for executing this application may be considered to be part of the solid-state imaging device 1.

[0034] In addition to these, when performing distance measurement using ToF, the solid-state imaging device 1 may also be provided with necessary components such as an irradiation unit, etc. This irradiation unit, etc., can also be controlled by the control unit 16. Furthermore, without being limited to these, the solid-state imaging device 1 may also be provided with necessary components for performing the functions of the solid-state imaging device 1.

[0035] 2 is a block diagram showing an example of a schematic configuration of a solid-state imaging device 10 according to an embodiment. The solid-state imaging device 10 includes a pixel array 100, a control circuit 102, a line driving circuit 104, a column driving circuit 106, and a signal processing circuit 108. The solid-state imaging device 10 may be, for example, an image sensor that appropriately processes signals output from pixels and outputs the processed signals.

[0036] The pixel array 100 is an area in which light-receiving pixels are arranged in a two-dimensional array. For example, the pixel array 100 has a plurality of pixels arranged in a two-dimensional array along a first direction and a second direction intersecting the first direction. Here, the first direction may be a line direction, and the second direction may be a column direction, but is not limited thereto.

[0037] The control circuit 102 is a circuit that receives signals from the control unit 16, for example, so that appropriate information is output from the pixel array 100, and controls each component within the solid-state imaging device 10. In the following description, each component may perform various processes, which may be controlled by the control circuit 102.

[0038] The line driver circuit 104 is a circuit that selects a line in the pixel array 100 and drives the pixels that belong to that line to output signals. In addition, when a pixel operates as an event detection pixel that performs event detection, the line driver circuit 104 may also function as an arbiter.

[0039] The column driving circuit 106 is a circuit that selects a column from among the pixels belonging to the line selected by the line driving circuit 104, and drives the pixels belonging to the selected column to realize output from the pixels. The column driving circuit 106 may also be a circuit that also functions as an arbiter, like the line driving circuit 104.

[0040] The signal processing circuit 108 is a circuit that performs signal processing on and outputs signals output from each pixel of the pixel array 100. The signal processing circuit 108 may include, for example, an ADC (Analog to Digital Converter) that converts analog signals output from the pixel array 100 into digital signals.

[0041] The signal processing circuit 108 may process this digital signal to generate an image signal. The signal processing circuit 108 may also perform various processes on this digital signal using a model trained by machine learning, such as algorithms for object detection and object recognition. The signal processing circuit 108 can output the processed signal inside the solid-state imaging device 10 or to the outside via the interface 18.

[0042] Although not shown, a temporary or non-temporary storage area may be provided inside the solid-state imaging device 10. The storage area may be used for the same purpose as the storage unit 17 described above, or may function as various buffers or the like for temporarily storing signals processed by the signal processing circuit 108.

[0043] <2. Example of pixel configuration>

[0044] Next, the pixel circuit will be described. As described above, pixels each having a light receiving element are arranged in a two-dimensional array in the pixel array 100. The pixels are formed by pixel circuits.

[0045] 3 is a diagram illustrating an example of a pixel circuit according to an embodiment. The pixel 110 includes a light-receiving element P, a memory region MEM, a floating diffusion region FD, an overflow drain OFD, a transfer gate M1, a transfer gate M2, a reset transistor RS, and an amplifier transistor AMP.

[0046] The light receiving element P may be any type of light receiving element, such as a photodiode, and may be an element for receiving light in ToF, particularly iToF, or an element for acquiring general image information such as RGB format. The light receiving element P is not limited to these, and may also be an element for acquiring other information. For example, the light receiving element P has an anode connected to a power supply voltage Vss via a power line, and outputs a signal based on the intensity of light received from the cathode.

[0047] The memory region MEM is a charge storage region that accumulates carriers based on the signal output from the light-receiving element P, and may include, for example, a capacitor. The signal output from the light-receiving element P is transferred to the memory region MEM at an appropriate timing via a transfer gate M1. Note that a capacitor does not necessarily have to be included.

[0048] The transfer gate M1 is a transistor for transferring the signal output from the light-receiving element P to the memory region MEM, and is formed, for example, from an n-type MOSFET, with its drain connected to the cathode of the light-receiving element P and its source connected to the memory region MEM. The transfer gate M1 transfers the signal output to the cathode of the light-receiving element P to the memory region MEM based on the voltage applied to its gate.

[0049] The floating diffusion region FD is a region that accumulates carriers based on a transferred signal, and based on the signal related to the carriers accumulated in this floating diffusion region FD, the amplification transistor AMP appropriately amplified the signal Sig and output it to the signal line VSL from the pixel 110. A capacitor may be connected to the floating diffusion region FD if necessary, but this is not a required configuration.

[0050] The transfer gate M2 is a transistor that transfers a signal from the memory region MEM to the floating diffusion region FD at the appropriate timing, and is formed, for example, by an n-type MOSFET, with its drain connected to the memory region MEM and its source connected to the floating diffusion region FD. The transfer gate M2 transfers the signal held in the memory region MEM to the floating diffusion region FD based on the voltage applied to its gate.

[0051] The overflow drain OFD is an area formed by the transfer gate M3, which is an overflow transistor (overflow gate) that transfers the overflowed signal to the power supply voltage Vdd via the signal line when the output of the light-receiving element P overflows.

[0052] The reset transistor RS is a transistor that turns on at the initialization timing and resets the potential of the floating diffusion region FD. By turning on the reset transistor RS, the potential of the floating diffusion region FD (including the potential due to the capacitor) can be properly initialized.

[0053] The amplifier transistor AMP is a transistor that passes a signal based on the potential of the floating diffusion region FD, that is, the signal transferred from the light receiving element P, to the signal line VSL.

[0054] The pixel 110 may have the above configuration as a non-limiting example. However, the pixel 110 is not limited to this configuration. For example, the pixel 110 may not have an overflow drain OFD and / or may not have a memory region MEM. Furthermore, not all of the elements are essential components, and elements may be omitted or added as appropriate.

[0055] 3 is given as a non-limiting example, and does not exclude configurations including more gates (transistors), capacitors, etc., or configurations in which one or more elements are omitted from the embodiments of the present disclosure. Various circuit elements, such as transistors and capacitors, can be added or deleted within the scope of the embodiments of the present disclosure without causing any contradiction.

[0056] The embodiments of the present disclosure are not limited to these configurations, but relate to configurations of gate electrodes of transfer transistors and transistors that achieve similar operations. In the embodiments of the present disclosure, the term "accumulator" refers to any of the floating diffusion region FD, the memory region MEM, and the overflow drain OFD.

[0057] 3. First embodiment

[0058] FIG. 4 is a plan view schematically showing a transfer transistor in a pixel according to an embodiment, illustrating, as an example, a case where a signal is transferred from the cathode of a light-receiving element P to a floating diffusion region FD.

[0059] As described above, the transfer from the cathode of the light-receiving element P to the floating diffusion region FD, which is an example of an accumulation section, is realized by using, for example, a virtually formed transfer gate TG. The transfer gate TG operates as a transistor that propagates a signal through a channel formed between two gate electrodes VG1 and VG2.

[0060] By applying an on-voltage to both gate electrodes VG1 and VG2 at the appropriate timing, a channel is formed between these electrodes, and a signal is transferred from the cathode of the light-receiving element P to the floating diffusion region FD.

[0061] Thus, two transfer gates VG1 and VG2 are used for transfer to the storage region (e.g., floating diffusion region FD) in pixel 110. As will be described later, if there are multiple storage regions, a single transfer gate may be used to form channels of transfer transistors for multiple storage regions.

[0062] Fig. 5 is a perspective view showing the transfer gate and the floating diffusion region FD serving as the storage section in Fig. 4. As shown in this figure, the gate electrode VG1 and the gate electrode VG2 can be formed as vertical gates.

[0063] By applying an on-voltage to gate electrodes VG1 and VG2, a channel of the transfer gate TG can be formed between gate electrodes VG1 and VG2, forming a carrier path from the front left side of the drawing to the back right side (the floating diffusion region FD side). In other words, by turning on gate electrodes VG1 and VG2 at the same time, a channel is formed and the transfer gate TG becomes conductive.

[0064] When the gate electrodes VG1 and VG2 are turned on, the potential between these gate electrodes becomes higher than that in other regions, allowing charges to flow between these gate electrodes.

[0065] In this state, even if, for example, charges existing outside the channel region of gate electrode VG2 are stuck to gate electrode VG2, charges will flow between these gate electrodes during transfer because gate electrodes VG1 and VG2 have a certain depth.

[0066] Furthermore, when gate electrode VG1 is turned off and gate electrode VG2 is turned on, the charges around gate electrode VG1 are collected around gate electrode VG2. As a result, when the gate electrode located on the opposite side of gate electrode VG1 is turned on in this state, a channel is formed between gate electrode VG2 and the gate electrode on the opposite side, and charges move along this channel, resulting in a state in which no charges move to the floating diffusion region FD shown in the diagram.

[0067] As described above, according to the gate electrode configuration of this embodiment, a transistor can be formed using two gate electrodes for an accumulation region (for example, a floating diffusion region FD). With this configuration, the threshold voltage can be defined for each electrode, and a channel is formed by the threshold voltages of multiple electrodes, so the threshold voltages are averaged, and the variation in threshold voltage can be reduced compared to when a single transistor is used.

[0068] Although the gate electrode is of the trench type, a planar type gate electrode can also provide the same effect on the surface side of the substrate.

[0069] 4. Second embodiment

[0070] In the following embodiments, various configurations of the gate electrode structure shown in the first embodiment will be described. First, in this embodiment, the relationship between the storage region and the gate electrode will be described. In the following description, an element constituting a transistor having a gate electrode will be referred to as a transfer gate. Furthermore, when a transfer gate is turned on, it means that an on-voltage is applied to the transfer gate.

[0071] 6 is a plan view showing an example of a transfer gate according to one embodiment. A floating diffusion region FD and an overflow drain OFD are provided as an accumulation region, and transfer gates TG1, TG2, and TG3 control the movement of carriers from the lower right side of the drawing to this accumulation region.

[0072] When the transfer gates TG1 and TG2 are turned on at the same time, a channel is formed between the transfer gates TG1 and TG2, allowing carriers to move to the floating diffusion region FD.

[0073] From this state, by turning off transfer gate TG1 and turning on transfer gate TG3, a channel is formed between transfer gate TG2 and transfer gate TG3, allowing carriers to move to the overflow drain OFD.

[0074] 6, there is no memory region MEM, but the transfer gates TG1 and TG2 form the transfer gate M2, and the transfer gates TG2 and TG3 form the transfer gate M3. In this way, a plurality of transfer gates can be used to form transfer transistors that move carriers to the respective regions.

[0075] Also, like the operation of the transfer gate TG2, for example, one transfer gate can also operate as a gate electrode forming transfer transistors to a plurality of storage sections.

[0076] As described above, according to this embodiment, the same effects as those of the first embodiment can be achieved, and it is also possible to share a gate electrode of a transfer transistor, such as the transfer gate TG2, which connects to a plurality of storage regions. As a result, even when one transistor is configured with a plurality of vertical gate electrodes, it is possible to reduce the number of gate electrodes, improving area efficiency and increasing the degree of freedom in layout.

[0077] 5. Third embodiment

[0078] 7 is a plan view showing an example of a transfer gate according to one embodiment. The pixel may have a memory region MEM, which is a charge storage region. In this arrangement, for example, the lower right side of the drawing may be the cathode region of the light-receiving element P.

[0079] The signal output from the cathode of photodetector P is transferred to memory area MEM by turning on transfer gates TG1 and TG2 at the same appropriate timing. At the appropriate timing when the signal from the cathode of photodetector P is transferred to memory area MEM, transfer gate TG1 turns off and transfer gate TG3 turns on, moving carriers to overflow drain OFD and setting the potential of the cathode of photodetector P appropriately.

[0080] The memory region MEM may be configured to include a transfer transistor (transfer gate M2 in Figure 3) to the floating diffusion region FD, in which case a signal is transferred from the memory region MEM to the floating diffusion region FD at an appropriate timing.

[0081] In this way, the memory area MEM can be used as a storage unit to realize the same operations as those in the above-described embodiment.

[0082] 8 is a plan view schematically illustrating an example of a transfer gate according to an embodiment. In FIG. 7, the transfer gate M2 is configured to be included in the memory region MEM, but this is not limiting. The transfer gate M2 may be provided between the memory region MEM and the floating diffusion region FD. Alternatively, the transfer gate M2 may be configured such that the gate electrode is formed on the substrate surface side of the region between the memory region MEM and the floating diffusion region FD.

[0083] Even in this case, signal transfer from the cathode of the photodetector P to the memory region MEM and overflow drain OFD, which are multiple storage units, can be properly achieved by forming a transfer gate using multiple electrodes, some of which are shared by the multiple storage units.

[0084] 6. Fourth embodiment

[0085] FIG. 9 is a cross-sectional view showing an example of the AA cross section of FIG. 6. The transfer gates TG1 and TG2 have vertical (trench) gate electrodes and can be arranged so that the vertical electrodes are embedded in the substrate. Note that the channel formation region is shown as a rectangle, but this shape is not specific and exists as a region where a clear boundary does not need to be defined. The same applies below to the floating diffusion region FD and the overflow drain OFD regions.

[0086] In this configuration, when appropriate voltages are applied to the transfer gates TG1 and TG2, a channel is formed between the transfer gates TG1 and TG2. Carriers move from the front side of the drawing to the back side of the drawing through the formed channel, transferring a signal to the floating diffusion region FD.

[0087] Fig. 10 is a cross-sectional view showing a schematic example of the cross section BB in Fig. 6. For example, a channel formation region is present around the transfer gate TG2, and the floating diffusion region FD and overflow drain OFD as an accumulation section are connected via this channel formation region to the cathode side of the light receiving element P so that carriers can move when a transfer transistor formed by multiple transfer gates is turned on.

[0088] As shown in FIGS. 9 and 10, each transfer gate TG can have a vertical gate electrode, and in this case, it is possible to extend the region where the channel is formed in the depth direction.

[0089] 11 is a cross-sectional view schematically illustrating another example of the AA cross section of FIG. 6. The transfer gates TG1 and TG2 may have a structure including planar gate electrodes. In the drawing, the transfer gates TG1 and TG2 are formed so as to face the surface of the substrate, but this is not limiting, and they may be formed so that at least a portion thereof is embedded inside the surface.

[0090] In the planar type transfer gate TG1 and transfer gate TG2, a channel formation region exists near the surface of the substrate, and when an on-voltage is applied to both gate electrodes, carriers can move from the front side of the drawing to the back side of the drawing through this channel formation region.

[0091] 12 is a cross-sectional view schematically showing an example of the cross section BB of FIG. 6 in the case of FIG. 11. A channel formation region is located directly below the transfer gate TG2. When only the transfer gate TG2 is turned on, a channel is not formed in the entire channel formation region. For example, when the transfer gate TG1 is turned on at the same time, the region on the right side of the channel formation region as viewed in the drawing is activated as a channel, and when the transfer gate TG3 is turned on at the same time, the region on the left side of the channel formation region as viewed in the drawing is activated as a channel.

[0092] In this way, as described above, by appropriately forming a channel with multiple gate electrodes, a channel is formed by multiple gate electrodes among multiple storage sections, and carriers can be made to be able to move to the storage section connected via the channel.

[0093] 10 and 12, note that one transfer gate is shared to control transfer to multiple reservoirs.

[0094] 7. Fifth embodiment

[0095] 13 is a timing chart showing an example of the configurations of the second to fourth embodiments, showing the timing at which voltages (on / off voltages) are applied to the gate electrodes of the transfer gates TG1, TG2, and TG3, in that order from the top.

[0096] First, the transfer gates TG1, TG2, and TG3 are turned off at the timing of light reception in the light receiving element P. In this off state, a signal generated by photoelectric conversion in the light receiving element P is accumulated on the cathode side.

[0097] After the light-receiving period is completed, the transfer gates TG1 and TG2 are turned on. By turning on the transfer gates TG1 and TG2, a channel is formed that connects the cathode of the light-receiving element P and the floating diffusion region FD, and the signal is transferred through this channel.

[0098] After the transfer period is completed, transfer gate TG1 is turned off, and while transfer gate TG2 remains on, transfer gate TG3 is turned on. The timing at which transfer gate TG3 is turned on can be set so that it does not overlap with the timing at which transfer gate TG1 is turned on. When transfer gates TG2 and TG3 are turned on, a channel is formed that connects the cathode of light-receiving element P and overflow drain OFD, and a signal is transferred through this channel. This accumulation period can also be used as a readout period for the signal transferred to floating diffusion region FD.

[0099] In this way, by turning on two or more transfer gates TG at the same time, a channel is formed between the appropriate storage section and the gate, and the signal is transferred appropriately.

[0100] 8. Sixth Embodiment

[0101] Although the above describes an example of operation, in this embodiment, some non-limiting examples of the arrangement of the storage section and the transfer gate are given. Note that the shape of the storage section does not have to be rectangular, and may be any shape.

[0102] The transfer gate may be arranged to have trench or planar gate electrodes at the vertices of a polygon, particularly a regular polygon, and the trench may have a cylindrical shape as described above, or any other shape.

[0103] A signal output from the light receiving element may be accumulated in the center of the polygon. Each of the plurality of accumulation units is disposed outside the plurality of transfer gates at a position where transfer to each region is controlled by two transfer gates.

[0104] In the drawings, polygonal shapes may be shown by dashed lines, but these are intended to indicate the positions of transfer gates, and do not actually represent any particular object.

[0105] 14 is a diagram schematically illustrating an example of an arrangement of transfer gates according to an embodiment. Transfer gates TG1, TG2, and TG3 may be arranged at the vertices of an equilateral triangle, for example.

[0106] The floating diffusion region FD1 is located at the end of the path between the transfer gate TG1 and the transfer gate TG2, passing through the center.

[0107] The floating diffusion region FD2 is located at the end of the path between the transfer gate TG2 and the transfer gate TG3, passing through the center.

[0108] The overflow drain OFD is placed at the end of the path between the transfer gate TG3 and the transfer gate TG1, passing through the center.

[0109] Transfer gate TG1 and transfer gate TG2 are gates that control the transfer to the floating diffusion region FD1.

[0110] Transfer gate TG2 and transfer gate TG3 are gates that control the transfer to the floating diffusion region FD2.

[0111] Transfer gate TG3 and transfer gate TG1 are gates that control the transfer to the overflow drain OFD.

[0112] When a signal is transferred to each storage unit, the gates in the above combination are turned on. When two gates are turned on, a channel is formed between the two gates, and the signal is transferred to the corresponding storage unit.

[0113] 15 is a diagram schematically illustrating an example of an arrangement of transfer gates according to an embodiment. Transfer gates TG1, TG2, TG3, and TG4 may be arranged at the vertices of a square.

[0114] The floating diffusion region FD1 is located at the end of the path between the transfer gate TG1 and the transfer gate TG2, passing through the center.

[0115] The floating diffusion region FD2 is located at the end of the path between the transfer gate TG3 and the transfer gate TG4, passing through the center.

[0116] The overflow drain OFD1 is placed at the end of the path between the transfer gate TG4 and the transfer gate TG1, passing through the center.

[0117] The overflow drain OFD2 is placed at the end of the path between the transfer gate TG2 and the transfer gate TG3, passing through the center.

[0118] Transfer gate TG1 and transfer gate TG2 are gates that control the transfer to the floating diffusion region FD1.

[0119] Transfer gate TG2 and transfer gate TG3 are gates that control the transfer to the overflow drain OFD2.

[0120] Transfer gate TG3 and transfer gate TG4 are gates that control the transfer to the floating diffusion region FD2.

[0121] Transfer gate TG4 and transfer gate TG1 are gates that control the transfer to the overflow drain OFD1.

[0122] When a signal is transferred to each storage unit, the gates in the above combination are turned on. When two gates are turned on, a channel is formed between the two gates, and the signal is transferred to the corresponding storage unit.

[0123] 16 is a diagram schematically illustrating an example of an arrangement of transfer gates according to an embodiment. Transfer gates TG1, TG2, TG3, TG4, and TG5 may be arranged at the vertices of a regular pentagon.

[0124] The floating diffusion region FD1 is located at the end of the path between the transfer gate TG1 and the transfer gate TG2, passing through the center.

[0125] The floating diffusion region FD2 is located at the end of the path between the transfer gate TG2 and the transfer gate TG3, passing through the center.

[0126] The floating diffusion region FD3 is disposed at the end of the path between the transfer gate TG4 and the transfer gate TG5, passing through the center.

[0127] The floating diffusion region FD4 is located at the end of the path between the transfer gate TG5 and the transfer gate TG1, passing through the center.

[0128] The overflow drain OFD is placed at the end of the path between the transfer gate TG3 and the transfer gate TG4, passing through the center.

[0129] Transfer gate TG1 and transfer gate TG2 are gates that control the transfer to the floating diffusion region FD1.

[0130] Transfer gate TG2 and transfer gate TG3 are gates that control the transfer to the floating diffusion region FD2.

[0131] Transfer gates TG3 and TG4 are gates that control the transfer to the overflow drain OFD.

[0132] Transfer gate TG4 and transfer gate TG5 are gates that control transfer to floating diffusion region FD3.

[0133] Transfer gate TG5 and transfer gate TG1 are gates that control transfer to floating diffusion region FD4.

[0134] When a signal is transferred to each storage unit, the gates in the above combination are turned on. When two gates are turned on, a channel is formed between the two gates, and the signal is transferred to the corresponding storage unit.

[0135] 17 is a diagram schematically illustrating an example of an arrangement of transfer gates according to an embodiment. Transfer gates TG1, TG2, TG3, TG4, TG5, and TG6 may be arranged at the vertices of a regular hexagon.

[0136] The floating diffusion region FD1 is located at the end of the path between the transfer gate TG1 and the transfer gate TG2, passing through the center.

[0137] The floating diffusion region FD2 is located at the end of the path between the transfer gate TG2 and the transfer gate TG3, passing through the center.

[0138] The floating diffusion region FD3 is disposed at the end of the path between the transfer gate TG4 and the transfer gate TG5, passing through the center.

[0139] The floating diffusion region FD4 is disposed at the end of the path between the transfer gate TG5 and the transfer gate TG6, passing through the center.

[0140] The overflow drain OFD1 is placed at the end of the path between the transfer gate TG6 and the transfer gate TG1, passing through the center.

[0141] The overflow drain OFD2 is placed at the end of the path between the transfer gate TG3 and the transfer gate TG4, passing through the center.

[0142] Transfer gate TG1 and transfer gate TG2 are gates that control the transfer to the floating diffusion region FD1.

[0143] Transfer gate TG2 and transfer gate TG3 are gates that control the transfer to the floating diffusion region FD2.

[0144] Transfer gate TG3 and transfer gate TG4 are gates that control the transfer to the overflow drain OFD2.

[0145] Transfer gate TG4 and transfer gate TG5 are gates that control transfer to floating diffusion region FD3.

[0146] Transfer gate TG5 and transfer gate TG6 are gates that control transfer to floating diffusion region FD4.

[0147] Transfer gate TG6 and transfer gate TG1 are gates that control the transfer to the overflow drain OFD1.

[0148] When a signal is transferred to each storage unit, the gates in the above combination are turned on. When two gates are turned on, a channel is formed between the two gates, and the signal is transferred to the corresponding storage unit.

[0149] 18 is a diagram schematically illustrating an example of an arrangement of transfer gates according to an embodiment. Transfer gates TG1, TG2, TG3, TG4, TG5, TG6, TG7, and TG8 may be arranged at the vertices of a regular octagon.

[0150] The floating diffusion region FD1 is located at the end of the path between the transfer gate TG1 and the transfer gate TG2, passing through the center.

[0151] The floating diffusion region FD2 is located at the end of the path between the transfer gate TG3 and the transfer gate TG4, passing through the center.

[0152] The floating diffusion region FD3 is disposed at the end of the path between the transfer gate TG5 and the transfer gate TG6, passing through the center.

[0153] The floating diffusion region FD4 is located at the end of the path between the transfer gate TG7 and the transfer gate TG8, passing through the center.

[0154] The overflow drain OFD1 is placed at the end of the path between the transfer gate TG8 and the transfer gate TG1, passing through the center.

[0155] The overflow drain OFD2 is placed at the end of the path between the transfer gate TG2 and the transfer gate TG3, passing through the center.

[0156] The overflow drain OFD3 is placed at the end of the path between the transfer gate TG4 and the transfer gate TG5, passing through the center.

[0157] The overflow drain OFD4 is placed at the end of the path between the transfer gate TG6 and the transfer gate TG7, passing through the center.

[0158] Transfer gate TG1 and transfer gate TG2 are gates that control the transfer to the floating diffusion region FD1.

[0159] Transfer gate TG2 and transfer gate TG3 are gates that control the transfer to the overflow drain OFD2.

[0160] Transfer gate TG3 and transfer gate TG4 are gates that control the transfer to the floating diffusion region FD2.

[0161] Transfer gate TG4 and transfer gate TG5 are gates that control the transfer to the overflow drain OFD3.

[0162] Transfer gate TG5 and transfer gate TG6 are gates that control transfer to floating diffusion region FD3.

[0163] Transfer gates TG6 and TG7 are gates that control the transfer to the overflow drain OFD4.

[0164] Transfer gate TG7 and transfer gate TG8 are gates that control transfer to floating diffusion region FD4.

[0165] Transfer gate TG8 and transfer gate TG1 are gates that control the transfer to the overflow drain OFD1.

[0166] When a signal is transferred to each storage unit, the gates in the above combination are turned on. When two gates are turned on, a channel is formed between the two gates, and the signal is transferred to the corresponding storage unit.

[0167] As described above, according to the arrangement of the transfer gates TG of this embodiment, the transfer of signals to each accumulation region (overflow drain OFD, floating diffusion region FD) is controlled by two gates, and each gate controls the transfer of signals to two accumulation regions. With this arrangement, transfer to the accumulation regions is controlled by two gates, and the arrangement of the minimum number of gates can be realized.

[0168] Therefore, according to the non-limiting example arrangement of this embodiment, it is possible to minimize the number of gate electrodes while achieving accurate transfer to the storage section, thereby improving area efficiency and layout freedom.

[0169] 9. Seventh Embodiment

[0170] The positional relationship between the gate electrode and the storage region has been described above. In this embodiment, more specific, non-limiting examples of the shape of the gate electrode and the arrangement of the storage region will be given.

[0171] 19 is a diagram schematically illustrating an example of the arrangement of transfer gates according to an embodiment. Transfer gates TG1, TG2, TG3, TG4, TG5, and TG6 may be arranged at the vertices of a regular hexagon. Furthermore, the shape of the gate voltage application portion (contact) of each of these transfer gates may also be a regular hexagon.

[0172] The floating diffusion region FD1 is located at the end of the path between the transfer gate TG1 and the transfer gate TG2, passing through the center.

[0173] The floating diffusion region FD2 is located at the end of the path between the transfer gate TG2 and the transfer gate TG3, passing through the center.

[0174] The floating diffusion region FD3 is disposed at the end of the path between the transfer gate TG4 and the transfer gate TG5, passing through the center.

[0175] The floating diffusion region FD4 is disposed at the end of the path between the transfer gate TG5 and the transfer gate TG6, passing through the center.

[0176] The overflow drain OFD1 is placed at the end of the path between the transfer gate TG6 and the transfer gate TG1, passing through the center.

[0177] The overflow drain OFD2 is placed at the end of the path between the transfer gate TG3 and the transfer gate TG4, passing through the center.

[0178] Transfer gate TG1 and transfer gate TG2 are gates that control the transfer to the floating diffusion region FD1.

[0179] Transfer gate TG2 and transfer gate TG3 are gates that control the transfer to the floating diffusion region FD2.

[0180] Transfer gate TG3 and transfer gate TG4 are gates that control the transfer to the overflow drain OFD2.

[0181] Transfer gate TG4 and transfer gate TG5 are gates that control transfer to floating diffusion region FD3.

[0182] Transfer gate TG5 and transfer gate TG6 are gates that control transfer to floating diffusion region FD4.

[0183] Transfer gate TG6 and transfer gate TG1 are gates that control the transfer to the overflow drain OFD1.

[0184] When a signal is transferred to each storage unit, the gates in the above combination are turned on. When two gates are turned on, a channel is formed between the two gates, and the signal is transferred to the corresponding storage unit.

[0185] In this embodiment, the gate electrodes forming the channels of the storage regions may be arranged in line-symmetrical positions and shapes with respect to the storage regions. For example, the transfer gates TG1 and TG2 may be arranged in line-symmetrical positions and shapes with respect to the floating diffusion region FD1 as the axis of symmetry.

[0186] In this embodiment, the gate electrode may be either a trench type or a planar type. In the case of a trench type, the embedded portion of the gate electrode may be, for example, cylindrical, or may be a regular hexagon that is the same as or smaller than the shape of the voltage application portion shown in the figure, as in the above-described embodiment.

[0187] 20 is a diagram schematically illustrating an example of an arrangement of transfer gates according to an embodiment. Transfer gates TG1, TG2, TG3, TG4, TG5, TG6, TG7, and TG8 may be arranged at the vertices of a regular octagon.

[0188] The floating diffusion region FD1 is located at the end of the path between the transfer gate TG1 and the transfer gate TG2, passing through the center.

[0189] The floating diffusion region FD2 is located at the end of the path between the transfer gate TG3 and the transfer gate TG4, passing through the center.

[0190] The floating diffusion region FD3 is disposed at the end of the path between the transfer gate TG5 and the transfer gate TG6, passing through the center.

[0191] The floating diffusion region FD4 is located at the end of the path between the transfer gate TG7 and the transfer gate TG8, passing through the center.

[0192] The overflow drain OFD1 is placed at the end of the path between the transfer gate TG8 and the transfer gate TG1, passing through the center.

[0193] The overflow drain OFD2 is placed at the end of the path between the transfer gate TG2 and the transfer gate TG3, passing through the center.

[0194] The overflow drain OFD3 is placed at the end of the path between the transfer gate TG4 and the transfer gate TG5, passing through the center.

[0195] The overflow drain OFD4 is placed at the end of the path between the transfer gate TG6 and the transfer gate TG7, passing through the center.

[0196] Transfer gate TG1 and transfer gate TG2 are gates that control the transfer to the floating diffusion region FD1.

[0197] Transfer gate TG2 and transfer gate TG3 are gates that control the transfer to the overflow drain OFD2.

[0198] Transfer gate TG3 and transfer gate TG4 are gates that control the transfer to the floating diffusion region FD2.

[0199] Transfer gate TG4 and transfer gate TG5 are gates that control the transfer to the overflow drain OFD3.

[0200] Transfer gate TG5 and transfer gate TG6 are gates that control transfer to floating diffusion region FD3.

[0201] Transfer gates TG6 and TG7 are gates that control the transfer to the overflow drain OFD4.

[0202] Transfer gate TG7 and transfer gate TG8 are gates that control transfer to floating diffusion region FD4.

[0203] Transfer gate TG8 and transfer gate TG1 are gates that control the transfer to the overflow drain OFD1.

[0204] When the signal is transferred to each storage unit, the gates in the above combination are turned on. When two gates are turned on, a channel is formed between the two gates, and the signal is transferred to the corresponding storage unit.

[0205] As described above, the gate electrode may be of either a trench type or a planar type. In the case of a trench type, the embedded portion of the gate electrode may be, for example, cylindrical, or may be a regular octagonal shape similar to or smaller than the shape of the voltage application portion shown in the figure.

[0206] 21 is a diagram illustrating an example of an arrangement of transfer gates according to an embodiment. Transfer gates TG1, TG2, TG3, and TG4 are arranged at the vertices of a square, and may also have a cylindrical shape.

[0207] The floating diffusion region FD1 is located at the end of the path between the transfer gate TG1 and the transfer gate TG2, passing through the center.

[0208] The floating diffusion region FD2 is located at the end of the path between the transfer gate TG3 and the transfer gate TG4, passing through the center.

[0209] The overflow drain OFD1 is placed at the end of the path between the transfer gate TG4 and the transfer gate TG1, passing through the center.

[0210] The overflow drain OFD2 is placed at the end of the path between the transfer gate TG2 and the transfer gate TG3, passing through the center.

[0211] Transfer gate TG1 and transfer gate TG2 are gates that control the transfer to the floating diffusion region FD1.

[0212] Transfer gate TG2 and transfer gate TG3 are gates that control the transfer to the overflow drain OFD2.

[0213] Transfer gate TG3 and transfer gate TG4 are gates that control the transfer to the floating diffusion region FD2.

[0214] Transfer gate TG4 and transfer gate TG1 are gates that control the transfer to the overflow drain OFD1.

[0215] When the signal is transferred to each storage unit, the gates in the above combination are turned on. When two gates are turned on, a channel is formed between the two gates, and the signal is transferred to the corresponding storage unit.

[0216] In this case, too, the gate electrodes are arranged in symmetrical positions and shapes with the corresponding storage regions as the axis of symmetry. It should be noted that not only when a square is formed, but also when the transfer gate is formed in another polygonal shape, the gate electrodes can be made cylindrical, as in Fig. 21. That is, a cylindrical gate electrode can be selected depending on the circumstances such as the circuit area, layout, and process.

[0217] As described above, the arrangement of the transfer gates and storage units according to this embodiment not only achieves the same effects as the sixth embodiment, but also ensures symmetry of the transfer gates relative to the storage units, resulting in more even transfer to each storage unit and achieving stable signal transfer.

[0218] 10. Eighth Embodiment

[0219] In the sixth and seventh embodiments described above, the arrangement of the transfer gate and the floating diffusion region and the overflow gate as the storage section was explained. In this embodiment, the arrangement of the memory region, which is the charge storage region, is taken into consideration. Note that although a hexagonal shape is used as an example and not a limitation, other shapes can also be used for implementation in the same way.

[0220] 22 is a diagram schematically illustrating an example of an arrangement of transfer gates according to an embodiment. Transfer gates TG1, TG2, TG3, TG4, TG5, and TG6 are arranged at the vertices of a regular hexagon and have voltage application portions in the shape of a regular hexagon.

[0221] The memory region MEM1 is located at the end of the path between the transfer gates TG1 and TG2. The memory region MEM1 has a configuration (e.g., a transistor) that can transfer the stored signal to the floating diffusion region FD1.

[0222] The memory region MEM2 is located at the end of the path between the transfer gates TG2 and TG3. The memory region MEM2 has a configuration (e.g., a transistor) that can transfer the stored signal to the floating diffusion region FD2.

[0223] The memory region MEM3 is located at the end of the path between the transfer gates TG4 and TG5. The memory region MEM3 has a configuration (e.g., a transistor) that can transfer the stored signal to the floating diffusion region FD3.

[0224] The memory region MEM4 is located at the end of the path between the transfer gates TG5 and TG6. The memory region MEM4 has a configuration (e.g., a transistor) that can transfer the stored signal to the floating diffusion region FD4.

[0225] The floating diffusion region FD1 is arranged so that signals can be transferred directly from the memory region MEM1.

[0226] The floating diffusion region FD2 is arranged so that signals can be transferred directly from the memory region MEM2.

[0227] The floating diffusion region FD3 is arranged so that signals can be transferred directly from the memory region MEM3.

[0228] The floating diffusion region FD4 is arranged so that signals can be transferred directly from the memory region MEM4.

[0229] The overflow drain OFD1 is placed at the end of the path between the transfer gate TG6 and the transfer gate TG1, passing through the center.

[0230] The overflow drain OFD2 is placed at the end of the path between the transfer gate TG3 and the transfer gate TG4, passing through the center.

[0231] Transfer gate TG1 and transfer gate TG2 are gates that control transfers to memory area MEM1.

[0232] Transfer gates TG2 and TG3 are gates that control transfers to memory area MEM2.

[0233] Transfer gate TG3 and transfer gate TG4 are gates that control the transfer to the overflow drain OFD2.

[0234] Transfer gates TG4 and TG5 are gates that control transfers to memory area MEM3.

[0235] Transfer gates TG5 and TG6 are gates that control transfers to memory area MEM4.

[0236] Transfer gate TG6 and transfer gate TG1 are gates that control the transfer to the overflow drain OFD1.

[0237] When a signal is transferred to each storage unit, the gates in the above combination are turned on. When two gates are turned on, a channel is formed between the two gates, and the signal is transferred to the corresponding storage unit, the memory area, and the overflow drain.

[0238] The signals transferred to each memory region MEM are transferred to the corresponding floating diffusion region FD at the appropriate timing.

[0239] 23 is a diagram showing an example of the arrangement of transfer gates according to one embodiment. Transfer gates TG1, TG2, TG3, TG4, TG5, and TG6 are arranged at the vertices of a regular hexagon and have voltage application portions in the shape of a regular hexagon.

[0240] The memory area MEM1 is located at the end of the path between the transfer gates TG1 and TG2, passing through the center.

[0241] The memory area MEM2 is located at the end of the path between the transfer gates TG2 and TG3, passing through the center.

[0242] The memory area MEM3 is located at the end of the path between the transfer gates TG4 and TG5, passing through the center.

[0243] The memory area MEM4 is located at the end of the path between the transfer gates TG5 and TG6, passing through the center.

[0244] The floating diffusion region FD1 is arranged so that signals can be transferred from the memory region MEM1.

[0245] The floating diffusion region FD2 is arranged so that signals can be transferred from the memory region MEM2.

[0246] The floating diffusion region FD3 is arranged so that signals can be transferred from the memory region MEM3.

[0247] The floating diffusion region FD4 is arranged so that signals can be transferred from the memory region MEM4.

[0248] The memory transfer gate MT1 transfers a signal stored in the memory region MEM1 to the floating diffusion region FD1. The memory transfer gate MT1 may be configured with, for example, a transistor.

[0249] The memory transfer gate MT2 transfers the signal stored in the memory region MEM2 to the floating diffusion region FD2. The memory transfer gate MT2 may be configured with, for example, a transistor.

[0250] The memory transfer gate MT3 transfers the signal stored in the memory region MEM3 to the floating diffusion region FD3. The memory transfer gate MT3 may be configured with, for example, a transistor.

[0251] The memory transfer gate MT4 transfers the signal stored in the memory region MEM4 to the floating diffusion region FD4. The memory transfer gate MT4 may be configured with, for example, a transistor.

[0252] The overflow drain OFD1 is placed at the end of the path between the transfer gate TG6 and the transfer gate TG1, passing through the center.

[0253] The overflow drain OFD2 is placed at the end of the path between the transfer gate TG3 and the transfer gate TG4, passing through the center.

[0254] Transfer gate TG1 and transfer gate TG2 are gates that control transfers to memory area MEM1.

[0255] Transfer gates TG2 and TG3 are gates that control transfers to memory area MEM2.

[0256] Transfer gate TG3 and transfer gate TG4 are gates that control the transfer to the overflow drain OFD2.

[0257] Transfer gates TG4 and TG5 are gates that control transfers to memory area MEM3.

[0258] Transfer gates TG5 and TG6 are gates that control transfers to memory area MEM4.

[0259] Transfer gate TG6 and transfer gate TG1 are gates that control the transfer to the overflow drain OFD1.

[0260] When a signal is transferred to each storage unit, the gates in the above combination are turned on. When two gates are turned on, a channel is formed between the two gates, and the signal is transferred to the corresponding storage unit, the memory area, and the overflow drain.

[0261] The signal transferred to each memory region MEM is transferred to the corresponding floating diffusion region FD by turning on the corresponding memory transfer gate MT at the appropriate timing.

[0262] As described above, even when a memory region is provided as a storage section, appropriate signal transfer can be achieved by using two gate electrodes in the same manner.

[0263] 11. Ninth Embodiment

[0264] In the sixth to eighth embodiments described above, signals from the light-receiving elements are transferred in principle by electrodes constituting the transfer gates, but electrodes that facilitate transfer may also be provided. In this embodiment, a case where the transfer gates are arranged at the vertices of a regular hexagon will be described, but the present invention is not limited to this and can be applied to other shapes of arrangements as well as to cases where a memory area is provided.

[0265] 24 is a diagram showing an example of an arrangement of transfer gates according to one embodiment. Transfer gates TG1, TG2, TG3, TG4, TG5, and TG6 may be arranged at the vertices of a regular hexagon.

[0266] The floating diffusion region FD1 is located at the end of the path between the transfer gate TG1 and the transfer gate TG2, passing through the center.

[0267] The floating diffusion region FD2 is located at the end of the path between the transfer gate TG2 and the transfer gate TG3, passing through the center.

[0268] The floating diffusion region FD3 is disposed at the end of the path between the transfer gate TG4 and the transfer gate TG5, passing through the center.

[0269] The floating diffusion region FD4 is disposed at the end of the path between the transfer gate TG5 and the transfer gate TG6, passing through the center.

[0270] The overflow drain OFD1 is placed at the end of the path between the transfer gate TG6 and the transfer gate TG1, passing through the center.

[0271] The overflow drain OFD2 is placed at the end of the path between the transfer gate TG3 and the transfer gate TG4, passing through the center.

[0272] Transfer gate TG1 and transfer gate TG2 are gates that control the transfer to the floating diffusion region FD1.

[0273] Transfer gate TG2 and transfer gate TG3 are gates that control the transfer to the floating diffusion region FD2.

[0274] Transfer gate TG3 and transfer gate TG4 are gates that control the transfer to the overflow drain OFD2.

[0275] Transfer gate TG4 and transfer gate TG5 are gates that control transfer to floating diffusion region FD3.

[0276] Transfer gate TG5 and transfer gate TG6 are gates that control transfer to floating diffusion region FD4.

[0277] Transfer gate TG6 and transfer gate TG1 are gates that control the transfer to the overflow drain OFD1.

[0278] The photogate PG is a gate provided on the light-receiving element side, which is the signal source. The photogate PG is a gate for reinforcing the channel formed in each transfer gate. Like the transfer gate, the photogate PG may have a trench-type electrode or a planar-type electrode.

[0279] When the signal is transferred to each storage unit, the gates in the above combination are turned on. When two gates and a photogate are turned on, a channel is formed between the two gates, and the signal is transferred to the corresponding storage unit.

[0280] Furthermore, by turning on the photogate PG, it is possible to connect channels over a wide range. For example, when transferring a signal to the floating diffusion region FD1, turning on the photogate PG in addition to the transfer gates TG1 and TG2 generates a channel around the photogate PG, which assists the movement of carriers from around the photodetector PD to the channel formed by the transfer gates TG1 and TG2, thereby reinforcing the signal transfer.

[0281] 25 is a diagram showing an example of an arrangement of transfer gates according to one embodiment. Transfer gates TG1, TG2, TG3, TG4, TG5, and TG6 may be arranged at the vertices of a regular hexagon.

[0282] The floating diffusion region FD1 is located at the end of the path between the transfer gate TG1 and the transfer gate TG2, passing through the center.

[0283] The floating diffusion region FD2 is located at the end of the path between the transfer gate TG2 and the transfer gate TG3, passing through the center.

[0284] The floating diffusion region FD3 is disposed at the end of the path between the transfer gate TG4 and the transfer gate TG5, passing through the center.

[0285] The floating diffusion region FD4 is disposed at the end of the path between the transfer gate TG5 and the transfer gate TG6, passing through the center.

[0286] The overflow drain OFD1 is placed at the end of the path between the transfer gate TG6 and the transfer gate TG1, passing through the center.

[0287] The overflow drain OFD2 is placed at the end of the path between the transfer gate TG3 and the transfer gate TG4, passing through the center.

[0288] Transfer gate TG1 and transfer gate TG2 are gates that control the transfer to the floating diffusion region FD1.

[0289] Transfer gate TG2 and transfer gate TG3 are gates that control the transfer to the floating diffusion region FD2.

[0290] Transfer gate TG3 and transfer gate TG4 are gates that control the transfer to the overflow drain OFD2.

[0291] Transfer gate TG4 and transfer gate TG5 are gates that control transfer to floating diffusion region FD3.

[0292] Transfer gate TG5 and transfer gate TG6 are gates that control transfer to floating diffusion region FD4.

[0293] Transfer gate TG6 and transfer gate TG1 are gates that control the transfer to the overflow drain OFD1.

[0294] Photogate PG1 is a gate provided on the signal source side between transfer gates TG1 and TG2. Photogate PG1 turns on when transfer gates TG1 and TG2 turn on, reinforcing the signal transfer channel to floating diffusion region FD1.

[0295] Photogate PG2 is a gate provided on the signal source side between transfer gates TG2 and TG3. Photogate PG2 turns on when transfer gates TG2 and TG3 turn on, reinforcing the signal transfer channel to floating diffusion region FD2.

[0296] Photogate PG3 is a gate provided on the signal source side between transfer gates TG3 and TG4. Photogate PG3 turns on when transfer gates TG3 and TG4 turn on, reinforcing the signal transfer channel to overflow drain OFD2.

[0297] Photogate PG4 is a gate provided on the signal source side between transfer gates TG4 and TG5. Photogate PG4 turns on when transfer gates TG4 and TG5 turn on, reinforcing the signal transfer channel to floating diffusion region FD3.

[0298] Photogate PG5 is a gate provided on the signal source side between transfer gates TG5 and TG6. Photogate PG5 is a gate that turns on when transfer gates TG5 and TG6 turn on, reinforcing the signal transfer channel to floating diffusion region FD4.

[0299] Photogate PG6 is a gate provided on the signal source side between transfer gates TG6 and TG1. Photogate PG6 turns on when transfer gates TG6 and TG1 turn on, reinforcing the signal transfer channel to overflow drain OFD1.

[0300] Each photogate, like the transfer gate, may have a trench-type electrode or a planar-type electrode.

[0301] When the signal is transferred to each storage unit, the gates in the above combination are turned on. When two gates and the corresponding photogate are turned on, a channel is formed between the two gates, and the signal is transferred to the corresponding storage unit.

[0302] Furthermore, by turning on each photogate PG at the appropriate timing, it is possible to connect channels over a wide range. For example, when transferring a signal to the floating diffusion region FD1, turning on the photogate PG in addition to the transfer gates TG1 and TG2 generates a channel around the photogate PG, which assists the movement of carriers from around the light-receiving element PD to the channel formed by the transfer gates TG1 and TG2, thereby reinforcing the signal transfer.

[0303] As described above, according to this embodiment, by providing one or more photogates on the light receiving element side (signal transfer source side), it is possible to reduce the influence of process variations in signal transfer. In particular, when the solid-state imaging device 1 is intended for distance measurement using ToF (including iToF), the influence of process variations is likely to be significant. Even in such a case, the configuration of this embodiment makes it possible to reduce distance measurement variations.

[0304] 12. Tenth Embodiment

[0305] In the ninth embodiment described above, a gate is further provided on the light receiving element side, which is the signal transfer source side, but a gate may also be provided on the storage section side, which is the signal transfer destination side. In this embodiment, a case where the transfer gates are arranged at the vertices of a regular hexagon will be described, but this is not limiting and the same applies to arrangements of other shapes, and a similar configuration can also be used when there is a memory area.

[0306] 26 is a diagram showing an example of an arrangement of transfer gates according to one embodiment. Transfer gates TG1, TG2, TG3, TG4, TG5, and TG6 may be arranged at the vertices of a regular hexagon.

[0307] The floating diffusion region FD1 is located at the end of the path between the transfer gate TG1 and the transfer gate TG2, passing through the center.

[0308] The floating diffusion region FD2 is located at the end of the path between the transfer gate TG2 and the transfer gate TG3, passing through the center.

[0309] The floating diffusion region FD3 is disposed at the end of the path between the transfer gate TG4 and the transfer gate TG5, passing through the center.

[0310] The floating diffusion region FD4 is disposed at the end of the path between the transfer gate TG5 and the transfer gate TG6, passing through the center.

[0311] The overflow drain OFD1 is placed at the end of the path between the transfer gate TG6 and the transfer gate TG1, passing through the center.

[0312] The overflow drain OFD2 is placed at the end of the path between the transfer gate TG3 and the transfer gate TG4, passing through the center.

[0313] Transfer gate TG1 and transfer gate TG2 are gates that control the transfer to the floating diffusion region FD1.

[0314] Transfer gate TG2 and transfer gate TG3 are gates that control the transfer to the floating diffusion region FD2.

[0315] Transfer gate TG3 and transfer gate TG4 are gates that control the transfer to the overflow drain OFD2.

[0316] Transfer gate TG4 and transfer gate TG5 are gates that control transfer to floating diffusion region FD3.

[0317] Transfer gate TG5 and transfer gate TG6 are gates that control transfer to floating diffusion region FD4.

[0318] Transfer gate TG6 and transfer gate TG1 are gates that control the transfer to the overflow drain OFD1.

[0319] The lateral gate LTG1 is a gate provided on the floating diffusion region FD1 side, which is the storage side that is the destination of the signal between the transfer gates TG1 and TG2. The lateral gate LTG1 is a gate that turns on when the transfer gates TG1 and TG2 turn on, and reinforces the transfer channel of the signal to the floating diffusion region FD1.

[0320] The lateral gate LTG2 is a gate provided on the floating diffusion region FD2 side, which is the storage side that is the destination of the signal between the transfer gates TG2 and TG3. The lateral gate LTG2 is a gate that turns on when the transfer gates TG2 and TG3 turn on, and reinforces the transfer channel of the signal to the floating diffusion region FD2.

[0321] The lateral gate LTG3 is a gate provided on the floating diffusion region FD3 side, which is the storage side that is the destination of the signal between the transfer gates TG4 and TG5. The lateral gate LTG3 is a gate that turns on when the transfer gates TG4 and TG5 turn on, and reinforces the transfer channel of the signal to the floating diffusion region FD3.

[0322] Lateral gate LTG4 is a gate provided on the floating diffusion region FD4 side, which is the storage side that is the destination of the signal between transfer gates TG5 and TG6. Lateral gate LTG4 is a gate that turns on when transfer gates TG5 and TG6 turn on, and reinforces the transfer channel of the signal to floating diffusion region FD1.

[0323] Although no lateral gate is provided on the overflow drain side in FIG. 26, this does not exclude a configuration in which a lateral gate is provided on the overflow drain side.

[0324] As described above, according to this embodiment, a lateral gate can be provided to reinforce the channel in the transfer destination area. When the solid-state imaging device 1 is a ToF (including iToF) imaging device, providing this lateral gate makes it possible to particularly improve the resolution, and as a result, improve the accuracy of distance measurement.

[0325] 13. Eleventh Embodiment

[0326] Next, the on / off of the transfer gates in each of the above-described embodiments will be described using a timing chart. As an example, a case where the transfer gates are arranged at the vertices of a regular hexagon as shown in FIG. 17 will be described. However, similar operations can also be performed when the transfer gates are arranged at the vertices of other shapes.

[0327] The transfer gates may be switched on and off in a predetermined order.

[0328] 27 is a timing chart showing the on / off timing of a transfer gate according to one embodiment. The top row, Light, indicates the timing of receiving pulsed light for defining the pulse width when performing distance measurement using ToF, and is not an essential component as long as the pulse width can be measured correctly or the clock signal is input correctly. The same applies to other examples of this embodiment.

[0329] The second to seventh rows show the on / off states of transfer gates TG1, TG2, TG3, TG4, TG5, and TG6. In each row, the upper side indicates on and the lower side indicates off.

[0330] First, at the timing of the first pulse width, the transfer gates TG1 and TG2 are turned on, which transfers the signal to the floating diffusion region FD1.

[0331] At the timing of the next pulse width, transfer gate TG1 is turned off, and transfer gate TG3 is turned on while transfer gate TG2 is kept on. This operation ends the transfer of the signal to floating diffusion region FD1, and the signal is transferred to floating diffusion region FD2.

[0332] At the timing of the next pulse width, both transfer gates TG2 and TG3 are turned off, and transfer gates TG4 and TG5 are turned on. This operation ends the transfer of the signal to the floating diffusion region FD2, and the signal is transferred to the floating diffusion region FD3.

[0333] At the timing of the next pulse width, transfer gate TG4 is turned off, and transfer gate TG6 is turned on while transfer gate TG5 is kept on. This operation ends the transfer of the signal to floating diffusion region FD3, and the signal is transferred to floating diffusion region FD4.

[0334] In this way, during the signal transfer period, signals are transferred to each floating diffusion region at appropriate timing. After the signal transfer, the transfer gate is turned off. It is also possible to initialize the light receiving region at the transfer timing.

[0335] Subsequently, after a predetermined period, the transfer gates TG1 and TG6 are turned on to transfer the signal of the light-receiving region to the overflow drain OFD1, thereby controlling the overflow of the light-receiving region.

[0336] Overflow control of the photosensitive region is performed by turning off transfer gates TG1 and TG6 and turning on transfer gates TG3 and TG4 to transfer the signal of the photosensitive region to overflow drain OFD2.

[0337] If necessary, this operation may be repeated. After a predetermined period has elapsed and the data accumulation period has begun, the transfer gates TG1, TG3, TG4, and TG6 are turned on to initialize the light receiving region.

[0338] In this manner, the transfer gates may be switched on and off to transfer the signal in a clockwise (or counterclockwise) direction to the reservoirs, at least to the respective floating diffusion regions.

[0339] Figure 28 shows another example of this case, in which overflow control during the transfer period is omitted. In this way, it is possible to perform overflow control as initialization only during the data accumulation period, without performing overflow control during the transfer period.

[0340] FIG. 29 is a timing chart showing the on / off timing of a transfer gate according to one embodiment.

[0341] First, at the timing of the first pulse width, the transfer gates TG1 and TG2 are turned on, which transfers the signal to the floating diffusion region FD1.

[0342] At the timing of the next pulse width, both transfer gates TG1 and TG2 are turned off, and transfer gates TG4 and TG5 are turned on. This operation ends the transfer of the signal to the floating diffusion region FD1, and the signal is transferred to the floating diffusion region FD3.

[0343] At the timing of the next pulse width, both transfer gates TG4 and TG5 are turned off, and transfer gates TG2 and TG3 are turned on. This operation ends the transfer of the signal to floating diffusion region FD3, and the signal is transferred to floating diffusion region FD2.

[0344] At the timing of the next pulse width, both transfer gates TG2 and TG3 are turned off, and transfer gates TG5 and TG6 are turned on. This operation ends the transfer of the signal to floating diffusion region FD2, and the signal is transferred to floating diffusion region FD4.

[0345] The subsequent operations are the same as those in FIG.

[0346] FIG. 30 is a diagram showing another example of this case, in which overflow control during the transfer period is omitted.

[0347] In this manner, the transfer gates may be switched on and off to transfer signals alternately left and right and up and down to the storage portions, at least to the respective floating diffusion regions.

[0348] As described above, according to this embodiment, signals can be transferred to the storage unit in a predetermined order. By transferring signals clockwise (counterclockwise) or alternately up, down, left, and right, it is possible to achieve stable signal transfer for each frame.

[0349] For example, by transferring signals sequentially in a clockwise (counterclockwise) direction, at least one transfer gate can be kept on, improving the charge transfer efficiency.

[0350] Furthermore, for example, by transferring signals alternately and sequentially from left to right (up to down), it is possible to improve the symmetry relative to the light receiving elements of the storage section to which the signals are transferred.

[0351] If there is a bias in the signals, it is possible to arbitrarily switch this predetermined order to one of the above-mentioned orders or to another order.

[0352] 14. Twelfth Embodiment

[0353] The transfer gates formed as described above can have variously changed driver sharing relationships. In this embodiment, the layout shown in FIG. 17 is also used as a reference, but this does not exclude application to other layouts, and the present invention can also be applied to other layouts as appropriate.

[0354] 31 is a diagram showing an example of connections between transfer gates and drivers according to one embodiment, and as shown in this Fig. 31, each transfer gate may be provided with a driver for applying a voltage.

[0355] That is, as a non-limiting example, the solid-state imaging device 1 may include a driver DR1 corresponding to the transfer gate TG1, a driver DR2 corresponding to the transfer gate TG2, a driver DR3 corresponding to the transfer gate TG3, a driver DR4 corresponding to the transfer gate TG4, a driver DR5 corresponding to the transfer gate TG5, and a driver DR6 corresponding to the transfer gate TG6.

[0356] 32 is a diagram showing an example of connections between transfer gates and drivers according to one embodiment, at least some of the transfer gates can share drivers as shown in FIG.

[0357] That is, as a non-limiting example, the solid-state imaging device 1 may include a driver DR1 and a buffer BF1 corresponding to the transfer gates TG1 and TG2, a driver DR2 and a buffer BF2 corresponding to the transfer gates TG3 and TG4, and a driver DR3 and a buffer BF3 corresponding to the transfer gates TG5 and TG6.

[0358] Each buffer operates to distribute the voltage output from the corresponding driver to the appropriate transfer gate.

[0359] Although each buffer is connected to two transfer gates, the connection to the two transfer gates is not limited to this diagram.

[0360] For example, a symmetrical connection may be used, in which driver DR1 is connected to transfer gates TG1 and TG4 via buffer BF1, driver DR2 is connected to transfer gates TG2 and TG5 via buffer BF2, and driver DR3 is connected to transfer gates TG3 and TG6 via buffer BF3. In this case, since there are no two transfer gates that turn on at the same time via the same driver, the buffer can control the application of voltage to one transfer gate. It is also possible to ensure the symmetry of the circuit.

[0361] As another non-limiting example, driver DR1 may be connected to transfer gates TG1 and TG6 via buffer BF1, driver DR2 may be connected to transfer gates TG2 and TG5 via buffer BF2, and driver DR3 may be connected to transfer gates TG3 and TG4 via buffer BF3. In this case, multiple transfer gates may not be turned on by the same driver when transferring a signal, while two transfer gates via buffer BF1 or BF3, which are the same driver, may be turned on when transferring a signal to the overflow drain, making it possible to separately control the voltage at the timing of transfer to the floating diffusion region and the voltage at the timing of transfer to the overflow drain.

[0362] In this case, since the same driver can be used for the transfer gates arranged in the horizontal direction in FIG. 17 and the like, it is possible to achieve effects such as facilitating layout adjustment and processes.

[0363] 33 is a diagram showing an example of connections between transfer gates and drivers according to one embodiment. As shown in this Fig. 33, the number of transfer gates connected to a buffer may be three or more.

[0364] That is, as a non-limiting example, the solid-state imaging device 1 may include a driver DR1 and a buffer BF1 corresponding to transfer gates TG1, TG2, and TG3, and a driver DR2 and a buffer BF2 corresponding to transfer gates TG4, TG5, and TG6.

[0365] 34 is a diagram showing an example of connections between transfer gates and drivers according to one embodiment, all of the transfer gates may be controlled by the same driver as shown in FIG.

[0366] That is, as a non-limiting example, the solid-state imaging device 1 may include a driver DR1 and a buffer BF1 corresponding to the transfer gates TG1, TG2, TG3, TG4, TG5, and TG6. Even in this case, by applying an on-voltage to any two gate electrodes, it is possible to generate a channel that transfers a signal to an appropriate storage section.

[0367] As described above, according to this embodiment, a driver that controls the voltage applied to the transfer gate can be shared by multiple transfer gates. By configuring the driver in this way, it is possible to reduce the layout, circuit area, and process costs.

[0368] 15. Thirteenth Embodiment The technology according to the present disclosure can be applied to various electronic devices. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, a robot, a construction machine, or an agricultural machine (tractor).

[0369] 35 is a block diagram showing a schematic configuration example of a vehicle control system 7000, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied. The vehicle control system 7000 includes a plurality of electronic control units connected via a communication network 7010. In the example shown in FIG. 35, the vehicle control system 7000 includes a drive system control unit 7100, a body system control unit 7200, a battery control unit 7300, an outside-vehicle information detection unit 7400, an inside-vehicle information detection unit 7500, and an integrated control unit 7600. The communication network 7010 connecting these multiple control units may be an in-vehicle communication network conforming to any standard, such as a Controller Area Network (CAN), a Local Interconnect Network (LIN), a Local Area Network (LAN), or FlexRay (registered trademark).

[0370] Each control unit includes a microcomputer that performs arithmetic processing according to various programs, a memory unit that stores the programs executed by the microcomputer or parameters used in various calculations, and a drive circuit that drives various controlled devices. Each control unit includes a network I / F for communicating with other control units via a communication network 7010, and a communication I / F for communicating with devices or sensors inside and outside the vehicle via wired or wireless communication. Figure 35 illustrates the functional configuration of the integrated control unit 7600, including a microcomputer 7610, a general-purpose communication I / F 7620, a dedicated communication I / F 7630, a positioning unit 7640, a beacon receiving unit 7650, an in-vehicle device I / F 7660, an audio / video output unit 7670, an in-vehicle network I / F 7680, and a memory unit 7690. Similarly, the other control units also include a microcomputer, a communication I / F, a memory unit, and the like.

[0371] The drivetrain control unit 7100 controls the operation of devices related to the drivetrain of the vehicle according to various programs. For example, the drivetrain control unit 7100 functions as a control device for a driving force generating device for generating driving force for the vehicle, such as an internal combustion engine or a drive motor, a driving force transmission mechanism for transmitting driving force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating braking force for the vehicle. The drivetrain control unit 7100 may also function as a control device for an ABS (Antilock Brake System) or ESC (Electronic Stability Control), etc.

[0372] A vehicle state detection unit 7110 is connected to the drivetrain control unit 7100. The vehicle state detection unit 7110 includes at least one of a gyro sensor that detects the angular velocity of the axial rotational motion of the vehicle body, an acceleration sensor that detects the acceleration of the vehicle, or a sensor that detects the amount of operation of the accelerator pedal, the amount of operation of the brake pedal, the steering angle of the steering wheel, the engine rotation speed, the wheel rotation speed, etc. The drivetrain control unit 7100 performs arithmetic processing using signals input from the vehicle state detection unit 7110, and controls the internal combustion engine, the drive motor, the electric power steering device, the brake device, etc.

[0373] The body system control unit 7200 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 7200 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as head lamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 7200. The body system control unit 7200 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0374] The battery control unit 7300 controls the secondary battery 7310, which is the power supply source for the drive motor, in accordance with various programs. For example, information such as battery temperature, battery output voltage, or remaining battery capacity is input to the battery control unit 7300 from a battery device equipped with the secondary battery 7310. The battery control unit 7300 performs arithmetic processing using these signals, and controls the temperature regulation of the secondary battery 7310 or a cooling device or the like equipped in the battery device.

[0375] The outside vehicle information detection unit 7400 detects information outside the vehicle equipped with the vehicle control system 7000. For example, at least one of an imaging unit 7410 and an outside vehicle information detection unit 7420 is connected to the outside vehicle information detection unit 7400. The imaging unit 7410 includes at least one of a ToF (Time Of Flight) camera, a stereo camera, a monocular camera, an infrared camera, and other cameras. The outside vehicle information detection unit 7420 includes at least one of an environmental sensor for detecting the current weather or climate, or a surrounding information detection sensor for detecting other vehicles, obstacles, pedestrians, etc. around the vehicle equipped with the vehicle control system 7000.

[0376] The environmental sensor may be, for example, at least one of a raindrop sensor that detects rain, a fog sensor that detects fog, a sunshine sensor that detects the level of sunshine, and a snow sensor that detects snowfall. The surrounding information detection sensor may be at least one of an ultrasonic sensor, a radar device, and a LIDAR (Light Detection and Ranging, Laser Imaging Detection and Ranging) device. The imaging unit 7410 and the outside vehicle information detection unit 7420 may each be provided as an independent sensor or device, or may be provided as a device in which multiple sensors or devices are integrated.

[0377] 36 shows an example of the installation positions of the imaging unit 7410 and the vehicle exterior information detection unit 7420. The imaging units 7910, 7912, 7914, 7916, and 7918 are installed, for example, at least one of the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle cabin of the vehicle 7900. The imaging unit 7910 installed on the front nose and the imaging unit 7918 installed on the upper part of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 7900. The imaging units 7912 and 7914 installed on the side mirrors mainly acquire images of the sides of the vehicle 7900. The imaging unit 7916 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 7900. The imaging unit 7918 provided on the top of the windshield inside the vehicle is primarily used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0378] 36 shows an example of the imaging ranges of the imaging units 7910, 7912, 7914, and 7916. Imaging range a indicates the imaging range of the imaging unit 7910 provided on the front nose, imaging ranges b and c indicate the imaging ranges of the imaging units 7912 and 7914 provided on the side mirrors, respectively, and imaging range d indicates the imaging range of the imaging unit 7916 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 7910, 7912, 7914, and 7916, a bird's-eye view image of the vehicle 7900 viewed from above can be obtained.

[0379] The outside vehicle information detection units 7920, 7922, 7924, 7926, 7928, 7930 provided on the front, rear, sides, corners, and above the windshield inside the vehicle cabin of the vehicle 7900 may be, for example, ultrasonic sensors or radar devices. The outside vehicle information detection units 7920, 7926, 7930 provided on the front nose, rear bumper, back door, and above the windshield inside the vehicle cabin of the vehicle 7900 may be, for example, LIDAR devices. These outside vehicle information detection units 7920 to 7930 are mainly used to detect preceding vehicles, pedestrians, obstacles, etc.

[0380] Returning to FIG. 35 , the explanation continues. The outside-vehicle information detection unit 7400 causes the imaging unit 7410 to capture an image outside the vehicle and receives the captured image data. The outside-vehicle information detection unit 7400 also receives detection information from the connected outside-vehicle information detection unit 7420. If the outside-vehicle information detection unit 7420 is an ultrasonic sensor, a radar device, or a LIDAR device, the outside-vehicle information detection unit 7400 emits ultrasonic waves or electromagnetic waves and receives information on the received reflected waves. The outside-vehicle information detection unit 7400 may perform object detection processing or distance detection processing for people, vehicles, obstacles, signs, or text on the road surface, etc., based on the received information. The outside-vehicle information detection unit 7400 may also perform environment recognition processing to recognize rainfall, fog, road conditions, etc., based on the received information. The outside-vehicle information detection unit 7400 may also calculate the distance to an object outside the vehicle based on the received information.

[0381] The outside vehicle information detection unit 7400 may also perform image recognition processing or distance detection processing to recognize people, vehicles, obstacles, signs, characters on the road, etc. based on the received image data. The outside vehicle information detection unit 7400 may perform processing such as distortion correction or alignment on the received image data, and may also generate an overhead image or a panoramic image by combining image data captured by different imaging units 7410. The outside vehicle information detection unit 7400 may also perform viewpoint conversion processing using image data captured by different imaging units 7410.

[0382] The interior information detection unit 7500 detects information inside the vehicle. The interior information detection unit 7500 is connected to, for example, a driver state detection unit 7510 that detects the state of the driver. The driver state detection unit 7510 may include a camera that captures an image of the driver, a biosensor that detects the driver's biometric information, or a microphone that collects sound inside the vehicle. The biosensor may be provided, for example, on the seat or steering wheel, and detect biometric information of a passenger sitting in the seat or the driver gripping the steering wheel. The interior information detection unit 7500 may calculate the driver's level of fatigue or concentration, or may determine whether the driver is dozing, based on the detection information input from the driver state detection unit 7510. The interior information detection unit 7500 may perform processing such as noise canceling on the collected audio signal.

[0383] The integrated control unit 7600 controls the overall operation of the vehicle control system 7000 in accordance with various programs. An input unit 7800 is connected to the integrated control unit 7600. The input unit 7800 is realized by a device that can be operated by a passenger, such as a touch panel, a button, a microphone, a switch, or a lever. Data obtained by voice recognition of voice input through a microphone may be input to the integrated control unit 7600. The input unit 7800 may be, for example, a remote control device using infrared or other radio waves, or an externally connected device such as a mobile phone or PDA (Personal Digital Assistant) that is compatible with the operation of the vehicle control system 7000. The input unit 7800 may be, for example, a camera, in which case the passenger can input information using gestures. Alternatively, data obtained by detecting the movement of a wearable device worn by the passenger may be input. Furthermore, the input unit 7800 may include, for example, an input control circuit that generates an input signal based on information input by a passenger or the like using the input unit 7800 and outputs the signal to the integrated control unit 7600. The passenger or the like operates the input unit 7800 to input various data to the vehicle control system 7000 and to instruct processing operations.

[0384] The storage unit 7690 may include a ROM (Read Only Memory) that stores various programs executed by the microcomputer, and a RAM (Random Access Memory) that stores various parameters, calculation results, sensor values, etc. The storage unit 7690 may also be realized by a magnetic storage device such as an HDD (Hard Disc Drive), a semiconductor storage device, an optical storage device, a magneto-optical storage device, or the like.

[0385] The general-purpose communication I / F 7620 is a general-purpose communication I / F that mediates communication with various devices present in the external environment 7750. The general-purpose communication I / F 7620 may implement a cellular communication protocol such as GSM (Global System of Mobile communications), WiMAX (registered trademark), LTE (Long Term Evolution), or LTE-Advanced (LTE-A), or other wireless communication protocols such as wireless LAN (also known as Wi-Fi (registered trademark)) or Bluetooth (registered trademark). The general-purpose communication I / F 7620 may connect to devices (e.g., application servers or control servers) present on an external network (e.g., the Internet, a cloud network, or an operator-specific network) via, for example, a base station or an access point. The general-purpose communication I / F 7620 may also connect to a terminal located near the vehicle (e.g., a terminal of a driver, pedestrian, or store, or an MTC (Machine Type Communication) terminal) using, for example, P2P (Peer To Peer) technology.

[0386] The dedicated communication I / F 7630 is a communication I / F that supports a communication protocol designed for use in vehicles. The dedicated communication I / F 7630 may implement a standard protocol such as WAVE (Wireless Access in Vehicle Environment), which is a combination of a lower layer IEEE802.11p and an upper layer IEEE1609, a dedicated short range communications (DSRC), or a cellular communication protocol. The dedicated communication I / F 7630 typically performs V2X communication, which is a concept including one or more of vehicle-to-vehicle communication, vehicle-to-infrastructure communication, vehicle-to-home communication, and vehicle-to-pedestrian communication.

[0387] The positioning unit 7640 performs positioning by receiving, for example, GNSS signals from GNSS (Global Navigation Satellite System) satellites (for example, GPS signals from GPS (Global Positioning System) satellites) and generates position information including the latitude, longitude, and altitude of the vehicle. Note that the positioning unit 7640 may identify the current position by exchanging signals with a wireless access point, or may obtain position information from a terminal such as a mobile phone, PHS, or smartphone that has a positioning function.

[0388] The beacon receiving unit 7650 receives, for example, radio waves or electromagnetic waves transmitted from radio stations or the like installed on the road, and acquires information such as the current location, congestion, road closures, required travel time, etc. The function of the beacon receiving unit 7650 may be included in the dedicated communication I / F 7630 described above.

[0389] The in-vehicle device I / F 7660 is a communication interface that mediates connections between the microcomputer 7610 and various in-vehicle devices 7760 present in the vehicle. The in-vehicle device I / F 7660 may establish wireless connections using wireless communication protocols such as wireless LAN, Bluetooth (registered trademark), NFC (Near Field Communication), or WUSB (Wireless USB). The in-vehicle device I / F 7660 may also establish a wired connection such as USB (Universal Serial Bus), HDMI (High-Definition Multimedia Interface), or MHL (Mobile High-Definition Link) via a connection terminal (and a cable, if necessary) not shown. The in-vehicle device 7760 may include, for example, at least one of a mobile device or a wearable device owned by a passenger, or an information device carried into or attached to a vehicle. The in-vehicle device 7760 may also include a navigation device that searches for a route to an arbitrary destination. The in-vehicle device I / F 7660 exchanges control signals or data signals with these in-vehicle devices 7760.

[0390] The in-vehicle network I / F 7680 is an interface that mediates communication between the microcomputer 7610 and the communication network 7010. The in-vehicle network I / F 7680 transmits and receives signals in accordance with a predetermined protocol supported by the communication network 7010.

[0391] The microcomputer 7610 of the integrated control unit 7600 controls the vehicle control system 7000 in accordance with various programs based on information acquired via at least one of the general-purpose communication I / F 7620, the dedicated communication I / F 7630, the positioning unit 7640, the beacon receiving unit 7650, the in-vehicle device I / F 7660, and the in-vehicle network I / F 7680. For example, the microcomputer 7610 may calculate control target values ​​for the driving force generating device, the steering mechanism, or the braking device based on acquired information inside and outside the vehicle, and output control commands to the drivetrain control unit 7100. For example, the microcomputer 7610 may perform cooperative control aimed at realizing functions of an Advanced Driver Assistance System (ADAS), including vehicle collision avoidance or impact mitigation, following driving based on the following distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc. In addition, the microcomputer 7610 may perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling a driving force generating device, steering mechanism, braking device, etc. based on information acquired about the vehicle's surroundings.

[0392] The microcomputer 7610 may generate three-dimensional distance information between the vehicle and objects such as surrounding structures and people, and create local map information including information about the vicinity of the vehicle's current location, based on information acquired via at least one of the general-purpose communication I / F 7620, the dedicated communication I / F 7630, the positioning unit 7640, the beacon receiving unit 7650, the in-vehicle device I / F 7660, and the in-vehicle network I / F 7680. The microcomputer 7610 may also predict dangers, such as a vehicle collision, the approach of a pedestrian, or entry into a closed road, based on the acquired information, and generate a warning signal. The warning signal may be, for example, a signal for generating a warning sound or turning on a warning lamp.

[0393] The audio / video output unit 7670 transmits at least one of audio and visual output signals to an output device capable of visually or audibly notifying vehicle occupants or the outside of the vehicle of information. In the example of FIG. 35 , an audio speaker 7710, a display unit 7720, and an instrument panel 7730 are illustrated as output devices. The display unit 7720 may include, for example, at least one of an on-board display and a head-up display. The display unit 7720 may have an AR (Augmented Reality) display function. The output device may be other devices, such as headphones, a wearable device such as a glasses-type display worn by the occupant, a projector, or a lamp. When the output device is a display device, the display device visually displays results obtained by various processes performed by the microcomputer 7610 or information received from other control units in various formats, such as text, images, tables, and graphs. Furthermore, when the output device is an audio output device, the audio output device converts an audio signal consisting of reproduced voice data or acoustic data into an analog signal and outputs it audibly.

[0394] In the example shown in FIG. 35 , at least two control units connected via the communication network 7010 may be integrated into a single control unit. Alternatively, each control unit may be composed of multiple control units. Furthermore, the vehicle control system 7000 may include another control unit not shown. In the above description, some or all of the functions performed by one control unit may be performed by another control unit. In other words, as long as information is transmitted and received via the communication network 7010, predetermined arithmetic processing may be performed by one of the control units. Similarly, a sensor or device connected to one control unit may be connected to another control unit, and multiple control units may transmit and receive detection information to each other via the communication network 7010.

[0395] A computer program for realizing each function of the solid-state imaging device 1 according to this embodiment described with reference to FIGS. 1 to 34 can be implemented in any control unit or the like. A computer-readable recording medium storing such a computer program can also be provided. Examples of the recording medium include a magnetic disk, an optical disk, a magneto-optical disk, and a flash memory. The computer program may also be distributed, for example, via a network without using a recording medium.

[0396] In the vehicle control system 7000 described above, the solid-state imaging device 1 according to this embodiment described using FIGS. 1 to 34 can be applied to the positioning unit 7640, imaging unit 7410, outside vehicle information detection unit 7420, or driver state detection unit 7510 of the integrated control unit 7600 of the application example shown in FIG. 35.

[0397] 1 to 34 may be realized in a module (for example, an integrated circuit module configured on a single die) for the positioning unit 7640, the imaging unit 7410, the outside vehicle information detection unit 7420, or the driver state detection unit 7510 of the integrated control unit 7600 shown in Fig. 35. Alternatively, the solid-state imaging device 1 described using Fig. 1 to 34 may be realized by a plurality of control units of the vehicle control system 7000 shown in Fig. 35.

[0398] The embodiments of the present disclosure can also be summarized as follows.

[0399] (1) A solid-state imaging device comprising a pixel including a light-receiving element, one or more storage sections that store signals output by the light-receiving element, and a plurality of transfer gates that transfer the signals output by the light-receiving element to the storage sections at predetermined timing, wherein at least two of the plurality of transfer gates are used for transfer to each of the storage sections, and when there are a plurality of storage sections, at least one of the transfer gates is used for transfer to a plurality of the storage sections.

[0400] (2) The solid-state imaging device according to (1), wherein at least one of the plurality of storage sections is a charge storage region.

[0401] (3) The solid-state imaging device according to (1) or (2), wherein at least one of the plurality of storage sections is a floating diffusion region.

[0402] (4) The solid-state imaging device according to any one of (1) to (3), wherein the transfer gate is formed by at least one vertical transistor.

[0403] (5) The solid-state imaging device according to any one of (1) to (4), wherein at least two of the plurality of transfer gates are turned on at the same timing.

[0404] (6) The solid-state imaging device according to any one of (1) to (5), wherein the pixels form an indirect time of flight (iToF) sensor.

[0405] (7) The solid-state imaging device according to any one of (1) to (6), further comprising at least one overflow drain.

[0406] (8) The solid-state imaging device according to (7), wherein at least one of the plurality of transfer gates is an overflow gate that transfers a signal to the overflow drain.

[0407] (9) The solid-state imaging device according to (7) or (8), wherein the plurality of transfer gates are arranged so that two transfer gates corresponding to each of the plurality of storage sections are line-symmetrically arranged.

[0408] (10) A solid-state imaging device described in any one of (7) to (9), wherein the plurality of transfer gates are arranged at positions that form a polygon, and the plurality of storage sections are arranged outside the plurality of transfer gates at positions where the transfer of signals to each of the storage sections is controlled by two of the transfer gates.

[0409] (11) The solid-state imaging device according to (7), wherein the plurality of transfer gates are turned on in a predetermined order.

[0410] (12) The solid-state imaging device according to (11), wherein the plurality of transfer gates are turned on at the same timing in a clockwise or counterclockwise order.

[0411] (13) The solid-state imaging device according to (11), wherein the plurality of transfer gates are alternately turned on in the left and right sides of the pixel.

[0412] (14) The solid-state imaging device according to any one of (7) to (13), wherein the plurality of transfer gates share a driver.

[0413] (15) A solid-state imaging device according to any one of (1) to (14), further comprising one or more photogates formed by electrodes in an area on the light receiving element side from which the signal is transferred, wherein when at least two of the plurality of transfer gates are turned on, the photogates corresponding to the two transfer gates are turned on, and a voltage is applied to assist the two transfer gates in transferring the signal.

[0414] (16) A solid-state imaging device according to any one of (1) to (15), further comprising one or more lateral gates composed of electrodes in the region on the storage section side to which the signal is transferred, wherein the lateral gates corresponding to at least two of the plurality of transfer gates are turned on at the timing when the two transfer gates are turned on, and a voltage is applied to assist the transfer of the signal by the two transfer gates.

[0415] (17) An electronic device comprising an imaging unit having pixels each having a light receiving element, one or more storage units that store signals output by the light receiving element, and a plurality of transfer gates that transfer the signals output by the light receiving element to the storage units at a predetermined timing, wherein at least two of the plurality of transfer gates are used in transfer to each of the storage units, and when a plurality of the storage units are provided, at least one of the transfer gates is used in transfer to a plurality of the storage units.

[0416] (18) The electronic device according to (17), wherein the imaging unit has the configuration and / or performs the operation according to any one of (1) to (16).

[0417] The aspects of the present disclosure are not limited to the above-described embodiments and include various conceivable modifications, and the effects of the present disclosure are not limited to the above-described contents. The components in each embodiment may be appropriately combined and applied. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and intent of the present disclosure, which is derived from the content defined in the claims and their equivalents.

[0418] 1: solid-state imaging device, 10: solid-state imaging element, 100: pixel array, 102: control circuit, 104: line driving circuit, 106: column driving circuit, 108: signal processing circuit, 110: pixel, P: photodetector, MEM, MEM1, MEM2, MEM3, MEM4: memory area, FD, FD1, FD2, FD3, FD4, FD5, FD6: floating diffusion area, OFD, OFD1, OFD2, OFD3, OFD4: overflow drain, M1, M2, M3: transfer gate, RS: reset transistor, AMP: amplifying transistor, TG, TG1, TG2, TG3, TG4, TG5, TG6, TG7, TG8: Transfer gate, VG1, VG2: gate electrode, MT, MT1, MT2, MT3, MT4: memory transfer gate, PG, PG1, PG2, PG3, PG4, PG5, PG6: photogate, LTG1, LTG2, LTG3, LTG4: lateral gate, DR1, DR2, DR3, DR4, DR5, DR6: driver BF1, BF2, BF3: buffer, 16: control unit, 17: memory unit, 18: interface, 19: optical system, 2: external device.

Claims

1. A solid-state imaging device comprising a pixel comprising: a light-receiving element; one or more storage sections that store signals output by the light-receiving element; and a plurality of transfer gates that transfer the signals output by the light-receiving element to the storage sections at a predetermined timing, wherein at least two of the plurality of transfer gates are used for transfer to each of the storage sections, and when there are a plurality of storage sections, at least one of the transfer gates is used for transfer to a plurality of the storage sections.

2. The solid-state imaging device according to claim 1, wherein at least one of the plurality of storage sections is a charge storage region.

3. The solid-state imaging device according to claim 1, wherein at least one of the plurality of storage sections is a floating diffusion region.

4. The solid-state imaging device according to claim 1, wherein the transfer gate is formed by at least one vertical transistor.

5. The solid-state imaging device according to claim 1, wherein at least two of the plurality of transfer gates are turned on at the same time.

6. The solid-state imaging device according to claim 1, wherein the pixels form an indirect time of flight (iToF) sensor.

7. The solid-state imaging device according to claim 1, comprising at least one overflow drain.

8. The solid-state imaging device according to claim 7, wherein at least one of the plurality of transfer gates is an overflow gate that transfers a signal to the overflow drain.

9. The solid-state imaging device according to claim 7, wherein the plurality of transfer gates are arranged in line symmetry, with two transfer gates corresponding to each of the plurality of storage sections.

10. The solid-state imaging device according to claim 7, wherein the plurality of transfer gates are arranged at positions that form a polygon, and the plurality of storage sections are arranged outside the plurality of transfer gates at positions where transfer of signals to each section is controlled by two of the transfer gates.

11. The solid-state imaging device according to claim 7, wherein the plurality of transfer gates are turned on in a predetermined order.

12. The solid-state imaging device according to claim 11, wherein the plurality of transfer gates are arranged in a clockwise or counterclockwise order, with adjacent transfer gates being turned on at the same timing.

13. The solid-state imaging device according to claim 11, wherein the plurality of transfer gates are arranged such that the transfer gates located on the left and right of the pixel are alternately turned on.

14. The solid-state imaging device according to claim 7, wherein the plurality of transfer gates share a driver.

15. The solid-state imaging device of claim 1, further comprising one or more photogates formed by electrodes in an area on the light receiving element side, which is the source of signal transfer, wherein when at least two of the multiple transfer gates are turned on, the photogates corresponding to those two transfer gates are turned on and a voltage is applied to assist the two transfer gates in transferring signals.

16. The solid-state imaging device of claim 1, further comprising one or more lateral gates formed of electrodes in a region on the storage section side to which the signal is transferred, wherein when at least two of the plurality of transfer gates are turned on, the lateral gates corresponding to those two transfer gates are turned on, and a voltage is applied to assist the transfer of the signal by those two transfer gates.

17. An electronic device comprising an imaging unit having pixels each having a light receiving element, one or more storage units that store signals output by the light receiving element, and a plurality of transfer gates that transfer the signals output by the light receiving element to the storage units at a predetermined timing, wherein at least two of the plurality of transfer gates are used in transfer to each of the storage units, and when a plurality of storage units are provided, at least one of the transfer gates is used in transfer to a plurality of the storage units.

Images