Three-dimensional memory array and method for manufacturing same

Abstract

Disclosed are a three-dimensional memory array and a method for manufacturing same. More specifically, according to an embodiment, a method for manufacturing a three-dimensional memory array in which a transistor and a capacitor are individually configured comprises: a step of preparing a semiconductor structure including isolation insulating layers and memory cell layers, which are alternately stacked in the vertical direction, wherein each of the memory cell layers is formed of a first semiconductor material; a step of etching a transistor hole in the semiconductor structure in the vertical direction; a step of recessing a portion of each of the memory cell layers in the horizontal direction through the transistor hole; and a step of selectively depositing a second semiconductor material in each of recessed spaces to form uniform channels for each layer of the memory cell layers; a step of depositing a gate insulating layer in the transistor hole in which the second semiconductor material is selectively deposited; and a step of forming a gate layer in the transistor hole in which the gate insulating layer is deposited.

Description

Three-dimensional memory array and its manufacturing method

[0001] The following examples relate to a three-dimensional memory array and a method for manufacturing the same.

[0002] Semiconductor devices such as DRAM (Dynamic Random Access Memory) have a MOS transistor including a source and a drain, a capacitor electrically connected to the source of the MOS transistor, and wiring such as a bit line electrically connected to the drain of the MOS transistor.

[0003] In this type of DRAM, a three-dimensional structure that breaks away from the two-dimensional structure has been proposed in line with the trend toward high integration.

[0004] 3D DRAM is an alternative that can overcome the limitations of 2D DRAM in miniaturization and high integration by separating and individually configuring transistors and capacitors based on vertically alternating stacked isolation insulating layers and memory cell layers.

[0005] However, implementing 3D DRAM presents numerous technical challenges. For example, referring to U.S. Patent Publication No. 10,535,659, which describes forming transistor channels through anisotropic etching in each memory cell layer, conventional 3D DRAMs suffer from channel widths that vary across memory cell layers, preventing transistor performance from being maintained uniformly across layers.

[0006] Therefore, a technology needs to be proposed to maintain the performance of the transistor uniformly from layer to layer.

[0007] One embodiment proposes a three-dimensional memory array and a method for manufacturing the same, which maintains uniform channels in each layer of memory cell layers to ensure transistor performance.

[0008] However, the technical problems to be solved by the present invention are not limited to the above problems, and can be expanded in various ways without departing from the technical spirit and scope of the present invention.

[0009] According to one embodiment, a method for manufacturing a three-dimensional memory array in which transistors and capacitors are individually configured may include: preparing a semiconductor structure including vertically alternately stacked isolation insulating layers and memory cell layers, each of the memory cell layers being formed of a first semiconductor material; etching a transistor hole in the semiconductor structure in the vertical direction; recessing a portion of each of the memory cell layers in a horizontal direction through the transistor hole; selectively depositing a second semiconductor material in each of the recessed spaces such that uniform channels are formed in each layer of the memory cell layers using the second semiconductor material; depositing a gate insulating film in the transistor hole in which the second semiconductor material is selectively deposited; and forming a gate film in the transistor hole in which the gate insulating film is deposited.

[0010] According to one aspect, the step of selectively depositing the second semiconductor material may be characterized in that the channels are formed with the second semiconductor material having a lower etching rate than the first semiconductor material, thereby minimizing the influence of the channels from etching in the memory cell layers, thereby implementing uniform channels for each layer of the memory cell layers.

[0011] According to another aspect, the step of selectively depositing the second semiconductor material may be characterized by forming uniform channels for each layer of the memory cell layers so that the channels have a uniform profile regardless of the layer of the memory cell layers.

[0012] According to another aspect, the method for manufacturing the three-dimensional memory may further include the steps of: etching a capacitor hole in the semiconductor structure in the vertical direction; recessing a portion of each of the memory cell layers in the horizontal direction through the capacitor hole; depositing a capacitor first electrode in each of the recessed spaces; and depositing a capacitor dielectric film in each of the spaces in which the capacitor first electrode is formed and in the capacitor hole; and forming a capacitor second electrode in each of the spaces in which the capacitor dielectric film is deposited and in the capacitor hole.

[0013] According to another aspect, the recessing step may be characterized by using the channels in each of the memory cell layers as etch stoppers and recessing a portion of each of the memory cell layers in a horizontal direction.

[0014] According to another aspect, the capacitor first electrode, the capacitor dielectric film, and the capacitor second electrode may be uniformly implemented in each layer of the memory cell layers as the channels are used as etching stoppers in the recessing step.

[0015] According to another aspect, the step of depositing a capacitor first electrode in each of the recessed spaces may include the step of forming an ohmic film in each of the recessed spaces to improve contact resistance with each of the channels; and the step of depositing the capacitor first electrode in each of the spaces in which the ohmic film is formed.

[0016] According to another aspect, the method for manufacturing the three-dimensional memory array may further include the steps of: etching a bit line trench in the semiconductor structure in the vertical direction; recessing a portion of each of the memory cell layers in the horizontal direction through the bit line trench; and forming bit lines in each of the recessed spaces.

[0017] According to another aspect, the recessing step may include a step of recessing a portion of each of the memory cell layers while using the channels as etching stoppers in each of the memory cell layers, and the step of forming the bit lines may include a step of forming an ohmic film in each of the recessed spaces to improve contact resistance with each of the channels; and a step of forming the bit lines in each of the spaces in which the ohmic film is formed.

[0018] According to another aspect, the method for manufacturing the three-dimensional memory array may further include the step of etching a horizontal isolation trench in the semiconductor structure in the vertical direction so that side surfaces of the channels are exposed through the horizontal isolation trench in the memory cell layers; and the step of forming a horizontal isolation insulating film in the horizontal isolation trench.

[0019] According to one embodiment, in a three-dimensional memory array that individually configures a transistor and a capacitor while including vertically alternately stacked isolation insulating layers and memory cell layers, the transistor may include: a gate film formed to extend in the vertical direction; a gate insulating film formed to surround a side surface of the gate film and extend in the vertical direction; channels formed uniformly in each layer of the memory cell layers, each of which surrounds at least a portion of a side surface of the gate film; and bit lines connected to one side surface of the channels in the memory cell layers, respectively.

[0020] According to one aspect, the channels may be formed of a second semiconductor material having a lower etching rate than the first semiconductor material forming each of the memory cell layers, thereby minimizing the influence from etching in the memory cell layers and thereby being uniformly implemented in each layer of the memory cell layers.

[0021] According to another aspect, the channels may be characterized by having a uniform profile regardless of the layer of the memory cell layers.

[0022] According to another aspect, the capacitor may be characterized by including: a capacitor first electrode formed to extend in a horizontal direction so as to be connected to the channels in each of the memory cell layers; a capacitor dielectric film formed to extend in the horizontal direction and the vertical direction so as to be in contact with the capacitor first electrode; and a capacitor second electrode formed to extend in the horizontal direction and the vertical direction so as to be in contact with the capacitor dielectric film.

[0023] According to another aspect, the capacitor first electrode, the capacitor dielectric film, and the capacitor second electrode may be uniformly implemented in each layer of the memory cell layers as the channels are used as etch stoppers in the process of recessing the spaces in which the capacitor first electrode, the capacitor dielectric film, and the capacitor second electrode are formed in the memory cell layers.

[0024] One embodiment proposes a three-dimensional memory array and a manufacturing method thereof that maintains uniform channels in each layer of memory cell layers, thereby achieving a technical effect that ensures the performance of a transistor.

[0025] However, the effects of the present invention are not limited to the above effects, and can be expanded in various ways without departing from the technical spirit and scope of the present invention.

[0026] FIGS. 1A and 1B are diagrams illustrating a three-dimensional memory array according to one embodiment.

[0027] FIGS. 2A and 2B are cross-sectional views illustrating a three-dimensional memory array according to another embodiment.

[0028] FIG. 3 is a flow chart illustrating a method for manufacturing a three-dimensional memory array according to one embodiment.

[0029] FIGS. 4A to 4R are plan views illustrating a method for manufacturing a three-dimensional memory array according to one embodiment.

[0030] FIGS. 5A to 5R are cross-sectional views illustrating a method for manufacturing a three-dimensional memory array according to one embodiment.

[0031] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. However, the present invention is not limited or restricted by these embodiments. In addition, the same reference numerals in each drawing represent the same components.

[0032] In addition, the terminology used in this specification is a term used to appropriately express the preferred embodiments of the present invention, and this may vary depending on the intention of the viewer or operator, or the customs of the field to which the present invention belongs. Therefore, the definition of these terms should be determined based on the contents throughout this specification. For example, in this specification, the singular also includes the plural unless specifically stated in the phrase. In addition, the terms "comprises" and / or "comprising" as used herein do not exclude the presence or addition of one or more other components, steps, operations, and / or elements with respect to the mentioned components, steps, operations, and / or elements. In addition, although the terms first, second, etc. are used in this specification to describe various regions, directions, shapes, etc., these regions, directions, and shapes should not be limited by these terms. These terms are only used to distinguish a certain region, direction, or shape from another region, direction, or shape. Therefore, a part referred to as a first part in one embodiment may be referred to as a second part in another embodiment.

[0033] It should also be understood that the various embodiments of the present invention, while different, are not necessarily mutually exclusive. For example, specific shapes, structures, and characteristics described herein may be implemented in other embodiments without departing from the spirit and scope of the present invention. Furthermore, it should be understood that the location, arrangement, or configuration of individual components within each of the disclosed embodiments may be modified without departing from the spirit and scope of the present invention.

[0034] Hereinafter, a three-dimensional memory array, a manufacturing method thereof, and an electronic system including the same according to embodiments will be described in detail with reference to the drawings.

[0035]

[0036] FIGS. 1A and 1B are diagrams illustrating a three-dimensional memory array according to one embodiment, and FIGS. 2A and 2B are cross-sectional views illustrating a three-dimensional memory array according to another embodiment. More specifically, FIG. 1A is a plan view illustrating a three-dimensional memory array according to one embodiment, FIG. 1B is a cross-sectional view illustrating a three-dimensional memory array according to one embodiment, FIG. 2A is a plan view illustrating a three-dimensional memory array according to another embodiment, and FIG. 2B is a cross-sectional view illustrating a three-dimensional memory array according to another embodiment.

[0037] Referring to the drawings, a three-dimensional memory array according to one embodiment individually configures transistors (TR) and capacitors (CAP) while including isolation insulating layers (ILD) and memory cell layers (MEM) that are alternately stacked in a vertical direction on a substrate (SUB).

[0038] The substrate (SUB) may be a semiconductor substrate such as a silicon substrate composed of single-crystal silicon, polycrystalline silicon, or amorphous silicon, a silicon-germanium substrate, a germanium substrate, or a single-crystal epitaxial layer grown on a monocrystalline silicon substrate. The substrate (SUB) may include a conductive region, such as a well or an active region doped with impurities (e.g., P-type impurities).

[0039] In addition, a gate connection channel (GCC; not shown) connected to a gate film (G) may be formed on the substrate (SUB) through high-concentration doping, and a device isolation insulating film (DIE; not shown) may be formed surrounding the gate connection channel (GCC) to isolate the gate connection channel (GCC). In addition, an etch stopper (ES; not shown) for protecting the silicon substrate during the manufacturing process may be formed on top of the gate connection channel (GCC) using an aluminum oxide film or a silicon nitride film.

[0040] Each of the isolation insulating layers (ILD) may be formed of an insulating material such as a silicon oxide film or a silicon nitride film, and may also be formed of a low-k insulating material to improve the sensing margin by reducing the capacitance of cells formed in the memory cell layers (MEM).

[0041] Each of the memory cell layers (MEM) is initially formed of a first semiconductor material (M1) having an etching rate higher than a preset value during the manufacturing process, but as the manufacturing process progresses, a channel (C), a bit line (BL), a first ohmic film (OM1), a first capacitor electrode (EL1), a capacitor dielectric film (CD), and a second capacitor electrode (EL2) formed of a second semiconductor material (M2) having an etching rate lower than that of the first semiconductor material (M1) may be included.

[0042] At this time, the source (SO) of the transistor (TR) may be omitted. This is because the function of providing electrons to the drain (DR) can be performed by components (for example, the first ohmic film (OM1)) positioned opposite the drain (DR) with respect to the channel (C). In other words, components (for example, the first ohmic film (OM1)) positioned opposite the drain (DR) with respect to the channel (C) can replace the role of the source (SO).

[0043] In this case, each of the memory cell layers (MEM) may include a drain (DR) formed of a first semiconductor material (M1), a channel (C) formed of a second semiconductor material (M2), a bit line (BL), an ohmic film (OM), a capacitor first electrode (EL1), a capacitor dielectric film (CD), and a capacitor second electrode (EL2) as the manufacturing process progresses, as shown in FIGS. 1A and 1B.

[0044] Additionally, the drain (DR) of the transistor (TR) may also be omitted. This may be possible because the role of the source (SO) is replaced by components (e.g., the first ohmic film (OM1)) positioned opposite the bit line (BL), while the role of the drain (DR) is replaced by the second ohmic film (OM2) in contact with the bit line (BL).

[0045] In this case, each of the memory cell layers (MEM) may include a channel (C) formed of a second ohmic film (OM2), a second semiconductor material (M2), a bit line (BL), a first ohmic film (OM1), a capacitor first electrode (EL1), a capacitor dielectric film (CD), and a capacitor second electrode (EL2) as the manufacturing process progresses, as shown in FIGS. 2a and 2b.

[0046] In this way, in each of the memory cell layers (MEM), the channel (C) of the transistor (TR) is doped with a first type (e.g., p-type) impurity, and the components (e.g., the first ohmic film (OM1), the second ohmic film (OM2), or the drain (DR)) that serve as the source (SO) and drain (DR) are doped with a second type (e.g., n-type) impurity, thereby forming an npn junction, etc., so that the transistor (TR) can be implemented.

[0047] A transistor (TR) can be electrically connected to a first electrode (EL) of a capacitor (CAP), including a gate film (G), a gate insulating film (GD), channels (C), and bit lines (BL).

[0048] The gate film (G) may be formed to extend in a vertical direction (e.g., a third direction (D3)). The gate film (G) may be formed of a semiconductor material (e.g., polysilicon, etc.) or a conductive material (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), titanium nitride, tantalum nitride, etc.).

[0049] A gate insulating film (GD) may be formed to extend in a vertical direction (e.g., a third direction (D3)) surrounding a side surface of the gate film (G). The gate insulating film (GD) may be formed of an insulating material having insulating properties like a dielectric (e.g., a high-k dielectric material such as a silicon oxide film, a silicon nitride film, an aluminum oxide film, or hafnium oxide).

[0050] The channels (C) may be implemented in a separate form, each corresponding to a memory cell layer (MEM), and may be formed to surround at least a portion of a side of the gate film (G) in the memory cell layers (MEM).

[0051] At this time, the channels (C) are formed of a second semiconductor material (M2) having a lower etching rate than the first semiconductor material (M1) forming each of the memory cell layers (MEM), so that the influence from etching (etching of the first semiconductor material (M1) performed during the manufacturing process) in the memory cell layers (MEM) is minimized, and thus the channels (C) can be uniformly implemented for each layer of the memory cell layers (MEM). That is, the channels (C) can have a uniform profile for each layer of the memory cell layers (MEM).

[0052] More specifically, since the channels (C) have a uniform profile regardless of the layer of the memory cell layers (MEM) (for example, the channel (C) formed in the lowest memory cell layer (MEM) among the memory cell layers (MEM) and the channel (C) located in the highest memory cell layer (MEM) have the same profile), the performance of the transistor (TR) can be maintained uniformly for each layer of the memory cell layers (MEM).

[0053] Bit lines (BL) are respectively connected to one side of channels (C) in memory cell layers (MEM) and can be formed in a horizontal direction (e.g., a first direction (D1)) of a semiconductor material (e.g., polysilicon, etc.) or a conductive material (e.g., tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), molybdenum (Mo), ruthenium (Ru), gold (Au), titanium nitride, tantalum nitride, etc.). ALD or CVD can be used as a forming method.

[0054] Here, a second ohmic film (OM2) may be formed between each of the bit lines (BL) and each of the channels (C) to improve the contact resistance between each of the bit lines (BL) and each of the channels (C), as illustrated in FIGS. 2a and 2b. In this case, the second ohmic film (OM2) may be used as a drain (DR) of the transistor (TR).

[0055] The second ohmic film (OM2) can be formed of a single metal, such as tungsten, molybdenum, cobalt, titanium, nickel, ruthenium, or a metal silicide formed by the reaction of the single metal with silicon, using a selective ALD or CVD method. For example, an ohmic silicide formed by heat treatment on cobalt or nickel can be used as the second ohmic film (OM2). For a more specific example, cobalt silicide formed by performing a first heat treatment between 150°C and 250°C on cobalt and a second heat treatment between 500°C and 650°C can be used as the second ohmic film (OM2), and cobalt that does not react in the heat treatment can be removed by wet etching using sulfuric acid, hydrogen peroxide, or the like.

[0056] However, without being limited or restricted thereto, each of the bit lines (BL) may be in contact with each of the channels (C) through the first semiconductor material (M1) as illustrated in FIGS. 1A and 1B. In this case, the first semiconductor material (M1) may be used as a drain (DR).

[0057] In addition, although not shown in the drawing, a counter doping layer (CP; not shown) may be further included in the transistor (TR) to prevent the occurrence of counter doping. For example, when the transistor (TR) is implemented with a structure as shown in FIGS. 2a and 2b, the counter doping layer (CP) may be interposed between the channel (C) and the second ohmic film (OM2). As another example, when the transistor (TR) is implemented with a structure as shown in FIGS. 1a and 1b, the counter doping layer (CP) may be interposed between the channel (C) and the first semiconductor material (M1).

[0058] The capacitor (CAP) may include a first capacitor electrode (EL1), a capacitor dielectric film (CD), a second capacitor electrode (EL2), and a first ohmic film (OM1).

[0059] The capacitor first electrode (EL1) may be formed to extend in a horizontal direction (e.g., a second direction (D2)) using a semiconductor material (e.g., polysilicon, etc.) or a conductive material (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), titanium nitride, tantalum nitride, etc.) so as to be connected to each of the channels (C) in the memory cell layers (MEM). ALD or CVD may be used as a forming method.

[0060] At this time, the capacitor first electrode (EL1) can be connected to each of the channels (C) through the first ohmic film (OM1).

[0061] The first ohmic film (OM1) can be used as a source (SO) of a transistor (TR), and can be formed of a single metal including tungsten, molybdenum, cobalt, titanium, nickel, ruthenium, etc., or a metal silicide formed by a reaction of the single metal with silicon using a selective ALD or CVD method. For example, an ohmic silicide formed by performing a heat treatment on cobalt or nickel, etc. can be used as the first ohmic film (OM1). For a more specific example, cobalt silicide formed by performing a first heat treatment between 150°C and 250°C on cobalt and a second heat treatment between 500°C and 650°C can be used as the first ohmic film (OM1), and cobalt that has not reacted in the heat treatment can be removed by wet etching using sulfuric acid, hydrogen peroxide, etc.

[0062] The capacitor dielectric film (CD) can be formed by extending along the horizontal direction (e.g., the second direction (D2)) and the vertical direction (e.g., the third direction (D3)) using an insulating material (e.g., silicon nitride film, aluminum oxide, hafnium oxide, zirconium oxide, etc.) or a mixture thereof having insulating properties such as a dielectric so as to be in contact with the capacitor first electrode (EL1).

[0063] A capacitor dielectric film (CD) is formed to contact a capacitor first electrode (EL1) and a capacitor second electrode (EL2) having a protruding shape and to cover the upper surface, side surface, and lower surface of the protrusion of the capacitor second electrode (EL2), thereby having a structure that improves the orientation area.

[0064] The capacitor second electrode (EL2) may be formed to extend along a horizontal direction (e.g., a second direction (D2)) and a vertical direction (e.g., a third direction (D3)) with a semiconductor material (e.g., polysilicon, etc.) or a conductive material (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), titanium nitride, tantalum nitride, etc.) so as to be in contact with the capacitor dielectric film (CD).

[0065] The capacitor first electrode (EL1), capacitor dielectric film (CD), and capacitor second electrode (CD2) can be uniformly implemented in each layer of the memory cell layers (MEM) as the channels (C) are used as etch stoppers (ES) in the process of recessing the spaces in which the capacitor first electrode (EL1), capacitor dielectric film (CD), and capacitor second electrode (CD2) are formed in the memory cell layers (MEM).

[0066] In the process of recessing the spaces where the capacitor first electrode (EL1), the capacitor dielectric film (CD), and the capacitor second electrode (CD2) are formed in the memory cell layers (MEM), the channels (C) are used as etch stoppers (ES), which means that they are uniformly implemented for each layer of the memory cell layers (MEM). This means that the horizontal width of the second semiconductor material (M2) used as the channel (C) in the memory cell layers (MEM) is the same as that in the upper and lower layers, so that they have similar thicknesses.

[0067] Hereinafter, a method for manufacturing the described three-dimensional memory array is disclosed.

[0068]

[0069] FIG. 3 is a flow chart illustrating a method for manufacturing a three-dimensional memory array according to one embodiment, FIGS. 4a to 4r are plan views illustrating a method for manufacturing a three-dimensional memory array according to one embodiment, and FIGS. 5a to 5r are cross-sectional views illustrating a method for manufacturing a three-dimensional memory array according to one embodiment.

[0070] The method for manufacturing a three-dimensional memory array described below is for manufacturing a three-dimensional memory array having the structure shown in FIGS. 1A and 1B, and is assumed to be performed by an automated and mechanized manufacturing system.

[0071] Referring to the drawings, in step (310), the manufacturing system can prepare a semiconductor structure (SEMI-STR) including vertically alternately stacked isolation insulating layers (ILD) and memory cell layers (MEM), as illustrated in FIGS. 4a and 5a.

[0072] Here, each of the memory cell layers (MEM) can be formed of a first semiconductor material such as silicon or silicon germanium having an n-type high impurity concentration to have n-type low-resistance semiconductor characteristics, and each of the isolation insulating layers (ILD) can be formed of an insulating material (e.g., low-k) such as a silicon oxide film or a silicon nitride film.

[0073] In step (S320), the manufacturing system can etch a transistor hole (TH) in a vertical direction (e.g., a third direction (D3)) in the semiconductor structure (SEM-STR), as illustrated in FIGS. 4b and 5b. When the transistor hole (TH) is etched in this way, the position and size at which the transistor (TR) is to be formed in the three-dimensional memory array can be considered.

[0074] In step (S330), the manufacturing system can recess a portion of each of the memory cell layers (MEM) in a horizontal direction (e.g., a first direction (D1) and a second direction (D2)) through a transistor hole (TH) as illustrated in FIGS. 4c and 5c.

[0075] At this time, the horizontal depth and size of the recess can be determined based on the planar size of the designed channel (C).

[0076] In this recess step (S330), a wet etching method based on ammonia water or TMAH can be utilized. For example, the recess step (S330) can be performed using a wet etching method in which TMAH is diluted with IPA at a chemical temperature of 50°C or lower and an etching rate is maintained at 20 nm per minute or lower.

[0077] In step (S340), the manufacturing system can selectively deposit the second semiconductor material (M2) into each of the recessed spaces so that uniform channels (C) are formed in each layer of the memory cell layers (MEM) with the second semiconductor material (M2), as illustrated in FIGS. 4d and 5d.

[0078] In particular, the manufacturing system can implement uniform channels (C) for each layer of the memory cell layers (MEM) by forming the channels (C) with a second semiconductor material (M2) having a lower etching rate than the first semiconductor material (M1), thereby minimizing the influence of the channels (C) from etching in the memory cell layers (MEM) (etching of the first semiconductor material (M1) performed during the manufacturing process; for example, a horizontal recess of the first semiconductor material (M1) through a capacitor hole (CAPH).

[0079] More specifically, the manufacturing system can maintain the performance of the transistor (TR) uniformly across layers of the memory cell layers (MEM) by forming the channels (C) so that the channels (C) have a uniform profile regardless of the layer of the memory cell layers (MEM) (e.g., forming the channel (C) formed in the lowest memory cell layer (MEM) among the memory cell layers (MEM) and the channel (C) located in the highest memory cell layer (MEM) so that they have the same profile).

[0080] In the selective deposition method, a method can be utilized in which the selective deposition and etching of the second semiconductor material (M2) are repeated through repeated ALD or CVD to increase the selectivity and form a channel (C) in an intended portion. In this case, in the selective deposition and etching, SiH4 or Si2H6 can be used for the selective deposition, and GeH4 can be used as the source gas of germanium. Furthermore, in order for the channel (C) to be formed as a p-type, BH3 or B2H6 gas can be used as a doping gas. HCl can be used as a gas for etching the second semiconductor material (M2) deposited in an unwanted portion for the selective deposition.

[0081] Additionally, in step (S340), the manufacturing system may perform heat treatment to ensure stable crystallization of the channel (C) after deposition of the second semiconductor material (M2). The heat treatment may be performed at a temperature of 700°C or higher to allow the doped impurities to diffuse. In particular, by gradually reducing the concentration of the impurities from an initial high concentration during deposition of the second semiconductor material (M2), the deposited second semiconductor material (M2) can have a uniform concentration.

[0082] In step (S350), the manufacturing system can deposit a gate insulating film (GD) on a transistor hole (TH) in which a second semiconductor material (M2) is selectively deposited, as illustrated in FIGS. 4e and 5e.

[0083] More specifically, the manufacturing system can deposit a gate insulating film (GD) formed of an insulating material having insulating properties like a dielectric (e.g., a high-k dielectric material such as a silicon oxide film, a silicon nitride film, an aluminum oxide film, or a hafnium oxide film) on a transistor hole (TH) in which a second semiconductor material (M2) is selectively deposited.

[0084] In step (S360), the manufacturing system can form a gate film (G) in a transistor hole (TH) on which a gate insulating film (GD) is deposited, as illustrated in FIGS. 4f and 5f. The gate film (G) can be formed of a semiconductor material (e.g., polysilicon, etc.) or a conductive material (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), titanium nitride, tantalum nitride, etc.).

[0085] Although not depicted as a separate step in FIG. 3, the manufacturing system may perform a transistor (TR) cell separation process after step (S360).

[0086] Specifically, in the first step of the transistor (TR) cell separation process, the manufacturing system can etch a horizontal isolation trench (ST) in the semiconductor structure (SEMI-STR) in a vertical direction (e.g., a third direction (D3)) so that side surfaces of channels (C) are exposed through the horizontal isolation trench (ST) in the memory cell layers (MEM), as illustrated in FIGS. 4g and 5g. When the horizontal isolation trench (ST) is etched in this way, the position and size of the transistor (TR) formed in the three-dimensional memory array can be considered. For example, the horizontal isolation trench (ST) can be etched along the horizontal direction (e.g., the second direction (D2)) and the vertical direction (e.g., the third direction (D3)) so that side surfaces of the channels (C) of the transistor (TR) are exposed through the horizontal isolation trench (ST).

[0087] In the second step of the transistor (TR) cell separation process, the manufacturing system can form a horizontal separation insulating film (S-DIE) using an insulating material such as a silicon oxide film or a silicon nitride film, or a low-k dielectric material in a horizontal separation trench (ST), as shown in FIGS. 4h and 5h.

[0088] In addition, although not depicted as a separate step in FIG. 3, the manufacturing system may perform a bit line (BL) formation process after step (S360). In the bit line (BL) formation process described below, etching in a vertical direction (e.g., the third direction (D3)), recessing in a horizontal direction (e.g., the second direction (D2)), etc. may be performed in the same or similar manner as the etching in the vertical direction (e.g., the third direction (D3)) and recessing in the horizontal direction (e.g., the second direction (D2)) described above.

[0089] More specifically, in the first step of the bit line (BL) formation process, the manufacturing system can etch a bit line trench (BL-T) in the semiconductor structure (SEMI-STR) in the vertical direction (third direction (D3)) as illustrated in FIGS. 4i and 5i.

[0090] In the second step of the bit line (BL) formation process, the manufacturing system can recess a portion of each of the memory cell layers (MEM) in a horizontal direction (e.g., a first direction (D1) and a second direction (D2)) through a bit line trench (BL-T) as illustrated in FIGS. 4j and 5j.

[0091] For the etching and recessing process, wet etching methods based on ammonia water or TMAH can be used.

[0092] In the third step of the bit line (BL) formation process, the manufacturing system can form bit lines (BL) in the recessed spaces, as shown in FIGS. 4k and 5k, using a semiconductor material (e.g., polysilicon, etc.) or a conductive material (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), titanium nitride, tantalum nitride, etc.).

[0093] If a transistor (TR) having a structure including a second ohmic film (OM2) as illustrated in FIGS. 2A and 2B, rather than a structure as illustrated in FIGS. 1A and 1B, is manufactured, the manufacturing system may use the channels (C) in each of the memory cell layers (MEM) as an etch stopper when performing the second step of the bit line (BL) forming process and recess a portion of each of the memory cell layers (MEM). Accordingly, the manufacturing system may form a second ohmic film (OM2) in each of the recessed spaces to improve contact resistance with each of the channels (C) when performing the third step of the bit line (BL) forming process, and may form bit lines (BL) in each of the spaces in which the second ohmic film (OM2) is formed.

[0094] The second ohmic film (OM2) can be formed of a single metal, such as tungsten, molybdenum, cobalt, titanium, nickel, ruthenium, or a metal silicide formed by the reaction of the single metal with silicon, using a selective ALD or CVD method. For example, an ohmic silicide formed by heat treatment on cobalt or nickel can be used as the second ohmic film (OM2). For a more specific example, cobalt silicide formed by performing a first heat treatment between 150°C and 250°C on cobalt and a second heat treatment between 500°C and 650°C can be used as the second ohmic film (OM2), and cobalt that does not react in the heat treatment can be removed by wet etching using sulfuric acid, hydrogen peroxide, or the like.

[0095] In the fourth step of the bit line (BL) formation process, the manufacturing system can complete the transistor (TR) manufacturing process by filling the bit line trench (BL-T) with an insulating film as illustrated in FIGS. 4l and 5l.

[0096] Additionally, although not depicted as a separate step in FIG. 3, the manufacturing system may perform a capacitor (CAP) formation process after step (S360).

[0097] In the first step of the capacitor (CAP) formation process, the manufacturing system can etch a capacitor hole (CAPH) in a vertical direction (e.g., a third direction (D3)) in a semiconductor structure (SEMI-STR), as illustrated in FIGS. 4m and 5m. When the capacitor hole (CAPH) is etched in this way, the position and size of the capacitor (CAP) to be formed in the three-dimensional memory array can be considered. In particular, the position and size of the capacitor hole (CAPH) can be determined so that a first ohmic film (OM1) included in the capacitor (CAP), which will be described later, can be brought into contact with the aforementioned channel (C).

[0098] In the second step of the capacitor (CAP) forming process, the manufacturing system can recess a portion of each of the memory cell layers (MEM) in a horizontal direction (e.g., a second direction (D2)) through a capacitor hole (CAPH) as illustrated in FIGS. 4n and 5n. The depth and size of the horizontal recess can be determined based on the planar size of the designed capacitor (CAP). The recessing method can be the aforementioned ammonia water or TMAH-based wet etching method.

[0099] In particular, the manufacturing system can horizontally recess a portion of each of the memory cell layers (MEM) using the channels (C) as etch stoppers when performing the second step of the capacitor (CAP) formation process.

[0100] In the third step of the capacitor (CAP) formation process, the manufacturing system can deposit a capacitor first electrode (EL1) into each of the recessed spaces.

[0101] At this time, the manufacturing system can form a first ohmic film (OM1) for improving contact resistance with each of the channels (C) in each of the recessed spaces as shown in FIGS. 4o and 5o before depositing the capacitor first electrode (EL1).

[0102] The first ohmic film (OM1) can be formed of a single metal, such as tungsten, molybdenum, cobalt, titanium, nickel, ruthenium, or a metal silicide formed by the reaction of the single metal with silicon, by a selective ALD or CVD method. For example, an ohmic silicide formed by performing a heat treatment on cobalt, nickel, or the like can be used as the first ohmic film (OM1). For a more specific example, cobalt silicide formed by performing a first heat treatment between 150°C and 250°C on cobalt and a second heat treatment between 500°C and 650°C can be used as the first ohmic film (OM1), and cobalt that does not react in the heat treatment can be removed by wet etching using sulfuric acid, hydrogen peroxide, or the like.

[0103] Accordingly, the manufacturing system can deposit a capacitor first electrode (EL1) using a semiconductor material (e.g., polysilicon, etc.) or a conductive material (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), titanium nitride, tantalum nitride, etc.) in each of the spaces where the first ohmic film (OM1) is formed, as shown in FIGS. 4p and 5p in the third step of the capacitor (CAP) forming process.

[0104] In the fourth step of the capacitor (CAP) forming process, the manufacturing system can deposit a capacitor dielectric film (CD) using an insulating material (e.g., silicon nitride film, aluminum oxide, hafnium oxide, zirconium oxide, etc.) or a mixture thereof having insulating properties such as a dielectric, in each of the spaces where the capacitor first electrode (EL1) is formed and in the capacitor hole (CAPH) so as to be in contact with the capacitor first electrode (EL1), as shown in FIGS. 4q and 5q.

[0105] In the fifth step of the capacitor (CAP) forming process, the manufacturing system can form a capacitor second electrode (EL2) using a semiconductor material (e.g., polysilicon, etc.) or a conductive material (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), titanium nitride, tantalum nitride, etc.) in each of the spaces where the capacitor dielectric film (CD) is deposited and in the capacitor hole (CAPH), as shown in FIGS. 4r and 5r.

[0106] As described, in the second step of the capacitor (CAP) formation process, since each channel (C) in the memory cell layers (MEM) is used as an etching stopper so that a portion of each of the memory cell layers (MEM) is recessed in the horizontal direction, the capacitor first electrode (EL1), the capacitor dielectric film (CD), and the capacitor second electrode (EL2) can be uniformly implemented for each layer of the memory cell layers (MEM).

[0107]

[0108] Although the embodiments described above have been described by way of limited examples and drawings, those skilled in the art will appreciate that various modifications and variations can be made based on the above teachings. For example, appropriate results can still be achieved even if the described techniques are performed in a different order than described, and / or components of the described systems, structures, devices, circuits, etc. are combined or combined in a different manner than described, or are replaced or substituted with other components or equivalents.

[0109] Therefore, other implementations, other embodiments, and equivalents to the claims also fall within the scope of the claims described below.

Claims

1. A method for manufacturing a three-dimensional memory array in which transistors and capacitors are individually configured, A step of preparing a semiconductor structure including vertically alternately stacked isolation insulating layers and memory cell layers, each of the memory cell layers being formed of a first semiconductor material; A step of etching a transistor hole in the semiconductor structure in the vertical direction; A step of horizontally recessing a portion of each of the memory cell layers through the transistor hole; A step of selectively depositing a second semiconductor material into each of the recessed spaces so that uniform channels are formed in each layer of the memory cell layers using the second semiconductor material; A step of depositing a gate insulating film in the transistor hole in which the second semiconductor material is selectively deposited; and A step of forming a gate film in the transistor hole on which the gate insulating film is deposited. A method for manufacturing a three-dimensional memory array including:

2. In paragraph 1, The step of selectively depositing the second semiconductor material is: A method for manufacturing a three-dimensional memory array, characterized in that uniform channels are implemented for each layer of the memory cell layers by forming the channels with the second semiconductor material having a lower etching rate than the first semiconductor material, thereby minimizing the influence of the channels from etching in the memory cell layers.

3. In paragraph 1, The step of selectively depositing the second semiconductor material is: A method for manufacturing a three-dimensional memory array, characterized in that uniform channels are formed for each layer of the memory cell layers so that the channels have a uniform profile regardless of the layer of the memory cell layers.

4. In paragraph 1, A step of etching a capacitor hole in the semiconductor structure in the vertical direction; A step of horizontally recessing a portion of each of the memory cell layers through the capacitor hole; A step of depositing a first capacitor electrode in each of the recessed spaces; and A step of depositing a capacitor dielectric film in each of the spaces where the first capacitor electrode is formed and in the capacitor hole; and A step of forming a capacitor second electrode in each of the spaces where the capacitor dielectric film is deposited and in the capacitor hole. A method for manufacturing a three-dimensional memory array, characterized in that it further includes.

5. In paragraph 4, The above recessing step is, A method for manufacturing a three-dimensional memory array, characterized in that each of the channels in the memory cell layers is used as an etch stopper and a portion of each of the memory cell layers is recessed in a horizontal direction.

6. In paragraph 5, The capacitor first electrode, the capacitor dielectric film and the capacitor second electrode, A method for manufacturing a three-dimensional memory array, characterized in that the channels are uniformly implemented layer by layer of the memory cell layers as they are used as etching stoppers in the recessing step.

7. In paragraph 4, The step of depositing a capacitor first electrode in each of the above recessed spaces is: A step of forming an ohmic film in each of the recessed spaces to improve contact resistance with each of the channels; and A step of depositing the first capacitor electrode in each of the spaces where the above ohmic film is formed. A method for manufacturing a three-dimensional memory array, characterized by including:

8. In paragraph 1, A step of etching a bit line trench in the semiconductor structure in the vertical direction; A step of horizontally recessing a portion of each of the memory cell layers through the bit line trench; and Step of forming bit lines in each recessed space A method for manufacturing a three-dimensional memory array further comprising:

9. In paragraph 8, The above recessing step is, A step of recessing a portion of each of the memory cell layers using the channels as etching stoppers in each of the memory cell layers. Including, The step of forming the above bit lines is: A step of forming an ohmic film in each of the recessed spaces to improve contact resistance with each of the channels; and A step of forming the bit lines in each of the spaces where the above ohmic film is formed. A method for manufacturing a three-dimensional memory array, characterized by including:

10. In paragraph 1, A step of etching a horizontal separation trench in the semiconductor structure in the vertical direction so that the side surfaces of the channels are exposed through the horizontal separation trench in the memory cell layers; and A step of forming a horizontal separation insulating film in the above horizontal separation trench A method for manufacturing a three-dimensional memory array further comprising:

11. In a three-dimensional memory array that individually configures transistors and capacitors, including vertically alternately stacked isolation insulating layers and memory cell layers, The above transistor, A gate film formed to extend in the vertical direction; A gate insulating film formed to surround the side surface of the gate film and extend in the vertical direction; Channels uniformly formed in each layer of the memory cell layers, each surrounding at least a portion of the side surface of the gate film in the memory cell layers; and Bit lines each connected to one side of the channels in the above memory cell layers A three-dimensional memory array containing .

12. In paragraph 11, The above channels are, A three-dimensional memory array characterized in that the memory cell layers are uniformly implemented in each layer by minimizing the influence from etching on the memory cell layers by forming the memory cell layers with a second semiconductor material having a lower etching rate than the first semiconductor material forming each of the memory cell layers.

13. In paragraph 11, The above channels are, A three-dimensional memory array characterized by having a uniform profile regardless of the layer of the memory cell layers.

14. In paragraph 11, The above capacitor, A capacitor first electrode formed to extend horizontally so as to be connected to the channels in each of the memory cell layers; A capacitor dielectric film formed to extend in the horizontal direction and the vertical direction so as to contact the first electrode of the capacitor; and A capacitor second electrode formed to extend in the horizontal direction and the vertical direction so as to contact the capacitor dielectric film. A three-dimensional memory array comprising:

15. In paragraph 14, The capacitor first electrode, the capacitor dielectric film and the capacitor second electrode, A three-dimensional memory array characterized in that the channels are used as etch stoppers in the process of recessing the spaces in which the capacitor first electrode, the capacitor dielectric film, and the capacitor second electrode are formed in the memory cell layers, thereby being uniformly implemented for each layer of the memory cell layers.

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