Uninterruptible power supply device

Abstract

An AC input filter (2) includes a first reactor (12RA) having a first terminal connected to a second terminal of a switch (1) and a second reactor (12RB) having a first terminal connected to the second terminal of the switch (1). A converter (3) includes a first multilevel circuit (3A) connected between a second terminal of the first reactor (12RA) and first to third DC lines (L1 to L3) and a second multilevel circuit (3B) connected between a second terminal of the second reactor (12RB) and the first to third DC lines (L1 to L3). A control device calculates a first voltage, which is the sum of the voltages across the terminals of first and second capacitors (C1, C2), and a second voltage, which is the difference between the voltages across the terminals of the first and second capacitors (C1, C2). When an AC power supply is healthy, the control device controls the first and second multilevel circuits (3A, 3B) so that the first voltage goes to a reference voltage and the second voltage is eliminated. In the event of a power failure in the AC power supply, the control device controls the first and second multilevel circuits (3A, 3B) so that the second voltage is eliminated.

Description

uninterruptible power supply

[0001] The present disclosure relates to uninterruptible power supplies.

[0002] For example, Japanese Patent Laid-Open Publication No. 2013-176296 (Patent Document 1) discloses an uninterruptible power supply system including a converter, a DC voltage converter, and an inverter. When the AC power supply is healthy, the converter converts an AC voltage from the AC power supply into first to third DC voltages and outputs them to the first to third DC lines. When the AC power supply is out of service, the DC voltage converter converts a fourth DC voltage from the power storage device into first to third DC voltages and supplies them to the first to third DC lines. The inverter converts the first to third DC voltages from the first to third DC lines into AC voltages and supplies them to a load.

[0003] The uninterruptible power supply further includes a first capacitor connected between the first and second DC lines, a second capacitor connected between the second and third DC lines, and a control device. As a "balance control" for eliminating the imbalance in the terminal voltages of the first and second capacitors, when the AC power supply is normal, the control device controls the converter so that a first voltage, which is the sum of the terminal voltages of the first and second capacitors, becomes a reference voltage and a second voltage, which is the difference between the terminal voltages of the first and second capacitors, disappears. When the AC power supply fails, the control device stops operation of the converter and controls the DC voltage converter so that the first voltage becomes the reference voltage and the second voltage disappears.

[0004] As another technique for balancing the first and second capacitors, International Publication No. 2020 / 105126 (Patent Document 2) discloses an uninterruptible power supply (UPS) in which the AC power supply and the load are three-phase, four-wire. In this uninterruptible power supply, when the AC power supply is healthy, the control device controls the converter so that the first voltage becomes the reference voltage and the second voltage, which is the difference between the terminal voltages of the first and second capacitors, disappears. When the AC power supply is out of service, the control device controls the DC voltage converter so that the first voltage becomes the reference voltage and the second voltage disappears. If the absolute value of the second voltage exceeds a predetermined threshold voltage during the AC power supply outage, the control device further controls the converter to reduce the second voltage.

[0005] JP 2013-176296 A International Publication No. 2020 / 105126

[0006] In the balance control described in Patent Document 1, if the load current is small during a power outage of the AC power supply, the output current of the DC voltage converter becomes small, which may make it difficult to eliminate the imbalance in the voltage between the terminals of the first and second capacitors.

[0007] On the other hand, in the balance control described in Patent Document 2, if the absolute value of the second voltage exceeds the threshold voltage during a power outage of the AC power supply, the converter is started, thereby making it possible to eliminate the imbalance in the voltages between the terminals of the first and second capacitors even when the load current is small.

[0008] However, in Patent Document 2, during a power outage of the AC power supply, the AC power supply and the AC input filter are electrically disconnected, and the converter is operated using a capacitor (hereinafter also referred to as a "filter capacitor") included in the AC input filter (LC filter circuit) as a power buffer to discharge or charge the first and second capacitors. In this case, the magnitude of the current input to and output from the first and second capacitors depends on the difference between the terminal voltages of the first and second capacitors and the terminal voltage of the filter capacitor. However, because the uninterruptible power supply does not have a detector for detecting the terminal voltage of the filter capacitor, it is not possible to determine the difference between the terminal voltages of the first and second capacitors and the terminal voltage of the filter capacitor, which raises concerns that balance control by the converter may become difficult.

[0009] Furthermore, in Patent Document 2, when the difference between the terminal voltages of the first and second capacitors and the terminal voltage of the filter capacitor disappears, the first and second capacitors cannot be discharged or charged even when the converter is operated, and an operation to discharge the filter capacitor is required. Therefore, Patent Document 2 reduces the second voltage by alternately repeating an operation to discharge or charge the first and second capacitors and an operation to discharge the filter capacitor. This raises concerns that it may be difficult to quickly resolve the imbalance between the first and second capacitors during a power outage of the AC power supply.

[0010] The present disclosure has been made to solve such problems, and an object of the present disclosure is to provide an uninterruptible power supply that can easily and quickly eliminate the imbalance in the voltages between the terminals of the first and second capacitors when the AC power supply fails.

[0011] An uninterruptible power supply according to one aspect of the present disclosure includes first to third DC lines, a first capacitor, a second capacitor, a switch, an AC input filter, a converter, an inverter, first and second voltage detectors, and a control device. The first capacitor is connected between the first and second DC lines. The second capacitor is connected between the second and third DC lines. The switch has a first terminal that receives AC voltage supplied from an AC power source and is turned on when the AC power source is normal and turned off when there is a power outage in the AC power source. The AC input filter has a first terminal that is connected to a second terminal of the switch. The converter is connected between a second terminal of the AC input filter and the first to third DC lines. When the AC power source is normal, the converter converts AC power from the AC power source into DC power and supplies it to the first to third DC lines. The inverter is connected between the first to third DC lines and the load, and converts DC power from the first to third DC lines into AC power and supplies it to the load. The first and second voltage detectors detect voltages across the first and second capacitors, respectively. The control device controls the converter based on values ​​detected by the first and second voltage detectors.

[0012] The AC input filter includes a first reactor having a first terminal connected to the second terminal of the switch and a second reactor having a first terminal connected to the second terminal of the switch. The converter includes a first multilevel circuit and a second multilevel circuit. The first multilevel circuit is connected between the second terminal of the first reactor and the first to third DC lines and is configured to be able to convert an AC voltage to and from the first to third DC voltages. The second multilevel circuit is connected between the second terminal of the second reactor and the first to third DC lines and is configured to be able to convert an AC voltage to and from the first to third DC voltages.

[0013] The control device calculates a first voltage that is the sum of the terminal voltages of the first and second capacitors and a second voltage that is the difference between the terminal voltages of the first and second capacitors based on the detection values ​​of the first and second voltage detectors. When the AC power supply is normal, the control device controls the first and second multilevel circuits so that the first voltage becomes the first reference voltage and the second voltage disappears. When the AC power supply fails, the control device controls the first and second multilevel circuits so that the second voltage disappears.

[0014] According to the present disclosure, it is possible to provide an uninterruptible power supply that can easily and quickly eliminate the imbalance in the voltages between the terminals of the first and second capacitors when the AC power supply fails.

[0015] 7 is a block diagram showing the overall configuration of an uninterruptible power supply according to a first embodiment. FIG. 8 is a block diagram showing an example of the hardware configuration of a control device. FIG. 9 is a circuit diagram showing an example of the configuration of the converter shown in FIG. 1. FIG. 10 is a circuit diagram showing an example of the configuration of the DC voltage converter shown in FIG. 1. FIG. 11 is a block diagram showing a portion of the control device related to control of the converter and the DC voltage converter. FIG. 9 is a block diagram showing the configuration of the first control circuit shown in FIG. 5. FIG. 11 is a block diagram showing the configuration of the PWM circuit shown in FIG. 6. FIG. 12 is a time chart showing waveforms of a voltage command value, a triangular wave signal, and a PWM signal shown in FIG. 13. FIG. 14 is a diagram showing switching patterns of four IGBTs included in each bridge circuit. FIG. 15 is a time chart showing the operation of the second control circuit shown in FIG. 14. FIG. 15 is an equivalent circuit diagram showing the operation of one phase of the converter when Ep>En. FIG. 16 is an equivalent circuit diagram showing the operation of one phase of the converter when Ep>En. FIG. 17 is an equivalent circuit diagram showing the operation of one phase of the converter when Ep<En. FIG. 18 is a block diagram showing the configuration of the control circuit shown in FIG. 15. FIG. 18 is a flowchart showing an example of balance control by a converter during a power outage of a commercial AC power supply. FIG. 19 is a circuit diagram showing a main part of an uninterruptible power supply according to a third embodiment. FIG. 1 is a diagram showing switching patterns of four IGBTs included in each bridge circuit. FIG. 2 is a time chart showing the operation of the second control circuit. FIG. 3 is an equivalent circuit diagram showing the operation of one phase of the converter when Ep>En. FIG. 4 is an equivalent circuit diagram showing the operation of one phase of the converter when Ep>En. FIG. 5 is a time chart showing the operation of the second control circuit. FIG. 6 is an equivalent circuit diagram showing the operation of one phase of the converter when Ep<En. FIG. 7 is an equivalent circuit diagram showing the operation of one phase of the converter when Ep<En.

[0016] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are designated by the same reference numerals, and description thereof will not be repeated.

[0017] [Embodiment 1] <Configuration of Uninterruptible Power Supply> Figure 1 is a block diagram showing the overall configuration of an uninterruptible power supply 100 according to embodiment 1. As shown in Figure 1, uninterruptible power supply 100 includes a switch 1, an AC input filter 2, a converter 3, an inverter 4, an AC output filter 5, a DC voltage converter (hereinafter referred to as "DC / DC") 6, a control device 10, DC lines L1 to L3, a neutral point line L4, capacitors C1 and C2, voltage detectors 31, 34, and 35, current detectors 32 and 37, and a power outage detector 33.

[0018] Switch 1 includes switches 1R, 1S, and 1T. First terminals of switches 1R, 1S, and 1T are connected to an R-phase terminal TR, an S-phase terminal TS, and a T-phase terminal TT, respectively, of commercial AC power supply 41, and receive an R-phase voltage VR, an S-phase voltage VS, and a T-phase voltage VT, respectively, supplied from commercial AC power supply 41. A neutral terminal TN of commercial AC power supply 41 is connected to one end of neutral line L4.

[0019] The switches 1R, 1S, and 1T are controlled by the control device 10, and are turned on when three-phase AC power is being normally supplied from the commercial AC power supply 41 (when the commercial AC power supply 41 is healthy), and are turned off when the supply of three-phase AC power from the commercial AC power supply 41 is stopped (when the commercial AC power supply 41 experiences a power outage). The switches 1R, 1S, and 1T are turned off when the commercial AC power supply 41 experiences a power outage, and electrically disconnect the commercial AC power supply 41 and the AC input filter 2.

[0020] The AC input filter 2 is a three-phase LC filter circuit configured with capacitors 11 (capacitors 11R, 11S, and 11T) and reactors 12 (reactors 12R, 12S, and 12T). The positive electrodes of capacitors 11R, 11S, and 11T are connected to second terminals of switches 1R, 1S, and 1T, respectively, and their negative electrodes are both connected to neutral line L4. The first terminals of reactors 12R, 12S, and 12T are connected to second terminals of switches 1R, 1S, and 1T, respectively, and the second terminals of reactors 12R, 12S, and 12T are connected to three input nodes of converter 3.

[0021] The AC input filter 2 is a low-pass filter that passes AC power of the commercial frequency supplied from the commercial AC power supply 41 to the converter 3 and prevents signals of the switching frequency generated in the converter 3 from passing to the commercial AC power supply 41 side.

[0022] First ends of DC lines L1 to L3 are connected to three output nodes of converter 3, and second ends thereof are connected to three input nodes of inverter 4. DC line L2 is connected to neutral line L4. DC lines L1 to L3 are also connected to three high-voltage nodes of DC voltage converter 6. DC lines L1 to L3 are set to a positive voltage, a neutral voltage, and a negative voltage by converter 3 and DC voltage converter 6, respectively.

[0023] The capacitor C1 is connected between the DC lines L1 and L2 to smooth and stabilize the DC voltage Ep between the DC lines L1 and L2. The capacitor C2 is connected between the DC lines L2 and L3 to smooth and stabilize the DC voltage En between the DC lines L2 and L3.

[0024] Converter 3 is controlled by control device 10, and when commercial AC power supply 41 is operating normally, converts three-phase AC power supplied from commercial AC power supply 41 via AC input filter 2 into DC power, and supplies the DC power to inverter 4 and DC voltage converter 6 via DC lines L1 to L3.

[0025] At this time, the control device 10 controls the converter 3 so that the DC voltage VDC = Ep + En, which is the sum of the DC voltages Ep and En, becomes the reference DC voltage VDCR, and the DC voltage ΔE = Ep - En, which is the difference between the DC voltages Ep and En, becomes zero.

[0026] Furthermore, when commercial AC power supply 41 experiences a power outage, control device 10 controls converter 3 so that the DC voltage difference between DC voltages Ep and En, ΔE=Ep−En, becomes 0. When the DC voltage difference between DC voltages Ep and En, ΔE=Ep−En, becomes 0, control device 10 stops the operation of converter 3.

[0027] The inverter 4 is controlled by the control device 10 and converts the DC power from the converter 3 and the DC voltage converter 6 into three-phase AC power at a commercial frequency. The three-phase AC power generated by the inverter 4 is supplied to a load 42 via an AC output filter 5.

[0028] The AC output filter 5 is a three-phase LC filter circuit configured with reactors 18 (reactors 18U, 18V, 18W) and capacitors 19 (capacitors 19U, 19V, 19W). First terminals of reactors 18U, 18V, 18W are connected to the three output nodes of inverter 4, respectively, and second terminals thereof are connected to a U-phase terminal TU, a V-phase terminal TV, and a W-phase terminal TW of load 42.

[0029] The positive electrodes of capacitors 19U, 19V, 19W are connected to the second terminals of reactors 18U, 18V, 18W, and their negative electrodes are both connected to neutral line L4. AC output filter 5 is a low-pass filter that passes the commercial frequency three-phase AC power generated by inverter 4 and prevents a switching frequency signal generated by inverter 4 from passing to load 42. A neutral terminal TNA of load 42 is connected to neutral line L4. Load 42 is driven by the three-phase AC power supplied from uninterruptible power supply 100.

[0030] Battery B1 (power storage device) is connected between the two low-voltage nodes of DC voltage converter 6. DC voltage converter 6 is controlled by control device 10, and when commercial AC power supply 41 is normal, DC power generated by converter 3 is stored in battery B1. At that time, control device 10 controls DC voltage converter 6 so that terminal voltage VB of battery B1 becomes equal to reference battery voltage VBR.

[0031] Furthermore, in the event of a power outage of commercial AC power supply 41, DC voltage converter 6 supplies DC power from battery B1 to inverter 4 via DC lines L1 to L3. At that time, control device 10 controls DC voltage converter 6 so that the sum of DC voltages Ep and En, DC voltage VDC = Ep + En, becomes reference DC voltage VDCR.

[0032] It should be noted that a capacitor (for example, an electric double layer capacitor) may be connected to DC voltage converter 6 instead of battery B1. In the present embodiment, battery B1 is installed outside uninterruptible power supply 100, but battery B1 may also be built into uninterruptible power supply 100.

[0033] The voltage detector 31 detects instantaneous values ​​of the AC voltages VR, VS, and VT at the second terminals of the switches 1R, 1S, and 1T, and outputs three-phase voltage signals indicating the three-phase AC voltages VR, VS, and VT to the control device 10 and the power failure detector 33. The current detector 32 detects instantaneous values ​​of the AC currents IR, IS, and IT flowing into the three input nodes of the converter 3, and outputs three-phase current signals indicating the three-phase AC currents IR, IS, and IT to the control device 10.

[0034] The power failure detector 33 determines whether a power failure has occurred in the commercial AC power supply 41 based on the three-phase voltage signal from the voltage detector 31, and outputs a power failure signal PC indicating the determination result. When the commercial AC power supply 41 is operating normally, the power failure signal PC is at an inactive "L" level. When a power failure occurs in the commercial AC power supply 41, the power failure signal PC is at an active "H" level. The power failure signal PC is provided to the control device 10.

[0035] Voltage detector 34 detects the voltage Ep across the terminals of capacitor C1 and outputs a signal indicating the detected voltage Ep to control device 10. Voltage detector 35 detects the voltage En across the terminals of capacitor C2 and outputs a signal indicating the detected voltage En to control device 10. Voltage detector 36 detects the voltage VB across the terminals of battery B1 and outputs a signal indicating the detected voltage VB to control device 10. Current detector 37 detects the current IB output from battery B1 and outputs a signal indicating the detected current IB to control device 10.

[0036] The control device 10 receives a three-phase voltage signal from the voltage detector 31, a three-phase current signal from the current detector 32, signals from the voltage detectors 34 to 36, a signal from the current detector 37, and a power outage signal PC from the power outage detector 33, and controls the entire uninterruptible power supply 100.

[0037] The converter 3, the inverter 4, and the DC voltage converter 6 are configured with semiconductor switches including semiconductor switching elements. In this embodiment, IGBTs (Insulated Gate Bipolar Transistors) are used as the semiconductor switching elements. Pulse Width Modulation (PWM) control can be applied as a control method for the semiconductor switching elements.

[0038] FIG. 2 is a block diagram showing an example of the hardware configuration of the control device 10. As shown in FIG. 2, the control device 10 includes a CPU (Central Processing Unit) 102, a memory 104, and an input / output (I / O) circuit 106. The CPU 102, the memory 104, and the I / O circuit 106 can exchange data with each other via a bus 108. Programs are stored in a partial area of ​​the memory 104, and the CPU 102 executes these programs to realize various functions described below. The I / O circuit 106 inputs and outputs signals and data to and from the outside of the control device 10.

[0039] 2, at least a part of the control device 10 may be configured using a circuit such as an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit), or at least a part of the control device 10 may be configured using an analog circuit.

[0040] (Example of Converter Circuit Configuration) Fig. 3 is a circuit diagram showing an example of the configuration of converter 3 shown in Fig. 1. As shown in Fig. 3, converter 3 includes an R-phase arm 3R, an S-phase arm 3S, and a T-phase arm 3T. Since each of the phase arms 3R, 3S, and 3T of converter 3 has the same circuit configuration, the circuit configuration of R-phase arm 3R will be described as a representative example.

[0041] As shown in Fig. 3, reactor 12R includes reactors 12RA and 12RB. R-phase arm 3R includes three-level circuits 3A and 3B. A first terminal of reactor 12RA is connected to a second terminal of switch 1R, and a second terminal of reactor 12RA is connected to an input node 3a of three-level circuit 3A. A first terminal of reactor 12RB is connected to a second terminal of switch 1R, and a second terminal of reactor 12RB is connected to an input node 3b of three-level circuit 3B. Reactor 12RA corresponds to an example of a "first reactor," and reactor 12RB corresponds to an example of a "second reactor."

[0042] The three-level circuit 3A includes IGBTs Q1A to Q4A and diodes D1A to D4A. The collector of IGBT Q1A is connected to DC line L1, and its emitter is connected to input node 3a. The emitters of IGBTs Q2A and Q4A are connected to each other, and their collectors are connected to input node 3a and DC line L2, respectively. The collector of IGBT Q3A is connected to input node 3a, and its emitter is connected to DC line L3. Diodes D1A to D4A are connected in anti-parallel to IGBTs Q1A to Q4A, respectively.

[0043] Three-level circuit 3A corresponds to one embodiment of a "first multilevel circuit." IGBT Q1A and diode D1A form a "first switch," IGBTs Q2A and Q4A and diodes D2A and D4A form a "second switch," and IGBT Q3A and diode D3A form a "third switch."

[0044] The three-level circuit 3B includes IGBTs Q1B to Q4B and diodes D1B to D4B. The collector of IGBT Q1B is connected to DC line L1, and its emitter is connected to input node 3b. The emitters of IGBTs Q2B and Q4B are connected to each other, and their collectors are connected to input node 3b and DC line L2, respectively. The collector of IGBT Q3B is connected to input node 3b, and its emitter is connected to DC line L3. Diodes D1B to D4B are connected in anti-parallel to IGBTs Q1B to Q4B, respectively.

[0045] Three-level circuit 3B corresponds to one embodiment of a "second multilevel circuit." IGBT Q1B and diode D1B form a "fourth switch," IGBTs Q2B and Q4B and diodes D2B and D4B form a "fifth switch," and IGBT Q3B and diode D3B form a "sixth switch."

[0046] (Circuit Configuration Example of DC Voltage Converter) Fig. 4 is a circuit diagram showing a configuration example of DC voltage converter 6 shown in Fig. 1. As shown in Fig. 4, DC voltage converter 6 includes a semiconductor switch 21 and a reactor 22. Semiconductor switch 21 is configured as a three-level circuit, and includes IGBTs Q1D to Q4D connected in series between DC lines L1 and L3, and diodes D1D to D4D connected in anti-parallel to IGBTs Q1D to Q4D, respectively.

[0047] Reactor 22 includes reactors 22P and 22N. Reactor 22P is connected between the connection point of IGBTs Q1D and Q2D and the positive electrode of battery B1. Reactor 22N is connected between the connection point of IGBTs Q3D and Q4D and the negative electrode of battery B1. Note that reactor 22 may include either reactor 22P or 22N.

[0048] <Control Configuration of Uninterruptible Power Supply> FIG. 5 is a block diagram showing the portion of the control device 10 that is related to the control of the converter 3 and the DC voltage converter 6. As shown in FIG.

[0049] As shown in FIG. 5, the control device 10 includes an adder 51 , a subtractor 52 , a first control circuit 53 , a second control circuit 54 , a switching circuit 55 , and a control circuit 80 .

[0050] An adder 51 adds the inter-terminal voltages Ep and En of the capacitors C1 and C2 detected by the voltage detectors 34 and 35 to obtain the DC voltage VDC between the DC lines L1 and L3 (VDC=Ep+En). The DC voltage VDC is supplied to each of the control circuits 53 and 80.

[0051] Subtractor 52 subtracts the voltage En across capacitor C2 detected by voltage detector 35 from the voltage Ep across capacitor C1 detected by voltage detector 34 to obtain a DC voltage ΔE=Ep−En, which is the difference between the voltages Ep and En across capacitors C1 and C2. The DC voltage ΔE is supplied to each of control circuits 53, 54, and 80.

[0052] The first control circuit 53 controls the converter 3 based on the three-phase voltage signal from the voltage detector 31, the three-phase current signal from the current detector 32, the signal indicating the DC voltage VDC from the adder 51, and the signal indicating the DC voltage ΔE from the subtractor 52. Specifically, the first control circuit 53 controls the converter 3 so that the phases of the three-phase AC voltages VR, VS, VT and the phases of the three-phase AC currents IR, IS, IT match, the DC voltage VDC becomes the reference DC voltage VDCR, and the DC voltage ΔE becomes zero.

[0053] The second control circuit 54 controls the converter 3 based on the signal indicating the DC voltage ΔE from the subtractor 52. Specifically, the second control circuit 54 controls the converter 3 so that the DC voltage ΔE becomes zero.

[0054] The switching circuit 55 is provided between the control circuits 53, 54 and the converter 3. The switching circuit 55 connects one of the control circuits 53, 54 and the converter 3 based on a power failure signal PC from the power failure detector 33. Specifically, when the power failure signal PC is at an inactive "L" level (when the commercial AC power supply 41 is normal), the switching circuit 55 connects the first control circuit 53 and the converter 3. When the power failure signal PC is at an active "H" level (when the commercial AC power supply 41 is in a power failure), the switching circuit 55 connects the second control circuit 54 and the converter 3.

[0055] The switching circuit 55 further controls the on / off of the switches 1R, 1S, and 1T based on a power failure signal PC from the power failure detector 33. Specifically, the switching circuit 55 turns on the switches 1R, 1S, and 1T when the power failure signal PC is at the inactivation level "L" (when the commercial AC power supply 41 is normal), and turns off the switches 1R, 1S, and 1T when the power failure signal PC is at the activation level "H" (when the commercial AC power supply 41 is in a power failure).

[0056] (Configuration of First Control Circuit) Fig. 6 is a block diagram showing the configuration of first control circuit 53 shown in Fig. 5. As shown in Fig. 6, first control circuit 53 includes a voltage command generating circuit 60, a balance control circuit 70, adders 71A to 71C, and a PWM circuit 72.

[0057] The voltage command generating circuit 60 includes a reference voltage generating circuit 61, subtractors 62, 66A to 66C, a DC voltage control circuit 63, a sine wave generating circuit 64, multipliers 65A to 65C, a current control circuit 67, and adders 68A to 68C.

[0058] The reference voltage generation circuit 61 generates a reference DC voltage VDCR. The subtractor 62 calculates the voltage difference ΔVDC=VDCR-VDC between the reference DC voltage VDCR and the DC voltage VDC from the adder 51. The DC voltage control circuit 63 calculates a current command value I* for controlling the current flowing to the input side of the converter 3 so that the voltage ΔVDC becomes zero. The DC voltage control circuit 63 calculates the current command value I* by, for example, performing a proportional operation or a proportional-integral operation on ΔVDC.

[0059] The sine wave generating circuit 64 outputs a sine wave signal in phase with the R-phase voltage VR of the commercial AC power supply 41, a sine wave signal in phase with the S-phase voltage VS of the commercial AC power supply 41, and a sine wave signal in phase with the T-phase voltage VT of the commercial AC power supply 41. The three sine wave signals are input to multipliers 65A to 65C, respectively, and multiplied by a current command value I*. As a result, current command values ​​IR*, IS*, IT* in phase with the three-phase AC voltages VR, VS, VT of the commercial AC power supply 41 are generated.

[0060] Subtractor 66A calculates the difference between current command value IR* and R-phase current IR detected by current detector 32R. Subtractor 66B calculates the difference between current command value IS* and S-phase current IS detected by current detector 32S. Subtractor 66C calculates the difference between current command value IT* and T-phase current IT detected by current detector 32T.

[0061] The current control circuit 67 generates voltage command values ​​VRa*, VSa*, and VTa* as voltages to be applied to the reactor 12 so that the difference between the current command value IR* and the R-phase current IR, the difference between the current command value IS* and the S-phase current IS, and the difference between the current command value IT* and the T-phase current IT all become 0. The current control circuit 67 generates the voltage command value, for example, by amplifying the difference between the current command value and the current value detected by the current detector 32 in accordance with proportional control or proportional-integral control.

[0062] Adder 68A generates a voltage command value VR0* by adding together voltage command value VRa* and the R-phase voltage VR detected by voltage detector 31. Adder 71B generates a voltage command value VS0* by adding together voltage command value VSa* and the S-phase voltage VS detected by voltage detector 31. Adder 68C adds together voltage command value VTa* and the T-phase voltage VT detected by voltage detector 31 to generate a voltage command value VT0*.

[0063] In this way, voltage command generating circuit 60 receives three-phase AC voltages VR, VS, VT detected by voltage detector 31, three-phase AC currents IR, IS, IT detected by current detector 32, and DC voltage VDC calculated by adder 51, and generates voltage command values ​​VR0*, VS0*, VT0* corresponding to the R phase, S phase, and T phase, respectively.

[0064] The balance control circuit 70 generates a voltage command value V1* based on the DC voltage ΔE=Ep-En from the subtractor 52. For example, the balance control circuit 70 generates the voltage command value V1* by performing a proportional operation or a proportional-integral operation on ΔE. If ΔE=Ep-En>0, the voltage command value V1* is generated so that the charging time of the capacitor C1 is shorter than the charging time of the capacitor C2. If ΔE=Ep-En<0, the voltage command value V1* is generated so that the charging time of the capacitor C1 is longer than the charging time of the capacitor C2.

[0065] Adder 71A adds voltage command values ​​VR0* and V1* to generate a voltage command value VR*. Adder 71B adds voltage command values ​​VS0* and V1* to generate a voltage command value VS*. Adder 71C adds voltage command values ​​VT0* and V1* to generate a voltage command value VT*. The voltage command values ​​VR*, VS*, and VT* are sinusoidal signals at commercial frequency.

[0066] PWM circuit 72 outputs signals based on voltage command values ​​VR*, VS*, VT* to make three-phase AC voltages VR, VS, VT detected by voltage detector 31 equal to voltage command values ​​VR*, VS*, VT*, respectively. These signals are PWM signals φ1A to φ4A, φ1B to φ4B for controlling the on / off of eight IGBTs Q1A to Q4A, Q1B to Q4B included in each phase arm of converter 3.

[0067] Fig. 7 is a block diagram showing the configuration of the PWM circuit 72 shown in Fig. 6. Fig. 7 shows the configuration of the portion related to the control of the R-phase arm 3R.

[0068] As shown in FIG. 7, the PWM circuit 72 includes an oscillator 90, triangular wave generators 91 to 94, comparators 95 to 98, buffers 110, 112, 114, and 116, and NOT circuits 111, 113, 115, and 117.

[0069] An oscillator 90 outputs a clock signal having a frequency sufficiently higher than the commercial frequency. Triangular wave generators 91 to 94 output triangular wave signals Cu1a, Cu1b, Cu2a, and Cu2b, respectively, having the same frequency as the output clock signal of oscillator 90.

[0070] The triangular wave signals Cu1a and Cu1b are in-phase signals. The triangular wave signals Cu2a and Cu2b are in-phase signals. The triangular wave signals Cu1a and Cu2a are out of phase. In the example of FIG. 7, the triangular wave signal Cu2a is 180° out of phase with the triangular wave signal Cu1a.

[0071] Comparator 95 compares the voltage command value VR* with the triangular wave signal Cu1a from triangular wave generator 91 to determine whether they are high or low, and outputs a PWM signal φ1A indicative of the comparison result. Buffer 110 provides PWM signal φ1A to three-level circuit 3A. NOT circuit 111 inverts PWM signal φ1A to generate PWM signal φ2A, which is provided to three-level circuit 3A. IGBTs Q1A and Q2A are turned on when PWM signals φ1A and φ2A are at "H" level, and are turned off when PWM signals φ1A and φ2A are at "L" level, respectively.

[0072] Comparator 96 compares the voltage command value VR* with the triangular wave signal Cu1b from triangular wave generator 92, and outputs a PWM signal φ3A indicating the comparison result. Buffer 112 provides PWM signal φ3A to three-level circuit 3A. NOT circuit 113 inverts PWM signal φ3A to generate PWM signal φ4A, which is provided to three-level circuit 3A. IGBTs Q3A and Q4A are turned on when PWM signals φ3A and φ4A are at "H" level, and are turned off when PWM signals φ3A and φ4A are at "L" level, respectively.

[0073] Comparator 97 compares the voltage command value VR* with the triangular wave signal Cu2a from triangular wave generator 93 to determine whether they are high or low, and outputs a PWM signal φ1B indicative of the comparison result. Buffer 114 provides PWM signal φ1B to three-level circuit 3B. NOT circuit 115 inverts PWM signal φ1B to generate PWM signal φ2B, which is provided to three-level circuit 3B. IGBTs Q1B and Q2B are turned on when PWM signals φ1B and φ2B are at "H" level, respectively, and are turned off when PWM signals φ1B and φ2B are at "L" level, respectively.

[0074] Comparator 98 compares the voltage command value VR* with the triangular wave signal Cu2b from triangular wave generator 94 to determine whether they are high or low, and outputs a PWM signal φ3B indicative of the comparison result. Buffer 116 provides PWM signal φ3b to three-level circuit 3B. NOT circuit 117 inverts PWM signal φ3B to generate PWM signal φ4B, which is provided to three-level circuit 3B. IGBTs Q3B and Q4B are turned on when PWM signals φ3B and φ4B are at "H" level, respectively, and are turned off when PWM signals φ3B and φ4B are at "L" level, respectively.

[0075] Fig. 8 is a time chart showing the waveforms of the voltage command value VR*, the triangular wave signals Cu1a, Cu1b, Cu2a, and Cu2b, and the PWM signals φ1A to φ4A and φ1B to φ4B shown in Fig. 7. In Fig. 8, (A) shows the waveforms of the voltage command value VR* and the triangular wave signals Cu1a, Cu1b, Cu2a, and Cu2b, (B) to (E) show the waveforms of the PWM signals φ1A, φ3A, φ4A, and φ2A, respectively. (F) to (I) show the waveforms of the PWM signals φ1B, φ3B, φ4B, and φ2B, respectively.

[0076] 8A, the voltage command value VR* is a sine wave signal of commercial frequency. The voltage command value VR* is the voltage command value (VR*=VR0*) when Ep=En (i.e., when not corrected by the balance control circuit 70).

[0077] The minimum values ​​of the triangular wave signals Cu1a and Cu2a are 0 V, and their maximum values ​​are higher than the positive peak value of the voltage command value VR*. The maximum values ​​of the triangular wave signals Cu1b and Cu2b are 0 V, and their minimum values ​​are lower than the negative peak value of the voltage command value VR*. The triangular wave signals Cu1a and Cu1b are in-phase signals. The triangular wave signals Cu2a and Cu2b are in-phase signals. The triangular wave signal Cu2a is 180° out of phase with the triangular wave signal Cu1a. The triangular wave signal Cu2b is 180° out of phase with the triangular wave signal Cu1b.

[0078] 8A and 8B, when the level of the triangular wave signal Cu1a is higher than the voltage command value VR* (times t0 to t1, t2 to t3, t4 to t9, ...), the PWM signal φ1A is at the "L" level. Conversely, when the level of the triangular wave signal Cu1a is lower than the voltage command value VR* (times t1 to t2, t3 to t4, ...), the PWM signal φ1A is at the "H" level. As shown in FIGS. 8B and 8E, the PWM signal φ2A is an inverted version of the PWM signal φ1A.

[0079] 8A and 8C, when the level of the triangular wave signal Cu1b is lower than the voltage command value VR* (times t0 to t5, t6 to t7, ...), the PWM signal φ3A is at the "L" level. Conversely, when the level of the triangular wave signal Cu1b is higher than the voltage command value VR* (times t5 to t6, t7 to t8, ...), the PWM signal φ3A is at the "H" level. As shown in FIGS. 8C and 8D, the PWM signal φ4A is an inverted version of the PWM signal φ3A.

[0080] 8A and 8F, when the level of the triangular wave signal Cu2a is higher than the voltage command value VR* (times t0 to t21, t22 to t23, t24 to t29, ...), the PWM signal φ1B is at the "L" level. Conversely, when the level of the triangular wave signal Cu2a is lower than the voltage command value VR* (times t21 to t22, t23 to t24, ...), the PWM signal φ1B is at the "H" level. As shown in FIGS. 8F and 8I, the PWM signal φ2B is an inverted version of the PWM signal φ1B.

[0081] 8A and 8G, when the level of the triangular wave signal Cu2b is lower than the voltage command value VR* (times t0 to t25, t26 to t27, ...), the PWM signal φ3B is at the "L" level. Conversely, when the level of the triangular wave signal Cu2b is higher than the voltage command value VR* (times t25 to t26, t27 to t28, ...), the PWM signal φ3B is at the "H" level. As shown in FIGS. 8G and 8H, the PWM signal φ4B is an inverted version of the PWM signal φ3B.

[0082] 8A to 8I show the voltage command value VR* and the waveforms of the signals Cu1a, Cu1b, Cu2a, Cu2b, φ1A to φ4A, and φ1B to φ4B corresponding to the R phase, but the voltage command values ​​and signal waveforms corresponding to the S phase and T phase are similar. However, the voltage command values ​​and signal waveforms corresponding to the R phase, S phase, and T phase are shifted by 120°.

[0083] In the first embodiment, in each phase arm, two parallel-connected three-bell circuits 3A, 3B are interleaved. As shown in Fig. 8, triangular wave signals Cu1a, Cu1b and triangular wave signals Cu2a, Cu2b that are out of phase with the triangular wave signals Cu1a, Cu1b are prepared. The comparison results of the voltage command value VR* and the triangular wave signals Cu1a, Cu1b are defined as PWM signals φ1A to φ4A, and the comparison results of the voltage command value VR* and the triangular wave signals Cu2a, Cu2b are defined as PWM signals φ1B to φ4B.

[0084] In this way, by intentionally shifting the phases of the PWM signals φ1A to φ4B and the PWM signals φ1B to φ4B, the ripples (fluctuations in current that occur during switching) generated by each three-level circuit can be canceled out by each other.

[0085] This reduces the ripple component contained in the sum of the output currents of the three-level circuits 3A and 3B, and doubles the effective frequency of the ripple component, thereby enabling a reduction in the size of the AC input filter 2. Furthermore, because the current is divided into the three-level circuits 3A and 3B in each phase arm, the power loss per IGBT is reduced, resulting in easier thermal design of the IGBT.

[0086] It can be seen that the switching patterns of the IGBTs in each bridge circuit are composed of three modes. Fig. 9 is a diagram showing the switching patterns of the four IGBTs included in each bridge circuit. Fig. 9 also shows the operation of the bridge circuit 3A in each mode.

[0087] FIG. 9A shows mode 1. In mode 1, IGBTs Q1A and Q4A are turned on, IGBTs Q2A and Q3A are turned off, and positive-side capacitor C1 is charged or discharged. FIG. 9B shows mode 2. In mode 2, IGBTs Q2A and Q4A are turned on, IGBTs Q1A and Q3A are turned off, and the charge states of positive-side capacitor C1 and negative-side capacitor C2 do not change significantly. FIG. 9C shows mode 3. In mode 3, IGBTs Q2A and Q3A are turned on, IGBTs Q1A and Q4A are turned off, and negative-side capacitor C2 is charged or discharged. Note that the arrows in FIGS. 9A and 9C indicate the direction of current flow during charging. During discharging, current flows in the opposite direction to the arrows.

[0088] Returning to FIG. 8 , when Ep<En, the voltage command value VR* is the sum of the voltage command value VR0* and the voltage command value V1*. The voltage command value V1* is positive when Ep<En. The PWM circuit 72 determines the switching pattern of the four IGBTs included in each bridge circuit by comparing the voltage command value VR* with the triangular wave signals Cu1a, Cu1b, Cu2a, and Cu2b. When Ep<En, the time in mode 1 (charging time of capacitor C1) is longer and the time in mode 3 (charging time of capacitor C2) is shorter than when Ep=En. Therefore, ΔE=Ep-En decreases.

[0089] When Ep > En, the voltage command value VR* is the sum of the voltage command value VR0* and the voltage command value V1*. When Ep > En, the voltage command value V1* becomes negative. In the PWM circuit 72, the voltage command value VR* is compared with the triangular wave signals Cu1a, Cu1b, Cu2a, and Cu2b to determine the switching pattern of the four IGBTs included in each bridge circuit. When Ep > En, the time in mode 1 (charging time of capacitor C1) becomes shorter and the time in mode 3 (charging time of capacitor C2) becomes longer than when Ep = En. Therefore, ΔE = Ep - En decreases.

[0090] In this way, first control circuit 53 generates PWM signals φ1A to φ4A and φ1B to φ4B so that the phases of three-phase AC voltages VR, VS, and VT match the phases of three-phase AC currents IR, IS, and IT, DC voltage VDC becomes reference DC voltage VDCR, and DC voltage ΔE becomes 0. When power outage signal PC is at the inactivation level "L" (when commercial AC power supply 41 is functioning normally), first control circuit 53 and converter 3 are connected by switching circuit 55. As a result, PWM signals φ1A to φ4A and φ1B to φ4B are applied via switching circuit 55 to the gates of IGBTs Q1A to Q4A and Q1B to Q4B of R-phase arm 3R, respectively.

[0091] (Configuration of Second Control Circuit) Fig. 10 is a time chart showing the operation of the second control circuit 54 shown in Fig. 5. Fig. 10 shows the control of one phase of the converter 3 (for example, the R-phase arm 3R) when Ep > En. Fig. 10(A) shows the waveforms of Ep and En. Figs. 10(B) to 10(E) show the waveforms of the PWM signals φ1A to φ4 and φ1B to φ4B generated by the second control circuit 54.

[0092] If Ep>En (time t1), the PWM signal φ1A is set to the "H" level and the "L" level at a predetermined frequency fc. The PWM signals φ2A to φ4A, φ1B, and φ3B are fixed to the "L" level, and the PWM signals φ2B and φ4B are fixed to the "H" level.

[0093] 11 and 12 are equivalent circuit diagrams showing the operation of one phase of the converter 3 when Ep > En. As shown in FIG. 11 , when the PWM signal φ1A is set to the "H" level and the PWM signals φ2B and φ4B are set to the "H" level, the IGBT Q1A (first switch) is turned on and the IGBTs Q2B and Q4B (fifth switch) are turned on. As a result, as shown by the arrows in FIG. 11 , a current flows from the positive electrode of the capacitor C1 through the DC line L1, the IGBT Q1A, the reactors 12RA and 12RB, the IGBT Q2B, the diode D4B, and the DC line L2 to the negative electrode of the capacitor C1. This discharges the capacitor C1, and the voltage Ep across the capacitor C1 decreases. At this time, electromagnetic energy is stored in the reactors 12RA and 12RB.

[0094] Next, when PWM signal φ1A is set to the "L" level, IGBT Q1A (first switch) is turned off, as shown in Fig. 12. As a result, current flows from reactor 12RA through reactor 12RB, IGBT Q2B, diode D4B, DC line L2, capacitor C2, DC line L3, and diode D3A to reactor 12RA, as shown by the arrows in Fig. 12. At this time, electromagnetic energy is released from reactors 12RA and 12RB, charging capacitor C2 and increasing voltage En across capacitor C2.

[0095] In this way, by repeatedly setting PWM signal φ1A to the "H" level and "L" level to turn IGBT Q1A (first switch) on and off, ΔE = Ep - En gradually decreases. When ΔE = 0 (time t2), PWM signals φ1A, φ2B, and φ4B are fixed at the "L" level. That is, IGBTs Q1A to Q4A and Q1B to Q4B are all turned off, and operation of converter 3 is stopped.

[0096] FIG. 13 is a time chart showing the operation of the second control circuit 54 shown in FIG. 13 illustrates the control of one phase (e.g., the R-phase arm 3R) of the converter 3 when Ep<En. FIG. 13(A) shows the waveforms of Ep and En. FIG. 13(B) to (E) show the waveforms of the PWM signals φ1A to φ4 and φ1B to φ4B generated by the second control circuit 54.

[0097] If Ep<En (time t1), the PWM signal φ3A is set to the “H” level and the “L” level at a predetermined frequency fc. The PWM signals φ1A, φ2A, φ4A, φ1B, and φ3B are fixed to the “L” level, and the PWM signals φ2B and φ4B are fixed to the “H” level.

[0098] 14 and 15 are equivalent circuit diagrams showing the operation of one phase of converter 3 when Ep<En. As shown in FIG. 14 , when PWM signal φ3A is set to the “H” level and PWM signals φ2B and φ4B are set to the “H” level, IGBT Q3A (third switch) is turned on and IGBTs Q2B and Q4B (fifth switch) are turned on. As a result, as shown by the arrows in FIG. 14 , current flows from the positive electrode of capacitor C2 through DC line L2, IGBT Q4B, diode D2B, reactors 12RB and 12RA, IGBT Q3A, and DC line L3 to the negative electrode of capacitor C2. This discharges capacitor C2, reducing the voltage En across capacitor C2. At this time, electromagnetic energy is stored in reactors 12RA and 12RB.

[0099] Next, when PWM signal φ3A is set to the "L" level, IGBT Q3A (third switch) is turned off, as shown in Fig. 15. As a result, current flows from reactor 12RB to reactor 12RA via reactor 12RA, diode D1A, DC line L1, capacitor C1, DC line L2, IGBT Q4B, diode D2B, and reactor 12RB, as shown by the arrows in Fig. 15. At this time, electromagnetic energy is released from reactors 12RA and 12RB, charging capacitor C1 and increasing voltage Ep across capacitor C1.

[0100] In this way, by repeatedly setting PWM signal φ3A to the "H" level and "L" level to turn IGBT Q3A (third switch) on and off, ΔE = Ep - En gradually decreases. When ΔE = 0 (time t2), PWM signals φ3A, φ2B, and φ4B are fixed at the "L" level. That is, IGBTs Q1A to Q4A and Q1B to Q4B are all turned off, and operation of converter 3 is stopped.

[0101] When power failure signal PC is at the activated "H" level (when commercial AC power supply 41 is experiencing a power failure), second control circuit 54 is connected to converter 3 by switching circuit 55. As a result, PWM signals φ1A to φ4A and φ1B to φ4B are applied via switching circuit 55 to the gates of IGBTs Q1A to Q4A and Q1B to Q4B of R-phase arm 3R, respectively.

[0102] (Balance Control by Converter) Next, a description will be given of balance control by the converter 3 when the commercial AC power supply 41 is normal. When the commercial AC power supply 41 is normal, the first control circuit 53 and the converter 3 are connected by the switching circuit 55.

[0103] When Ep<En, the first control circuit 53 generates voltage command values ​​VR*, VS*, and VT* by adding a positive voltage command value V1* to the voltage command values ​​VR0*, VS0*, and VT0* to balance the voltages of the capacitors C1 and C2. When Ep>En, the first control circuit 53 generates voltage command values ​​VR*, VS*, and VT* by adding a negative voltage command value V1* to the voltage command values ​​VR0*, VS0*, and VT0* to balance the voltages of the capacitors C1 and C2.

[0104] In the PWM circuit 72, the voltage command values ​​VR*, VS*, VT* and the triangular wave signals Cu1a, Cu1b, Cu2a, Cu2b are compared in level to generate PWM signals φ1A to φ4A and φ1B to φ4B. Capacitor C1 is charged during periods when the voltage command values ​​VR*, VS*, VT* are positive. Capacitor C2 is charged during periods when the voltage command values ​​VR*, VS*, VT* are negative.

[0105] When Ep<En, the charging time of capacitor C1 is longer than the charging time of capacitor C2 compared to when Ep=En, so that voltage Ep can be made higher than voltage En. Since voltage command value V1* is output so that Ep=En, the voltages of capacitors C1 and C2 match and are balanced.

[0106] When Ep>En, the charging time of capacitor C2 is longer than the charging time of capacitor C1 compared to when Ep=En, so that voltage En can be made higher than voltage Ep. Since voltage command value V1* is output so that Ep=En, the voltages of capacitors C1 and C2 match and are balanced.

[0107] Next, the balance control by the converter 3 when the commercial AC power supply 41 is powered down will be described.

[0108] When Ep>En, in order to balance the voltages of the capacitors C1 and C2, the second control circuit 54 turns on the IGBTs Q2B and Q4B (fifth switches) of the three-level circuit 3B and performs an operation of turning on and off the IGBT Q1A (first switch) of the three-level circuit 3A at a predetermined frequency fc, as shown in FIG. 10 .

[0109] When IGBT Q1A is turned on, current flows out of capacitor C1, decreasing the voltage Ep across capacitor C1, and electromagnetic energy is stored in reactors 12RA and 12RB, as shown in FIG. 11. When IGBT Q1A is turned off, the electromagnetic energy stored in reactors 12RA and 12RB is released, charging capacitor C2 and increasing the voltage En across capacitor C2, as shown in FIG. By turning IGBT Q1A on and off at a predetermined frequency fc, ΔE = Ep - En gradually decreases. When ΔE = 0, IGBTs Q1A to Q4A and Q1B to Q4B are turned off, and converter 3 stops operating.

[0110] When Ep<En, in order to balance the voltages of the capacitors C1 and C2, the second control circuit 54 turns on the IGBTs Q2B and Q4B (fifth switches) of the three-level circuit 3B and turns on and off the IGBT Q3A (third switch) of the three-level circuit 3A at a predetermined frequency fc, as shown in FIG. 13 .

[0111] When IGBT Q3A is turned on, current flows out of capacitor C2, decreasing the voltage En across capacitor C2, and electromagnetic energy is stored in reactors 12RA and 12RB, as shown in FIG. 14. When IGBT Q3A is turned off, the electromagnetic energy stored in reactors 12RA and 12RB is released, charging capacitor C1 and increasing the voltage Ep across capacitor C1, as shown in FIG. By turning IGBT Q3A on and off at a predetermined frequency fc, ΔE = Ep - En gradually decreases. When ΔE = 0, IGBTs Q1A to Q4A and Q1B to Q4B are turned off, and converter 3 stops operating.

[0112] (Configuration of Control Circuit) Returning to FIG. 5 , control circuit 80 controls DC voltage converter 6 based on power outage signal PC from power outage detector 33, a signal indicating battery voltage VB from voltage detector 36, a signal indicating battery current IB from current detector 37, and a signal indicating DC voltage VDC from adder 51.

[0113] Specifically, when the power failure signal PC is at the inactivation level "L" (when the commercial AC power supply 41 is healthy), the control circuit 80 controls the DC voltage converter 6 so that a battery current IB at a level corresponding to the DC voltage VDC flows from the capacitors C1 and C2 to the battery B1, and the battery voltage VB becomes the reference battery voltage VBR.

[0114] When power failure signal PC is at the "H" level, which is the activation level (when commercial AC power supply 41 is powered down), control circuit 80 controls DC voltage converter 6 so that battery current IB at a level corresponding to battery voltage VB flows from battery B1 to capacitors C1 and C2, and DC voltage VDC becomes reference DC voltage VDCR. In other words, this differs from the balance control described in Patent Documents 1 and 2 in that balance control by DC voltage converter 6 is not performed when commercial AC power supply 41 is powered down.

[0115] Fig. 16 is a block diagram showing the configuration of the control circuit 80 shown in Fig. 5. As shown in Fig. 16, the control circuit 80 includes control units 81 and 82.

[0116] The control unit 81 is activated when the power outage signal PC is at the inactivation level "L" (when the commercial AC power supply 41 is healthy), and controls the DC voltage converter 6 so that a current IB of a level corresponding to the DC voltage VDC flows from the capacitors C1 and C2 to the battery B1, and the terminal voltage VB of the battery B1 becomes the reference battery voltage VBR.

[0117] Control unit 82 is activated when power failure signal PC is at the "H" level, which is the activation level (when commercial AC power supply 41 is powered down), and controls DC voltage converter 6 so that current IB at a level corresponding to voltage VB between terminals of battery B1 flows from battery B1 to capacitors C1 and C2, and DC voltage VDC becomes reference DC voltage VDCR. Specifically, control unit 82 includes a reference voltage generation circuit 83, subtractors 84 and 86, a voltage control circuit 85, a current control circuit 87, and a PWM circuit 88.

[0118] The reference voltage generating circuit 83 generates a reference DC voltage VDCR. The subtractor 84 calculates a voltage ΔVDC which is the difference between the reference DC voltage VDCR and the DC voltage VDC detected by the adder 51.

[0119] Voltage control circuit 85 calculates a current command value IB* at a level corresponding to voltage ΔVDC based on voltage VB across battery B1 detected by voltage detector 36. Voltage control circuit 85 calculates current command value IB* by, for example, performing a proportional operation or a proportional-integral operation on ΔVDC.

[0120] Subtractor 86 determines the deviation ΔIB=IB*−IB between current command value IB* generated by voltage control circuit 85 and current value IB of battery B1 detected by current detector 37. Current control circuit 87 generates voltage command value V* based on the deviation ΔIB between current command value IB* and current value IB.

[0121] When power failure signal PC is at the "H" level, which is the activation level (when commercial AC power supply 41 experiences a power failure), PWM circuit 88 is activated and outputs a signal for driving the four IGBTs included in semiconductor switch 21 based on voltage command value V*. DC voltage converter 6 is controlled by a signal from PWM circuit 88, and supplies DC power from battery B1 to inverter 4.

[0122] When power failure signal PC is at the inactivation level "L" (when commercial AC power supply 41 is functioning normally), PWM circuit 88 is deactivated and does not perform PWM control of DC voltage converter 6. When commercial AC power supply 41 is functioning normally, DC voltage converter 6 is controlled by control unit 81 and stores DC power in battery B1.

[0123] <Operation of Uninterruptible Power Supply> Next, the operation of uninterruptible power supply 100 according to the first embodiment will be described.

[0124] When commercial AC power supply 41 is operating normally, switch 1 is turned on, and three-phase AC power from commercial AC power supply 41 is supplied to converter 3 via switch 1 and AC input filter 2 and converted to DC power by converter 3. The DC power is stored in battery B1 by DC voltage converter 6 and is then converted to three-phase AC power by inverter 4. The three-phase AC power generated by inverter 4 is supplied to load 42 via AC output filter 5 to drive load 42.

[0125] At this time, the converter 3 is controlled by the first control circuit 53 so that the DC voltage VDC = Ep + En, which is the sum of the inter-terminal voltages Ep, En of the capacitors C1, C2, becomes the reference DC voltage VDCR, and the DC voltage ΔE = Ep - En, which is the difference between the inter-terminal voltages Ep, En of the capacitors C1, C2, becomes zero.

[0126] During a power outage of commercial AC power supply 41, switch 1 is basically turned off, operation of converter 3 is stopped, and DC power from battery B1 is supplied to inverter 4 via DC voltage converter 6 and converted into three-phase AC power of the commercial frequency by inverter 4. The three-phase AC power generated by inverter 4 is supplied to load 42 via AC output filter 5.

[0127] At this time, the control unit 82 controls the DC voltage converter 6 so that the DC voltage VDC=Ep+En, which is the sum of the inter-terminal voltages Ep and En of the capacitors C1 and C2, becomes the reference DC voltage VDCR.

[0128] However, if the voltages Ep and En between the terminals of capacitors C1 and C2 become unbalanced, the converter 3 is started. If Ep > En, the converter 3 discharges capacitor C1 and charges capacitor C2, and if Ep < En, the converter 3 discharges capacitor C2 and charges capacitor C1, thereby reducing the DC voltage difference ΔE = Ep - En between the terminal voltages Ep and En of capacitors C1 and C2. If the DC voltage ΔE becomes 0, the converter 3 stops operating.

[0129] <Effects of First Embodiment> As described above, in the first embodiment, when commercial AC power supply 41 experiences a power outage, switch 1 is turned off to electrically disconnect commercial AC power supply 41 from AC input filter 2, and converter 3 is controlled to reduce DC voltage ΔE so that the difference between terminal voltages Ep and En of capacitors C1 and C2, ΔE=Ep-En, disappears. Therefore, even when the load current is small, it is possible to eliminate the imbalance between terminal voltages Ep and En of capacitors C1 and C2 when commercial AC power supply 41 experiences a power outage.

[0130] Furthermore, in the first embodiment, each phase arm of converter 3 is configured with three-level circuits 3A, 3B connected in parallel, and during a power outage of commercial AC power supply 41, three-level circuits 3A, 3B are operated to discharge or charge capacitors C1, C2, thereby reducing DC voltage ΔE. At this time, the discharging and charging of capacitors C1, C2 is achieved by storing electromagnetic energy in reactor 12 of AC input filter 2 and releasing the electromagnetic energy, respectively. According to the first embodiment, capacitors C1, C2 can be discharged or charged without using capacitor 11 of AC input filter 2 as a power buffer. Therefore, balance control by converter 3 during a power outage of commercial AC power supply 41 can be simplified.

[0131] Furthermore, according to the first embodiment, the operation of discharging capacitor 11 of AC input filter 2 is not required in order to discharge or charge capacitors C1 and C2, so that the imbalance in the inter-terminal voltages Ep and En of capacitors C1 and C2 can be quickly eliminated in the event of a power outage in commercial AC power supply 41.

[0132] Second Embodiment In the first embodiment, the configuration has been described in which the three-level circuits 3A, 3B of each phase arm of the converter 3 are operated to eliminate the imbalance between the inter-terminal voltages Ep, En of the capacitors C1, C2.

[0133] This configuration can quickly eliminate the imbalance between the terminal voltages Ep and En of the capacitors C1 and C2 when the commercial AC power supply 41 is interrupted. However, losses occur in each phase arm of the converter 3. Specifically, the losses in each phase arm include conduction losses (losses when the IGBTs and diodes are energized) and switching losses of the IGBTs. Therefore, there is a concern that the operating efficiency of the uninterruptible power supply 100 may be reduced when the commercial AC power supply 41 is interrupted.

[0134] In response to such concerns, the second embodiment is configured to change the number of phase arms of converter 3 that are operated during a power outage of commercial AC power supply 41, depending on the absolute value of DC voltage ΔE, which is the difference between inter-terminal voltages Ep and En of capacitors C1 and C2.

[0135] 17 is a flowchart showing a modified example of the balance control by the converter 3 during a power outage of the commercial AC power supply 41. The flowchart shown in FIG. 17 is executed by the second control circuit 54 shown in FIG.

[0136] 17, first, in step S01, the second control circuit 54 compares the absolute value of the DC voltage difference ΔE = Ep - En between the terminal voltages Ep and En of the capacitors C1 and C2 (hereinafter referred to as |ΔE|) with a predetermined first threshold voltage V1. The first threshold voltage V1 is a positive voltage.

[0137] If the absolute value of ΔE is greater than the first threshold voltage V1 (YES in S01), second control circuit 54 operates R-phase arm 3R, S-phase arm 3S, and T-phase arm 3T in step S04. In S04, three-level circuits 3A and 3B of each of three-phase arms 3R, 3T, and 3S are controlled so that DC voltage ΔE is eliminated.

[0138] If the absolute value of ΔE is equal to or less than the first threshold voltage V1 (NO in S01), the second control circuit 54 compares the absolute value of ΔE with a predetermined second threshold voltage V2 in step S02. The second threshold voltage V2 is a positive voltage lower than the first threshold voltage V1.

[0139] If the absolute value of ΔE is equal to or less than the first threshold voltage V1 and greater than the second threshold voltage V2 (YES in S02), the second control circuit 54 operates two of the three-phase arms (e.g., the R-phase arm 3R and the S-phase arm 3S) and stops the operation of the remaining one-phase arm (e.g., the T-phase arm 3T) in step S05. In S05, the three-level circuits 3A, 3B of the R-phase arm 3R and the S-phase arm 3S are controlled so that the DC voltage ΔE is eliminated.

[0140] If the absolute value of ΔE is equal to or less than the second threshold voltage V2 (NO in S02), the second control circuit 54 compares the absolute value of ΔE with 0 in step S03. If the absolute value of ΔE is equal to or less than the second threshold voltage V2 and greater than 0 (YES in S02), the second control circuit 54 operates one of the three-phase arms (e.g., R-phase arm 3R) and stops the operation of the remaining two-phase arms (e.g., S-phase arm 3S and T-phase arm 3T) in step S06. In S06, the three-level circuits 3A and 3B of the R-phase arm 3R are controlled so that the DC voltage ΔE is eliminated.

[0141] If the absolute value of ΔE is 0 (NO in S03), the second control circuit 54 stops the operation of the three-phase arms 3R, 3S, 3T in step S07.

[0142] As described above, according to the second embodiment, when the absolute value of the DC voltage ΔE exceeds the first threshold voltage V1, it is possible to quickly reduce the DC voltage ΔE = Ep - En by operating the three-phase arms 3R, 3S, 3T of the converter 3. Then, by reducing the number of phase arms to be operated as the absolute value of the DC voltage ΔE decreases, it is possible to reduce the loss of the converter 3 and to improve the operating efficiency of the uninterruptible power supply 100 during a power outage of the commercial AC power supply 41.

[0143] [Embodiment 3] Figure 18 is a circuit diagram showing the main parts of an uninterruptible power supply according to embodiment 3, and is a diagram to be compared with Figure 3. As shown in Figure 18, embodiment 3 differs from embodiment 1 in that each phase arm 3R, 3S, 3T of converter 3 is configured with three-level circuits 3Ax, 3Bx. Since each phase arm 3R, 3S, 3T of converter 3 has the same circuit configuration, the circuit configuration of R-phase arm 3R will be described as a representative example.

[0144] The three-level circuit 3Ax includes IGBTs Q1A to Q4A and diodes D1A to D6A. The IGBTs Q1A to Q4A are connected in series between DC lines L1 and L3. The diodes D1A to D4A are connected in anti-parallel to the IGBTs Q1A to Q4A, respectively. The diode D5A is connected to the connection point of the IGBTs Q1A and Q2A and the DC line L2. The diode D6A is connected to the connection point of the IGBTs Q3A and Q4A and the DC line L.

[0145] The diodes D1A to D4A function as freewheeling diodes, and the diodes D5A and D6A function as clamp diodes. An input node 3a of the three-level circuit 3Ax is connected to a second terminal of the reactor 12RA and to a connection point of the IGBTs Q2A and Q3A.

[0146] Three-level circuit 3Ax corresponds to one embodiment of a “first multilevel circuit.” IGBTs Q1A and Q2A and diodes D1A and D2A form a “first switch,” IGBTs Q2A and Q3A and diodes D2A, D3A, D5A, and D6A form a “second switch,” and IGBTs Q3A and Q4A and diodes D3A and D4A form a “third switch.”

[0147] The three-level circuit 3Bx includes IGBTs Q1B to Q4B and diodes D1B to D6B. The IGBTs Q1B to Q4B are connected in series between DC lines L1 and L3. The diodes D1B to D4B are connected in anti-parallel to the IGBTs Q1B to Q4B, respectively. The diode D5B is connected to the connection point of the IGBTs Q1B and Q2B and the DC line L2. The diode D6B is connected to the connection point of the IGBTs Q3B and Q4B and the DC line L.

[0148] The diodes D1B to D4B function as freewheeling diodes, and the diodes D5B and D6B function as clamp diodes. An input node 3b of the three-level circuit 3Bx is connected to a second terminal of the reactor 12RB and to a connection point of the IGBTs Q2B and QBA.

[0149] Three-level circuit 3Bx corresponds to one embodiment of a "second multilevel circuit." IGBTs Q1B and Q2B and diodes D1B and D2B form a "fourth switch," IGBTs Q2B and Q3B and diodes D2B, D3B, D5B, and D6B form a "fifth switch," and IGBTs Q3B and Q4B and diodes D3B and D4B form a "sixth switch."

[0150] The switching pattern of the IGBTs in each bridge circuit is composed of three modes. Fig. 19 is a diagram showing the switching patterns of the four IGBTs included in each bridge circuit. Fig. 19 shows the operation of bridge circuit 3Ax in each mode.

[0151] FIG. 19(A) shows mode 1. In mode 1, IGBTs Q1A and Q2A are turned on, IGBTs Q3A and Q4A are turned off, and positive-side capacitor C1 is charged or discharged. FIG. 19(B) shows mode 2. In mode 2, IGBTs Q2A and Q3A are turned on, IGBTs Q1A and Q4A are turned off, and the charge states of positive-side capacitor C1 and negative-side capacitor C2 do not change significantly. FIG. 19(C) shows mode 3. In mode 3, IGBTs Q3A and Q4A are turned on, IGBTs Q1A and Q2A are turned off, and negative-side capacitor C2 is charged or discharged. Note that the arrows in FIGS. 19(A) and 19(C) indicate the direction of current flow during charging. During discharging, current flows in the opposite direction to the arrows.

[0152] In the third embodiment, as in the first embodiment, the first control circuit 53 generates PWM signals φ1A to φ4A and φ1B to φ4B so that the phases of the three-phase AC voltages VR, VS, VT and the phases of the three-phase AC currents IR, IS, IT coincide with each other, the DC voltage VDC that is the sum of the inter-terminal voltages Ep, En of the capacitors C1, C2 becomes the reference DC voltage VDCR, and the DC voltage ΔE that is the difference between the inter-terminal voltages Ep, En of the capacitors C1, C2 becomes zero.

[0153] When power failure signal PC is at the inactivation level "L" (when commercial AC power supply 41 is normal), first control circuit 53 and converter 3 are connected by switching circuit 55. As a result, PWM signals φ1A to φ4A and φ1B to φ4B are applied to the gates of IGBTs Q1A to Q4A and Q1B to Q4B of R-phase arm 3R, respectively, via switching circuit 55. Note that in each phase arm 3R, 3S, 3T of converter 3, parallel-connected three-level circuits 3Ax, 3Bx are interleaved. This allows ripples generated by each three-level circuit to cancel each other out, achieving the same effect as in embodiment 1.

[0154] Also in the third embodiment, similarly to the first embodiment, the second control circuit 54 controls the converter 3 based on the signal indicating the DC voltage ΔE from the subtractor 52 so that the DC voltage ΔE becomes zero.

[0155] FIG. 20 is a time chart showing the operation of the second control circuit 54. FIG. 20 shows the control of one phase (e.g., the R-phase arm 3R) of the converter 3 when Ep>En. FIG. 20(A) shows the waveforms of Ep and En. FIG. 20(B) to (E) show the waveforms of the PWM signals φ1A to φ4A and φ1B to φ4B generated by the second control circuit 54.

[0156] If Ep>En (time t1), the PWM signals φ1A and φ2A are set to the "H" level and "L" level at a predetermined frequency fc. The PWM signals φ3A, φ4A, φ1B, φ2B, and φ4B are fixed to the "L" level, and the PWM signal φ3B is fixed to the "H" level.

[0157] 21 and 22 are equivalent circuit diagrams showing the operation of one phase of converter 3 when Ep > En. As shown in FIG. 21 , when PWM signals φ1A and φ2A are set to the "H" level and PWM signal φ3B is set to the "H" level, IGBTs Q1A and Q2A (first switches) are turned on, and IGBT Q3B (fifth switch) is turned on. As a result, as shown by the arrows in FIG. 21 , current flows from the positive electrode of capacitor C1 through DC line L1, IGBTs Q1A and Q2A, reactors 12RA and 12RB, IGBT Q3B, diode D6B, and DC line L2 to the negative electrode of capacitor C1. This discharges capacitor C1, reducing the voltage Ep across capacitor C1. At this time, electromagnetic energy is stored in reactors 12RA and 12RB.

[0158] Next, when the PWM signals φ1A and φ2A are set to the "L" level, the IGBTs Q1A and Q2A (first switches) are turned off, as shown in Fig. 22. As a result, a current flows from the reactor 12RA to the reactor 12RA via the reactor 12RB, the IGBT Q3B, the diode D6B, the DC line L2, the capacitor C2, the DC line L3, and the diodes D2A and D3A, as shown by the arrows in Fig. 22. At this time, the electromagnetic energy of the reactors 12RA and 12RB is released, the capacitor C2 is charged, and the voltage En between the terminals of the capacitor C2 rises.

[0159] In this way, by repeatedly setting PWM signals φ1A and φ2A to "H" level and "L" level to turn IGBTs Q1A and Q2A (first switches) on and off, ΔE = Ep - En gradually decreases. When ΔE = 0 (time t2), PWM signals φ1A, φ2A, and φ3B are fixed at "L" level. That is, IGBTs Q1A to Q4A and Q1B to Q4B are all turned off, and operation of converter 3 is stopped.

[0160] FIG. 23 is a time chart showing the operation of the second control circuit 54. FIG. 23 shows the control of one phase (e.g., the R-phase arm 3R) of the converter 3 when Ep<En. FIG. 23(A) shows the waveforms of Ep and En. FIG. 23(B) to (E) show the waveforms of the PWM signals φ1A to φ4A and φ1B to φ4B generated by the second control circuit 54.

[0161] If Ep<En (time t1), the PWM signals φ3A and φ4A are set to the "H" level and "L" level at a predetermined frequency fc. The PWM signals φ1A, φ2A, φ1B, and φ3B are fixed to the "L" level, and the PWM signal φ2B is fixed to the "H" level.

[0162] 24 and 25 are equivalent circuit diagrams showing the operation of one phase of converter 3 when Ep<En. As shown in FIG. 24 , when PWM signals φ3A and φ4A are set to the “H” level and PWM signal φ2B is set to the “H” level, IGBTs Q3A and Q4A (third switches) are turned on and IGBT Q2B (fifth switch) is turned on. As a result, as shown by the arrows in FIG. 24 , current flows from the positive electrode of capacitor C2 through DC line L2, diode D5B, IGBT Q2B, reactors 12RB and 12RA, IGBTs Q3A and Q4A, and DC line L3 to the negative electrode of capacitor C2. This discharges capacitor C2, reducing the voltage En across capacitor C2. At this time, electromagnetic energy is stored in reactors 12RA and 12RB.

[0163] Next, when the PWM signals φ3A and φ4A are set to the "L" level, the IGBTs Q3A and Q4A (third switches) are turned off, as shown in Fig. 25. As a result, as shown by the arrows in Fig. 25, a current flows from the reactor 12RB to the reactor 12RA via the reactor 12RA, the diodes D2A and D1A, the DC line L1, the capacitor C1, the DC line L2, the diode D5B, the IGBT Q2B, and the reactor 12RB. At this time, the electromagnetic energy of the reactors 12RA and 12RB is released, the capacitor C1 is charged, and the voltage Ep between the terminals of the capacitor C1 increases.

[0164] In this way, by repeatedly setting PWM signals φ3A and φ4A to "H" level and "L" level to turn IGBTs Q3A and Q4A (third switches) on and off, ΔE = Ep - En gradually decreases. When ΔE = 0 (time t2), PWM signals φ3A, φ2B, and φ4B are fixed at "L" level. That is, IGBTs Q1A to Q4A and Q1B to Q4B are all turned off, and operation of converter 3 is stopped.

[0165] When power failure signal PC is at the activated "H" level (when commercial AC power supply 41 is experiencing a power failure), second control circuit 54 is connected to converter 3 by switching circuit 55. As a result, PWM signals φ1A to φ4A and φ1B to φ4B are applied via switching circuit 55 to the gates of IGBTs Q1A to Q4A and Q1B to Q4B of R-phase arm 3R, respectively.

[0166] (Balance Control by Converter) When commercial AC power supply 41 is healthy, balance control by converter 3 is the same as that described in embodiment 1. That is, first control circuit 53 and converter 3 are connected by switching circuit 55. When Ep<En, first control circuit 53 adds positive voltage command value V1* to voltage command values ​​VR0*, VS0*, VT0* to generate voltage command values ​​VR*, VS*, VT*. When Ep>En, first control circuit 53 adds negative voltage command value V1* to voltage command values ​​VR0*, VS0*, VT0* to generate voltage command values ​​VR*, VS*, VT*. PWM circuit 72 generates PWM signals φ1A to φ4A and φ1B to φ4B by comparing the voltage command values ​​VR*, VS*, VT* with the triangular wave signals Cu1a, Cu1b, Cu2a, Cu2b. PWM circuit 72 applies the generated PWM signals φ1A to φ4A and φ1B to φ4B to the gates of IGBTs Q1A to Q4A and Q1B to Q4B of three-level circuits 3Ax, 3Bx of phase arms 3R, 3S, 3T via switching circuit 55.

[0167] Next, the balance control by the converter 3 when the commercial AC power supply 41 is powered down will be described.

[0168] When Ep>En, in order to balance the voltages of the capacitors C1 and C2, the second control circuit 54 turns on the IGBT Q3B of the three-level circuit 3Bx and turns on and off the IGBTs Q1A and Q2A of the three-level circuit 3Ax at a predetermined frequency fc, as shown in FIG. 20.

[0169] When IGBTs Q1A and Q2A are turned on, current flows out of capacitor C1, decreasing the voltage Ep across capacitor C1, and electromagnetic energy is stored in reactors 12RA and 12RB, as shown in FIG. 21. When IGBTs Q1A and Q2A are turned off, the electromagnetic energy stored in reactors 12RA and 12RB is released, charging capacitor C2 and increasing the voltage En across capacitor C2, as shown in FIG. By turning IGBTs Q1A and Q2A on and off at a predetermined frequency fc, ΔE = Ep - En gradually decreases. When ΔE = 0, IGBTs Q1A to Q4A and Q1B to Q4B are turned off, and converter 3 stops operating.

[0170] When Ep<En, in order to balance the voltages of the capacitors C1 and C2, the second control circuit 54 turns on the IGBT Q2B of the three-level circuit 3Bx and turns on and off the IGBTs Q3A and Q4A of the three-level circuit 3Ax at a predetermined frequency fc, as shown in FIG. 23.

[0171] When IGBTs Q3A and Q4A are turned on, current flows out of capacitor C2, decreasing the voltage En across capacitor C2, and electromagnetic energy is stored in reactors 12RA and 12RB, as shown in FIG. 24. When IGBTs Q3A and Q4A are turned off, the electromagnetic energy stored in reactors 12RA and 12RB is released, charging capacitor C1 and increasing the voltage Ep across capacitor C1, as shown in FIG. By turning IGBTs Q3A and Q4A on and off at a predetermined frequency fc, ΔE = Ep - En gradually decreases. When ΔE = 0, IGBTs Q1A to Q4A and Q1B to Q4B are turned off, and converter 3 stops operating.

[0172] In the third embodiment, similar to the first embodiment, when the commercial AC power supply 41 experiences a power outage, the switch 1 is turned off to electrically disconnect the commercial AC power supply 41 from the AC input filter 2, and the converter 3 is controlled so that the difference between the terminal voltages Ep and En of the capacitors C1 and C2, that is, the DC voltage ΔE = Ep - En, is eliminated, thereby reducing the DC voltage ΔE. Furthermore, when the commercial AC power supply 41 experiences a power outage, each phase arm 3R, 3S, 3T of the converter 3 is configured with two three-level circuits 3Ax, 3Bx connected in parallel, and the three-level circuits 3Ax, 3Bx are operated to discharge or charge the capacitors C1, C2. Therefore, the third embodiment can also achieve the same effects as the first embodiment.

[0173] Furthermore, by applying to the third embodiment the configuration described in the second embodiment in which the number of phase arms of converter 3 to be operated during a power outage of commercial AC power supply 41 is changed in accordance with the absolute value of DC voltage ΔE, it is possible to reduce the loss of converter 3 while quickly reducing the absolute value of DC voltage ΔE.

[0174] [Other Configuration Examples] In the above-described first to third embodiments, the configuration has been described in which each phase arm of the converter 3 includes two three-level circuits 3A and 3B. However, each phase arm of the converter 3 may include three or more three-level circuits. In this case, when the commercial AC power supply 41 is operating normally, the three or more three-level circuits can be interleaved. Furthermore, when the commercial AC power supply 41 experiences a power outage, the three or more three-level circuits can be operated to discharge or charge the capacitors C1 and C2.

[0175] Although the present embodiment shows an uninterruptible power supply that can be applied to a three-phase, four-wire AC power supply and load, the present disclosure can also be applied to a three-phase, three-wire AC power supply and load. Furthermore, the AC power supply and load are not limited to three-phase ones, and may be single-phase ones.

[0176] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of the present disclosure is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims.

[0177] 1 Switch, 2 AC input filter, 3 Converter, 3R R-phase arm, 3S S-phase arm, 3T T-phase arm, 4 Inverter, 5 AC output filter, 6 DC voltage converter, 10 Control device, 11, 11R, 11S, 11T, 19, 19U, 19V, 19W, C1, C2 Capacitor, 12, 12R, 12RA, 12RB, 12S, 12T, 18, 18U, 18V, 18W, 22, 22P, 22N Reactor, 21 Semiconductor switch, 31, 34 to 36 Voltage detector, 32, 32R, 32S, 32T, 37 Current detector, 33 Power outage detector, 41 Commercial AC power supply, 42 Load, 51, 68A to 68C, 71A to 71C Adder, 52, 62, 66A to 66C, 84, 86 Subtractor, 53 First control circuit, 54 Second control circuit, 55 Switching circuit, 60 Voltage command generating circuit, 61, 83 Reference voltage generating circuit, 63 DC voltage control circuit, 64 Sine wave generating circuit, 65A to 65C Multiplier, 67, 87 Current control circuit, 70 Balance control circuit, 72, 88 PWM circuit, 80 Control circuit, 85 Voltage control circuit, 90 Oscillator, 91 to 94 Triangular wave generator, 95 to 98 Comparator, 100 Uninterruptible power supply, 102 CPU, 104 Memory, 106 I / O circuit, 108 Bus, 110, 112, 114, 116 Buffer, 111, 113, 115, 117 NOT circuit, B1 Battery, L1 to L3 DC line, Cu1a, Cu1b, Cu2a, Cu2b triangular wave signal.

Claims

a first capacitor connected between the first and second DC lines; a second capacitor connected between the second and third DC lines; a switch having a first terminal receiving an AC voltage supplied from an AC power source, the switch being turned on when the AC power source is operating normally and turned off when there is a power outage; an AC input filter having a first terminal connected to a second terminal of the switch; a converter connected between the second terminal of the AC input filter and the first to third DC lines, the converter converting AC power from the AC power source into DC power and supplying the DC power to the first to third DC lines when the AC power source is operating normally; an inverter connected between the first to third DC lines and a load, the inverter converting DC power from the first to third DC lines into AC power and supplying the AC power to the load; first and second voltage detectors detecting voltages between the terminals of the first and second capacitors, respectively; and a control device controlling the converter based on values ​​detected by the first and second voltage detectors. the AC input filter includes: a first reactor having a first terminal connected to the second terminal of the switch; and a second reactor having a first terminal connected to the second terminal of the switch; the converter includes: a first multilevel circuit connected between a second terminal of the first reactor and the first to third DC lines and configured to be able to convert an AC voltage into the first to third DC voltages, and a second multilevel circuit connected between a second terminal of the second reactor and the first to third DC lines and configured to be able to convert an AC voltage into the first to third DC voltages, and an uninterruptible power supply that controls the first and second multilevel circuits so that the second voltage is eliminated when the AC power supply fails; 2. The uninterruptible power supply according to claim 1, wherein, in the event of a power outage of the AC power supply, the control device controls the first and second multilevel circuits so that the first capacitor is discharged and the second capacitor is charged when the terminal voltage of the first capacitor is greater than the terminal voltage of the second capacitor, and controls the first and second multilevel circuits so that the second capacitor is discharged and the first capacitor is charged when the terminal voltage of the first capacitor is less than the terminal voltage of the second capacitor.

3. When the voltage across the terminals of the first capacitor is greater than the voltage across the terminals of the second capacitor during a power outage of the AC power supply, the control device is configured to alternately execute a first operation for discharging the first capacitor and a second operation for charging the second capacitor, wherein in the first operation, the control device controls the first and second multilevel circuits so that a current flows from the positive electrode of the first capacitor to the negative electrode of the first capacitor via the first DC line, the first multilevel circuit, the first and second reactors, the second multilevel circuit, and the second DC line, and in the second operation, the control device controls the first and second multilevel circuits so that a current flows from the second terminal of the second reactor to the second terminal of the first reactor via the second multilevel circuit, the second DC line, the second capacitor, the third DC line, and the first multilevel circuit, 3. The uninterruptible power supply according to claim 2, wherein the control device stops the first and second operations in response to the second voltage being removed.

4. The first multilevel circuit includes: a first switch connected between the first DC line and the second terminal of the first reactor; a second switch connected between the second DC line and the second terminal of the first reactor; and a third switch connected between the third DC line and the second terminal of the first reactor; the second multilevel circuit includes: a fourth switch connected between the first DC line and the second terminal of the second reactor; a fifth switch connected between the second DC line and the second terminal of the second reactor; and a sixth switch connected between the third DC line and the second terminal of the second reactor; and in the first operation, the control device turns on the first and fifth switches and turns off the second, third, fourth and sixth switches; 4. The uninterruptible power supply according to claim 3, wherein in the second operation, the control device turns on the fifth switch and turns off the first, second, third, fourth and sixth switches.

5. When the AC power supply fails, if the voltage across the first capacitor is smaller than the voltage across the second capacitor, the control device is configured to alternately perform a third operation for discharging the second capacitor and a fourth operation for charging the first capacitor, wherein in the third operation, the control device controls the first and second multilevel circuits so that a current flows from the positive electrode of the second capacitor to the negative electrode of the first capacitor via the second DC line, the second multilevel circuit, the second and first reactors, the first multilevel circuit, and the third DC line, and in the fourth operation, the control device controls the first and second multilevel circuits so that a current flows from the second terminal of the first reactor to the second terminal of the second reactor via the first multilevel circuit, the first DC line, the first capacitor, the second DC line, and the second multilevel circuit, 3. The uninterruptible power supply according to claim 2, wherein the control device stops the third and fourth operations in response to the disappearance of the second voltage.

6. The first multilevel circuit includes: a first switch connected between the first DC line and the second terminal of the first reactor; a second switch connected between the second DC line and the second terminal of the first reactor; and a third switch connected between the third DC line and the second terminal of the first reactor; the second multilevel circuit includes: a fourth switch connected between the first DC line and the second terminal of the second reactor; a fifth switch connected between the second DC line and the second terminal of the second reactor; and a sixth switch connected between the third DC line and the second terminal of the second reactor; and in the third operation, the control device turns on the third and fifth switches and turns off the first, second, fourth and sixth switches; 6. The uninterruptible power supply according to claim 5, wherein in the fourth operation, the control device turns on the fifth switch and turns off the first, second, third, fourth and sixth switches.

7. An uninterruptible power supply according to any one of claims 1 to 6, wherein the AC power supply is a three-phase AC power supply, the first and second reactors are provided corresponding to each phase of the AC power supply, the converter includes three-phase arms provided corresponding to each of the three phases of the AC power supply, each of the three-phase arms including the first and second multilevel circuits, and when the AC power supply experiences a power outage, the control device changes the number of phase arms to be operated depending on the absolute value of the second voltage.

8. The uninterruptible power supply according to claim 7, wherein, in the event of a power outage of the AC power supply, the control device reduces the number of phase arms to be operated in accordance with a decrease in the absolute value of the second voltage.

9. An uninterruptible power supply according to any one of claims 1 to 6, wherein when the AC power supply is normal, the control device drives the first and second multilevel circuits in an interleaved manner.

10. An uninterruptible power supply according to any one of claims 1 to 6, further comprising a DC voltage converter connected between a power storage device and the first to third DC lines, for supplying DC power from the power storage device to the first to third DC lines in the event of a power outage in the AC power supply, wherein in the event of a power outage in the AC power supply, the control device controls the DC voltage converter so that the first voltage becomes the reference voltage.

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