Interposer and circuit board provided with same

Abstract

This interposer (10a) is provided with: a first insulating body (110) and a first mounting part (120d) that are provided to a first layer (100); a second insulating body (210) and a second mounting part (220d) that are provided to a second layer (200); and a via (240d) that electrically connects the first mounting part (120d) and the second mounting part (220d) to each other. The first mounting part (120d) has a first pad (121d) and a first protective film (122d) that covers the first pad (121d). The first protective film (122d) has an exposed portion (123d) that is exposed from the first insulating body (110). The melting point of the first protective film (122d) is higher than the melting point of the first pad (121d).

Description

Interposer and circuit board including the same

[0001] The present invention relates to an interposer and a circuit board including the same.

[0002] In recent years, semiconductor products have been required to have higher performance, faster speeds, and lower power consumption, but to achieve these, it is necessary to miniaturize the wiring within the substrate.To accommodate this miniaturization of the wiring within the substrate, a technology called an interposer, which provides a multilayer wiring substrate containing fine wiring between the substrate and the semiconductor element, has been adopted.

[0003] For example, as an example of an interposer, Patent Document 1 discloses an interposer having a substrate that transmits ultraviolet light, a light-transmitting layer that is a metal oxide layer provided on the substrate and transmits ultraviolet light with a transmittance of 60% or more, a first resin layer provided on the light-transmitting layer, and wiring provided on or inside the first resin layer.

[0004] JP 2023-100804 A

[0005] In the conventional interposer disclosed in Patent Document 1, the pads to which the semiconductor elements are connected are exposed on the outer surface, which causes problems of reduced reliability due to corrosion and poor heat resistance.

[0006] The present disclosure has been made in consideration of the above points, and its purpose is to provide an interposer that increases the reliability of pads on which semiconductor elements are mounted and improves heat resistance.

[0007] In order to solve the above problem, an interposer according to one aspect of the present disclosure includes a first insulator 110 made of a resin material and provided on a first layer 100; a first mounting section 120 provided on the first layer 100 and partially exposed from the first insulator 110; a second insulator 210 made of a resin material and provided on a second layer 200 located below the first layer 100 and in contact with the lower surface of the first mounting section 120; 0, and a via 240 electrically connecting the first mounting portion 120 and the second mounting portion 220, the first mounting portion 120 having a first pad 121 made of a conductive material and a first protective film 122 covering the first pad 121, the first protective film 122 having an exposed portion 123 exposed from the first insulator 110, and the melting point of the first protective film 122 being higher than the melting point of the first pad 121.

[0008] According to the present disclosure, it is possible to provide an interposer that increases the reliability of pads on which semiconductor elements are mounted and improves heat resistance.

[0009] FIG. 1A is a plan view showing a first wiring layer of an interposer according to the first embodiment. FIG. 1B is a plan view showing a via layer of the interposer according to the first embodiment. FIG. 1C is a plan view showing a second wiring layer of the interposer according to the first embodiment. FIG. 2 is a conceptual diagram obtained by superimposing FIGS. 1A to 1C. FIG. 3A is a cross-sectional view of the interposer according to the first embodiment taken along line IIIA-IIIA in FIG. 2. FIG. 3B is a cross-sectional view of the interposer according to the first embodiment taken along line IIIB-IIIB in FIG. 2. FIG. 3C is a cross-sectional view of the interposer according to the first embodiment taken along line IIIC-IIIC in FIG. 2. FIG. 4A is a top view of the interposer according to the first embodiment. FIG. 4B is a bottom view of the interposer according to the first embodiment. FIG. 5A is a plan view showing a first wiring layer of an interposer according to the second embodiment. FIG. 5B is a plan view showing a via layer of the interposer according to the second embodiment. FIG. 5C is a plan view showing a second wiring layer of the interposer according to the second embodiment. FIG. 6 is a conceptual diagram obtained by superimposing FIGS. 5A to 5C. FIG. 7A is a cross-sectional view of an interposer according to the second embodiment taken along line VIIA-VIIA in FIG. 6 . FIG. 7B is a cross-sectional view of an interposer according to the second embodiment taken along line VIII-VIIB in FIG. 6 . FIG. 7C is a cross-sectional view of an interposer according to the second embodiment taken along line VIII-VIIC in FIG. 6 . FIG. 8 is a cross-sectional view of an interposer according to the third embodiment. FIG. 9 is a cross-sectional view of an interposer according to the fourth embodiment. FIG. 10 is a cross-sectional view of an interposer according to the fifth embodiment. FIG. 11 is a cross-sectional view of a circuit board having an interposer according to the first embodiment mounted thereon. FIG. 12A is a diagram showing a process of forming a release layer over the entire lower surface of the support body in the manufacturing process of the interposer according to the first embodiment. FIG. 12B is a diagram showing a process of forming a first layer on the lower surface of the release layer in the manufacturing process of the interposer according to the first embodiment. FIG. 12C is a diagram showing a process of forming a second layer on the lower surface of the first layer in the manufacturing process of the interposer according to the first embodiment. FIG. 12D is a diagram showing a step of peeling the insulator from the release layer in the manufacturing process of the interposer according to the first embodiment.FIG. 12E is a diagram showing a step of forming an opening in an insulator with laser light in the manufacturing process of the interposer according to the first embodiment.

[0010] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. The following description of the preferred embodiments is merely exemplary in nature and is not intended to limit the present invention, its applications, or its uses.

[0011] Furthermore, in this disclosure, the terms "upper" and "lower" do not refer to the upper direction (vertically upper) and lower direction (vertically lower) in absolute spatial recognition, but are used as terms defined by the relative positional relationship of components in an interposer. Furthermore, the terms "upper" and "lower" are used not only when two components are arranged with a gap between them and another component is present between them, but also when two components are arranged closely together and are in contact with each other. Similarly to "upper" and "lower," terms indicating directions, such as "top," "bottom," "left," "right," "front," and "rear," are used as terms indicating relative positional relationships, not absolute positional relationships.

[0012] (Outline of First Embodiment) An interposer 10a according to a first embodiment will be described below with reference to FIGS. 1A to 4B.

[0013] FIG. 1A is a plan view showing a first wiring layer of an interposer according to embodiment 1. FIG. 1B is a plan view showing a via layer of an interposer according to embodiment 1. FIG. 1C is a plan view showing a second wiring layer of an interposer according to embodiment 1. FIG. 2 is a conceptual diagram obtained by superimposing FIGS. 1A to 1C. FIG. 3A is a cross-sectional view of an interposer according to embodiment 1 taken along line A-A in FIG. 2. FIG. 3B is a cross-sectional view of an interposer according to embodiment 1 taken along line B-B in FIG. 2. FIG. 3C is a cross-sectional view of an interposer according to embodiment 1 taken along line C-C in FIG. 2. FIG. 4A is a top view of an interposer according to embodiment 1. FIG. 4B is a bottom view of an interposer according to embodiment 1.

[0014] The letters D to K and d to k shown in FIGS. 1A to 1C and 2 are symbols used to make it easier to understand the correspondence between the layers.

[0015] In the following description, the arrangement and configuration of each component may be described using the top, bottom, left, right, front, and back indicated in each drawing.

[0016] As shown in Figures 3A to 3C, the first wiring layer 101 is filled with an insulator 110, and the via layer 201 is filled with an insulator 210, but for ease of understanding, the insulators 110 and 210 are omitted from the illustration in Figures 1A to 2.

[0017] 3A to 3C, the first layer 100 includes a first wiring layer 101, and the second layer 200 includes a via layer 201 and a second wiring layer 102. As shown in FIGS. 3A and 3C, the wirings 130d to 130k formed in the first wiring layer 101 are connected to second mounting portions 220d to 220k formed in the second wiring layer 102 via vias 240d to 240k arranged in the via layer 201, respectively.

[0018] As shown in FIG. 3A, the first mounting portions 120d-120k are connected to the second mounting portions 220d-220k through vias 240d-240k.

[0019] In the following explanation, the relationship between the first mounting unit 120d and the second mounting unit 220d will be described through an explanation of each unit connected to the first mounting unit 120d and the second mounting unit 220d. The following explanation also applies to the first mounting units 120e to 120k and the second mounting units 220e to 220k, and to each unit connected to the first mounting units 120e to 120k and the second mounting units 220e to 220k.

[0020] (Configuration of First Wiring Layer 101) First, the first wiring layer 101 will be described with reference to FIG. 1A.

[0021] As shown in FIG. 1A, the first wiring layer 101 is provided with first mounting portions 120d to 120k and wirings 130d to 130k.

[0022] As shown in FIG. 3B, the first mounting portion 120d includes a pad 121d and a protective film 122d that covers the pad 121d, but the protective film 122d is not shown in FIG. 1 for ease of understanding.

[0023] Furthermore, insulators 110 are provided between the first mounting portions 120d to 120k and the wirings 130d to 130k, respectively, but as mentioned above, they are not shown.

[0024] 1A, the first mounting portion 120d is connected to a wiring 130d having a connection portion 133d. Also, as shown in FIG. 3A, the connection portion 133d of the wiring 130d is connected to a via 240d arranged in the via layer 201.

[0025] (Configuration of Via Layer 201) Next, the via layer 201 will be described with reference to FIG. 1B.

[0026] As shown in FIG. 1B, vias 240d to 240k are arranged in the via layer 201.

[0027] Furthermore, insulators 210 are provided between each of the vias 240d to 240k, but as mentioned above, they are not shown.

[0028] The via 240d is connected to the wiring 130d (see FIGS. 1A and 3A) at the connection portion 133d, and also to the second mounting portion 220d (see FIGS. 1C and 3A).

[0029] (Configuration of Second Wiring Layer 102) Next, the second wiring layer 102 will be described with reference to FIG. 1C.

[0030] As shown in FIG. 1C, the second wiring layer 102 is provided with second mounting portions 220d to 220k.

[0031] As shown in FIG. 3A, the second mounting portion 220d is connected to the via 240d.

[0032] (Overall Configuration of Interposer 10a) Next, the connection relationship between the first mounting portions 120d to 120k and the second mounting portions 220d to 220k will be described with reference to FIG.

[0033] As shown in FIG. 2, the first mounting portion 120d is connected to the second mounting portion 220d via a wiring 130d and a via 240d (not shown in FIG. 2).

[0034] As described above, the first mounting portion 120d is disposed on the first wiring layer 101, and the second mounting portion 220d is disposed on the second wiring layer 102. Therefore, in the first wiring layer 101, the spacing between the first mounting portions 120d to 120k is narrow, so a semiconductor element 20 with narrow spacing between terminals can be connected above the interposer 10a. On the other hand, in the second wiring layer 102, the spacing between the second mounting portions 220d to 220k is wider than the spacing between the first mounting portions 120d to 120k, so a substrate 30 with wide spacing between pads can be connected below the interposer 10a (see FIG. 11).

[0035] The first mounting portions 120d to 120k are arranged in the first region 11, and the second mounting portions 220d to 220k are arranged in the second region 12. The first region 11 is located inside the second region 12.

[0036] In the interposer 10a, the first mounting portions 120d to 120k arranged in the first region 11 are connected to the second mounting portions 220d to 220k arranged in the second region 12. Therefore, by using the interposer 10a, it becomes possible to mount the semiconductor element 20 having narrow spacing between terminals on the substrate 30 having wide spacing between pads.

[0037] (Detailed Description of Interposer 10a According to First Embodiment) Below, the details of each part of interposer 10a will be described using first mounting portion 120d and second mounting portion 220d as examples. The following description applies to each part connected to first mounting portions 120e to 120k and second mounting portions 220e to 220k.

[0038] As shown in FIGS. 1A to 3C, the interposer 10a includes insulators 110 and 210, a first mounting portion 120d, a wiring 130d, a second mounting portion 220d, and a via 240d.

[0039] 3A to 3C, the interposer 10a includes a first layer 100 having a first wiring layer 101, and a second layer 200 having a via layer 201 and a second wiring layer 102. The first layer 100 is provided above the second layer 200. The via layer 201 is provided above the second wiring layer 102. That is, the first wiring layer 101, the via layer 201, and the second wiring layer 102 are arranged in this order from top to bottom: first wiring layer 101, via layer 201, second wiring layer 102.

[0040] (Configuration of First Layer 100) The configuration of the first layer 100 having the first wiring layer 101 will be described in detail below with reference to FIG. 1A and FIGS. 3A to 3C.

[0041] 3A to 3C, the insulator 110 is provided on the first wiring layer 101. The material of the insulator 110 is resin.

[0042] Since the insulator 110 has insulating properties, the insulator 110 can insulate between the first mounting portions 120d to 120k and the wirings 130d to 130k provided on the first wiring layer 101.

[0043] The insulator 110 is flexible, which allows easy processing of the first wiring layer 101. Furthermore, it is easy to control the length of the first wiring layer 101 in the vertical direction, i.e., the thickness of the first wiring layer 101. Furthermore, it is possible to realize microfabrication of the first wiring layer 101.

[0044] The material of the insulator 110 may be an epoxy resin, a polyimide resin, an acrylic resin, a bismaleimide resin, or the like.

[0045] Furthermore, the manufacturing cost is high when an inorganic material such as silicon is used as the material for the insulator 110. By using a resin material as the material for the insulator 110, the manufacturing cost of the interposer 10a can be reduced.

[0046] 3B and 3C, the insulator 110 has an opening 111d, and the first mounting portion 120d is exposed from the insulator 110 through the opening 111d.

[0047] 1A, 3B, and 3C, the first mounting portion 120d is provided on the first wiring layer 101. The boundary between the first mounting portion 120d and a wiring 130d (described later) is shown as a boundary line L1 in FIG. 1A.

[0048] 3B and 3C, a portion of the first mounting portion 120d is exposed upward from the insulator 110 at the opening 111d. The semiconductor element 20 is connected to the portion of the first mounting portion 120d that is exposed upward from the insulator 110 (see FIG. 11). Thus, the first mounting portion 120d can be electrically connected to the semiconductor element 20.

[0049] 4A and 4B, the portion of the first mounting portion 120d exposed from the insulator 110 (substantially corresponding to the exposed portion 123d) has a smaller area than the portion of the second mounting portion 220d exposed from the insulator 210d (substantially corresponding to the underside of the second mounting portion 220d), which will be described later. Therefore, by using the interposer 10a, it becomes possible to mount the semiconductor element 20 having a narrow spacing between terminals on the substrate 30 (see FIG. 11).

[0050] The portion of the first mounting portion 120d that is exposed from the insulator 110 has a width of 30 μm to 80 μm in plan view.

[0051] The width here refers to the longest length (W1) in the front-rear direction shown in FIG. 4A.

[0052] 3B and 3C, the first mounting portion 120d has a pad 121d and a protective film 122d. The protective film 122d covers the pad 121d. That is, the protective film 122d covers the entire top and side surfaces of the pad 121d.

[0053] The materials of the pad 121d and the protective film 122d will be described in detail below.

[0054] The melting point of the protective film 122d is higher than that of the pad 121d, improving the heat resistance of the pad 121d. As described below, the insulator 110 is opened at the opening 111d by laser processing. Heat is applied to the first mounting portion 120d during the laser processing. By covering the pad 121d with the protective film 122d, which has a higher melting point than the pad 121d, the pad 121d can be protected from heat. Note that the above laser processing is an example of heat applied to the first mounting portion 120. The above description does not limit the heat source.

[0055] The pad 121d is conductive, and the protective film 122d is conductive, so that the pad 121d and the semiconductor element 20 can be electrically connected when the semiconductor element 20 is mounted.

[0056] The material of the pad 121d is Cu. The material of the protective film 122d is a Ni-Cu alloy. NiCu has better adhesion to the protective film 122d than Cu. This improves the adhesion between the protective film 122d and the insulator 110. Therefore, the protective film 122d functions as an adhesive layer between the insulator 110 and the first mounting portion 120d, and can prevent the insulator 110 from peeling off from the first mounting portion 120d.

[0057] The material of the protective film 122d may be a Ni-Cu-Ti alloy, a metal made of Ni, Ti, Ta, W, or V, or an alloy containing Ni, Ti, Ta, W, or V.

[0058] The material of the pad 121d may be a conductive metal such as Au, etc. Even when the material of the pad 121d is other than Cu, the material of the protective film 122d is made of a material having a higher melting point than the material of the pad 121d.

[0059] As described above, the protective film 122d covers the entire top and side surfaces of the pads 121d. The relationship between the pads 121d and the protective film 122d will be described in detail below.

[0060] As shown in FIGS. 3B and 3C, the protective film 122d is composed of an exposed portion 123d exposed from the insulator 110 and a buried portion 124d buried in the insulator 110.

[0061] 3B and 3C, for convenience of illustration, the cross-sectional areas of exposed portion 123d and buried portion 124d are shown by dot hatching to distinguish exposed portion 123d and buried portion 124d from conductive portion 131d (described later) and protective film 132d (described later). Furthermore, for convenience of illustration, the boundary between exposed portion 123d and buried portion 124d is shown by a dashed line to clearly indicate the boundary between exposed portion 123d and buried portion 124d.

[0062] The exposed portion 123d is exposed from the insulator 110 at the opening 111d. The protective film 122d is also exposed from the insulator 110 at the exposed portion 123d. That is, the protective film 122d is provided on at least the portion of the surface of the pad 121d that is exposed to the outside. Therefore, the protective film 122d can protect the pad 121d from moisture present in the air and the like, and can improve the corrosion resistance of the pad 121d.

[0063] The buried portion 124d is covered with the insulator 110. That is, a protective film 122d is provided on at least the portion of the surface of the pad 121d that is covered with the insulator 110. Therefore, the buried portion 124d improves the adhesion between the pad 121d and the insulator 110, and can prevent the insulator 110 from peeling off from the first mounting portion 120d.

[0064] As shown in Figures 3B and 3C, the exposed portion 123d and the buried portion 124d are integrally formed. At the end of the opening 111d, the protective film 122d covers the pad 121d. The insulator 110 is prone to peeling off from the first mounting portion 120d at the end of the opening 111d. By having the protective film 122d cover the pad 121d at the end of the opening 111d, the adhesion between the insulator 110 and the first mounting portion 120d near the opening 111d is improved. Furthermore, moisture, dust, and the like are less likely to penetrate between the insulator 110 and the first mounting portion 120d. Therefore, the insulator 110 can be prevented from peeling off from the first mounting portion 120d.

[0065] As described above, the protective film 122d covers the entire top and side surfaces of the pad 121d, thereby improving the corrosion resistance of the pad 121d and preventing the insulator 110 from peeling off from the first mounting portion 120d.

[0066] 1A, 3A, and 3C, the wiring 130d is provided on the first layer 100. The wiring 130d is conductive. The wiring 130d is provided continuous with the first mounting portion 120d. The first mounting portion 120d and the wiring 130d are separated by a boundary line L1 shown in FIG. 1A.

[0067] 1A, 3A, and 3C, the wiring 130d is connected to the via 240d at a connection portion 133d. In FIG. 1A, the connection portion 133d is provided at the end of the wiring 130d, but the connection portion 133d may be provided at a location other than the end of the wiring 130d.

[0068] 3A shows a connection portion 133d of the wiring 130d (see FIG. 1A). That is, the wiring 130d shown in FIG. 3A is the connection portion 133d that is a part of the wiring 130d.

[0069] As shown in FIGS. 3A and 3C, the wiring 130d includes a conductive portion 131d and a protective film 132d.

[0070] The conductive portion 131d connects the first mounting portion 120d and the via 240d. The conductive portion 131d is made of the same material as the pad 121d, so the conductive portion 131d and the pad 121d can be molded integrally.

[0071] The protective film 132d covers the conductive portion 131d. That is, the protective film 132d covers the top and side surfaces of the conductive portion 131d. The material of the protective film 132d is the same as the material of the protective film 122d. As shown in FIG. 3C , the protective film 132d is provided continuously with the protective film 122d, so that the protective film 132d and the protective film 122d can be molded integrally. The protective film 132d and the protective film 122d are separated by the boundary line L1 shown in FIG. 1A .

[0072] The materials of the conductive portion 131d and the protective film 132d will be described in detail below.

[0073] The conductive portion 131d is made of Cu. The protective film 132d is made of a NiCu alloy. NiCu has better adhesion to the protective film 132d than Cu. This improves adhesion between the protective film 132d and the insulator 110, and prevents the insulator 110 from peeling off from the wiring 130d.

[0074] The material of the protective film 132d may be a Ni-Cu-Ti alloy, a metal made of Ni, Ti, Ta, W, or V, or an alloy containing Ni, Ti, Ta, W, or V.

[0075] The material of the conductive portion 131d may be a conductive metal such as Au.

[0076] The protective film 132d covers the upper and side surfaces of the conductive portion 131d, and therefore improves the adhesion between the conductive portion 131d and the insulator 110, and can prevent the insulator 110 from peeling off from the wiring 130d.

[0077] (Configuration of Second Layer 200) The configuration of the second layer 200 having the via layer 201 and the second wiring layer 102 will be described in detail below with reference to FIGS. 1B, 1C, and 3A to 3C.

[0078] 3A to 3C, the insulator 210 is provided on the second layer 200. The insulator 210 contacts the lower surface of the insulator 110. The insulator 210 contacts the lower surface of the first mounting portion 120d. The insulator 210 contacts the lower surface of the wiring 130d.

[0079] The material of the insulator 210 is resin. The insulator 210 has insulating properties, so that the insulator 210 can insulate between the members of the conductive material provided on the second layer 200.

[0080] The insulator 210 is flexible, which allows easy processing of the second layer 200. Furthermore, the length of the second layer 200 in the vertical direction, i.e., the thickness of the second layer 200, can be easily controlled.

[0081] The material of the insulator 210 may be an epoxy resin, a polyimide resin, an acrylic resin, a bismaleimide resin, or the like.

[0082] Furthermore, the manufacturing cost is high when an inorganic material such as silicon is used as the material for the insulator 210. By using a resin material as the material for the insulator 210, the manufacturing cost of the interposer 10a can be reduced.

[0083] 1B, 3A, and 3C, the via 240d is provided in the via layer 201. The upper surface of the via 240d is flush with the upper surface of the via layer 201. The lower surface of the via 240d is flush with the lower surface of the via layer 201.

[0084] 1C, 3A, and 3C, the second mounting portion 220d is provided on the second wiring layer 102. The second mounting portion 220d is exposed downward from the insulator 210. The portion of the second mounting portion 220d that is exposed downward from the insulator 210 is connected to the substrate 30 (see FIG. 11).

[0085] 4A and 4B, the portion of the second mounting portion 220d exposed from the insulator 210d (substantially corresponding to the bottom surface of the second mounting portion 220d) is larger than the portion of the first mounting portion 120d exposed from the insulator 110 (substantially corresponding to the exposed portion 123d). Therefore, by using the interposer 10a, the semiconductor element 20 can be mounted on a substrate 30 having a pad-to-pad distance that is larger than the terminal-to-terminal distance of the semiconductor element 20 (see FIG. 11).

[0086] The portion of the second mounting portion 220d that is exposed from the insulator 210 has a width of 40 μm to 5 mm in plan view.

[0087] The width here refers to the longest length (W2) in the front-rear direction shown in FIG. 4B.

[0088] The via 240d electrically connects the first mounting portion 120d and the second mounting portion 220d. As described above, the first mounting portion 120d is electrically connected to the semiconductor element 20. Since the second mounting portion 220d is electrically connected to the substrate 30, the interposer 10a can electrically connect the substrate 30 and the semiconductor element 20 through the first mounting portion 120, the via 240, and the second mounting portion 220.

[0089] A protective film 232d may be provided on the second mounting portion 220d. The protective film 232d is made of the same material as the protective film 122d. A third protective film 232d may cover the lower surface of the second mounting portion 220d. Covering the lower surface of the second mounting portion 220d with the third protective film 232d makes it difficult for moisture and dust to penetrate between the second mounting portion 220d and the insulator 210.

[0090] (Overall Configuration of Interposer 10) The overall configuration of the interposer 10a will be described in detail below with reference to FIG.

[0091] 2, the interposer 10a includes a plurality of first mounting portions 120d-120k and a plurality of second mounting portions 220d-220k. The plurality of first mounting portions 120d-120k are also referred to as a plurality of upper layer pads 120d-120k. The plurality of second mounting portions 220d-220k are also referred to as a plurality of lower layer pads 220d-220k.

[0092] The multiple first mounting portions 120d to 120k are exposed on the upper surface of the interposer 10a and are connected to the semiconductor element 20. The multiple second mounting portions 220d to 220k are exposed on the lower surface of the interposer 10a and are connected to the substrate 30 (see FIG. 11).

[0093] The multiple first mounting portions 120d-120k are located within the first region 11. The multiple second mounting portions 220d-220k are located within the second region 12. The first region 11 is rectangular. The second region 12 is rectangular. The boundary of the first region 11 is illustrated in FIGS. 1A-2 as boundary line L3. The boundary of the first region 12 is illustrated in FIGS. 1A-2 as boundary line L4. Because the first region 11 is located inside the second region 12, the semiconductor element 20 can be mounted using the interposer 10a on a substrate 30 that has a large inter-pad distance relative to the inter-terminal distance of the semiconductor element 20.

[0094] Each of the first mounting portions 120e to 120k has the same configuration as the first mounting portion 120d. Each of the second mounting portions 220e to 220k has the same configuration as the second mounting portion 220d.

[0095] Note that each of the first mounting sections 120e to 120k does not have to have the same configuration as the first mounting section 120d. For example, the interposer 10a may have the first mounting section 120d according to the first example and the first mounting section 120e according to the second embodiment described below. This allows for a variety of wiring patterns on the interposer 10a, enabling finer wiring. The same applies to the second mounting sections 220d to 220k.

[0096] (Explanation of Interposer 10b According to Second Embodiment) The configuration of interposer 10b according to the second embodiment will be described with reference to FIGS. 5 to 7. FIG. 5A is a plan view showing a first wiring layer of an interposer according to the second embodiment. FIG. 5B is a plan view showing a via layer of an interposer according to the second embodiment. FIG. 5C is a plan view showing a second wiring layer of an interposer according to the second embodiment. FIG. 6 is a conceptual diagram obtained by superimposing FIGS. 5A to 4C. FIG. 7A is a cross-sectional view of an interposer according to the second embodiment taken along line A-A in FIG. 6. FIG. 7B is a cross-sectional view of an interposer according to the second embodiment taken along line B-B in FIG. 6. FIG. 7C is a cross-sectional view of an interposer according to the second embodiment taken along line C-C in FIG. 6.

[0097] The letters D to K and d to k shown in FIGS. 1A to 1C and 2 are symbols used to make it easier to understand the correspondence between the layers.

[0098] In the second embodiment described in detail below, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof will be omitted. In addition, in Figures 7B and 7C, similar to Figures 3B and 3C shown in the first embodiment, the cross-sectional areas of exposed portion 123d and buried portion 124d are indicated by dot hatching, and the boundary between exposed portion 123d and buried portion 124d is indicated by a dashed line.

[0099] In the first embodiment, the wiring 130 is provided in the first wiring layer 101 , whereas in the second embodiment, the wiring 230 is provided in the second wiring layer 102 .

[0100] As shown in FIGS. 4 to 7, the interposer 10b includes insulators 110 and 210, first mounting portions 120d to 120k, second mounting portions 220d to 220k, wirings 230d to 230k, and vias 240d to 240k.

[0101] The following describes each unit in detail using the first mounting unit 120d and the second mounting unit 220d as examples. The same applies to the first mounting units 120e to 120k, the second mounting units 220e to 220k, and the units connected to each of them.

[0102] 4B, 7B, and 7C, the via 240d is provided in the via layer 201. The upper surface of the via 240d is directly connected to the lower surface of the first mounting portion 120d.

[0103] As shown in Figures 4C, 7B, and 7C, the wiring 230d is provided on the second wiring layer 102. The boundary between the second mounting portion 220d and the wiring 230d (described later) is shown as boundary line L2 in Figure 4C. The upper surface of the wiring 230d is flush with the upper surface of the second wiring layer 102. The lower surface of the wiring 230d is flush with the lower surface of the second mounting portion 220d.

[0104] 4C, 7B, and 7C, the wiring 230d is connected to the via 240d at a connection portion 233d. In Fig. 4C, the connection portion 233d is provided at the end of the wiring 230d, but the connection portion 233d may be provided at a location other than the end of the wiring 230d.

[0105] As shown in FIG. 7C, the wiring 230d connects the second mounting portion 220d and the via 240d.

[0106] The wiring 230d allows the circuit board 1 using the interposer 10b to be further miniaturized and highly dense.

[0107] (Explanation of Interposer 10c According to Third Embodiment) The configuration of the interposer 10c according to the third embodiment will be described with reference to Fig. 8. Fig. 8 is a cross-sectional view of the interposer according to the third embodiment.

[0108] In the third embodiment described in detail below, the same components as those in the first embodiment will be denoted by the same reference numerals and the description thereof will be omitted.

[0109] In the first embodiment, the wiring 230 is not provided in the second wiring layer 102, but in the third embodiment, the wiring 230 is provided in the second wiring layer 102. That is, in the third embodiment, the wiring 130 is provided in the first wiring layer 101, and the wiring 230 is provided in the second wiring layer 102.

[0110] 8, the interposer 10c has both the wiring 130d and the wiring 230d, so that the circuit board 1 using the interposer 10c can be miniaturized and highly dense. The wiring 130d and the wiring 230d may overlap in a top view. By having the wiring 130d and the wiring 230d overlap in a top view, the circuit board 1 using the interposer 10c can be further miniaturized and highly dense.

[0111] (Explanation of Interposer 10d According to Fourth Embodiment) The configuration of an interposer 10d according to the fourth embodiment will be described with reference to Fig. 9. Fig. 9 is a cross-sectional view of the interposer according to the fourth embodiment.

[0112] In the fourth embodiment described in detail below, the same components as those in the first embodiment will be denoted by the same reference numerals and the description thereof will be omitted.

[0113] In the first embodiment, the wiring 130 is provided in the first wiring layer 101, but in the fourth embodiment, the wiring 130 is not provided in the first wiring layer 101.

[0114] As shown in FIG. 9, an interposer 10d does not have either a wiring 130d or a wiring 230d.

[0115] (Explanation of Interposer 10e According to Fifth Embodiment) The configuration of an interposer 10e according to a fifth embodiment will be described with reference to Fig. 10. Fig. 10 is a cross-sectional view of the interposer according to the fifth embodiment.

[0116] Unlike the first embodiment, the fifth embodiment includes a third layer 300 .

[0117] As shown in FIG. 10, the interposer 10 e has a structure in which a third layer 300 is provided between a first layer 100 and a second layer 200 .

[0118] The third layer 300 includes a via layer 301 and a third wiring layer 103. The third layer 300 electrically connects the first mounting portion 120d and the second mounting portion 220d.

[0119] The via layer 301 has the same structure as the via layer 201. The third wiring layer 103 also includes a wiring 330. The wiring 330 has the same structure as the wiring 230. Therefore, miniaturization and high density of the circuit board using the interposer 10e can be realized.

[0120] 10 is merely an example, and any of the wiring patterns described in Embodiments 1 to 4 may be used. The interposer 10e may also have a structure of four or more layers.

[0121] (Description of Circuit Board 1) Fig. 11 is a cross-sectional view of a circuit board on which the interposer according to embodiment 1 is mounted. As shown in Fig. 11, the circuit board 1 includes an interposer 10a, a semiconductor element 20, and a substrate 30. Note that, for simplification, protective films 122 and 132 are not shown in Fig. 11.

[0122] In the interposer 10a according to this embodiment, the semiconductor element 20 is connected to one of the first mounting portions 120d to 120k, and is connected to the substrate 30 at one of the second mounting portions 220d to 220k.

[0123] The semiconductor element 20 is mounted on any of the first mounting portions 120d to 120k by solder 21d to 21k. Alternatively, the semiconductor element 20 may be mounted by providing a Cu pillar on any of the first mounting portions 120d to 120k. Alternatively, the semiconductor element 20 may be mounted on any of the first mounting portions 120d to 120k by wire bonding.

[0124] The substrate 30 is connected to one of the second mounting portions 220d to 220k by solders 31d to 31k.

[0125] (Method of Manufacturing Interposer 10a) Hereinafter, an example of a manufacturing process for the interposer 10a according to the first embodiment will be described with reference to FIGS. 12A to 12E.

[0126] 12A to 12E show the steps in the manufacturing process of the interposer according to embodiment 1. The up-down relationship in FIGS. 12A to 12E is the same as that in FIG. 3C.

[0127] Furthermore, the following explanation will only describe the first mounting portions 120d, 120e and second mounting portions 220d, 220e shown in Figures 12B to 12E, or the components connected to the first mounting portions 120d, 120e and second mounting portions 220d, 220e, but the same applies to the components connected to the first mounting portions 120f to 120k and second mounting portions 220f to 220k, or the first mounting portions 120f to 120k and second mounting portions 220f to 220k.

[0128] As shown in FIG. 12A, a release layer 500 is formed on the entire lower surface of the support 400 .

[0129] The interposer 10 a is formed on the release layer 500 and then peeled off from the release layer 500 .

[0130] 12B, insulator 110, first mounting portions 120d and 120e, and protective films 122d, 122e, 132d, and 132e are formed on the lower surface of release layer 500. In other words, first layer 100 is formed.

[0131] 12C, the insulator 210, the vias 240d and 240e, and the second mounting portions 220d and 220e are formed. In other words, the second layer 200 is formed.

[0132] Next, as shown in FIG. 12D, the insulator 110 is peeled off from the release layer 500.

[0133] Next, as shown in FIG. 12E, openings 111d and 111e are formed in the insulator 110 by laser light.

[0134] As described above, the first mounting portions 120d and 120e are exposed from the insulator 110 at the openings 111d and 111e, respectively. Therefore, in the step shown in Fig. 12E, laser light is irradiated near the first mounting portions 120d and 120e. The protective films 122d and 122e can protect the pads 121d and 121e from heat received from the laser light.

[0135] As described above, the interposer 10a according to the first embodiment is manufactured.

[0136] (summary) The interposer 10 comprises a first insulator 110 made of a resin material and provided on a first layer 100; a first mounting portion 120 provided on the first layer 100 and partially exposed from the first insulator 110; a second insulator 210 made of a resin material and provided on a second layer 200 located below the first layer 100 and in contact with the underside of the first mounting portion 120; a second mounting portion 220 provided on the second layer 200 and exposed from the second insulator 210; and a via 240 electrically connecting the first mounting portion 120 and the second mounting portion 220; the first mounting portion 120 has a first pad 121 made of a conductive material and a first protective film 122 covering the first pad 121; the first protective film 122 has an exposed portion 123 exposed from the first insulator 110; and the melting point of the first protective film 122 is higher than the melting point of the first pad 121.

[0137] According to the above configuration, it is possible to improve the heat resistance of the first pad 121. In addition, it is possible to improve the corrosion resistance of the pad 121.

[0138] The interposer 10 further includes a first wiring 130 provided on the first layer 100, and the first wiring 130 has a conductive portion 131 connecting the first mounting portion 120 and the via 240, and a second protective film 132 covering the conductive portion 131.

[0139] According to the above configuration, the adhesiveness between the conductive portion 131 and the insulator 110 can be improved, and peeling of the insulator 110 from the wiring 130 can be suppressed.

[0140] The interposer 10 further includes a second wiring 230 provided on the second layer 200 and connecting the second mounting portion 220 and the via 240 .

[0141] According to the above configuration, it is possible to achieve further miniaturization and higher density of the circuit board 1 using the interposer 10.

[0142] In a plan view, the area of ​​the second mounting portion 220 is larger than the area of ​​the portion of the first mounting portion 120 that is exposed from the first insulator 110 .

[0143] According to the above configuration, the semiconductor element 20 having a narrow space between the terminals can be mounted on the substrate 30 by using the interposer 10 .

[0144] The first protective film 122 further has a buried portion 124 , and the buried portion 124 is covered with the first insulator 110 .

[0145] According to the above configuration, the adhesiveness between the pad 121 and the insulator 110 can be improved, and peeling of the insulator 110 from the first mounting portion 120 can be suppressed.

[0146] The material of the pad 121 is Cu, and the material of the protective film 122 is a Ni—Cu alloy.

[0147] According to the above configuration, it is possible to improve the heat resistance of the first pad 121. In addition, it is possible to improve the corrosion resistance of the pad 121.

[0148] The portion of the first mounting portion 120 that is exposed from the first insulator 110 has a width of 30 μm to 80 μm in plan view, and the second mounting portion 220 has a width of 40 μm to 5 mm in plan view.

[0149] According to the above configuration, the semiconductor element 20 having a narrow space between the terminals can be mounted on the substrate 30 by using the interposer 10 .

[0150] The interposer 10 includes a plurality of upper layer pads and a plurality of lower layer pads. Each of the plurality of upper layer pads is a first mounting portion 120, and each of the plurality of lower layer pads is a second mounting portion 220. The plurality of upper layer pads are located within a first region 11, and the plurality of lower layer pads are located within a second region 12, with the first region being inside the second region 12.

[0151] According to the above configuration, the semiconductor element 20 having a narrow space between the terminals can be mounted on the substrate 30 by using the interposer 10 .

[0152] The circuit board 1 includes an interposer 10 , a semiconductor element 20 connected to the first mounting portion 120 , and a substrate 30 connected to the second mounting portion 220 .

[0153] 1 Circuit board 10a, 10b, 10c, 10d, 10e Interposer 11 First region 12 Second region 20 Semiconductor element 30 Substrate 21d to 21k, 31d to 31k Solder 100 First layer 101, 102, 103 Wiring layer 110, 210 Insulator 111d to 111k Opening 120d to 120k First mounting portion 121d to 121k Pad 122d to 122k, 132d to 132k, 232d to 232k Protective film 123d to 123k Exposed portion 124d to 124k Buried portion 130d to 130k, 230d to 230k, 330d to 330k Wiring 131d to 131k Conductive portions 133d to 133k, 233d to 233k Connecting portions 140d to 140k Seed layer 200 Second layer 201, 301 Via layers 220d to 220k Second mounting portions 240d to 240k, 340d to 340k Vias 300 Third layer 400 Support 500 Release layer

Claims

1. An interposer comprising: a first insulator made of a resin material and provided on a first layer; a first mounting portion provided on the first layer and partially exposed from the first insulator; a second insulator made of a resin material and provided on a second layer located below the first layer and in contact with the underside of the first mounting portion; a second mounting portion provided on the second layer and exposed from the second insulator; and a via that electrically connects the first mounting portion and the second mounting portion; wherein the first mounting portion has a first pad made of a conductive material and a first protective film that covers the first pad, the first protective film having an exposed portion that is exposed from the first insulator, and the melting point of the first protective film is higher than the melting point of the first pad.

2. An interposer as described in claim 1, further comprising a first wiring provided on the first layer, the first wiring having a conductive portion connecting the first mounting portion and the via, and a second protective film covering the conductive portion.

3. The interposer according to claim 1 or 2, further comprising a second wiring provided on the second layer and connecting the second mounting portion and the via.

4. An interposer according to any one of claims 1 to 3, wherein, in a plan view, the area of ​​the second mounting portion is larger than the area of ​​the portion of the first mounting portion that is exposed from the first insulator.

5. An interposer according to any one of claims 1 to 4, wherein the first protective film further has a buried portion, and the buried portion is covered with the first insulator.

6. The interposer according to any one of claims 1 to 5, wherein the material of the pad is Cu, and the material of the protective film is a Ni-Cu alloy.

7. An interposer as claimed in any one of claims 1 to 6, wherein the portion of the first mounting portion exposed from the first insulator has a width of 30 μm to 80 μm in a planar view, and the second mounting portion has a width of 40 μm to 5 mm in a planar view.

8. An interposer as described in any one of claims 1 to 7, comprising: a plurality of upper layer pads; and a plurality of lower layer pads, wherein each of the plurality of upper layer pads is the first mounting portion, and each of the plurality of lower layer pads is the second mounting portion, the plurality of upper layer pads are located within a first region, the plurality of lower layer pads are located within a second region, and the first region is inside the second region.

9. A circuit board comprising: an interposer according to any one of claims 1 to 8; a semiconductor element connected to the first mounting portion; and a substrate connected to the second mounting portion.

Images