Semiconductor device

Abstract

The present invention obtains a semiconductor device which properly protects a circuit to be protected from overvoltage. This semiconductor device comprises: first to third elements (M1 to M3) that are depletion-type MOSFET; and a fourth element (M4) that is a switching element. The drain terminal of the first element is connected to a power supply (92) and the source terminal thereof is connected to the drain terminal of the second element. The source terminal of the second element is connected to a first line (42). The gate terminal of the first element and the gate terminal of the second element are connected to the first line (42). The drain terminal of the third element is connected to the first line (42). The source terminal of the third element is connected to a second line (43). The gate terminal of the third element is connected to the second line (43). The internal impedance of the fourth element is controlled by the voltage of the first line (42).

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] As background art in this technical field, the abstract of Patent Document 1 listed below states that "a clamp circuit includes a first MOS transistor and a second MOS transistor connected in series to the first MOS transistor. The gate of the first MOS transistor is connected to the drain of the first MOS transistor. The gate of the second MOS transistor is connected to the drain of the second MOS transistor. The clamp circuit is configured so that a substrate bias effect occurs in at least one of the first MOS transistor and the second MOS transistor."

[0003] International Publication No. 2021 / 166679

[0004] However, in the above-mentioned technology, there is a demand for more appropriate protection of the circuit to be protected from overvoltage. The present invention has been made in consideration of the above-mentioned circumstances, and has an object to provide a semiconductor device that can appropriately protect the circuit to be protected from overvoltage.

[0005] In order to achieve the above object, a semiconductor device of the present invention comprises first to third elements which are depression-type MOSFETs and a fourth element which is a switching element, wherein a drain terminal of the first element is connected to a power supply, a source terminal of the first element is connected to a drain terminal of the second element, a source terminal of the second element is connected to a first line directly or via a first impedance element, a gate terminal of the first element and a gate terminal of the second element are connected to the first line, a drain terminal of the third element is connected to the first line, a source terminal of the third element is connected to a second line directly or via a second impedance element, and a gate terminal of the third element is connected to the second line, the fourth element is connected between the power supply and a circuit to be protected, an internal impedance of the fourth element is controlled by a voltage on the first line, and the second line is connected to the circuit to be protected or a predetermined potential.

[0006] According to the present invention, the circuit to be protected can be appropriately protected from overvoltage.

[0007] 1 is a circuit diagram of an overvoltage protection circuit according to a first embodiment; FIG. 2 is a diagram showing various characteristics in a lower-stage bias circuit; FIG. 3 is a diagram showing various characteristics in an upper-stage bias circuit; FIG. 4 is a diagram showing various characteristics of the entire overvoltage protection circuit; FIG. 5 is a diagram explaining the operation of the overvoltage protection circuit when the voltage is not limited; FIG. 6 is a diagram explaining the operation of the overvoltage protection circuit when the voltage is limited; FIG. 7 is a circuit diagram of an overvoltage protection circuit according to a second embodiment; FIG. 8 is a circuit diagram of an overvoltage protection circuit according to a third embodiment; FIG. 9 is a circuit diagram of an overvoltage protection circuit according to a fourth embodiment; FIG. 10 is a circuit diagram of an overvoltage protection circuit according to a fifth embodiment; FIG. 11 is a circuit diagram of an overvoltage protection circuit according to a sixth embodiment; FIG. 12 is a circuit diagram of an overvoltage protection circuit according to a seventh embodiment; FIG. 13 is a circuit diagram of an overvoltage protection circuit according to an eighth embodiment; FIG. 14 is a block diagram of an overvoltage protection circuit according to a ninth embodiment; FIG. 15 is a voltage characteristic diagram of the overvoltage protection circuit according to the ninth embodiment; FIG. 16 is a block diagram of an autonomous synchronous rectifier element according to a tenth embodiment; FIG. 17 is a voltage characteristic diagram of the autonomous synchronous rectifier element according to the tenth embodiment.

[0008] Overvoltage protection circuits 11 to 19 (semiconductor devices) and an autonomous synchronous rectifier element 20 (semiconductor device) according to first to tenth embodiments will be described below in order. [First Embodiment] <Configuration of First Embodiment> FIG. 1 is a circuit diagram of an overvoltage protection circuit 11 according to the first embodiment. The overvoltage protection circuit 11 includes an input terminal 30 and output terminals 31 and 32. An input voltage Vin is applied to the input terminal 30 by an external power supply circuit 92 (power supply). The output terminal 31 is connected to a ground potential. The output terminal 32 is connected to a circuit 90 to be protected. The input voltage Vin is usually close to a reference voltage Vn (not shown), but a surge voltage Vs (not shown) may be superimposed on the reference voltage Vn. The overvoltage protection circuit 11 suppresses the surge voltage Vs, thereby applying a voltage close to the reference voltage Vn as an output voltage Vout to the circuit 90 to be protected.

[0009] The overvoltage protection circuit 11 further includes an element M1 (first element), an element M2 (second element), an element M3 (third element), an element M4 (fourth element), a resistor R2 (first impedance element), and a resistor R3 (second impedance element). The elements M1, M2, M3, and M4 are all depletion-mode N-channel metal-oxide-semiconductor field-effect transistors (MOSFETs). The drain terminal of the element M1 is connected to the power supply circuit 92 via the input terminal 30, and the source terminal is connected to the drain terminal of the element M2.

[0010] The source terminal of element M2 is connected to line 42 (first line) via resistor R2. The gate terminals of elements M1 and M2 are both connected to line 42. The drain terminal of element M3 is connected to line 42, and the source terminal is connected to ground potential via resistor R3, line 43 (second line), and output terminal 31. The gate terminal of element M3 is also connected to line 43.

[0011] The drain terminal of the element M4 is connected to the input terminal 30, the source terminal is connected to the output terminal 32, and the gate terminal is connected to the line 42. Of the above-mentioned elements, the elements M1 and M2 and the resistor R2 are referred to as an upper stage bias circuit BP, and the element M3 and the resistor R3 are referred to as a lower stage bias circuit BS.

[0012] <Operation of the First Embodiment> Figure 2 is a diagram showing various characteristics of the lower-stage bias circuit BS. In graph G10 of Figure 2, the vertical axis represents the drain current Id, and the horizontal axis represents the gate-source voltage Vgs3 of element M3. Note that the drain current Id is a common drain current for elements M1, M2, and M3. Characteristics Q11 and Q12 are both the Id-Vgs characteristics of element M3. Characteristic Q13 is the voltage-current characteristic of resistor R3, and is linear. Characteristics Q11 and Q12 intersect with characteristic Q13 at intersections P14 and P15, respectively. Furthermore, characteristics Q11 and Q12 intersect with the vertical axis of graph G10 at intersections P16 and P17, respectively.

[0013] 2, the vertical axis represents the drain current Id, and the horizontal axis represents the drain-source voltage Vds3 of the element M3. A characteristic Q21 of the graph G20 is the Id-Vds characteristic of the element M3, and represents the change in the drain current Id when the drain-source voltage Vds3 is changed while the gate-source voltage Vgs3 is kept constant. Points P24 and P25 on the characteristic Q21 correspond to the characteristics Q11 and Q12 on the graph G10, respectively.

[0014] In graph G30 of Figure 2, the vertical axis represents the drain current Id, and the horizontal axis represents the drain-gate voltage Vd-g3 of element M3. In other words, the drain-gate voltage Vd-g3 is the voltage between lines 42 and 43 in Figure 1. Characteristic Q31 of graph G30 shows the Id-Vd-g3 characteristic of element M3. According to characteristic Q31, it can be seen that when the drain-gate voltage Vd-g3 is gradually increased from 0 [V], the drain current Id rises sharply near 0 [V] and then rises more gradually.

[0015] In graph G40 of Figure 2, the vertical axis represents the equivalent resistance Rd-g3, and the horizontal axis represents the drain-gate voltage Vd-g3. The equivalent resistance Rd-g3 is the equivalent resistance of the lower-stage bias circuit BS, including resistor R3 and element M3. Characteristic Q41 represents the characteristic of the equivalent resistance Rd-g3 versus the drain-gate voltage Vd-g3 of element M3. Characteristic Q41 shows that as the drain-gate voltage Vd-g3 is gradually increased from 0 V, the equivalent resistance Rd-g3 rises approximately linearly, and as the drain-gate voltage Vd-g3 further increases, the slope becomes gentler.

[0016] FIG. 3 shows various characteristics of the upper-stage bias circuit BP. The characteristics of the element M2 and resistor R2 in the upper-stage bias circuit BP are the same as those of the lower-stage bias circuit BS (see FIG. 2). In graph G50 of FIG. 3, the vertical axis represents the drain current Id, and the horizontal axis represents the gate-source voltage Vgs1 of element M1. Characteristics Q51 and Q52 are both Id-Vgs characteristics of element M1, and in the illustrated example, they have the same shape as characteristics Q11 and Q12 (see FIG. 2) of element M3. Characteristic Q53 is the characteristic of the drain-gate voltage Vd-g2 of element M2 relative to the gate-source voltage Vgs2 of element M2. In the illustrated example, characteristic Q53 has a shape that is horizontally inverted from characteristic Q31 in FIG. 2.

[0017] The characteristics Q51 and Q52 intersect with the characteristic Q53 at intersections P54 and P55, respectively. The drain current Id at intersections P54 and P55 is very close to the values ​​at intersections P14 and P15 (see FIG. 2) for the element M3. That is, it can be seen that the change in the drain current Id is very small relative to the change in the drain-source voltage Vds1 of the element M1.

[0018] In graph G60 of Figure 3, the vertical axis represents drain current Id, and the horizontal axis represents drain-gate voltage Vd-g1 of element M1. In other words, drain-gate voltage Vd-g1 is the voltage between input terminal 30 and line 42 in Figure 1. Characteristic Q61 of graph G60 shows the Id-Vd-g1 characteristic of element M1. According to characteristic Q61, it can be seen that when drain-gate voltage Vd-g1 is gradually increased from 0 [V], drain current Id rises sharply near 0 [V] and then remains approximately constant.

[0019] In graph G70 of Figure 3, the vertical axis represents the equivalent resistance Rd-g1, and the horizontal axis represents the drain-gate voltage Vd-g1. The equivalent resistance Rd-g1 is the equivalent resistance of the upper-stage bias circuit BP, including resistor R2 and elements M1 and M2. Characteristic Q71 represents the characteristic of the equivalent resistance Rd-g1 versus the drain-gate voltage Vd-g1 of element M1. Characteristic Q71 shows that the equivalent resistance Rd-g1 is approximately 0 [Ω] until the drain-gate voltage Vd-g1 reaches a predetermined value, and that once the drain-gate voltage Vd-g1 exceeds the predetermined value, the equivalent resistance Rd-g1 changes approximately linearly.

[0020] 4 is a diagram showing various overall characteristics of the overvoltage protection circuit 11. In graph G80 of FIG. 4, the vertical axis represents equivalent resistances Rd-g1 and Rd-g3, and the horizontal axis represents drain-gate voltage Vd-g. Because the drain-gate voltages Vd-g1 and Vd-g3 of the above-mentioned elements M1 and M3 are approximately equal, the horizontal axis of graph G80 represents the "drain-gate voltage Vd-g," which is a value common to both elements.

[0021] As a result, the characteristics Q41 and Q71 shown in graphs G40 and G70 (see FIGS. 2 and 3) can be superimposed as shown in graph G80. In graph G80, the equivalent resistances Rd-g1 and Rd-g3 match when the drain-gate voltage Vd-g is the illustrated voltage Va. The higher the drain-gate voltage Vd-g is relative to voltage Va, the smaller "Rd-g3 / (Rd-g3+Rd-g1)" becomes.

[0022] In graph G90 of FIG. 4, the vertical axis represents the resistance ratio K (= Rd-g3 / (Rd-g3+Rd-g1)), and the horizontal axis represents the input voltage Vin. The relationship between the two is shown by characteristic Q91. That is, when the input voltage Vin is low, the resistance ratio K is approximately 1, and the higher the input voltage Vin, the lower the resistance ratio K becomes.

[0023] The element M4 (see FIG. 1) is conductive when its gate-source voltage Vgs4 is higher than its threshold voltage Vth. Therefore, when the output voltage Vout becomes higher than "the drain-gate voltage Vd-g3 of the element M3 minus the threshold voltage Vth," the element M4 is turned off. This provides overvoltage protection to the protected circuit 90.

[0024] FIG. 5 is an explanatory diagram of the operation of the overvoltage protection circuit 11 when the voltage is not limited. In FIG. 5, the input voltage Vin is close to the reference voltage Vn. The threshold voltages Vth of elements M1 to M4 are also assumed to be equal. The voltage drops across resistors R2 and R3 and element M2 are all close to the threshold voltage Vth, and the voltage drop across element M1 is approximately 0 V. As a result, the drain-gate voltage Vd-g3 of element M3 is sufficiently high, turning element M4 on and reducing its voltage drop to approximately 0 V. As a result, the output voltage Vout is approximately equal to the input voltage Vin and the reference voltage Vn.

[0025] FIG. 6 is a diagram illustrating the operation of the overvoltage protection circuit 11 during voltage limiting. In FIG. 6, the input voltage Vin is a value obtained by superimposing a relatively high surge voltage Vs on the reference voltage Vn. As in the case of FIG. 5, the voltage drops across resistors R2 and R3 and element M2 are all near the threshold voltage Vth. As the input voltage Vin increases and the drain current Id of elements M1, M2, and M3 increases, the resistance ratio K (see FIG. 4) of the equivalent resistance Rd-g3 of element M3 decreases, causing the voltage drop across element M3 to become a voltage Vk slightly higher than the reference voltage Vn.

[0026] Accordingly, the voltage drop across element M1 approaches Vin-Vk. As the equivalent resistance Rd-g3 decreases, the gate-source voltage Vgs4 of element M4 becomes less than the threshold voltage Vth, turning element M4 off. In other words, the internal impedance of element M4 increases. As a result, the output voltage Vout approaches voltage Vk, and the drain-source voltage Vds4 of element M4 approaches "Vin-Vk." This achieves overvoltage protection for the protected circuit 90.

[0027] Second Embodiment Figure 7 is a circuit diagram of an overvoltage protection circuit 12 according to a second embodiment. In the description of each embodiment, parts corresponding to parts in other embodiments are given the same reference numerals, and their description may be omitted. In Figure 7, the overvoltage protection circuit 12 has an output terminal 33 instead of the output terminals 31 and 32 in the overvoltage protection circuit 11 (see Figure 1). That is, the protected circuit 90, the line 43, and the source terminal of the element M4 are all connected to the output terminal 33.

[0028] The operation of the second embodiment is similar to that of the first embodiment. However, a small current always flows through the lower-stage bias circuit BS and the upper-stage bias circuit BP of the overvoltage protection circuit 12. Therefore, in the circuit 90 to be protected, if a small current always flows through the circuit 90 to be protected, applying the overvoltage protection circuit 12 of this embodiment can simplify the circuit. On the other hand, if a situation may arise in which a small current cannot flow through the circuit 90 to be protected, applying the overvoltage protection circuit 11 of the first embodiment is preferable.

[0029] 8 is a circuit diagram of an overvoltage protection circuit 13 according to a third embodiment. The configuration of the overvoltage protection circuit 13 is the same as that of the overvoltage protection circuit 12 of the second embodiment (see FIG. 7), except that the resistance values ​​of the resistors R2 and R3 are set to 0 Ω.

[0030] The operation of the third embodiment is similar to that of the first and second embodiments, except that the intersections P14 and P15 on graph G10 (see FIG. 2) are shifted to the positions of intersections P16 and P17. If this does not impair operation, the configuration of the overvoltage protection circuit 13 of this embodiment can be further simplified compared to the overvoltage protection circuits 11 and 12 of the first and second embodiments.

[0031] [Fourth Embodiment] Figure 9 is a circuit diagram of an overvoltage protection circuit 14 according to a fourth embodiment. The overvoltage protection circuit 14 of this embodiment includes an input terminal 51 (first input terminal), an input terminal 52 (second input terminal), an output terminal 53 (first output terminal), an output terminal 54 (second output terminal), a Zener diode 57 (first overvoltage protection element), a Zener diode 58 (second overvoltage protection element), and the overvoltage protection circuit 12 of the second embodiment (see Figure 7). The input terminal 51 is connected to the input terminal 30 of the overvoltage protection circuit 12, the output terminal 53 is connected to the output terminal 33 of the overvoltage protection circuit 12, and the input terminal 52 is connected to the output terminal 54. In other words, the input terminal 51 is connected to the drain terminal of the device M1 (see Figure 7) via the input terminal 30. The output terminal 53 is connected to the source terminal of the device M4 via the output terminal 33.

[0032] Furthermore, a Zener diode 57 is connected between the input terminals 51 and 52, and a Zener diode 58 is connected between the output terminals 53 and 54. According to this embodiment, by providing the Zener diodes 57 and 58, surge voltages that cannot be absorbed by the overvoltage protection circuit 12 can be absorbed by the Zener diodes 57 and 58. Note that an active clamp circuit may be used instead of the Zener diodes 57 and 58.

[0033] Fifth Embodiment Fig. 10 is a circuit diagram of an overvoltage protection circuit 15 according to a fifth embodiment. The overvoltage protection circuit 15 of this embodiment includes a pair of input terminals 51 and 52, a pair of output terminals 53 and 54, Zener diodes 57 and 58, and the overvoltage protection circuit 11 (see Fig. 1) of the first embodiment. The input terminal 51 is connected to the input terminal 30 of the overvoltage protection circuit 11, the output terminal 53 is connected to the output terminal 31 of the overvoltage protection circuit 12, and the input terminal 52 and the output terminal 54 are connected to the output terminal 32 of the overvoltage protection circuit 11. In other words, the input terminal 51 is connected to the drain terminal of the device M1 (see Fig. 1) via the input terminal 30. The output terminal 53 is connected to the line 43 via the output terminal 31. The input terminal 52 and the output terminal 54 are connected to the source terminal of the device M4 via the output terminal 32.

[0034] Furthermore, a Zener diode 57 is connected between the input terminals 51 and 52, and a Zener diode 58 is connected between the output terminals 53 and 54. In this embodiment, as in the fourth embodiment, the Zener diodes 57 and 58 are provided, so that surge voltages that cannot be absorbed by the overvoltage protection circuit 12 can be absorbed by the Zener diodes 57 and 58. In this embodiment, an active clamp circuit may be used instead of the Zener diodes 57 and 58.

[0035] Sixth Embodiment FIG. 11 is a circuit diagram of an overvoltage protection circuit 16 according to a sixth embodiment. The configuration of the overvoltage protection circuit 16 according to the sixth embodiment is similar to that of the overvoltage protection circuit 11 according to the first embodiment (see FIG. 1), except for the following points. That is, in the sixth embodiment, the elements M1, M2, and M3 are depletion-type P-channel MOSFETs. As described above, the elements M1, M2, and M3 may also be P-channel MOSFETs as long as they are depletion-type. However, the connection relationship between the elements M1, M2, and M3 and the resistors R2 and R3 is changed to that corresponding to P-channel MOSFETs. The operation of this embodiment is similar to that of the first embodiment.

[0036] Seventh Embodiment Figure 12 is a circuit diagram of an overvoltage protection circuit 17 according to a seventh embodiment. The configuration of the overvoltage protection circuit 17 according to the seventh embodiment is similar to that of the overvoltage protection circuit 11 according to the first embodiment (see Figure 1), except for the following points. That is, in the seventh embodiment, Zener diodes ZD2 (first impedance element) and ZD3 (second impedance element) are used instead of resistors R2 and R3 in the first embodiment. This embodiment has the effect of reducing current consumption by the Zener diodes ZD2 and ZD3, and the effect of making the change in resistance ratio K (see Figure 4) more abrupt, allowing the boundary voltage for voltage limiting to be set more accurately.

[0037] Eighth Embodiment FIG. 13 is a circuit diagram of an overvoltage protection circuit 18 according to an eighth embodiment. The configuration of the overvoltage protection circuit 18 according to the eighth embodiment is similar to that of the overvoltage protection circuit 11 according to the first embodiment (see FIG. 1), except for the following points. That is, in the eighth embodiment, inductors L2 (first impedance element) and L3 (second impedance element) are used instead of the resistors R2 and R3 in the first embodiment. In this embodiment, when no surge voltage is superimposed on the input voltage Vin, the drain current Id of the elements M1, M2, and M3 is constant, and therefore the voltage drop across the inductors L2 and L3 is 0 V. On the other hand, when a surge voltage is superimposed on the input voltage Vin, a voltage drop of approximately the threshold voltage Vth occurs across the inductors L2 and L3. That is, the gate-source voltage Vgs of the elements M2 and M3 becomes approximately the threshold voltage Vth. This suppresses the current flowing through the elements M1, M2, and M3, thereby reducing current consumption.

[0038] 14 is a block diagram of an overvoltage protection circuit 19 according to a ninth embodiment. The overvoltage protection circuit 19 is a cascade connection of the overvoltage protection circuit 11 (see FIG. 1) of the first embodiment and the overvoltage protection circuit 12 (see FIG. 7) of the second embodiment. That is, the input terminal 30 of the overvoltage protection circuit 12 is connected to a power supply circuit 92, and the output terminal 33 is connected to the input terminal 30 of the overvoltage protection circuit 11. The output terminal 31 of the overvoltage protection circuit 11 is connected to the ground potential, and the output terminal 32 is connected to the circuit 90 to be protected.

[0039] FIG. 15 is a voltage characteristic diagram of the overvoltage protection circuit 19. In FIG. 15, the horizontal axis represents the input voltage Vin, and the vertical axis represents the voltage of each component. The output voltage Vout, voltages V11, and V12 are the voltages applied to the protected circuit 90 and the overvoltage protection circuits 11 and 12, respectively. As the input voltage Vin gradually increases from 0 V, the output voltage Vout first becomes approximately equal to the input voltage Vin and then continues to rise. When the output voltage Vout reaches near the reference voltage Vn, it remains near the reference voltage Vn. As the input voltage Vin further increases, the voltage V11 begins to rise. When the voltage V11 reaches near the reference voltage Vn, it remains near the reference voltage Vn. As the input voltage Vin further increases, the voltage V12 subsequently increases in response to the input voltage Vin. As described above, according to this embodiment, the overvoltage can be absorbed by both the overvoltage protection circuits 11 and 12, further improving the tolerance to overvoltage.

[0040] 16 is a block diagram of an autonomous synchronous rectifier device 20 according to a tenth embodiment. The autonomous synchronous rectifier device 20 includes an anode terminal 71 (first terminal), a cathode terminal 72 (second terminal), an overvoltage protection circuit 12, a control circuit 74, a capacitor 76, and a MOSFET device M5. The control circuit 74 includes a step-down circuit 74a.

[0041] The overvoltage protection circuit 12 is similar to that of the second embodiment. One of the anode terminal 71 or the cathode terminal 72 is connected to, for example, an AC power supply (not shown), and the other is connected to, for example, a DC load (not shown). The autonomous synchronous rectifier device 20 performs rectification similar to that of a diode. That is, it conducts forward current from the anode terminal 71 to the cathode terminal 72, but blocks reverse current from the cathode terminal 72 to the anode terminal 71. While a forward voltage drop generally occurs in a diode, the autonomous synchronous rectifier device 20 differs in that it can reduce the forward voltage drop to approximately 0 [V].

[0042] The control circuit 74 turns the element M5 off when a reverse voltage is applied to the autonomous synchronous rectifier element 20, and turns the element M5 on otherwise. When a reverse voltage is applied to the autonomous synchronous rectifier element 20, the control circuit 74 charges the capacitor 76 via the step-down circuit 74a. The control circuit 74 then controls the on / off state of the element M5 using the charge stored in the capacitor 76 as a power source. In this embodiment, an overvoltage protection circuit 12 is inserted between the cathode terminal 72 and the control circuit 74. This allows the control circuit 74 to be protected from overvoltage even when the reverse voltage exceeds the maximum voltage that can be applied to the control circuit 74.

[0043] FIG. 17 is a voltage characteristic diagram of the autonomous synchronous rectifier device 20. In FIG. 17, the horizontal axis represents the reverse input voltage Vin, and the vertical axis represents the voltage of each component. Voltages V12 and V74 are the voltage drops that occur in the overvoltage protection circuit 12 and the control circuit 74, respectively. Voltage V74n is the voltage drop that occurs in the control circuit 74 if the overvoltage protection circuit 12 were not present. Rated voltage Vmax is the rated voltage of the control circuit 74 and the overvoltage protection circuit 12.

[0044] With voltage V74n, when the input voltage Vin becomes equal to or greater than voltage Vin1, the voltage drop in the control circuit 74 becomes equal to or greater than voltage Vmax. On the other hand, with voltages V12 and V74 in this embodiment, the voltage drop in both the overvoltage protection circuit 12 and the control circuit 74 becomes smaller than the rated voltage Vmax until the input voltage Vin reaches voltage Vin2, which is higher than voltage Vin1.

[0045] Furthermore, until the input voltage Vin exceeds the voltage Vin1, the voltage V12 remains at a relatively low value, and the voltage V74 can be maintained at a relatively high value. This allows the step-down circuit 74a to efficiently charge the capacitor 76. As described above, according to this embodiment, the withstand voltage characteristics of the autonomous synchronous rectifier device 20 can be improved without impeding the operation of the step-down circuit 74a.

[0046] [Modifications] The present invention is not limited to the above-described embodiment, and various modifications are possible. The above-described embodiment is provided as an example to facilitate understanding of the present invention, and is not necessarily limited to an embodiment including all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, or to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is possible to delete part of the configuration of each embodiment, or to add or replace other configurations. Furthermore, the control lines and information lines shown in the figures are those considered necessary for explanation, and do not necessarily represent all control lines and information lines necessary for the product. In reality, it is possible to consider that almost all components are interconnected. Possible modifications of the above-described embodiment include, for example, the following.

[0047] (1) In the first embodiment (see FIG. 1) described above, the resistors R2 and R3 may be removed, and the source terminal of the element M2 may be directly connected to the line 42, and the source terminal of the element M3 may be directly connected to the line 43. Also, in the sixth to eighth embodiments (see FIGS. 11 to 13), the output terminals 31 and 32 may be connected and used in the same manner as the output terminal 33 in the second embodiment (see FIG. 7).

[0048] (2) In each of the above-described embodiments, a predetermined potential other than the ground potential may be applied instead of the ground potential.

[0049] (3) In the above-described embodiments, a depletion-mode MOSFET is used as element M4. However, element M4 may be any element as long as its internal impedance, such as its conductive / non-conductive state, is controlled in response to the voltage of line 42 (see FIG. 1). Specifically, element M4 may be an enhancement-mode MOSFET or a bipolar transistor.

[0050] (4) Furthermore, the element M5 in the tenth embodiment may be a MOSFET or a bipolar transistor as long as it switches the on / off state between the anode terminal 71 and the cathode terminal 72.

[0051] [Effects of the Embodiments] As described above, the overvoltage protection circuits 11 to 19 and the autonomous synchronous rectifier element 20 of each of the above-described embodiments include first to third elements (M1 to M3) that are depletion-type MOSFETs and a fourth element (M4) that is a switching element, the drain terminal of the first element (M1) is connected to a power supply (92), the source terminal of the first element (M1) is connected to a drain terminal of a second element (M2), the source terminal of the second element (M2) is connected to a first line (42) directly or via first impedance elements (R2, L2, ZD2), and the gate terminal of the first element (M1) and the gate terminal of the second element (M The gate terminal of the third element (M2) is connected to the first line (42), the drain terminal of the third element (M3) is connected to the first line (42), the source terminal of the third element (M3) is connected to the second line (43) directly or via a second impedance element (R3, L3, ZD3), the gate terminal of the third element (M3) is connected to the second line (43), and the fourth element (M4) is connected between the power supply (92) and the circuit 90 to be protected, and its internal impedance is controlled by the voltage on the first line (42), and the second line (43) is connected to the circuit 90 to be protected or a predetermined potential (0 V).

[0052] This allows the protected circuit to be appropriately protected from overvoltage. Furthermore, in each of the above embodiments, the drain current Id of the elements M1, M2, and M3 can be small, thereby suppressing current consumption and achieving high-speed operation. Furthermore, the withstand voltage of each element M1 to M4 can be equal to or lower than the withstand voltage required by the overvoltage protection circuits 11 to 19 themselves, allowing elements with relatively low withstand voltages to be used, thereby reducing costs. Furthermore, the overvoltage protection circuits 11 to 19 hardly suppress the input voltage Vin below the reference voltage Vn, thereby reducing power loss and heat generation in the overvoltage protection circuits 11 to 19. Furthermore, because the operation of the elements M1 to M4 utilizes the characteristics before breakdown, reliable operation of the elements M1 to M4 can be expected. Furthermore, in each of the above embodiments, the number and types of the elements M1 to M4 can be reduced, thereby reducing the impact of variations in these elements M1 to M4.

[0053] Furthermore, as in the overvoltage protection circuits 11 and 12 of the first and second embodiments, it is more preferable that the first and second impedance elements are resistors, the source terminal of the second element (M2) is connected to the first line (42) via the first impedance element (R2), and the source terminal of the third element (M3) is connected to the second line (43) via the second impedance element (R3). This makes it possible to further suppress the current flowing through the first to third elements (M1 to M3).

[0054] Also, as in the overvoltage protection circuit 13 of the third embodiment, it is preferable that the source terminal of the second element (M2) is directly connected to the first line (42) and the source terminal of the third element (M3) is directly connected to the second line (43), thereby further reducing the number of parts.

[0055] Also, like the overvoltage protection circuits 12 and 13 of the second and third embodiments, the second line (43) may preferably be connected to the protected circuit 90. This allows the configuration of the semiconductor device (12, 13) to be further simplified.

[0056] Also, like the overvoltage protection circuit 11 of the first embodiment, the second line (43) may be preferably connected to a predetermined potential, so that the circuit 90 to be protected can be appropriately protected even when a current cannot be constantly passed through the circuit 90 to be protected.

[0057] Furthermore, like the overvoltage protection circuits 14 and 15 of the fourth and fifth embodiments, it is also preferable to further include a first overvoltage protection element (57) connected between the first and second input terminals (51, 52) and a second overvoltage protection element (58) connected between the first and second output terminals (53, 54), thereby further increasing the resistance to overvoltage.

[0058] Furthermore, like the autonomous synchronous rectifier device 20 of the tenth embodiment, the autonomous synchronous rectifier device 20 may further include a first terminal (71) connected to the drain terminal of the first device (M1), a second terminal (72), a fifth device (M5) that is a switching device connected between the first and second terminals (71, 72), a capacitor 76, and a control circuit 74 that is a protected circuit 90 and operates using the charge stored in the capacitor 76. The control circuit 74 preferably has the following functions: when the potential of the first terminal (71) exceeds the potential of the second terminal (72), the fifth device (M5) is turned off to charge the capacitor 76; and when the potential of the first terminal (71) falls below the potential of the second terminal (72), the fifth device (M5) is turned on. This allows the control circuit 74 to efficiently charge the capacitor 76, thereby improving the withstand voltage characteristics of the autonomous synchronous rectifier device 20 without impeding the operation of the control circuit 74.

[0059] 11 to 19 Overvoltage protection circuit (semiconductor device) 20 Autonomous synchronous rectification element (semiconductor device) 42 Line (first line) 43 Line (second line) 51 Input terminal (first input terminal) 52 Input terminal (second input terminal) 53 Output terminal (first output terminal) 54 Output terminal (second output terminal) 57 Zener diode (first overvoltage protection element) 58 Zener diode (second overvoltage protection element) 71 Anode terminal (first terminal) 72 Cathode terminal (second terminal) 74 Control circuit 76 Capacitor 90 Circuit to be protected 92 Power supply circuit (power supply) L2 Inductor (first impedance element) L3 Inductor (second impedance element) M1 Element (first element) M2 Element (second element) M3 Element (third element) M4 Element (fourth element) M5 Element (fifth element) R2 Resistor (first impedance element) R3 Resistor (second impedance element) ZD2 Zener diode (first impedance element) ZD3 Zener diode (second impedance element)

Claims

1. A semiconductor device comprising first to third elements which are depletion-type MOSFETs; and a fourth element which is a switching element, wherein the drain terminal of the first element is connected to a power supply, the source terminal of the first element is connected to the drain terminal of the second element, the source terminal of the second element is connected to a first line directly or via a first impedance element, the gate terminal of the first element and the gate terminal of the second element are connected to the first line, the drain terminal of the third element is connected to the first line, the source terminal of the third element is connected to a second line directly or via a second impedance element, and the gate terminal of the third element is connected to the second line, the fourth element is connected between the power supply and a circuit to be protected, and its internal impedance is controlled by the voltage on the first line, and the second line is connected to the circuit to be protected or a predetermined potential.

2. The semiconductor device according to claim 1, wherein the first and second impedance elements are resistors, the source terminal of the second element is connected to the first line via the first impedance element, and the source terminal of the third element is connected to the second line via the second impedance element.

3. The semiconductor device according to claim 1, wherein the source terminal of the second element is directly connected to the first line, and the source terminal of the third element is directly connected to the second line.

4. The semiconductor device according to claim 1, wherein the second line is connected to the circuit to be protected.

5. The semiconductor device according to claim 1, wherein the second line is connected to a predetermined potential.

6. The semiconductor device according to claim 4, further comprising: first and second input terminals connected to the power supply; first and second output terminals connected to the circuit to be protected; a first overvoltage protection element connected between the first and second input terminals; and a second overvoltage protection element connected between the first and second output terminals, wherein the first input terminal is connected to the drain terminal of the first element, the first output terminal is connected to the second line and the fourth element, and the second input terminal is connected to the second output terminal.

7. The semiconductor device according to claim 5, further comprising: first and second input terminals connected to the power supply; first and second output terminals connected to the circuit to be protected; a first overvoltage protection element connected between the first and second input terminals; and a second overvoltage protection element connected between the first and second output terminals, wherein the first input terminal is connected to the drain terminal of the first element, the first output terminal is connected to the second line, and the second input terminal is connected to the second output terminal and the fourth element.

8. The semiconductor device according to claim 4, further comprising: a first terminal connected to the drain terminal of the first element; a second terminal; a fifth element which is a switching element connected between the first and second terminals; a capacitor; and a control circuit which is the circuit to be protected and operates using the charge stored in the capacitor, wherein the control circuit has the function of turning off the fifth element and charging the capacitor when the potential of the first terminal exceeds the potential of the second terminal, and the function of turning on the fifth element when the potential of the first terminal becomes equal to or lower than the potential of the second terminal.

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